From: Jan Michel Date: Tue, 15 Aug 2017 13:31:03 +0000 (+0200) Subject: Change files to links to vhdlbasics repository X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a8af67712dcea515424017b64d3ee05a24885085;p=logicbox.git Change files to links to vhdlbasics repository --- diff --git a/code/sedcheck.vhd b/code/sedcheck.vhd deleted file mode 100644 index 3843238..0000000 --- a/code/sedcheck.vhd +++ /dev/null @@ -1,198 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; - -library ecp5um; -use ecp5um.components.all; - -entity sedcheck is - port( - CLK : in std_logic; - ERROR_OUT : out std_logic; - - CONTROL_IN : in std_logic_vector(3 downto 0); - DEBUG : out std_logic_vector(31 downto 0) - ); -end entity; - - -architecture sed_arch of sedcheck is - - component SEDFA - generic ( - CHECKALWAYS : string :="DISABLED"; - SED_CLK_FREQ : string :="3.5" ; - DEV_DENSITY : string :="2100L" - ); - port ( - SEDSTDBY : in std_logic; - SEDENABLE : in std_logic; - SEDSTART : in std_logic; - SEDFRCERR : in std_logic; - SEDERR : out std_logic; - SEDDONE : out std_logic; - SEDINPROG : out std_logic; - SEDCLKOUT : out std_logic - ); - end component; - - type state_t is (IDLE, INIT_1, INIT_2, INIT_3, START_1, START_2, WAITACTIVE, WAITDONE); - signal state : state_t; - signal state_bits : std_logic_vector(3 downto 0); - - signal sed_edge : std_logic; - signal sed_clock_last : std_logic; - - signal sed_clock : std_logic; - signal sed_done : std_logic; - signal sed_enable : std_logic; - signal sed_error : std_logic; - signal sed_inprogress : std_logic; - signal sed_start : std_logic; - - signal sed_clock_q : std_logic; - signal sed_done_q : std_logic; - signal sed_error_q : std_logic; - signal sed_inprogress_q : std_logic; - - signal status_i : std_logic_vector(31 downto 0); - - signal run_counter : unsigned(7 downto 0) := (others => '0'); - signal error_counter : unsigned(7 downto 0) := (others => '0'); - signal timer : unsigned(22 downto 0); - -begin - -sed_clock_last <= sed_clock_q when rising_edge(CLK); -sed_edge <= sed_clock_q and not sed_clock_last when rising_edge(CLK); - -sed_clock_q <= sed_clock when rising_edge(CLK); -sed_done_q <= sed_done when rising_edge(CLK); -sed_inprogress_q <= sed_inprogress when rising_edge(CLK); -sed_error_q <= sed_error when rising_edge(CLK); - - ---------------------------------------------------------------------------- --- SED control state machine ---------------------------------------------------------------------------- -proc_ctrl : process begin - wait until rising_edge(CLK); - timer <= timer + 1; - case state is - when IDLE => - sed_enable <= '0'; - sed_start <= '0'; - if CONTROL_IN(0) = '1' then - state <= INIT_1; - timer <= (0 => '1', others => '0'); - end if; - when INIT_1 => - sed_enable <= '0'; - sed_start <= '0'; - if timer(5 downto 0) = 0 then - state <= INIT_2; - end if; - when INIT_2 => - sed_enable <= '1'; - sed_start <= '0'; - if timer(5 downto 0) = 0 then - state <= INIT_3; - end if; - when INIT_3 => - sed_enable <= '1'; - sed_start <= '0'; - if timer(5 downto 0) = 0 then - state <= START_1; - end if; - when START_1 => - sed_enable <= '1'; - sed_start <= '0'; - if sed_edge = '1' then - state <= START_2; - end if; - when START_2 => - sed_enable <= '1'; - sed_start <= '1'; - if sed_edge = '1' and sed_inprogress_q = '1' then - state <= WAITACTIVE; - end if; - when WAITACTIVE => - sed_enable <= '1'; - sed_start <= '1'; - if sed_edge = '1' and sed_done_q = '0' then - state <= WAITDONE; - end if; - when WAITDONE => - sed_enable <= '1'; - sed_start <= '1'; - if (sed_edge = '1' and sed_inprogress_q = '0' and sed_done_q = '1') then - state <= INIT_1; - timer <= (0 => '1', others => '0'); - run_counter <= run_counter + 1; - if sed_error_q = '1' then - error_counter <= error_counter + 1; - end if; - end if; - end case; - - if CONTROL_IN(0) = '0' or (timer = 0 and state /= IDLE) then - sed_enable <= '0'; - state <= IDLE; - end if; - -end process; - ---------------------------------------------------------------------------- --- Status Information ---------------------------------------------------------------------------- -state_bits <= x"8" when state = IDLE else - x"1" when state = INIT_1 else - x"2" when state = INIT_2 else - x"3" when state = INIT_3 else - x"4" when state = START_1 else - x"5" when state = START_2 else - x"6" when state = WAITACTIVE else - x"7" when state = WAITDONE else --- x"9" when state = RESULT else - x"F"; - -status_i(3 downto 0) <= state_bits; -status_i(4) <= sed_clock_q; -status_i(5) <= sed_enable; -status_i(6) <= sed_start; -status_i(7) <= sed_done_q; -status_i(8) <= sed_inprogress_q; -status_i(9) <= sed_error_q; -status_i(10) <= not sed_edge; -status_i(15 downto 11) <= (others => '0'); -status_i(23 downto 16) <= std_logic_vector(run_counter)(7 downto 0); -status_i(31 downto 24) <= std_logic_vector(error_counter)(7 downto 0); - -ERROR_OUT <= sed_error; -DEBUG <= status_i when rising_edge(CLK); - ---------------------------------------------------------------------------- --- SED ---------------------------------------------------------------------------- -THE_SED : SEDFA - generic map( - CHECKALWAYS => "DISABLED", - SED_CLK_FREQ => "3.5", - DEV_DENSITY => "2100L" - ) - port map( - SEDSTDBY => '0', - SEDENABLE => sed_enable, - SEDSTART => sed_start, - SEDFRCERR => '0', - SEDERR => sed_error, - SEDDONE => sed_done, - SEDINPROG => sed_inprogress, - SEDCLKOUT => sed_clock - ); - - -end architecture; diff --git a/code/sedcheck.vhd b/code/sedcheck.vhd new file mode 120000 index 0000000..9821eee --- /dev/null +++ b/code/sedcheck.vhd @@ -0,0 +1 @@ +../../vhdlbasics/machxo3/sedcheck.vhd \ No newline at end of file diff --git a/code/uart_sctrl.vhd b/code/uart_sctrl.vhd deleted file mode 100644 index 0b1f71b..0000000 --- a/code/uart_sctrl.vhd +++ /dev/null @@ -1,198 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; --- use work.version.all; --- --- library machxo2; --- use machxo2.all; - - -entity uart_sctrl is - generic( - CLOCK_SPEED : integer := 33250000; - BAUD : integer := 115200 - - ); - port( - CLK : in std_logic; - RESET : in std_logic; - UART_RX : in std_logic; - UART_TX : out std_logic; - - DATA_OUT : out std_logic_vector(31 downto 0); - DATA_IN : in std_logic_vector(31 downto 0); - ADDR_OUT : out std_logic_vector(7 downto 0); - WRITE_OUT : out std_logic; - READ_OUT : out std_logic; - READY_IN : in std_logic; - - DEBUG : out std_logic_vector(15 downto 0) - ); -end entity; - - -architecture uart_sctrl_arch of uart_sctrl is - -constant CLK_DIV : integer := CLOCK_SPEED/BAUD; - -signal rx_data : std_logic_vector(7 downto 0); -signal tx_data : std_logic_vector(7 downto 0); -signal rx_ready : std_logic; -signal tx_send : std_logic; -signal tx_ready : std_logic; -signal bytecount : integer range 0 to 15; -type rx_state_t is (IDLE,START,START2,DO_COMMAND,DO_READ,SEND_BYTE1,SEND_BYTE2,SEND_BYTE3,SEND_TERM,SEND_FINISH); -signal state : rx_state_t; -signal addr_data : std_logic_vector(39 downto 0); -signal addr_data_tx : std_logic_vector(31 downto 0); - -signal timer : unsigned(25 downto 0) := (others => '0'); -signal timeout : std_logic := '0'; -signal cmd_wr : std_logic := '0'; -signal cmd_rd : std_logic := '0'; - -begin - - -THE_RX : entity work.uart_rec - port map( - CLK_DIV => CLK_DIV, - CLK => CLK, - RST => RESET, - RX => UART_RX, - DATA_OUT => rx_data, - DATA_WAITING => rx_ready - ); - -THE_TX : entity work.uart_trans - port map( - CLK_DIV => CLK_DIV, - CLK => CLK, - RST => RESET, - DATA_IN => tx_data, - SEND => tx_send, - READY => tx_ready, - TX => UART_TX - ); - -PROC_RX : process - variable tmp,tmp2 : unsigned(7 downto 0); -begin - wait until rising_edge(CLK); - READ_OUT <= '0'; - WRITE_OUT <= '0'; - tx_send <= '0'; - timer <= timer + 1; - case state is - when IDLE => - cmd_rd <= '0'; - cmd_wr <= '0'; - bytecount <= 9; - timer <= (others => '0'); - if rx_ready = '1' then - state <= START; - if rx_data = x"52" then - cmd_rd <= '1'; - elsif rx_data = x"57" then - cmd_wr <= '1'; - end if; - end if; - - when START => - if rx_ready = '1' then - if rx_data >= x"40" then - tmp2 := unsigned(rx_data) + x"09"; - else - tmp2 := unsigned(rx_data); - end if; - state <= START2; - end if; - - when START2 => - addr_data(bytecount*4+3 downto bytecount*4) <= std_logic_vector(tmp2(3 downto 0)); - if (bytecount = 0 and cmd_wr = '1') or (bytecount = 8 and cmd_rd = '1') then - state <= DO_COMMAND; - else - bytecount <= bytecount - 1; - state <= START; - end if; - - when DO_COMMAND => - WRITE_OUT <= cmd_wr; - READ_OUT <= cmd_rd; - if cmd_rd = '1' then - state <= DO_READ; - else - state <= IDLE; - end if; - ---Read cycle - when DO_READ => - if READY_IN = '1' then - addr_data_tx(31 downto 0) <= DATA_IN; - tx_send <= '1'; - tx_data <= x"52"; - state <= SEND_BYTE1; - bytecount <= 7; - end if; - - when SEND_BYTE1 => - tmp := x"0" & unsigned(addr_data_tx(bytecount*4+3 downto bytecount*4)); - state <= SEND_BYTE2; - - when SEND_BYTE2 => - if tmp(3 downto 0) > x"9" then - tmp := tmp + x"41" - x"0a"; - else - tmp := tmp + x"30"; - end if; - state <= SEND_BYTE3; - - - when SEND_BYTE3 => - - if tx_ready = '1' then - tx_data <= std_logic_vector(tmp); - tx_send <= '1'; - if bytecount = 0 then - state <= SEND_TERM; - else - bytecount <= bytecount - 1; - state <= SEND_BYTE1; - end if; - end if; - - - - when SEND_TERM=> - if tx_ready = '1' then - tx_send <= '1'; - tx_data <= x"0a"; - state <= SEND_FINISH; - end if; - when SEND_FINISH=> - if tx_ready = '1' then - tx_send <= '1'; - tx_data <= x"0d"; - state <= IDLE; - end if; - - end case; - - if RESET = '1' or timeout = '1' then - state <= IDLE; - timer <= (others => '0'); - end if; -end process; - -DATA_OUT <= addr_data(31 downto 0); -ADDR_OUT <= addr_data(39 downto 32); - -timeout <= timer(19); - - - -end architecture; \ No newline at end of file diff --git a/code/uart_sctrl.vhd b/code/uart_sctrl.vhd new file mode 120000 index 0000000..028a483 --- /dev/null +++ b/code/uart_sctrl.vhd @@ -0,0 +1 @@ +../../vhdlbasics/interface/uart_sctrl.vhd \ No newline at end of file diff --git a/cores/UFM_WB.v b/cores/UFM_WB.v deleted file mode 100644 index 8521e99..0000000 --- a/cores/UFM_WB.v +++ /dev/null @@ -1,1181 +0,0 @@ -// -------------------------------------------------------------------- -// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< -// -------------------------------------------------------------------- -// Copyright (c) 2001 - 2012 by Lattice Semiconductor Corporation -// -------------------------------------------------------------------- -// -// Permission: -// -// Lattice Semiconductor grants permission to use this code for use -// in synthesis for any Lattice programmable logic product. Other -// use of this code, including the selling or duplication of any -// portion is strictly prohibited. -// -// Disclaimer: -// -// This verilog source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Lattice Semiconductor provides no warranty -// regarding the use or functionality of this code. -// -// -------------------------------------------------------------------- -// -// Lattice Semiconductor Corporation -// 5555 NE Moore Court -// Hillsboro, OR 97214 -// U.S.A -// -// TEL: 1-800-Lattice (USA and Canada) -// 503-268-8001 (other locations) -// -// web: http://www.latticesemi.com/ -// email: techsupport@latticesemi.com -// -// -------------------------------------------------------------------- -// Code Revision History : -// -------------------------------------------------------------------- -// Ver: | Author |Mod. Date |Changes Made: -// V1.0 | Vijay |3/09/12 |Initial ver -// V1.1 | SHossner|6/08/12 |Added READ_DELAY parameter -// -// -------------------------------------------------------------------- - -`timescale 1ns / 100ps -`include "efb_define_def.v" -//`include "/d/jspc29/lattice/diamond/2.0/ispfpga/verilog/data/machxo2/GSR.v" -//`include "/d/jspc29/lattice/diamond/2.0/ispfpga/verilog/data/machxo2/PUR.v" - -module UFM_WB( - input clk_i - , input rst_n - , input[2:0] cmd - , input[12:0] ufm_page - , input GO - , output reg BUSY - , output reg ERR - - /***************** DPRAM port B signals *************/ - , output reg mem_clk - , output reg mem_we - , output reg mem_ce - , output reg[3:0] mem_addr - , output reg[7:0] mem_wr_data - , input [7:0] mem_rd_data - - ); - - //***************** - // For clk_i speeds less than 16.6MHz, set READ_DELAY to zero for fastest UFM read operation - // For clk_i speeds greater than 16.6MHz, set READ_DELAY as follows: - // Calculate minimum READ_DELAY as follows: - // READ_DELAY(min) = 240/PERIOD - 4 - // Where PERIOD = clk_i period in ns - // Example, for clk_i = 45MHz, PERIOD = 22.22ns and READ_DELAY = 7 (6.8 rounded up) - // - // Or choose from the following table: - // READ_DELAY | Max Clk_i - // ------------+------------- - // 0 | 16.6 Mhz - // 2 | 25.0 Mhz - // 4 | 33.3 Mhz - // 8 | 50.0 Mhz - // 12 | 66.6 Mhz - // 14 | 75.0 Mhz - - parameter READ_DELAY = 4; - //***************** - - wire ufm_enable_cmd; - wire ufm_read_cmd; - wire ufm_write_cmd; - wire ufm_erase_cmd; - wire ufm_disable_cmd; - reg ufm_enabled; - reg n_ufm_enabled; - wire ufm_repeated_read; - wire ufm_repeated_write; - - - - reg [7:0] wb_dat_i ; - reg wb_stb_i ; - wire wb_cyc_i = wb_stb_i ; - reg [7:0] wb_adr_i ; - reg wb_we_i ; - wire [7:0] wb_dat_o ; - wire wb_ack_o ; - - reg [7:0] n_wb_dat_i ; - reg n_wb_stb_i ; - reg [7:0] n_wb_adr_i ; - reg n_wb_we_i ; - reg n_busy; - reg n_error; - reg [7:0] c_state ,n_state; - reg efb_flag,n_efb_flag; - reg [7:0] sm_wr_data; - reg [3:0] sm_addr; - reg sm_ce; - reg sm_we; - reg [4:0] count; - reg sm_addr_MSB; - reg [7:0] sm_rd_data; - - - reg [7:0] n_data_frm_ufm; - reg [3:0] n_addr_ufm; - reg n_clk_en_ufm; - reg n_wr_en_ufm; - reg [4:0] n_count; - reg n_ufm_addr_MSB; - - wire [7:0] cmd_read; - wire [7:0] cmd_erase; - wire [7:0] cmd_program; - wire [7:0] cmd_select_sector; - wire [12:0] real_address; - - - PUR PUR_INST (.PUR(1'b1)); - GSR GSR_INST (.GSR(1'b1)); - - flash inst1 ( .wb_clk_i(clk_i ), // EFB with UFM enabled - .wb_rst_i(!rst_n ), - .wb_cyc_i(wb_cyc_i ), - .wb_stb_i(wb_stb_i ), - .wb_we_i(wb_we_i ), - .wb_adr_i(wb_adr_i), - .wb_dat_i(wb_dat_i ), - .wb_dat_o(wb_dat_o ), - .wb_ack_o(wb_ack_o ), - .wbc_ufm_irq( ) - ); - - // flashram inst2 ( .DataInA(sm_wr_data ), // True dual port RAM. Port A controlled by internal SM and port B controlled by user. - // .DataInB(mem_wr_data ), - // .AddressA({sm_addr_MSB,sm_addr} ), - // .AddressB({!sm_addr_MSB,mem_addr} ), - // .ClockA(clk_i ), - // .ClockB(mem_clk ), - // .ClockEnA(sm_ce ), - // .ClockEnB(mem_ce ), - // .WrA(sm_we ), - // .WrB(mem_we ), - // .ResetA(!rst_n ), - // .ResetB(!rst_n ), - // .QA(sm_rd_data ), - // .QB(mem_rd_data )); - - - always @ (*) - begin - sm_rd_data <= mem_rd_data; - mem_we <= sm_we; - mem_ce <= sm_ce; - mem_clk <= clk_i; - mem_addr <= sm_addr; - mem_wr_data <= sm_wr_data; - end - - assign ufm_enable_cmd = (cmd == 3'b100) ? 1'b1 : 1'b0 ; - assign ufm_read_cmd = ((cmd == 3'b000) || (cmd == 3'b001)) ? 1'b1 : 1'b0 ; - assign ufm_write_cmd = ((cmd == 3'b010) || (cmd == 3'b011)) ? 1'b1 : 1'b0 ; - assign ufm_erase_cmd = (cmd == 3'b111) ? 1'b1 : 1'b0 ; - assign ufm_disable_cmd = (cmd == 3'b101) ? 1'b1 : 1'b0 ; - assign ufm_repeated_read = (cmd == 3'b001) ? 1'b1 : 1'b0 ; - assign ufm_repeated_write = (cmd == 3'b011) ? 1'b1 : 1'b0 ; - - - - assign cmd_read = (ufm_page[12:10] == 3'b111)? `CMD_UFM_READ : `CMD_CFG_READ ; - assign cmd_erase = (ufm_page[12:10] == 3'b111)? `CMD_UFM_ERASE : `CMD_CFG_ERASE ; - assign cmd_program = (ufm_page[12:10] == 3'b111)? `CMD_UFM_PROGRAM : `CMD_CFG_PROGRAM ; - assign real_address= (ufm_page[12:10] == 3'b111)? {3'b000,ufm_page[9:0]} : ufm_page ; - assign cmd_select_sector = (ufm_page[12:10] == 3'b111)? 8'h40 : 8'h00 ; - - - always @ (posedge clk_i or negedge rst_n) // generate clk enable and write enable signals for port A of the DPRAM - begin - if(!rst_n) - begin - sm_ce <= 1'b0; - sm_we <= 1'b0; - end - else if (((c_state == `state58) && (n_state == `state59)) || ((c_state == `state51))) - begin - sm_ce <= 1'b0; - sm_we <= 1'b0; - end - else if ((n_state == `state58) || ((c_state == `state50) && (n_state == `state51))) - begin - sm_ce <= 1'b1; - if (ufm_read_cmd) - sm_we <= 1'b1; - else - sm_we <= 1'b0; - end - else - begin - sm_ce <= 1'b0; - sm_we <= 1'b0; - end - end - - - always @ (posedge clk_i or negedge rst_n) - begin - if(!rst_n) - begin - wb_dat_i <= 8'h00; - wb_stb_i <= 1'b0 ; - wb_adr_i <= 8'h00; - wb_we_i <= 1'b0; - end - else - begin - wb_dat_i <= n_wb_dat_i; - wb_stb_i <= #0.1 n_wb_stb_i; - wb_adr_i <= n_wb_adr_i; - wb_we_i <= n_wb_we_i ; - - end - end - - always @ (posedge clk_i or negedge rst_n) - begin - if(!rst_n) begin - c_state <= 10'h000; - BUSY <= 1'b1; - efb_flag <= 1'b0 ; - ERR <= 1'b0; - ufm_enabled <= 1'b0; - sm_wr_data <= 8'h00; - sm_addr <= 4'b0000; - count <= 4'hF; - sm_addr_MSB <= 1'b0; - end - else begin - c_state <= n_state ; - BUSY <= n_busy; - efb_flag <= n_efb_flag; - ERR <= n_error; - ufm_enabled <= n_ufm_enabled; - sm_wr_data <= n_data_frm_ufm; - sm_addr <= n_addr_ufm; - count <= n_count; - sm_addr_MSB <= n_ufm_addr_MSB; - end - end - - - - always @ (*) - begin - n_state = c_state; - n_efb_flag = 1'b0 ; - n_busy = BUSY; - n_error = ERR; - n_ufm_enabled = ufm_enabled; - n_data_frm_ufm = sm_wr_data; - n_addr_ufm = sm_addr; - n_clk_en_ufm = sm_ce; - n_wr_en_ufm = sm_we; - n_count = count; - n_ufm_addr_MSB = sm_addr_MSB; - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - case (c_state) - - `state0 : begin - n_busy = 1'b1; - n_error = 1'b0; - n_ufm_enabled = 1'b0; - n_state = `state1; // (state1 - state8)--check if UFM is busy and deassert BUSY flag if free. - end - - `state1: begin // enable WB-UFM interface - if (wb_ack_o && efb_flag) begin - n_state = `state2; - end - else begin - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGCR; - n_wb_dat_i = 8'h80; - n_wb_stb_i = `HIGH ; - n_efb_flag = 1'b1 ; - end - end - - - `state2: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state3; - end - else begin - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = `CMD_CHECK_BUSY_FLAG; - n_wb_stb_i = `HIGH ; - n_efb_flag = 1'b1 ; - end - end - - - `state3: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state4; - end - else begin - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - n_efb_flag = 1'b1 ; - end - end - - - `state4: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state5; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - end - end - - - `state5: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state6; - end - else begin - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_efb_flag = 1'b1 ; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - n_efb_flag = 1'b1 ; - end - end - - - `state6: begin // Return Back to State 2 - if (wb_ack_o && efb_flag) begin - if(wb_dat_o & (8'h80) ) - n_state = `state7; - else - n_state = `state8; - end - else begin - n_wb_we_i = `READ_STATUS; - n_wb_adr_i = `CFGRXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - n_efb_flag = 1'b1 ; - end - end - - `state7: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state1; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGCR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - n_busy = 1'b1; - end - end - - `state8: begin // - if (wb_ack_o && efb_flag) begin - n_busy = 1'b0; - n_state = `state9; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGCR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - n_busy = 1'b1; - end - end - - `state9: begin - if (GO) - begin - n_busy = 1'b1; - n_error = 1'b0; - if (ufm_enabled && ufm_write_cmd) - n_ufm_addr_MSB = !sm_addr_MSB; - n_state = `state10; - end - else - begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_busy = 1'b0; - n_error = ERR; - end - end - - - `state10: begin - if(ufm_enable_cmd) // enable UFM - n_state = `state11; - else if (ufm_enabled)begin // decode command only if UFM is already enabled - if (ufm_read_cmd) - n_state = `state35; - else if (ufm_write_cmd) - n_state = `state35; - else if (ufm_erase_cmd) - n_state = `state17; - else if (ufm_disable_cmd) - n_state = `state23; - end - else begin // set ERR if a command is sent when UFM is disabled and go to previous state and wait for GO - n_busy = 1'b0; - n_error = 1'b1; - n_state = `state9; - end - end - - `state11: begin // (state11 - state16) enable UFM - if (wb_ack_o && efb_flag) begin - n_state = `state12; - end - else begin - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGCR; - n_efb_flag = 1'b1 ; - n_wb_dat_i = 8'h80; - n_wb_stb_i = `HIGH ; - end - end - - - `state12: begin // enable configuration - if (wb_ack_o && efb_flag) begin - n_state = `state13; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = `CMD_ENABLE_INTERFACE; - n_wb_stb_i = `HIGH ; - end - end - - - `state13: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state14; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h08; - n_wb_stb_i = `HIGH ; - end - end - - - `state14: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state15; - end - else begin - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_efb_flag = 1'b1 ; - n_wb_stb_i = `HIGH ; - end - end - - - `state15: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state16; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - end - end - - - `state16: begin // - if (wb_ack_o && efb_flag) begin - n_ufm_enabled = 1'b1; - n_state = `state1; // check for busy flag after enabling UFM - end - else begin - n_efb_flag = 1'b1 ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGCR ; - n_wb_dat_i = 8'h00; - n_busy = 1'b1; - n_wb_stb_i = `HIGH ; - n_ufm_enabled = 1'b0; - end - end - - - `state17: begin // (state17- state22) erase UFM - if (wb_ack_o && efb_flag) begin - n_state = `state18; - end - else begin - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGCR; - n_efb_flag = 1'b1 ; - n_wb_dat_i = 8'h80; - n_wb_stb_i = `HIGH ; - end - end - - - `state18: begin - if (wb_ack_o && efb_flag) begin - n_state = `state19; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = cmd_erase; - n_wb_stb_i = `HIGH ; - end - end - - - `state19: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state20; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h04; //JM added for 0xE to erase CFG Flash - n_wb_stb_i = `HIGH ; - end - end - - - `state20: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state21; - end - else begin - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_efb_flag = 1'b1 ; - n_wb_stb_i = `HIGH ; - end - end - - - `state21: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state22; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - end - end - - `state22: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state1; // check for busy flag after erasing UFM - end - else begin - n_efb_flag = 1'b1 ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGCR ; - n_wb_dat_i = 8'h00; - n_busy = 1'b1; - n_wb_stb_i = `HIGH ; - end - end - - - `state23: begin // open frame // (state23 - state 32) disable UFM - if (wb_ack_o && efb_flag) begin - n_state = `state24; - end - else begin - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGCR; - n_efb_flag = 1'b1 ; - n_wb_dat_i = 8'h80; - n_wb_stb_i = `HIGH ; - end - end - - - `state24: begin // disable configuration - if (wb_ack_o && efb_flag) begin - n_state = `state25; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = `CMD_DISABLE_INTERFACE; - n_wb_stb_i = `HIGH ; - end - end - - - `state25: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state26; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - end - end - - - `state26: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state27; - end - else begin - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_efb_flag = 1'b1 ; - n_wb_stb_i = `HIGH ; - end - end - - - `state27: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state28; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - end - end - `state28: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state29; - end - else begin - n_efb_flag = 1'b1 ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGCR ; - n_wb_dat_i = 8'h00; - n_busy = 1'b1; - n_wb_stb_i = `HIGH ; - end - end - - `state29: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state30; - end - else begin - n_efb_flag = 1'b1 ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGCR ; - n_wb_dat_i = 8'h80; - n_busy = 1'b1; - n_wb_stb_i = `HIGH ; - end - end - `state30: begin // bypass command - if (wb_ack_o && efb_flag) begin - n_state = `state31; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = `CMD_BYPASS; - n_wb_stb_i = `HIGH ; - end - end - - - `state31: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state32; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = `CMD_BYPASS; - n_wb_stb_i = `HIGH ; - end - end - - - `state32: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state33; - end - else begin - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = `CMD_BYPASS; - n_efb_flag = 1'b1 ; - n_wb_stb_i = `HIGH ; - end - end - - - `state33: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state34; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = `CMD_BYPASS; - n_wb_stb_i = `HIGH ; - end - end - - - `state34: begin // - if (wb_ack_o && efb_flag) begin - n_busy = 1'b0; - n_ufm_enabled = 1'b0; - n_state = `state9; - end - else begin - n_efb_flag = 1'b1 ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGCR ; - n_wb_dat_i = 8'h00; - n_busy = 1'b1; - n_wb_stb_i = `HIGH ; - end - end - - - `state35: begin // (state35 - state60 ) UFM read/write operations - if (wb_ack_o && efb_flag) begin - if (ufm_repeated_read) - n_state = `state46; - else if (ufm_repeated_write) - n_state = `state54; - else - n_state = `state36; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGCR; - n_wb_dat_i = 8'h80; - n_wb_stb_i = `HIGH ; - end - end - - - `state36: begin // Set UFM Page Address - if (wb_ack_o && efb_flag) begin - n_state = `state37; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = `CMD_SET_ADDRESS; - n_wb_stb_i = `HIGH ; - end - end - - - `state37: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state38; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - end - end - - - `state38: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state39; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - end - end - - - `state39: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state40; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - end - end - - - `state40: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state41; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = cmd_select_sector; - n_wb_stb_i = `HIGH ; - end - end - - - `state41: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state42; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - end - end - - - `state42: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state43; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = {3'b000,real_address[12:8]}; - n_wb_stb_i = `HIGH ; - end - end - - - `state43: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state44; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = real_address[7:0]; - n_wb_stb_i = `HIGH ; - end - end - - `state44: begin // - if (wb_ack_o && efb_flag) begin - if (ufm_write_cmd) - n_state = `state53; - else - n_state = `state45; - end - else begin - n_efb_flag = 1'b1 ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGCR ; - n_wb_dat_i = 8'h00; - n_busy = 1'b1; - n_wb_stb_i = `HIGH ; - end - end - - `state45: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state46; - end - else begin - n_efb_flag = 1'b1 ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGCR ; - n_wb_dat_i = 8'h80; - n_busy = 1'b1; - n_wb_stb_i = `HIGH ; - end - end - - `state46: begin // Read Operation - if (wb_ack_o && efb_flag) begin - n_count = READ_DELAY; - n_state = `stateRD_delay; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = cmd_read; - n_wb_stb_i = `HIGH ; - end - end - - `stateRD_delay: begin - if (count == 0) - n_state = `state47; - else begin - n_count = count - 1; - end - end - - `state47: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state48; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h10; - n_wb_stb_i = `HIGH ; - end - end - - - `state48: begin // - if (wb_ack_o && efb_flag) - n_state = `state49; - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - end - end - - - `state49: begin // - if (wb_ack_o && efb_flag) begin - n_count = 5'b10000; - n_addr_ufm = 4'h0; - n_clk_en_ufm = 1'b1; - n_state = `state50; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h01; - n_wb_stb_i = `HIGH ; - end - end - - - `state50: begin // - if (wb_ack_o && efb_flag) begin - n_count = count - 1; - n_data_frm_ufm = wb_dat_o; - n_state = `state51; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `READ_DATA; - n_wb_adr_i = `CFGRXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - end - end - - `state51: begin // - n_addr_ufm = sm_addr + 1; - if (count == 0) - n_state = `state52; - else begin - n_state = `state50; - end - end - - - `state52: begin // - if (wb_ack_o && efb_flag) begin - n_ufm_addr_MSB = !sm_addr_MSB; - n_busy = 1'b0; - n_state = `state9; - end - else begin - n_wb_we_i = `WRITE; - n_efb_flag = 1'b1 ; - n_wb_adr_i = `CFGCR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - n_busy = 1'b1; - end - end - - `state53: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state54; - end - else begin - n_efb_flag = 1'b1 ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGCR ; - n_wb_dat_i = 8'h80; - n_busy = 1'b1; - n_wb_stb_i = `HIGH ; - end - end - `state54: begin // Write Operation - if (wb_ack_o && efb_flag) begin - n_state = `state55; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = cmd_program; - n_wb_stb_i = `HIGH ; - end - end - - - `state55: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state56; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - end - end - - - `state56: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state57; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - end - end - - - `state57: begin // - if (wb_ack_o && efb_flag) begin - n_count = 5'b10000; - n_addr_ufm = 4'h0; - n_clk_en_ufm = 1'b1; - n_wr_en_ufm = 1'b0; - n_state = `state58; - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = 8'h01; - n_wb_stb_i = `HIGH ; - end - end - - - `state58: begin // - n_count = count - 1; - n_state = `state59; - end - - `state59: begin // - if (wb_ack_o && efb_flag) begin - n_addr_ufm = sm_addr + 1; - if (count == 0) - n_state = `state60; - else begin - n_state = `state58; - end - end - else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGTXDR; - n_wb_dat_i = sm_rd_data; - n_wb_stb_i = `HIGH ; - end - end - - `state60: begin // - if (wb_ack_o && efb_flag) begin - n_state = `state1; - end - else begin - n_efb_flag = 1'b1 ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `CFGCR ; - n_wb_dat_i = 8'h00; - n_busy = 1'b1; - n_wb_stb_i = `HIGH ; - end - end - endcase - end - - - -endmodule - - diff --git a/cores/UFM_WB.v b/cores/UFM_WB.v new file mode 120000 index 0000000..ab1fd76 --- /dev/null +++ b/cores/UFM_WB.v @@ -0,0 +1 @@ +../../vhdlbasics/machxo3/flash/UFM_WB.v \ No newline at end of file diff --git a/cores/efb_define_def.v b/cores/efb_define_def.v deleted file mode 100644 index 148cff8..0000000 --- a/cores/efb_define_def.v +++ /dev/null @@ -1,405 +0,0 @@ -/**************************************************************************** -** -** Description: -** `define Define for PULI Utility -** -** Disclaimer: -** This source code is intended as a design reference which -** illustrates how these types of functions can be implemented. It -** is the user's responsibility to verify their design for -** consistency and functionality through the use of formal -** verification methods. Lattice Semiconductor provides no warranty -** regarding the use or functionality of this code. -** -***************************************************************************** -** -** Lattice Semiconductor Corporation -** 5555 NE Moore Court -** Hillsboro, OR 97214 -** U.S.A -** -** TEL: 1-800-Lattice (USA and Canada ) -** (503 268-8001 (other locations ) -** -** web: http://www.latticesemi.com -** email: techsupport@latticesemi.com -** -***************************************************************************** -** Change History (Latest changes on top ) -** -** Ver Date Person -** -------------------------------------------------------------------------- -** 3.0 13/9/2011 Akhilesh LBN -** -*****************************************************************************/ - - -/*********************************************************************** - * * - * EFB REGISTER SET * - * * - ***********************************************************************/ - - -`define MICO_EFB_I2C_CR 8'h40 //4a -`define MICO_EFB_I2C_CMDR 8'h41 //4b -`define MICO_EFB_I2C_BLOR 8'h42 //4c -`define MICO_EFB_I2C_BHIR 8'h43 //4d -`define MICO_EFB_I2C_TXDR 8'h44 //4e -`define MICO_EFB_I2C_SR 8'h45 //4f -`define MICO_EFB_I2C_GCDR 8'h46 //50 -`define MICO_EFB_I2C_RXDR 8'h47 //51 -`define MICO_EFB_I2C_IRQSR 8'h48 //52 -`define MICO_EFB_I2C_IRQENR 8'h49 //53 - -`define MICO_EFB_SPI_CR0 8'h54 -`define MICO_EFB_SPI_CR1 8'h55 -`define MICO_EFB_SPI_CR2 8'h56 -`define MICO_EFB_SPI_BR 8'h57 -`define MICO_EFB_SPI_CSR 8'h58 -`define MICO_EFB_SPI_TXDR 8'h59 -`define MICO_EFB_SPI_SR 8'h5a -`define MICO_EFB_SPI_RXDR 8'h5b -`define MICO_EFB_SPI_IRQSR 8'h5c -`define MICO_EFB_SPI_IRQENR 8'h5d - - -`define MICO_EFB_TIMER_CR0 8'h5E -`define MICO_EFB_TIMER_CR1 8'h5F -`define MICO_EFB_TIMER_TOP_SET_LO 8'h60 -`define MICO_EFB_TIMER_TOP_SET_HI 8'h61 -`define MICO_EFB_TIMER_OCR_SET_LO 8'h62 -`define MICO_EFB_TIMER_OCR_SET_HI 8'h63 -`define MICO_EFB_TIMER_CR2 8'h64 -`define MICO_EFB_TIMER_CNT_SR_LO 8'h65 -`define MICO_EFB_TIMER_CNT_SR_HI 8'h66 -`define MICO_EFB_TIMER_TOP_SR_LO 8'h67 -`define MICO_EFB_TIMER_TOP_SR_HI 8'h68 -`define MICO_EFB_TIMER_OCR_SR_LO 8'h69 -`define MICO_EFB_TIMER_OCR_SR_HI 8'h6A -`define MICO_EFB_TIMER_ICR_SR_LO 8'h6B -`define MICO_EFB_TIMER_ICR_SR_HI 8'h6C -`define MICO_EFB_TIMER_SR 8'h6D -`define MICO_EFB_TIMER_IRQSR 8'h6E -`define MICO_EFB_TIMER_IRQENR 8'h6F - - -/*********************************************************************** - * * - * EFB SPI CONTROLLER PHYSICAL DEVICE SPECIFIC INFORMATION * - * * - ***********************************************************************/ - - - - -// Control Register 1 Bit Masks -`define MICO_EFB_SPI_CR1_SPE 8'h80 -`define MICO_EFB_SPI_CR1_WKUPEN 8'h40 -// Control Register 2 Bit Masks -`define MICO_EFB_SPI_CR2_LSBF 8'h01 -`define MICO_EFB_SPI_CR2_CPHA 8'h02 -`define MICO_EFB_SPI_CR2_CPOL 8'h04 -`define MICO_EFB_SPI_CR2_SFSEL_NORMAL 8'h00 -`define MICO_EFB_SPI_CR2_SFSEL_LATTICE 8'h08 -`define MICO_EFB_SPI_CR2_SRME 8'h20 -`define MICO_EFB_SPI_CR2_MCSH 8'h40 -`define MICO_EFB_SPI_CR2_MSTR 8'h80 -// Status Register Bit Masks -`define MICO_EFB_SPI_SR_TIP 8'h80 -`define MICO_EFB_SPI_SR_TRDY 8'h10 -`define MICO_EFB_SPI_SR_RRDY 8'h08 -`define MICO_EFB_SPI_SR_TOE 8'h04 -`define MICO_EFB_SPI_SR_ROE 8'h02 -`define MICO_EFB_SPI_SR_MDF 8'h01 - -/*********************************************************************** - * * - * EFB I2C CONTROLLER PHYSICAL DEVICE SPECIFIC INFORMATION * - * * - ***********************************************************************/ - - - -// Control Register Bit Masks -`define MICO_EFB_I2C_CR_I2CEN 8'h80 -`define MICO_EFB_I2C_CR_GCEN 8'h40 -`define MICO_EFB_I2C_CR_WKUPEN 8'h20 -// Status Register Bit Masks -`define MICO_EFB_I2C_SR_TIP 8'h80 -`define MICO_EFB_I2C_SR_BUSY 8'h40 -`define MICO_EFB_I2C_SR_RARC 8'h20 -`define MICO_EFB_I2C_SR_SRW 8'h10 -`define MICO_EFB_I2C_SR_ARBL 8'h08 -`define MICO_EFB_I2C_SR_TRRDY 8'h04 -`define MICO_EFB_I2C_SR_TROE 8'h02 -`define MICO_EFB_I2C_SR_HGC 8'h01 -// Command Register Bit Masks -`define MICO_EFB_I2C_CMDR_STA 8'h80 -`define MICO_EFB_I2C_CMDR_STO 8'h40 -`define MICO_EFB_I2C_CMDR_RD 8'h20 -`define MICO_EFB_I2C_CMDR_WR 8'h10 -`define MICO_EFB_I2C_CMDR_NACK 8'h08 -`define MICO_EFB_I2C_CMDR_CKSDIS 8'h04 - -/*********************************************************************** - * * - * EFB I2C USER DEFINE * - * * - ***********************************************************************/ -`define MICO_EFB_I2C_TRANSMISSION_DONE 8'h00 -`define MICO_EFB_I2C_TRANSMISSION_ONGOING 8'h80 -`define MICO_EFB_I2C_FREE 8'h00 -`define MICO_EFB_I2C_BUSY 8'h40 -`define MICO_EFB_I2C_ACK_NOT_RCVD 8'h20 -`define MICO_EFB_I2C_ACK_RCVD 8'h00 -`define MICO_EFB_I2C_ARB_LOST 8'h08 -`define MICO_EFB_I2C_ARB_NOT_LOST 8'h00 -`define MICO_EFB_I2C_DATA_READY 8'h04 - -/*********************************************************************** - * * - * EFB TIMER PHYSICAL DEVICE SPECIFIC INFORMATION * - * * - ***********************************************************************/ - - - -// Control Register 0 -`define MICO_EFB_TIMER_RSTN_MASK 8'h80 -`define MICO_EFB_TIMER_GSRN_MASK 8'h40 -`define MICO_EFB_TIMER_GSRN_ENABLE 8'h40 -`define MICO_EFB_TIMER_GSRN_DISABLE 8'h00 -`define MICO_EFB_TIMER_CCLK_MASK 8'h38 -`define MICO_EFB_TIMER_CCLK_DIV_0 8'h00 -`define MICO_EFB_TIMER_CCLK_DIV_1 8'h08 -`define MICO_EFB_TIMER_CCLK_DIV_8 8'h10 -`define MICO_EFB_TIMER_CCLK_DIV_64 8'h18 -`define MICO_EFB_TIMER_CCLK_DIV_256 8'h20 -`define MICO_EFB_TIMER_CCLK_DIV_1024 8'h28 -`define MICO_EFB_TIMER_SCLK_MASK 8'h07 -`define MICO_EFB_TIMER_SCLK_CIB_RE 8'h00 -`define MICO_EFB_TIMER_SCLK_OSC_RE 8'h02 -`define MICO_EFB_TIMER_SCLK_CIB_FE 8'h04 -`define MICO_EFB_TIMER_SCLK_OSC_FE 8'h06 -// Control Register 1 -`define MICO_EFB_TIMER_TOP_SEL_MASK 8'h80 -`define MICO_EFB_TIMER_TOP_MAX 8'h00 -`define MICO_EFB_TIMER_TOP_USER_SELECT 8'h10 -`define MICO_EFB_TIMER_OC_MODE_MASK 8'h0C -`define MICO_EFB_TIMER_OC_MODE_STATIC_ZERO 8'h00 -`define MICO_EFB_TIMER_OC_MODE_TOGGLE 8'h04 -`define MICO_EFB_TIMER_OC_MODE_CLEAR 8'h08 -`define MICO_EFB_TIMER_OC_MODE_SET 8'h0C -`define MICO_EFB_TIMER_MODE_MASK 8'h03 -`define MICO_EFB_TIMER_MODE_WATCHDOG 8'h00 -`define MICO_EFB_TIMER_MODE_CTC 8'h01 -`define MICO_EFB_TIMER_MODE_FAST_PWM 8'h02 -`define MICO_EFB_TIMER_MODE_TRUE_PWM 8'h03 -// Control Register 2 -`define MICO_EFB_TIMER_OC_FORCE 8'h04 -`define MICO_EFB_TIMER_CNT_RESET 8'h02 -`define MICO_EFB_TIMER_CNT_PAUSE 8'h01 -// Status Register -`define MICO_EFB_TIMER_SR_OVERFLOW 8'h01 -`define MICO_EFB_TIMER_SR_COMPARE_MATCH 8'h02 -`define MICO_EFB_TIMER_SR_CAPTURE 8'h04 - - - -`define CFGCR 8'h70 -`define CFGTXDR 8'h71 -`define CFGSR 8'h72 -`define CFGRXDR 8'h73 -`define CFGIRQ 8'h74 -`define CFGIRQEN 8'h75 - -/*********************************************************************** - * * - * PULI SPECIFIC * - * * - ***********************************************************************/ - - `define ALL_ZERO 8'h00 - `define READ 1'b0 - `define READ 1'b0 - `define HIGH 1'b1 - `define WRITE 1'b1 - `define LOW 1'b0 - `define READ_STATUS 1'b0 - `define READ_DATA 1'b0 - -/*********************************************************************** - * * - * State Machine Variables * - * * - ***********************************************************************/ - -`define CMD_CHECK_BUSY_FLAG 8'hF0 -`define CMD_BYPASS 8'hFF -`define CMD_ENABLE_INTERFACE 8'h74 -`define CMD_DISABLE_INTERFACE 8'h26 -`define CMD_SET_ADDRESS 8'hB4 - -`define CMD_UFM_READ 8'hCA -`define CMD_UFM_ERASE 8'hCB -`define CMD_UFM_PROGRAM 8'hC9 - -`define CMD_CFG_READ 8'h73 -`define CMD_CFG_ERASE 8'h0E -`define CMD_CFG_PROGRAM 8'h70 - - - -`define state0 7'd00 -`define state1 7'd01 -`define state2 7'd02 -`define state3 7'd03 -`define state4 7'd04 -`define state5 7'd05 -`define state6 7'd06 -`define state7 7'd07 -`define state8 7'd08 -`define state9 7'd09 -`define state10 7'd10 -`define state11 7'd11 -`define state12 7'd12 -`define state13 7'd13 -`define state14 7'd14 -`define state15 7'd15 -`define state16 7'd16 -`define state17 7'd17 -`define state18 7'd18 -`define state19 7'd19 -`define state20 7'd20 -`define state21 7'd21 -`define state22 7'd22 -`define state23 7'd23 -`define state24 7'd24 -`define state25 7'd25 -`define state26 7'd26 -`define state27 7'd27 -`define state28 7'd28 -`define state29 7'd29 -`define state30 7'd30 -`define state31 7'd31 -`define state32 7'd32 -`define state33 7'd33 -`define state34 7'd34 -`define state35 7'd35 -`define state36 7'd36 -`define state37 7'd37 -`define state38 7'd38 -`define state39 7'd39 -`define state40 7'd40 -`define state41 7'd41 -`define state42 7'd42 -`define state43 7'd43 -`define state44 7'd44 -`define state45 7'd45 -`define state46 7'd46 -`define state47 7'd47 -`define state48 7'd48 -`define state49 7'd49 -`define state50 7'd50 -`define state51 7'd51 -`define state52 7'd52 -`define state53 7'd53 -`define state54 7'd54 -`define state55 7'd55 -`define state56 7'd56 -`define state57 7'd57 -`define state58 7'd58 -`define state59 7'd59 -`define state60 7'd60 -`define stateRD_delay 7'd61 -`define state62 7'd62 -`define state63 7'd63 -`define state64 7'd64 -`define state65 7'd65 -`define state66 7'd66 -`define state67 7'd67 -`define state68 7'd68 -`define state69 7'd69 -`define state70 7'd70 -`define state71 7'd71 -`define state72 7'd72 -`define state73 7'd73 -`define state74 7'd74 -`define state75 7'd75 -`define state76 7'd76 -`define state77 7'd77 -`define state78 7'd78 -`define state79 7'd79 -`define state80 7'd80 -`define state81 7'd81 -`define state82 7'd82 -`define state83 7'd83 -`define state84 7'd84 -`define state85 7'd85 -`define state86 7'd86 -`define state87 7'd87 -`define state88 7'd88 -`define state89 7'd89 -`define state90 7'd90 -`define state91 7'd91 -`define state92 7'd92 -`define state93 7'd93 -`define state94 7'd94 -`define state95 7'd95 -`define state96 7'd96 -`define state97 7'd97 -`define state98 7'd98 -`define state99 7'd99 -`define state100 7'd100 -`define state101 7'd101 -`define state102 7'd102 -`define state103 7'd103 -`define state104 7'd104 -`define state105 7'd105 -`define state106 7'd106 -`define state107 7'd107 -`define state108 7'd108 -`define state109 7'd109 -`define state110 7'd110 -`define state111 7'd111 -`define state112 7'd112 -`define state113 7'd113 -`define state114 7'd114 -`define state115 7'd115 -`define state116 7'd116 -`define state117 7'd117 -`define state118 7'd118 -`define state119 7'd119 -`define state120 7'd120 -`define state121 7'd121 -`define state122 7'd122 -`define state123 7'd123 -`define state124 7'd124 -`define state125 7'd125 -`define state126 7'd126 -`define state127 7'd127 - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/cores/efb_define_def.v b/cores/efb_define_def.v new file mode 120000 index 0000000..18c8d31 --- /dev/null +++ b/cores/efb_define_def.v @@ -0,0 +1 @@ +../../vhdlbasics/machxo3/flash/efb_define_def.v \ No newline at end of file diff --git a/cores/flash.vhd b/cores/flash.vhd deleted file mode 100644 index c967b9e..0000000 --- a/cores/flash.vhd +++ /dev/null @@ -1,202 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4 --- Module Version: 1.2 ---/opt/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.33 -ufm -ufm_ebr 629 -mem_size 10 -ufm_0 -wb -dev 2100 - --- Thu Sep 29 10:00:20 2016 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library MACHXO3L; -use MACHXO3L.components.all; --- synopsys translate_on - -entity flash is - port ( - wb_clk_i: in std_logic; - wb_rst_i: in std_logic; - wb_cyc_i: in std_logic; - wb_stb_i: in std_logic; - wb_we_i: in std_logic; - wb_adr_i: in std_logic_vector(7 downto 0); - wb_dat_i: in std_logic_vector(7 downto 0); - wb_dat_o: out std_logic_vector(7 downto 0); - wb_ack_o: out std_logic; - wbc_ufm_irq: out std_logic); -end flash; - -architecture Structure of flash is - - -- internal signal declarations - signal scuba_vhi: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component EFB - generic (EFB_I2C1 : in String; EFB_I2C2 : in String; - EFB_SPI : in String; EFB_TC : in String; - EFB_TC_PORTMODE : in String; EFB_UFM : in String; - EFB_WB_CLK_FREQ : in String; DEV_DENSITY : in String; - UFM_INIT_PAGES : in Integer; - UFM_INIT_START_PAGE : in Integer; - UFM_INIT_ALL_ZEROS : in String; - UFM_INIT_FILE_NAME : in String; - UFM_INIT_FILE_FORMAT : in String; - I2C1_ADDRESSING : in String; I2C2_ADDRESSING : in String; - I2C1_SLAVE_ADDR : in String; I2C2_SLAVE_ADDR : in String; - I2C1_BUS_PERF : in String; I2C2_BUS_PERF : in String; - I2C1_CLK_DIVIDER : in Integer; - I2C2_CLK_DIVIDER : in Integer; I2C1_GEN_CALL : in String; - I2C2_GEN_CALL : in String; I2C1_WAKEUP : in String; - I2C2_WAKEUP : in String; SPI_MODE : in String; - SPI_CLK_DIVIDER : in Integer; SPI_LSB_FIRST : in String; - SPI_CLK_INV : in String; SPI_PHASE_ADJ : in String; - SPI_SLAVE_HANDSHAKE : in String; - SPI_INTR_TXRDY : in String; SPI_INTR_RXRDY : in String; - SPI_INTR_TXOVR : in String; SPI_INTR_RXOVR : in String; - SPI_WAKEUP : in String; TC_MODE : in String; - TC_SCLK_SEL : in String; TC_CCLK_SEL : in Integer; - GSR : in String; TC_TOP_SET : in Integer; - TC_OCR_SET : in Integer; TC_OC_MODE : in String; - TC_RESETN : in String; TC_TOP_SEL : in String; - TC_OV_INT : in String; TC_OCR_INT : in String; - TC_ICR_INT : in String; TC_OVERFLOW : in String; - TC_ICAPTURE : in String); - port (WBCLKI: in std_logic; WBRSTI: in std_logic; - WBCYCI: in std_logic; WBSTBI: in std_logic; - WBWEI: in std_logic; WBADRI7: in std_logic; - WBADRI6: in std_logic; WBADRI5: in std_logic; - WBADRI4: in std_logic; WBADRI3: in std_logic; - WBADRI2: in std_logic; WBADRI1: in std_logic; - WBADRI0: in std_logic; WBDATI7: in std_logic; - WBDATI6: in std_logic; WBDATI5: in std_logic; - WBDATI4: in std_logic; WBDATI3: in std_logic; - WBDATI2: in std_logic; WBDATI1: in std_logic; - WBDATI0: in std_logic; PLL0DATI7: in std_logic; - PLL0DATI6: in std_logic; PLL0DATI5: in std_logic; - PLL0DATI4: in std_logic; PLL0DATI3: in std_logic; - PLL0DATI2: in std_logic; PLL0DATI1: in std_logic; - PLL0DATI0: in std_logic; PLL0ACKI: in std_logic; - PLL1DATI7: in std_logic; PLL1DATI6: in std_logic; - PLL1DATI5: in std_logic; PLL1DATI4: in std_logic; - PLL1DATI3: in std_logic; PLL1DATI2: in std_logic; - PLL1DATI1: in std_logic; PLL1DATI0: in std_logic; - PLL1ACKI: in std_logic; I2C1SCLI: in std_logic; - I2C1SDAI: in std_logic; I2C2SCLI: in std_logic; - I2C2SDAI: in std_logic; SPISCKI: in std_logic; - SPIMISOI: in std_logic; SPIMOSII: in std_logic; - SPISCSN: in std_logic; TCCLKI: in std_logic; - TCRSTN: in std_logic; TCIC: in std_logic; - UFMSN: in std_logic; WBDATO7: out std_logic; - WBDATO6: out std_logic; WBDATO5: out std_logic; - WBDATO4: out std_logic; WBDATO3: out std_logic; - WBDATO2: out std_logic; WBDATO1: out std_logic; - WBDATO0: out std_logic; WBACKO: out std_logic; - PLLCLKO: out std_logic; PLLRSTO: out std_logic; - PLL0STBO: out std_logic; PLL1STBO: out std_logic; - PLLWEO: out std_logic; PLLADRO4: out std_logic; - PLLADRO3: out std_logic; PLLADRO2: out std_logic; - PLLADRO1: out std_logic; PLLADRO0: out std_logic; - PLLDATO7: out std_logic; PLLDATO6: out std_logic; - PLLDATO5: out std_logic; PLLDATO4: out std_logic; - PLLDATO3: out std_logic; PLLDATO2: out std_logic; - PLLDATO1: out std_logic; PLLDATO0: out std_logic; - I2C1SCLO: out std_logic; I2C1SCLOEN: out std_logic; - I2C1SDAO: out std_logic; I2C1SDAOEN: out std_logic; - I2C2SCLO: out std_logic; I2C2SCLOEN: out std_logic; - I2C2SDAO: out std_logic; I2C2SDAOEN: out std_logic; - I2C1IRQO: out std_logic; I2C2IRQO: out std_logic; - SPISCKO: out std_logic; SPISCKEN: out std_logic; - SPIMISOO: out std_logic; SPIMISOEN: out std_logic; - SPIMOSIO: out std_logic; SPIMOSIEN: out std_logic; - SPIMCSN7: out std_logic; SPIMCSN6: out std_logic; - SPIMCSN5: out std_logic; SPIMCSN4: out std_logic; - SPIMCSN3: out std_logic; SPIMCSN2: out std_logic; - SPIMCSN1: out std_logic; SPIMCSN0: out std_logic; - SPICSNEN: out std_logic; SPIIRQO: out std_logic; - TCINT: out std_logic; TCOC: out std_logic; - WBCUFMIRQ: out std_logic; CFGWAKE: out std_logic; - CFGSTDBY: out std_logic); - end component; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - EFBInst_0: EFB - generic map (UFM_INIT_FILE_FORMAT=> "HEX", UFM_INIT_FILE_NAME=> "NONE", - UFM_INIT_ALL_ZEROS=> "ENABLED", UFM_INIT_START_PAGE=> 0, - UFM_INIT_PAGES=> 0, DEV_DENSITY=> "2100L", EFB_UFM=> "ENABLED", - TC_ICAPTURE=> "DISABLED", TC_OVERFLOW=> "DISABLED", TC_ICR_INT=> "OFF", - TC_OCR_INT=> "OFF", TC_OV_INT=> "OFF", TC_TOP_SEL=> "OFF", - TC_RESETN=> "ENABLED", TC_OC_MODE=> "TOGGLE", TC_OCR_SET=> 32767, - TC_TOP_SET=> 65535, GSR=> "ENABLED", TC_CCLK_SEL=> 1, TC_MODE=> "CTCM", - TC_SCLK_SEL=> "PCLOCK", EFB_TC_PORTMODE=> "WB", EFB_TC=> "DISABLED", - SPI_WAKEUP=> "DISABLED", SPI_INTR_RXOVR=> "DISABLED", - SPI_INTR_TXOVR=> "DISABLED", SPI_INTR_RXRDY=> "DISABLED", - SPI_INTR_TXRDY=> "DISABLED", SPI_SLAVE_HANDSHAKE=> "DISABLED", - SPI_PHASE_ADJ=> "DISABLED", SPI_CLK_INV=> "DISABLED", - SPI_LSB_FIRST=> "DISABLED", SPI_CLK_DIVIDER=> 1, SPI_MODE=> "MASTER", - EFB_SPI=> "DISABLED", I2C2_WAKEUP=> "DISABLED", I2C2_GEN_CALL=> "DISABLED", - I2C2_CLK_DIVIDER=> 1, I2C2_BUS_PERF=> "100kHz", I2C2_SLAVE_ADDR=> "0b1000010", - I2C2_ADDRESSING=> "7BIT", EFB_I2C2=> "DISABLED", I2C1_WAKEUP=> "DISABLED", - I2C1_GEN_CALL=> "DISABLED", I2C1_CLK_DIVIDER=> 1, I2C1_BUS_PERF=> "100kHz", - I2C1_SLAVE_ADDR=> "0b1000001", I2C1_ADDRESSING=> "7BIT", - EFB_I2C1=> "DISABLED", EFB_WB_CLK_FREQ=> "33.3") - port map (WBCLKI=>wb_clk_i, WBRSTI=>wb_rst_i, WBCYCI=>wb_cyc_i, - WBSTBI=>wb_stb_i, WBWEI=>wb_we_i, WBADRI7=>wb_adr_i(7), - WBADRI6=>wb_adr_i(6), WBADRI5=>wb_adr_i(5), - WBADRI4=>wb_adr_i(4), WBADRI3=>wb_adr_i(3), - WBADRI2=>wb_adr_i(2), WBADRI1=>wb_adr_i(1), - WBADRI0=>wb_adr_i(0), WBDATI7=>wb_dat_i(7), - WBDATI6=>wb_dat_i(6), WBDATI5=>wb_dat_i(5), - WBDATI4=>wb_dat_i(4), WBDATI3=>wb_dat_i(3), - WBDATI2=>wb_dat_i(2), WBDATI1=>wb_dat_i(1), - WBDATI0=>wb_dat_i(0), PLL0DATI7=>scuba_vlo, - PLL0DATI6=>scuba_vlo, PLL0DATI5=>scuba_vlo, - PLL0DATI4=>scuba_vlo, PLL0DATI3=>scuba_vlo, - PLL0DATI2=>scuba_vlo, PLL0DATI1=>scuba_vlo, - PLL0DATI0=>scuba_vlo, PLL0ACKI=>scuba_vlo, - PLL1DATI7=>scuba_vlo, PLL1DATI6=>scuba_vlo, - PLL1DATI5=>scuba_vlo, PLL1DATI4=>scuba_vlo, - PLL1DATI3=>scuba_vlo, PLL1DATI2=>scuba_vlo, - PLL1DATI1=>scuba_vlo, PLL1DATI0=>scuba_vlo, - PLL1ACKI=>scuba_vlo, I2C1SCLI=>scuba_vlo, - I2C1SDAI=>scuba_vlo, I2C2SCLI=>scuba_vlo, - I2C2SDAI=>scuba_vlo, SPISCKI=>scuba_vlo, SPIMISOI=>scuba_vlo, - SPIMOSII=>scuba_vlo, SPISCSN=>scuba_vlo, TCCLKI=>scuba_vlo, - TCRSTN=>scuba_vlo, TCIC=>scuba_vlo, UFMSN=>scuba_vhi, - WBDATO7=>wb_dat_o(7), WBDATO6=>wb_dat_o(6), - WBDATO5=>wb_dat_o(5), WBDATO4=>wb_dat_o(4), - WBDATO3=>wb_dat_o(3), WBDATO2=>wb_dat_o(2), - WBDATO1=>wb_dat_o(1), WBDATO0=>wb_dat_o(0), WBACKO=>wb_ack_o, - PLLCLKO=>open, PLLRSTO=>open, PLL0STBO=>open, PLL1STBO=>open, - PLLWEO=>open, PLLADRO4=>open, PLLADRO3=>open, PLLADRO2=>open, - PLLADRO1=>open, PLLADRO0=>open, PLLDATO7=>open, - PLLDATO6=>open, PLLDATO5=>open, PLLDATO4=>open, - PLLDATO3=>open, PLLDATO2=>open, PLLDATO1=>open, - PLLDATO0=>open, I2C1SCLO=>open, I2C1SCLOEN=>open, - I2C1SDAO=>open, I2C1SDAOEN=>open, I2C2SCLO=>open, - I2C2SCLOEN=>open, I2C2SDAO=>open, I2C2SDAOEN=>open, - I2C1IRQO=>open, I2C2IRQO=>open, SPISCKO=>open, - SPISCKEN=>open, SPIMISOO=>open, SPIMISOEN=>open, - SPIMOSIO=>open, SPIMOSIEN=>open, SPIMCSN7=>open, - SPIMCSN6=>open, SPIMCSN5=>open, SPIMCSN4=>open, - SPIMCSN3=>open, SPIMCSN2=>open, SPIMCSN1=>open, - SPIMCSN0=>open, SPICSNEN=>open, SPIIRQO=>open, TCINT=>open, - TCOC=>open, WBCUFMIRQ=>wbc_ufm_irq, CFGWAKE=>open, - CFGSTDBY=>open); - -end Structure; diff --git a/cores/flash.vhd b/cores/flash.vhd new file mode 120000 index 0000000..607d366 --- /dev/null +++ b/cores/flash.vhd @@ -0,0 +1 @@ +../../vhdlbasics/machxo3/flash/flash.vhd \ No newline at end of file diff --git a/cores/flashram.vhd b/cores/flashram.vhd deleted file mode 100644 index 2592fb0..0000000 --- a/cores/flashram.vhd +++ /dev/null @@ -1,196 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 --- Module Version: 7.5 ---/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n flashram -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo3c00f -type bram -wp 11 -rp 1010 -data_width 8 -rdata_width 8 -num_rows 16 -cascade 11 -mem_init0 -writemodeA NORMAL -writemodeB NORMAL - --- Mon Apr 25 12:05:43 2016 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library MACHXO3L; -use MACHXO3L.components.all; --- synopsys translate_on - -entity flashram is - port ( - DataInA: in std_logic_vector(7 downto 0); - DataInB: in std_logic_vector(7 downto 0); - AddressA: in std_logic_vector(3 downto 0); - AddressB: in std_logic_vector(3 downto 0); - ClockA: in std_logic; - ClockB: in std_logic; - ClockEnA: in std_logic; - ClockEnB: in std_logic; - WrA: in std_logic; - WrB: in std_logic; - ResetA: in std_logic; - ResetB: in std_logic; - QA: out std_logic_vector(7 downto 0); - QB: out std_logic_vector(7 downto 0)); -end flashram; - -architecture Structure of flashram is - - -- internal signal declarations - signal scuba_vhi: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component VHI - port (Z: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - component DP8KC - generic (INIT_DATA : in String; INITVAL_1F : in String; - INITVAL_1E : in String; INITVAL_1D : in String; - INITVAL_1C : in String; INITVAL_1B : in String; - INITVAL_1A : in String; INITVAL_19 : in String; - INITVAL_18 : in String; INITVAL_17 : in String; - INITVAL_16 : in String; INITVAL_15 : in String; - INITVAL_14 : in String; INITVAL_13 : in String; - INITVAL_12 : in String; INITVAL_11 : in String; - INITVAL_10 : in String; INITVAL_0F : in String; - INITVAL_0E : in String; INITVAL_0D : in String; - INITVAL_0C : in String; INITVAL_0B : in String; - INITVAL_0A : in String; INITVAL_09 : in String; - INITVAL_08 : in String; INITVAL_07 : in String; - INITVAL_06 : in String; INITVAL_05 : in String; - INITVAL_04 : in String; INITVAL_03 : in String; - INITVAL_02 : in String; INITVAL_01 : in String; - INITVAL_00 : in String; ASYNC_RESET_RELEASE : in String; - RESETMODE : in String; GSR : in String; - WRITEMODE_B : in String; WRITEMODE_A : in String; - CSDECODE_B : in String; CSDECODE_A : in String; - REGMODE_B : in String; REGMODE_A : in String; - DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); - port (DIA8: in std_logic; DIA7: in std_logic; - DIA6: in std_logic; DIA5: in std_logic; - DIA4: in std_logic; DIA3: in std_logic; - DIA2: in std_logic; DIA1: in std_logic; - DIA0: in std_logic; ADA12: in std_logic; - ADA11: in std_logic; ADA10: in std_logic; - ADA9: in std_logic; ADA8: in std_logic; - ADA7: in std_logic; ADA6: in std_logic; - ADA5: in std_logic; ADA4: in std_logic; - ADA3: in std_logic; ADA2: in std_logic; - ADA1: in std_logic; ADA0: in std_logic; CEA: in std_logic; - OCEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; - CSA2: in std_logic; CSA1: in std_logic; - CSA0: in std_logic; RSTA: in std_logic; - DIB8: in std_logic; DIB7: in std_logic; - DIB6: in std_logic; DIB5: in std_logic; - DIB4: in std_logic; DIB3: in std_logic; - DIB2: in std_logic; DIB1: in std_logic; - DIB0: in std_logic; ADB12: in std_logic; - ADB11: in std_logic; ADB10: in std_logic; - ADB9: in std_logic; ADB8: in std_logic; - ADB7: in std_logic; ADB6: in std_logic; - ADB5: in std_logic; ADB4: in std_logic; - ADB3: in std_logic; ADB2: in std_logic; - ADB1: in std_logic; ADB0: in std_logic; CEB: in std_logic; - OCEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; - CSB2: in std_logic; CSB1: in std_logic; - CSB0: in std_logic; RSTB: in std_logic; - DOA8: out std_logic; DOA7: out std_logic; - DOA6: out std_logic; DOA5: out std_logic; - DOA4: out std_logic; DOA3: out std_logic; - DOA2: out std_logic; DOA1: out std_logic; - DOA0: out std_logic; DOB8: out std_logic; - DOB7: out std_logic; DOB6: out std_logic; - DOB5: out std_logic; DOB4: out std_logic; - DOB3: out std_logic; DOB2: out std_logic; - DOB1: out std_logic; DOB0: out std_logic); - end component; - attribute MEM_LPC_FILE : string; - attribute MEM_INIT_FILE : string; - attribute MEM_LPC_FILE of flashram_0_0_0_0 : label is "flashram.lpc"; - attribute MEM_INIT_FILE of flashram_0_0_0_0 : label is "INIT_ALL_0s"; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); - - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - flashram_0_0_0_0: DP8KC - generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", - INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", - CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", - WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", - REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, - DATA_WIDTH_A=> 9) - port map (DIA8=>scuba_vlo, DIA7=>DataInA(7), DIA6=>DataInA(6), - DIA5=>DataInA(5), DIA4=>DataInA(4), DIA3=>DataInA(3), - DIA2=>DataInA(2), DIA1=>DataInA(1), DIA0=>DataInA(0), - ADA12=>scuba_vlo, ADA11=>scuba_vlo, ADA10=>scuba_vlo, - ADA9=>scuba_vlo, ADA8=>scuba_vlo, ADA7=>scuba_vlo, - ADA6=>AddressA(3), ADA5=>AddressA(2), ADA4=>AddressA(1), - ADA3=>AddressA(0), ADA2=>scuba_vlo, ADA1=>scuba_vlo, - ADA0=>scuba_vhi, CEA=>ClockEnA, OCEA=>ClockEnA, CLKA=>ClockA, - WEA=>WrA, CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, - RSTA=>ResetA, DIB8=>scuba_vlo, DIB7=>DataInB(7), - DIB6=>DataInB(6), DIB5=>DataInB(5), DIB4=>DataInB(4), - DIB3=>DataInB(3), DIB2=>DataInB(2), DIB1=>DataInB(1), - DIB0=>DataInB(0), ADB12=>scuba_vlo, ADB11=>scuba_vlo, - ADB10=>scuba_vlo, ADB9=>scuba_vlo, ADB8=>scuba_vlo, - ADB7=>scuba_vlo, ADB6=>AddressB(3), ADB5=>AddressB(2), - ADB4=>AddressB(1), ADB3=>AddressB(0), ADB2=>scuba_vlo, - ADB1=>scuba_vlo, ADB0=>scuba_vhi, CEB=>ClockEnB, - OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB2=>scuba_vlo, - CSB1=>scuba_vlo, CSB0=>scuba_vlo, RSTB=>ResetB, DOA8=>open, - DOA7=>QA(7), DOA6=>QA(6), DOA5=>QA(5), DOA4=>QA(4), - DOA3=>QA(3), DOA2=>QA(2), DOA1=>QA(1), DOA0=>QA(0), - DOB8=>open, DOB7=>QB(7), DOB6=>QB(6), DOB5=>QB(5), - DOB4=>QB(4), DOB3=>QB(3), DOB2=>QB(2), DOB1=>QB(1), - DOB0=>QB(0)); - -end Structure; - --- synopsys translate_off -library MACHXO3L; -configuration Structure_CON of flashram is - for Structure - for all:VHI use entity MACHXO3L.VHI(V); end for; - for all:VLO use entity MACHXO3L.VLO(V); end for; - for all:DP8KC use entity MACHXO3L.DP8KC(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/cores/flashram.vhd b/cores/flashram.vhd new file mode 120000 index 0000000..a9739ce --- /dev/null +++ b/cores/flashram.vhd @@ -0,0 +1 @@ +../../vhdlbasics/machxo3/flash/flashram.vhd \ No newline at end of file