From: hadeshyp <hadeshyp>
Date: Wed, 3 Oct 2012 07:27:40 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~33
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a8daf48f260a41efa0862bc5e9113d76d7b02844;p=trbnet.git

*** empty log message ***
---

diff --git a/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd b/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd
index 0a2344d..7f1ca21 100644
--- a/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd
@@ -672,7 +672,7 @@ end process SELECTOR_PROC;
 --		
 --	end if;
 --end process SELECTOR_PROC;
--- ************
+-- ***********
 
 end trb_net16_gbe_protocol_selector;
 
diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd
index 07ef1d1..17d1421 100644
--- a/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd
@@ -137,8 +137,8 @@ signal fifo_rd_q               : std_logic;
 
 signal too_much_data           : std_logic;
 
-signal rx_fifo_data             : std_logic_vector(8 downto 0);
-
+signal rx_fifo_data            : std_logic_vector(8 downto 0);
+signal tx_fifo_data            : std_logic_vector(17 downto 0);
 
 begin
 
@@ -150,7 +150,7 @@ receive_fifo : fifo_2048x8x16
 	RPReset          => RESET,
     WrClock          => CLK,
 	RdClock          => CLK,
-    Data             => rx_fifo_data, --PS_DATA_IN,
+    Data             => rx_fifo_data,
     WrEn             => rx_fifo_wr,
     RdEn             => rx_fifo_rd,
     Q                => rx_fifo_q,
@@ -182,6 +182,15 @@ begin
 --			rx_fifo_rd <= '1';
 --		else
 --			rx_fifo_rd <= '0';
+--		end if;
+
+--		GSC_INIT_DATA_OUT(7 downto 0)  <= rx_fifo_q(16 downto 9);
+--		GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0);
+--		
+--		if (GSC_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB) or (dissect_current_state = WAIT_FOR_HUB) then
+--			gsc_init_dataready <= '1';
+--		else
+--			gsc_init_dataready <= '0';
 --		end if;
 		
 		rx_fifo_data <= PS_DATA_IN;
@@ -215,45 +224,58 @@ transmit_fifo : fifo_65536x18x9
 	RPReset           => tx_fifo_reset,
     WrClock           => CLK,
 	RdClock           => CLK,
-    Data(7 downto 0)  => GSC_REPLY_DATA_IN(15 downto 8),
-    Data(8)           => '0',
-    Data(16 downto 9) => GSC_REPLY_DATA_IN(7 downto 0),
-    Data(17)          => '0',
+	Data              => tx_fifo_data,
     WrEn              => tx_fifo_wr,
     RdEn              => tx_fifo_rd,
     Q                 => tx_fifo_q,
     Full              => tx_full,
     Empty             => tx_empty
   );
+  
+tx_fifo_data(7 downto 0)  <= GSC_REPLY_DATA_IN(15 downto 8);
+tx_fifo_data(8)           <= '0';
+tx_fifo_data(16 downto 9) <= GSC_REPLY_DATA_IN(7 downto 0);
+tx_fifo_data(17)          <= '0';
 
+tx_fifo_wr              <= '1' when (GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1') else '0';
 tx_fifo_reset           <= '1' when (RESET = '1') or (too_much_data = '1' and dissect_current_state = CLEANUP) else '0';
-tx_fifo_wr              <= '1' when GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1' else '0';
 tx_fifo_rd              <= '1' when TC_RD_EN_IN = '1' and dissect_current_state = LOAD_FRAME and (tx_frame_loaded /= g_MAX_FRAME_SIZE) else '0';
 
+--TX_FIFO_SYNC_PROC : process(CLK)
+--begin
+--	if rising_edge(CLK) then
+--		if (GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1') then
+--			tx_fifo_wr <= '1';
+--		else
+--			tx_fifo_wr <= '0';
+--		end if;		
+--	end if;
+--end process TX_FIFO_SYNC_PROC;
+
 TC_DATA_PROC : process(dissect_current_state, tx_loaded_ctr, tx_data_ctr, tx_frame_loaded, g_MAX_FRAME_SIZE)
 begin
-	if (dissect_current_state = LOAD_FRAME) then
-	
-		TC_DATA_OUT(7 downto 0) <= tx_fifo_q(7 downto 0);
-		
-		if (tx_loaded_ctr = tx_data_ctr or tx_frame_loaded = g_MAX_FRAME_SIZE - x"1") then
-			TC_DATA_OUT(8) <= '1';
-		else
-			TC_DATA_OUT(8) <= '0';
-		end if;
+		if (dissect_current_state = LOAD_FRAME) then
 		
-	elsif (dissect_current_state = LOAD_ACK) then
-	
-		TC_DATA_OUT(7 downto 0) <= tx_loaded_ctr(7 downto 0);
+			TC_DATA_OUT(7 downto 0) <= tx_fifo_q(7 downto 0);
+			
+			if (tx_loaded_ctr = tx_data_ctr or tx_frame_loaded = g_MAX_FRAME_SIZE - x"1") then
+				TC_DATA_OUT(8) <= '1';
+			else
+				TC_DATA_OUT(8) <= '0';
+			end if;
+			
+		elsif (dissect_current_state = LOAD_ACK) then
 		
-		if (tx_loaded_ctr = x"0010" + x"1") then
-			TC_DATA_OUT(8) <= '1';
+			TC_DATA_OUT(7 downto 0) <= tx_loaded_ctr(7 downto 0);
+			
+			if (tx_loaded_ctr = x"0010" + x"1") then
+				TC_DATA_OUT(8) <= '1';
+			else
+				TC_DATA_OUT(8) <= '0';
+			end if;
 		else
-			TC_DATA_OUT(8) <= '0';
+			TC_DATA_OUT <= (others => '0');
 		end if;
-	else
-		TC_DATA_OUT <= (others => '0');
-	end if;
 end process TC_DATA_PROC;
 
 GSC_REPLY_READ_OUT      <= gsc_reply_read;
diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd
index ebe1370..3f1cf11 100644
--- a/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd
+++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd
@@ -114,7 +114,7 @@ signal pause    : integer range 0 to 28;
 signal stat_data_temp           : std_logic_vector(31 downto 0);
 
 begin
-pause <= 10 when g_SIMULATE = 1 else 20;
+pause <= 10 when g_SIMULATE = 1 else 28;
 
 
 mem : statts_mem