From: Jan Michel <j.michel@gsi.de>
Date: Fri, 10 Aug 2018 09:52:02 +0000 (+0200)
Subject: add edge detect to trigger logic
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a8fa565aeda5f9e9d9ac889240958c6bf953199d;p=trb3.git

add edge detect to trigger logic
---

diff --git a/base/code/input_to_trigger_logic_record.vhd b/base/code/input_to_trigger_logic_record.vhd
index 9d53093..8ff21b5 100644
--- a/base/code/input_to_trigger_logic_record.vhd
+++ b/base/code/input_to_trigger_logic_record.vhd
@@ -38,6 +38,7 @@ signal inp_shift    : inp_t := (others => (others => '0'));
 signal inp_inv      : std_logic_vector(INPUTS-1 downto 0) := (others => '0');  
 signal inp_long     : std_logic_vector(INPUTS-1 downto 0) := (others => '0');  
 signal inp_verylong : std_logic_vector(INPUTS-1 downto 0) := (others => '0');  
+signal inp_edge     : std_logic_vector(INPUTS-1 downto 0) := (others => '0');  
 
 signal output_i     : std_logic_vector(OUTPUTS-1 downto 0) := (others => '0');
 signal out_reg      : std_logic_vector(OUTPUTS-1 downto 0) := (others => '0');
@@ -49,8 +50,9 @@ signal multiplicity_trigger : std_logic := '0';
 signal multiplicity_enable  : std_logic_vector(31 downto 0);
 
 signal set_output_coin, set_output_mult, set_output_simplecoin : std_logic_vector(7 downto 0);
+signal edge_enable  : std_logic_vector(7 downto 0) := (others => '0');
 
-type coincidence_arr is array(0 to 16) of integer range 0 to 31;
+type coincidence_arr is array(0 to 16) of integer range 0 to 63;
 signal coincidence_config_1, coincidence_config_2 : coincidence_arr;
 signal coincidence_enable : std_logic_vector(15 downto 0);
 
@@ -100,8 +102,8 @@ begin
         end case;          
       end if;  
     elsif BUS_RX.addr(6 downto 4) = "100" then
-      coincidence_config_1(to_integer(unsigned(BUS_RX.addr(3 downto 0)))) <= to_integer(unsigned(BUS_RX.data(12 downto 8)));
-      coincidence_config_2(to_integer(unsigned(BUS_RX.addr(3 downto 0)))) <= to_integer(unsigned(BUS_RX.data(4 downto 0)));
+      coincidence_config_1(to_integer(unsigned(BUS_RX.addr(3 downto 0)))) <= to_integer(unsigned(BUS_RX.data(13 downto 8)));
+      coincidence_config_2(to_integer(unsigned(BUS_RX.addr(3 downto 0)))) <= to_integer(unsigned(BUS_RX.data(5 downto 0)));
       coincidence_enable(to_integer(unsigned(BUS_RX.addr(3 downto 0))))   <= BUS_RX.data(31);
     elsif BUS_RX.addr(6 downto 0) = "0110010" then
       set_multiplicity <= unsigned(BUS_RX.data(23 downto 16));
@@ -111,6 +113,8 @@ begin
       set_output_simplecoin <= BUS_RX.data(7 downto 0);
       set_output_mult <= BUS_RX.data(15 downto 8);
       set_output_coin <= BUS_RX.data(23 downto 16);
+      edge_enable     <= BUS_RX.data(31 downto 24);
+
     else
       BUS_TX.nack <= '1'; 
       BUS_TX.ack  <= '0';
@@ -158,8 +162,8 @@ begin
         BUS_TX.unknown <= '1';
       end if;  
     elsif BUS_RX.addr(6 downto 4) = "100" then
-      BUS_TX.data(12 downto 8) <= std_logic_vector(to_unsigned(coincidence_config_1(to_integer(unsigned(BUS_RX.addr(3 downto 0)))),5));
-      BUS_TX.data( 4 downto 0) <= std_logic_vector(to_unsigned(coincidence_config_2(to_integer(unsigned(BUS_RX.addr(3 downto 0)))),5));
+      BUS_TX.data(13 downto 8) <= std_logic_vector(to_unsigned(coincidence_config_1(to_integer(unsigned(BUS_RX.addr(3 downto 0)))),6));
+      BUS_TX.data( 5 downto 0) <= std_logic_vector(to_unsigned(coincidence_config_2(to_integer(unsigned(BUS_RX.addr(3 downto 0)))),6));
       BUS_TX.data(31)          <= coincidence_enable(to_integer(unsigned(BUS_RX.addr(3 downto 0))));
     elsif BUS_RX.addr(6 downto 0) = "0110000" then
       BUS_TX.data(OUTPUTS-1 downto 0) <= out_reg;
@@ -173,7 +177,7 @@ begin
     elsif BUS_RX.addr(6 downto 0) = "0110011" then
       BUS_TX.data                 <= multiplicity_enable;
     elsif BUS_RX.addr(6 downto 0) = "0110100" then
-      BUS_TX.data <= x"00" & set_output_coin & set_output_mult & set_output_simplecoin;
+      BUS_TX.data <= edge_enable & set_output_coin & set_output_mult & set_output_simplecoin;
     else  
       BUS_TX.nack <= '1'; 
       BUS_TX.ack  <= '0';
@@ -197,11 +201,14 @@ inp_inv           <= INPUT xor invert(INPUTS-1 downto 0);
 inp_long          <= inp_shift(0) or inp_shift(1);
 inp_verylong      <= inp_shift(1) or inp_shift(2) or inp_shift(3) or inp_shift(4) when rising_edge(CLK);
 
+inp_edge          <= not inp_shift(1) and inp_shift(2) when rising_edge(CLK);
 ----------------------------
 --  Outputs
 ----------------------------
 gen_outs : for i in 0 to OUTPUTS-1 generate
-  output_i(i) <= or_all(((inp_long and stretch_inp(INPUTS-1 downto 0)) or (inp_inv(INPUTS-1 downto 0) and not stretch_inp(INPUTS-1 downto 0))) and enable(i)(INPUTS-1 downto 0))
+  output_i(i) <=     (or_all(inp_long and stretch_inp(INPUTS-1 downto 0) and enable(i)(INPUTS-1 downto 0)) and not edge_enable(i))
+                  or (or_all(inp_inv(INPUTS-1 downto 0) and not stretch_inp(INPUTS-1 downto 0) and enable(i)(INPUTS-1 downto 0)) and not edge_enable(i))
+                  or (or_all(inp_edge(INPUTS-1 downto 0) and enable(i)(INPUTS-1 downto 0)) and edge_enable(i))
                   or (got_simplecoin and set_output_simplecoin(i))
                   or (multiplicity_trigger and set_output_mult(i))
                   or (got_coincidence and set_output_coin(i))