From: Cahit Date: Mon, 11 May 2015 06:58:43 +0000 (+0200) Subject: fixed the problem with the missing reference channel with trigger window X-Git-Tag: v2.3~80 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=a998dbc90dba97010b8c8edfe5be550cb5da97c5;p=tdc.git fixed the problem with the missing reference channel with trigger window --- diff --git a/base/cores/ecp3/PLL/generate_core.tcl b/base/cores/ecp3/PLL/generate_core.tcl index 5122002..aa2cbac 100644 --- a/base/cores/ecp3/PLL/generate_core.tcl +++ b/base/cores/ecp3/PLL/generate_core.tcl @@ -85,7 +85,7 @@ set Para(install_dir) $env(TOOLRTF) set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" set scuba "$Para(FPGAPath)/scuba" -set modulename "pll_in125_out333" +set modulename "pll_in125_out33" set lang "vhdl" set lpcfile "$Para(sbp_path)/$modulename.lpc" set arch "ep5c00" diff --git a/base/cores/ecp3/PLL/generate_ngd.tcl b/base/cores/ecp3/PLL/generate_ngd.tcl index cf1605a..59c0863 100644 --- a/base/cores/ecp3/PLL/generate_ngd.tcl +++ b/base/cores/ecp3/PLL/generate_ngd.tcl @@ -50,7 +50,7 @@ set Para(install_dir) $env(TOOLRTF) set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" -set Para(ModuleName) "pll_in125_out333" +set Para(ModuleName) "pll_in125_out33" set Para(Module) "PLL" set Para(libname) latticeecp3 set Para(arch_name) ep5c00 diff --git a/base/cores/ecp3/PLL/msg_file.log b/base/cores/ecp3/PLL/msg_file.log index 65b2385..f792fdd 100644 --- a/base/cores/ecp3/PLL/msg_file.log +++ b/base/cores/ecp3/PLL/msg_file.log @@ -1,5 +1,5 @@ SCUBA, Version Diamond (64-bit) 3.4.0.80 -Tue Apr 28 16:10:12 2015 +Mon May 11 08:53:40 2015 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -9,20 +9,20 @@ Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. BEGIN SCUBA Module Synthesis - Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out333 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 33.3 -fclkop_tol 0.2 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw - Circuit name : pll_in125_out333 + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out33 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 33.3 -fclkop_tol 0.2 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + Circuit name : pll_in125_out33 Module type : pll Module Version : 5.7 Ports : Inputs : CLK Outputs : CLKOP, LOCK I/O buffer : not inserted - EDIF output : pll_in125_out333.edn - VHDL output : pll_in125_out333.vhd - VHDL template : pll_in125_out333_tmpl.vhd + EDIF output : pll_in125_out33.edn + VHDL output : pll_in125_out33.vhd + VHDL template : pll_in125_out33_tmpl.vhd VHDL purpose : for synthesis and simulation Bus notation : not used - Report output : pll_in125_out333.srp + Report output : pll_in125_out33.srp Estimated Resource Usage: END SCUBA Module Synthesis diff --git a/base/cores/ecp3/PLL/pll_in125_out33.edn b/base/cores/ecp3/PLL/pll_in125_out33.edn new file mode 100644 index 0000000..c1cfdcb --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out33.edn @@ -0,0 +1,167 @@ +(edif pll_in125_out33 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 5 11 8 53 40) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out33 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 33.3 -fclkop_tol 0.2 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell EHXPLLF + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CLKI + (direction INPUT)) + (port CLKFB + (direction INPUT)) + (port RST + (direction INPUT)) + (port RSTK + (direction INPUT)) + (port WRDEL + (direction INPUT)) + (port DRPAI3 + (direction INPUT)) + (port DRPAI2 + (direction INPUT)) + (port DRPAI1 + (direction INPUT)) + (port DRPAI0 + (direction INPUT)) + (port DFPAI3 + (direction INPUT)) + (port DFPAI2 + (direction INPUT)) + (port DFPAI1 + (direction INPUT)) + (port DFPAI0 + (direction INPUT)) + (port FDA3 + (direction INPUT)) + (port FDA2 + (direction INPUT)) + (port FDA1 + (direction INPUT)) + (port FDA0 + (direction INPUT)) + (port CLKOP + (direction OUTPUT)) + (port CLKOS + (direction OUTPUT)) + (port CLKOK + (direction OUTPUT)) + (port CLKOK2 + (direction OUTPUT)) + (port LOCK + (direction OUTPUT)) + (port CLKINTFB + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell pll_in125_out33 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CLK + (direction INPUT)) + (port CLKOP + (direction OUTPUT)) + (port LOCK + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance PLLInst_0 + (viewRef view1 + (cellRef EHXPLLF)) + (property FEEDBK_PATH + (string "CLKOP")) + (property CLKOK_BYPASS + (string "DISABLED")) + (property CLKOS_BYPASS + (string "DISABLED")) + (property FREQUENCY_PIN_CLKOP + (string "33.333333")) + (property CLKOP_BYPASS + (string "DISABLED")) + (property CLKOK_INPUT + (string "CLKOP")) + (property DELAY_PWD + (string "DISABLED")) + (property DELAY_VAL + (string "0")) + (property CLKOS_TRIM_DELAY + (string "0")) + (property CLKOS_TRIM_POL + (string "RISING")) + (property CLKOP_TRIM_DELAY + (string "0")) + (property CLKOP_TRIM_POL + (string "RISING")) + (property PHASE_DELAY_CNTL + (string "STATIC")) + (property DUTY + (string "8")) + (property PHASEADJ + (string "0.0")) + (property FREQUENCY_PIN_CLKI + (string "125.000000")) + (property CLKOK_DIV + (string "2")) + (property CLKOP_DIV + (string "16")) + (property CLKFB_DIV + (string "12")) + (property CLKI_DIV + (string "45")) + (property FIN + (string "125.000000"))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef FDA3 (instanceRef PLLInst_0)) + (portRef FDA2 (instanceRef PLLInst_0)) + (portRef FDA1 (instanceRef PLLInst_0)) + (portRef FDA0 (instanceRef PLLInst_0)) + (portRef WRDEL (instanceRef PLLInst_0)) + (portRef DFPAI3 (instanceRef PLLInst_0)) + (portRef DFPAI2 (instanceRef PLLInst_0)) + (portRef DFPAI1 (instanceRef PLLInst_0)) + (portRef DFPAI0 (instanceRef PLLInst_0)) + (portRef DRPAI3 (instanceRef PLLInst_0)) + (portRef DRPAI2 (instanceRef PLLInst_0)) + (portRef DRPAI1 (instanceRef PLLInst_0)) + (portRef DRPAI0 (instanceRef PLLInst_0)) + (portRef RSTK (instanceRef PLLInst_0)) + (portRef RST (instanceRef PLLInst_0)))) + (net LOCK + (joined + (portRef LOCK) + (portRef LOCK (instanceRef PLLInst_0)))) + (net CLKOP + (joined + (portRef CLKOP) + (portRef CLKFB (instanceRef PLLInst_0)) + (portRef CLKOP (instanceRef PLLInst_0)))) + (net CLK + (joined + (portRef CLK) + (portRef CLKI (instanceRef PLLInst_0)))))))) + (design pll_in125_out33 + (cellRef pll_in125_out33 + (libraryRef ORCLIB))) +) diff --git a/base/cores/ecp3/PLL/pll_in125_out33.ipx b/base/cores/ecp3/PLL/pll_in125_out33.ipx new file mode 100644 index 0000000..b47dc60 --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out33.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/base/cores/ecp3/PLL/pll_in125_out33.jhd b/base/cores/ecp3/PLL/pll_in125_out33.jhd new file mode 100644 index 0000000..e69de29 diff --git a/base/cores/ecp3/PLL/pll_in125_out33.lpc b/base/cores/ecp3/PLL/pll_in125_out33.lpc new file mode 100644 index 0000000..0b403c2 --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out33.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.7 +ModuleName=pll_in125_out33 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=05/11/2015 +Time=08:53:40 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=125 +Div=45 +ClkOPBp=0 +Post=16 +U_OFrq=33.3 +OP_Tol=0.2 +OFrq=33.333333 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=12 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq= +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=0.570720 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_in125_out33 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 33.3 -fclkop_tol 0.2 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw diff --git a/base/cores/ecp3/PLL/pll_in125_out33.sort b/base/cores/ecp3/PLL/pll_in125_out33.sort new file mode 100644 index 0000000..11a3739 --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out33.sort @@ -0,0 +1 @@ +pll_in125_out33.vhd diff --git a/base/cores/ecp3/PLL/pll_in125_out33.srp b/base/cores/ecp3/PLL/pll_in125_out33.srp new file mode 100644 index 0000000..e27b12c --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out33.srp @@ -0,0 +1,26 @@ +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Mon May 11 08:53:40 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out33 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 33.3 -fclkop_tol 0.2 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + Circuit name : pll_in125_out33 + Module type : pll + Module Version : 5.7 + Ports : + Inputs : CLK + Outputs : CLKOP, LOCK + I/O buffer : not inserted + EDIF output : pll_in125_out33.edn + VHDL output : pll_in125_out33.vhd + VHDL template : pll_in125_out33_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : not used + Report output : pll_in125_out33.srp + Element Usage : + EHXPLLF : 1 + Estimated Resource Usage: diff --git a/base/cores/ecp3/PLL/pll_in125_out33.vhd b/base/cores/ecp3/PLL/pll_in125_out33.vhd new file mode 100644 index 0000000..2c7431c --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out33.vhd @@ -0,0 +1,99 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out33 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 33.3 -fclkop_tol 0.2 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + +-- Mon May 11 08:53:40 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_in125_out33 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_in125_out33 : entity is true; +end pll_in125_out33; + +architecture Structure of pll_in125_out33 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "33.333333"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 16, CLKFB_DIV=> 12, CLKI_DIV=> 45, + FIN=> "125.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_in125_out33 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/cores/ecp3/PLL/pll_in125_out333.edn b/base/cores/ecp3/PLL/pll_in125_out333.edn new file mode 100644 index 0000000..d84a9a4 --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out333.edn @@ -0,0 +1,167 @@ +(edif pll_in125_out333 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 5 11 8 52 12) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out333 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 333 -fclkop_tol 0.2 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell EHXPLLF + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CLKI + (direction INPUT)) + (port CLKFB + (direction INPUT)) + (port RST + (direction INPUT)) + (port RSTK + (direction INPUT)) + (port WRDEL + (direction INPUT)) + (port DRPAI3 + (direction INPUT)) + (port DRPAI2 + (direction INPUT)) + (port DRPAI1 + (direction INPUT)) + (port DRPAI0 + (direction INPUT)) + (port DFPAI3 + (direction INPUT)) + (port DFPAI2 + (direction INPUT)) + (port DFPAI1 + (direction INPUT)) + (port DFPAI0 + (direction INPUT)) + (port FDA3 + (direction INPUT)) + (port FDA2 + (direction INPUT)) + (port FDA1 + (direction INPUT)) + (port FDA0 + (direction INPUT)) + (port CLKOP + (direction OUTPUT)) + (port CLKOS + (direction OUTPUT)) + (port CLKOK + (direction OUTPUT)) + (port CLKOK2 + (direction OUTPUT)) + (port LOCK + (direction OUTPUT)) + (port CLKINTFB + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell pll_in125_out333 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CLK + (direction INPUT)) + (port CLKOP + (direction OUTPUT)) + (port LOCK + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance PLLInst_0 + (viewRef view1 + (cellRef EHXPLLF)) + (property FEEDBK_PATH + (string "CLKOP")) + (property CLKOK_BYPASS + (string "DISABLED")) + (property CLKOS_BYPASS + (string "DISABLED")) + (property FREQUENCY_PIN_CLKOP + (string "333.333333")) + (property CLKOP_BYPASS + (string "DISABLED")) + (property CLKOK_INPUT + (string "CLKOP")) + (property DELAY_PWD + (string "DISABLED")) + (property DELAY_VAL + (string "0")) + (property CLKOS_TRIM_DELAY + (string "0")) + (property CLKOS_TRIM_POL + (string "RISING")) + (property CLKOP_TRIM_DELAY + (string "0")) + (property CLKOP_TRIM_POL + (string "RISING")) + (property PHASE_DELAY_CNTL + (string "STATIC")) + (property DUTY + (string "8")) + (property PHASEADJ + (string "0.0")) + (property FREQUENCY_PIN_CLKI + (string "125.000000")) + (property CLKOK_DIV + (string "2")) + (property CLKOP_DIV + (string "2")) + (property CLKFB_DIV + (string "8")) + (property CLKI_DIV + (string "3")) + (property FIN + (string "125.000000"))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef FDA3 (instanceRef PLLInst_0)) + (portRef FDA2 (instanceRef PLLInst_0)) + (portRef FDA1 (instanceRef PLLInst_0)) + (portRef FDA0 (instanceRef PLLInst_0)) + (portRef WRDEL (instanceRef PLLInst_0)) + (portRef DFPAI3 (instanceRef PLLInst_0)) + (portRef DFPAI2 (instanceRef PLLInst_0)) + (portRef DFPAI1 (instanceRef PLLInst_0)) + (portRef DFPAI0 (instanceRef PLLInst_0)) + (portRef DRPAI3 (instanceRef PLLInst_0)) + (portRef DRPAI2 (instanceRef PLLInst_0)) + (portRef DRPAI1 (instanceRef PLLInst_0)) + (portRef DRPAI0 (instanceRef PLLInst_0)) + (portRef RSTK (instanceRef PLLInst_0)) + (portRef RST (instanceRef PLLInst_0)))) + (net LOCK + (joined + (portRef LOCK) + (portRef LOCK (instanceRef PLLInst_0)))) + (net CLKOP + (joined + (portRef CLKOP) + (portRef CLKFB (instanceRef PLLInst_0)) + (portRef CLKOP (instanceRef PLLInst_0)))) + (net CLK + (joined + (portRef CLK) + (portRef CLKI (instanceRef PLLInst_0)))))))) + (design pll_in125_out333 + (cellRef pll_in125_out333 + (libraryRef ORCLIB))) +) diff --git a/base/cores/ecp3/PLL/pll_in125_out333.ipx b/base/cores/ecp3/PLL/pll_in125_out333.ipx new file mode 100644 index 0000000..ff83d92 --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out333.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/base/cores/ecp3/PLL/pll_in125_out333.jhd b/base/cores/ecp3/PLL/pll_in125_out333.jhd new file mode 100644 index 0000000..e69de29 diff --git a/base/cores/ecp3/PLL/pll_in125_out333.lpc b/base/cores/ecp3/PLL/pll_in125_out333.lpc new file mode 100644 index 0000000..e9452a0 --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out333.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.7 +ModuleName=pll_in125_out333 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=05/11/2015 +Time=08:52:12 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=125 +Div=3 +ClkOPBp=0 +Post=2 +U_OFrq=333 +OP_Tol=0.2 +OFrq=333.333333 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=8 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq= +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=2.191564 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_in125_out333 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 333 -fclkop_tol 0.2 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw diff --git a/base/cores/ecp3/PLL/pll_in125_out333.sort b/base/cores/ecp3/PLL/pll_in125_out333.sort new file mode 100644 index 0000000..7ca649a --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out333.sort @@ -0,0 +1 @@ +pll_in125_out333.vhd diff --git a/base/cores/ecp3/PLL/pll_in125_out333.srp b/base/cores/ecp3/PLL/pll_in125_out333.srp new file mode 100644 index 0000000..fb59deb --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out333.srp @@ -0,0 +1,26 @@ +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Mon May 11 08:52:12 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out333 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 333 -fclkop_tol 0.2 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + Circuit name : pll_in125_out333 + Module type : pll + Module Version : 5.7 + Ports : + Inputs : CLK + Outputs : CLKOP, LOCK + I/O buffer : not inserted + EDIF output : pll_in125_out333.edn + VHDL output : pll_in125_out333.vhd + VHDL template : pll_in125_out333_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : not used + Report output : pll_in125_out333.srp + Element Usage : + EHXPLLF : 1 + Estimated Resource Usage: diff --git a/base/cores/ecp3/PLL/pll_in125_out333.vhd b/base/cores/ecp3/PLL/pll_in125_out333.vhd new file mode 100644 index 0000000..2f3de41 --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out333.vhd @@ -0,0 +1,99 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out333 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 333 -fclkop_tol 0.2 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + +-- Mon May 11 08:52:12 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_in125_out333 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_in125_out333 : entity is true; +end pll_in125_out333; + +architecture Structure of pll_in125_out333 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "333.333333"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 8, CLKI_DIV=> 3, + FIN=> "125.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_in125_out333 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/base/cores/ecp3/PLL/pll_in125_out333_generate.log b/base/cores/ecp3/PLL/pll_in125_out333_generate.log new file mode 100644 index 0000000..9d50114 --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out333_generate.log @@ -0,0 +1,44 @@ +Starting process: Module + +Starting process: + +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Mon May 11 08:52:12 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out333 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 333 -fclkop_tol 0.2 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + Circuit name : pll_in125_out333 + Module type : pll + Module Version : 5.7 + Ports : + Inputs : CLK + Outputs : CLKOP, LOCK + I/O buffer : not inserted + EDIF output : pll_in125_out333.edn + VHDL output : pll_in125_out333.vhd + VHDL template : pll_in125_out333_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : not used + Report output : pll_in125_out333.srp + Estimated Resource Usage: + +END SCUBA Module Synthesis + +File: pll_in125_out333.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/base/cores/ecp3/PLL/pll_in125_out333_tmpl.vhd b/base/cores/ecp3/PLL/pll_in125_out333_tmpl.vhd new file mode 100644 index 0000000..b4a319d --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out333_tmpl.vhd @@ -0,0 +1,12 @@ +-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +-- Mon May 11 08:52:12 2015 + +-- parameterized module component declaration +component pll_in125_out333 + port (CLK: in std_logic; CLKOP: out std_logic; LOCK: out std_logic); +end component; + +-- parameterized module component instance +__ : pll_in125_out333 + port map (CLK=>__, CLKOP=>__, LOCK=>__); diff --git a/base/cores/ecp3/PLL/pll_in125_out33_generate.log b/base/cores/ecp3/PLL/pll_in125_out33_generate.log new file mode 100644 index 0000000..050bfab --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out33_generate.log @@ -0,0 +1,44 @@ +Starting process: Module + +Starting process: + +SCUBA, Version Diamond (64-bit) 3.4.0.80 +Mon May 11 08:53:40 2015 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out33 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 33.3 -fclkop_tol 0.2 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + Circuit name : pll_in125_out33 + Module type : pll + Module Version : 5.7 + Ports : + Inputs : CLK + Outputs : CLKOP, LOCK + I/O buffer : not inserted + EDIF output : pll_in125_out33.edn + VHDL output : pll_in125_out33.vhd + VHDL template : pll_in125_out33_tmpl.vhd + VHDL purpose : for synthesis and simulation + Bus notation : not used + Report output : pll_in125_out33.srp + Estimated Resource Usage: + +END SCUBA Module Synthesis + +File: pll_in125_out33.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/base/cores/ecp3/PLL/pll_in125_out33_tmpl.vhd b/base/cores/ecp3/PLL/pll_in125_out33_tmpl.vhd new file mode 100644 index 0000000..6c45e0b --- /dev/null +++ b/base/cores/ecp3/PLL/pll_in125_out33_tmpl.vhd @@ -0,0 +1,12 @@ +-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.7 +-- Mon May 11 08:53:40 2015 + +-- parameterized module component declaration +component pll_in125_out33 + port (CLK: in std_logic; CLKOP: out std_logic; LOCK: out std_logic); +end component; + +-- parameterized module component instance +__ : pll_in125_out33 + port map (CLK=>__, CLKOP=>__, LOCK=>__); diff --git a/releases/tdc_v2.1.2/Channel_200.vhd b/releases/tdc_v2.1.2/Channel_200.vhd index 66bf595..b9cb566 100644 --- a/releases/tdc_v2.1.2/Channel_200.vhd +++ b/releases/tdc_v2.1.2/Channel_200.vhd @@ -5,7 +5,7 @@ -- File : Channel_200.vhd -- Author : c.ugur@gsi.de -- Created : 2012-08-28 --- Last update: 2015-04-29 +-- Last update: 2015-05-10 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -58,6 +58,7 @@ architecture Channel_200 of Channel_200 is signal data_a : std_logic_vector(303 downto 0); signal data_b : std_logic_vector(303 downto 0); signal result : std_logic_vector(303 downto 0); + signal thermocode : std_logic_vector(303 downto 0); signal ff_array_en : std_logic; -- hit detection @@ -160,7 +161,7 @@ begin -- Channel_200 FC : Adder_304 port map ( CLK => CLK_200, - RESET => '0', --RESET_200, + RESET => RESET_200, DataA => data_a, DataB => data_b, CLKEn => ff_array_en, @@ -173,7 +174,8 @@ begin -- Channel_200 result_2_r <= result(2) when rising_edge(CLK_200); result_3_r <= result(3) when rising_edge(CLK_200); - hit_detect <= ((not result_2_r) and result(2)) or ((not result_3_r) and result(3)); -- detects the hit by +-- hit_detect <= ((not result_2_r) and result(2)) or ((not result_3_r) and result(3)); -- detects the hit by + hit_detect <= (not result_2_r) and result(2); -- detects the hit by -- comparing the -- previous state of the -- hit detection bit @@ -266,10 +268,11 @@ begin -- Channel_200 RESET => RESET_200, CLK => CLK_200, START_IN => encoder_start, - THERMOCODE_IN => result, + THERMOCODE_IN => thermocode, --result, FINISHED_OUT => encoder_finished, BINARY_CODE_OUT => encoder_data_out, ENCODER_DEBUG => encoder_debug); + thermocode <= "11" & result(303 downto 2); RingBuffer_128_dyn : if RING_BUFFER_SIZE = 7 generate FIFO : FIFO_DC_36x128_DynThr_OutReg diff --git a/releases/tdc_v2.1.2/Readout.vhd b/releases/tdc_v2.1.2/Readout.vhd index ff5319d..8265086 100644 --- a/releases/tdc_v2.1.2/Readout.vhd +++ b/releases/tdc_v2.1.2/Readout.vhd @@ -5,7 +5,7 @@ -- File : Readout.vhd -- Author : cugur@gsi.de -- Created : 2012-10-25 --- Last update: 2015-04-29 +-- Last update: 2015-05-10 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -566,7 +566,7 @@ begin -- behavioral begin if rising_edge(CLK_100) then if ch_data_3r(fifo_nr_wr_r)(35 downto 32) = x"1" and ch_data_3r(fifo_nr_wr_r)(31) = '1' then --DATA word - if TRG_WIN_EN_IN = '1' then -- trigger window enabled + if TRG_WIN_EN_IN = '1' then -- trigger window enabled --elsif (TW_pre(10) = '1' and ref_time_coarse(10) = '0') or (TW_post(10) = '0' and ref_time_coarse(10) = '1') then -- if one of the trigger window edges has an overflow -- if (trg_win_l = '0' and trg_win_r = '1') or (trg_win_l = '1' and trg_win_r = '0') then -- ch_data_4r <= ch_data_3r(fifo_nr); diff --git a/releases/tdc_v2.1.2/tdc_components.vhd b/releases/tdc_v2.1.2/tdc_components.vhd index c14f603..2efdda6 100644 --- a/releases/tdc_v2.1.2/tdc_components.vhd +++ b/releases/tdc_v2.1.2/tdc_components.vhd @@ -540,5 +540,12 @@ package tdc_components is CLKOP : out std_logic; LOCK : out std_logic); end component pll_in125_out333; - + + component pll_in125_out33 is + port ( + CLK : in std_logic; + CLKOP : out std_logic; + LOCK : out std_logic); + end component pll_in125_out33; + end package tdc_components; diff --git a/releases/tdc_v2.1.2/tdc_constraints_64.lpf b/releases/tdc_v2.1.2/tdc_constraints_64.lpf index 2c20f3a..6b86b04 100644 --- a/releases/tdc_v2.1.2/tdc_constraints_64.lpf +++ b/releases/tdc_v2.1.2/tdc_constraints_64.lpf @@ -22,7 +22,7 @@ UGROUP "hitBuf_1" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.1.hit_mux_ch; LOCATE UGROUP "hitBuf_1" SITE "R31C4D" ; UGROUP "ff_en_1" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_1" SITE "R30C27D" ; # @@ -33,7 +33,7 @@ UGROUP "hitBuf_2" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.2.hit_mux_ch; LOCATE UGROUP "hitBuf_2" SITE "R49C4D" ; UGROUP "ff_en_2" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.2.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_2" SITE "R48C27D" ; # @@ -44,7 +44,7 @@ UGROUP "hitBuf_3" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.3.hit_mux_ch; LOCATE UGROUP "hitBuf_3" SITE "R36C4D" ; UGROUP "ff_en_3" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.3.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_3" SITE "R35C27D" ; # @@ -55,7 +55,7 @@ UGROUP "hitBuf_4" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.4.hit_mux_ch; LOCATE UGROUP "hitBuf_4" SITE "R38C4D" ; UGROUP "ff_en_4" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.4.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.4.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.4.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_4" SITE "R37C27D" ; # @@ -66,7 +66,7 @@ UGROUP "hitBuf_5" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.5.hit_mux_ch; LOCATE UGROUP "hitBuf_5" SITE "R51C4D" ; UGROUP "ff_en_5" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.5.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.5.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.5.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_5" SITE "R50C27D" ; # @@ -77,7 +77,7 @@ UGROUP "hitBuf_6" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.6.hit_mux_ch; LOCATE UGROUP "hitBuf_6" SITE "R72C4D" ; UGROUP "ff_en_6" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.6.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_6" SITE "R71C27D" ; # @@ -88,7 +88,7 @@ UGROUP "hitBuf_7" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.7.hit_mux_ch; LOCATE UGROUP "hitBuf_7" SITE "R87C4D" ; UGROUP "ff_en_7" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.7.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.7.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.7.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_7" SITE "R86C27D" ; # @@ -99,7 +99,7 @@ UGROUP "hitBuf_8" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.8.hit_mux_ch; LOCATE UGROUP "hitBuf_8" SITE "R85C4D" ; UGROUP "ff_en_8" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.8.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.8.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.8.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_8" SITE "R84C27D" ; # @@ -110,7 +110,7 @@ UGROUP "hitBuf_9" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.9.hit_mux_ch; LOCATE UGROUP "hitBuf_9" SITE "R74C4D" ; UGROUP "ff_en_9" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.9.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.9.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.9.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_9" SITE "R73C27D" ; # @@ -121,7 +121,7 @@ UGROUP "hitBuf_10" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.10.hit_mux_ch; LOCATE UGROUP "hitBuf_10" SITE "R103C4D" ; UGROUP "ff_en_10" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.10.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_10" SITE "R102C27D" ; # @@ -132,7 +132,7 @@ UGROUP "hitBuf_11" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.11.hit_mux_ch; LOCATE UGROUP "hitBuf_11" SITE "R105C4D" ; UGROUP "ff_en_11" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.11.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.11.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.11.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_11" SITE "R104C27D" ; # @@ -143,7 +143,7 @@ UGROUP "hitBuf_12" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.12.hit_mux_ch; LOCATE UGROUP "hitBuf_12" SITE "R92C4D" ; UGROUP "ff_en_12" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.12.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.12.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.12.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_12" SITE "R91C27D" ; # @@ -154,7 +154,7 @@ UGROUP "hitBuf_13" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.13.hit_mux_ch; LOCATE UGROUP "hitBuf_13" SITE "R9C4D" ; UGROUP "ff_en_13" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.13.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_13" SITE "R8C27D" ; # @@ -165,7 +165,7 @@ UGROUP "hitBuf_14" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.14.hit_mux_ch; LOCATE UGROUP "hitBuf_14" SITE "R11C4D" ; UGROUP "ff_en_14" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.14.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_14" SITE "R10C27D" ; # @@ -176,7 +176,7 @@ UGROUP "hitBuf_15" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.15.hit_mux_ch; LOCATE UGROUP "hitBuf_15" SITE "R22C4D" ; UGROUP "ff_en_15" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.15.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.15.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.15.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_15" SITE "R21C27D" ; # @@ -187,7 +187,7 @@ UGROUP "hitBuf_16" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.16.hit_mux_ch; LOCATE UGROUP "hitBuf_16" SITE "R24C4D" ; UGROUP "ff_en_16" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.16.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.16.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.16.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_16" SITE "R23C27D" ; # @@ -198,7 +198,7 @@ UGROUP "hitBuf_17" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.17.hit_mux_ch; LOCATE UGROUP "hitBuf_17" SITE "R105C60D" ; UGROUP "ff_en_17" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.17.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_17" SITE "R104C83D" ; # @@ -209,7 +209,7 @@ UGROUP "hitBuf_18" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.18.hit_mux_ch; LOCATE UGROUP "hitBuf_18" SITE "R90C60D" ; UGROUP "ff_en_18" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.18.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_18" SITE "R89C83D" ; # @@ -220,7 +220,7 @@ UGROUP "hitBuf_19" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.19.hit_mux_ch; LOCATE UGROUP "hitBuf_19" SITE "R92C60D" ; UGROUP "ff_en_19" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.19.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.19.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.19.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_19" SITE "R91C83D" ; # @@ -231,7 +231,7 @@ UGROUP "hitBuf_20" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.20.hit_mux_ch; LOCATE UGROUP "hitBuf_20" SITE "R103C60D" ; UGROUP "ff_en_20" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.20.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_20" SITE "R102C83D" ; # @@ -242,7 +242,7 @@ UGROUP "hitBuf_21" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.21.hit_mux_ch; LOCATE UGROUP "hitBuf_21" SITE "R112C60D" ; UGROUP "ff_en_21" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.21.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_21" SITE "R111C83D" ; # @@ -253,7 +253,7 @@ UGROUP "hitBuf_22" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.22.hit_mux_ch; LOCATE UGROUP "hitBuf_22" SITE "R114C60D" ; UGROUP "ff_en_22" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.22.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_22" SITE "R113C83D" ; # @@ -264,7 +264,7 @@ UGROUP "hitBuf_23" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.23.hit_mux_ch; LOCATE UGROUP "hitBuf_23" SITE "R69C4D" ; UGROUP "ff_en_23" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.23.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.23.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.23.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_23" SITE "R68C27D" ; # @@ -275,7 +275,7 @@ UGROUP "hitBuf_24" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.24.hit_mux_ch; LOCATE UGROUP "hitBuf_24" SITE "R56C4D" ; UGROUP "ff_en_24" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.24.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_24" SITE "R55C27D" ; # @@ -286,7 +286,7 @@ UGROUP "hitBuf_25" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.25.hit_mux_ch; LOCATE UGROUP "hitBuf_25" SITE "R54C4D" ; UGROUP "ff_en_25" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.25.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.25.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.25.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_25" SITE "R53C27D" ; # @@ -297,7 +297,7 @@ UGROUP "hitBuf_26" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.26.hit_mux_ch; LOCATE UGROUP "hitBuf_26" SITE "R67C4D" ; UGROUP "ff_en_26" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.26.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.26.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.26.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_26" SITE "R66C27D" ; # @@ -308,7 +308,7 @@ UGROUP "hitBuf_27" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.27.hit_mux_ch; LOCATE UGROUP "hitBuf_27" SITE "R112C4D" ; UGROUP "ff_en_27" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.27.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.27.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.27.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_27" SITE "R111C27D" ; # @@ -319,7 +319,7 @@ UGROUP "hitBuf_28" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.28.hit_mux_ch; LOCATE UGROUP "hitBuf_28" SITE "R114C4D" ; UGROUP "ff_en_28" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.28.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_28" SITE "R113C27D" ; # @@ -330,7 +330,7 @@ UGROUP "hitBuf_29" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.29.hit_mux_ch; LOCATE UGROUP "hitBuf_29" SITE "R9C60D" ; UGROUP "ff_en_29" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.29.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_29" SITE "R8C83D" ; # @@ -341,7 +341,7 @@ UGROUP "hitBuf_30" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.30.hit_mux_ch; LOCATE UGROUP "hitBuf_30" SITE "R11C60D" ; UGROUP "ff_en_30" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.30.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_30" SITE "R10C83D" ; # @@ -352,7 +352,7 @@ UGROUP "hitBuf_31" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.31.hit_mux_ch; LOCATE UGROUP "hitBuf_31" SITE "R22C60D" ; UGROUP "ff_en_31" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.31.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_31" SITE "R21C83D" ; # @@ -363,7 +363,7 @@ UGROUP "hitBuf_32" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.32.hit_mux_ch; LOCATE UGROUP "hitBuf_32" SITE "R24C60D" ; UGROUP "ff_en_32" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.32.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_32" SITE "R23C83D" ; # @@ -374,7 +374,7 @@ UGROUP "hitBuf_33" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.33.hit_mux_ch; LOCATE UGROUP "hitBuf_33" SITE "R31C60D" ; UGROUP "ff_en_33" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.33.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.33.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.33.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_33" SITE "R30C83D" ; # @@ -385,7 +385,7 @@ UGROUP "hitBuf_34" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.34.hit_mux_ch; LOCATE UGROUP "hitBuf_34" SITE "R33C60D" ; UGROUP "ff_en_34" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.34.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.34.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.34.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_34" SITE "R32C83D" ; # @@ -396,7 +396,7 @@ UGROUP "hitBuf_35" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.35.hit_mux_ch; LOCATE UGROUP "hitBuf_35" SITE "R35C60D" ; UGROUP "ff_en_35" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.35.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.35.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.35.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_35" SITE "R35C83D" ; # @@ -407,7 +407,7 @@ UGROUP "hitBuf_36" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.36.hit_mux_ch; LOCATE UGROUP "hitBuf_36" SITE "R38C60D" ; UGROUP "ff_en_36" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.36.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.36.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.36.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_36" SITE "R37C83D" ; # @@ -418,7 +418,7 @@ UGROUP "hitBuf_37" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.37.hit_mux_ch; LOCATE UGROUP "hitBuf_37" SITE "R49C60D" ; UGROUP "ff_en_37" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.37.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.37.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.37.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_37" SITE "R48C83D" ; # @@ -429,7 +429,7 @@ UGROUP "hitBuf_38" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.38.hit_mux_ch; LOCATE UGROUP "hitBuf_38" SITE "R51C60D" ; UGROUP "ff_en_38" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.38.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.38.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.38.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_38" SITE "R50C83D" ; # @@ -440,7 +440,7 @@ UGROUP "hitBuf_39" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.39.hit_mux_ch; LOCATE UGROUP "hitBuf_39" SITE "R90C133D" ; UGROUP "ff_en_39" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.39.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.39.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.39.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_39" SITE "R89C156D" ; # @@ -451,7 +451,7 @@ UGROUP "hitBuf_40" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.40.hit_mux_ch; LOCATE UGROUP "hitBuf_40" SITE "R92C133D" ; UGROUP "ff_en_40" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.40.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.40.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.40.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_40" SITE "R91C156D" ; # @@ -462,7 +462,7 @@ UGROUP "hitBuf_41" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.41.hit_mux_ch; LOCATE UGROUP "hitBuf_41" SITE "R103C133D" ; UGROUP "ff_en_41" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.41.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.41.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.41.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_41" SITE "R102C156D" ; # @@ -473,7 +473,7 @@ UGROUP "hitBuf_42" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.42.hit_mux_ch; LOCATE UGROUP "hitBuf_42" SITE "R105C133D" ; UGROUP "ff_en_42" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.42.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.42.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.42.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_42" SITE "R104C156D" ; # @@ -484,7 +484,7 @@ UGROUP "hitBuf_43" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.43.hit_mux_ch; LOCATE UGROUP "hitBuf_43" SITE "R87C133D" ; UGROUP "ff_en_43" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.43.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.43.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.43.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_43" SITE "R86C156D" ; # @@ -495,7 +495,7 @@ UGROUP "hitBuf_44" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.44.hit_mux_ch; LOCATE UGROUP "hitBuf_44" SITE "R85C133D" ; UGROUP "ff_en_44" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.44.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.44.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.44.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_44" SITE "R84C156D" ; # @@ -506,7 +506,7 @@ UGROUP "hitBuf_45" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.45.hit_mux_ch; LOCATE UGROUP "hitBuf_45" SITE "R74C133D" ; UGROUP "ff_en_45" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.45.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.45.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.45.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_45" SITE "R73C156D" ; # @@ -517,7 +517,7 @@ UGROUP "hitBuf_46" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.46.hit_mux_ch; LOCATE UGROUP "hitBuf_46" SITE "R72C133D" ; UGROUP "ff_en_46" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.46.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.46.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.46.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_46" SITE "R71C156D" ; # @@ -528,7 +528,7 @@ UGROUP "hitBuf_47" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.47.hit_mux_ch; LOCATE UGROUP "hitBuf_47" SITE "R112C133D" ; UGROUP "ff_en_47" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.47.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.47.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.47.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_47" SITE "R111C156D" ; # @@ -539,7 +539,7 @@ UGROUP "hitBuf_48" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.48.hit_mux_ch; LOCATE UGROUP "hitBuf_48" SITE "R114C133D" ; UGROUP "ff_en_48" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.48.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.48.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.48.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_48" SITE "R113C156D" ; # @@ -550,7 +550,7 @@ UGROUP "hitBuf_49" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.49.hit_mux_ch; LOCATE UGROUP "hitBuf_49" SITE "R9C133D" ; UGROUP "ff_en_49" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.49.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_49" SITE "R8C156D" ; # @@ -561,7 +561,7 @@ UGROUP "hitBuf_50" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.50.hit_mux_ch; LOCATE UGROUP "hitBuf_50" SITE "R11C133D" ; UGROUP "ff_en_50" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.50.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_50" SITE "R10C156D" ; # @@ -572,7 +572,7 @@ UGROUP "hitBuf_51" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.51.hit_mux_ch; LOCATE UGROUP "hitBuf_51" SITE "R22C133D" ; UGROUP "ff_en_51" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.51.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_51" SITE "R21C156D" ; # @@ -583,7 +583,7 @@ UGROUP "hitBuf_52" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.52.hit_mux_ch; LOCATE UGROUP "hitBuf_52" SITE "R24C133D" ; UGROUP "ff_en_52" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.52.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_52" SITE "R23C156D" ; # @@ -594,7 +594,7 @@ UGROUP "hitBuf_53" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.53.hit_mux_ch; LOCATE UGROUP "hitBuf_53" SITE "R31C133D" ; UGROUP "ff_en_53" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.53.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_53" SITE "R30C156D" ; # @@ -605,7 +605,7 @@ UGROUP "hitBuf_54" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.54.hit_mux_ch; LOCATE UGROUP "hitBuf_54" SITE "R33C133D" ; UGROUP "ff_en_54" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.54.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_54" SITE "R32C156D" ; # @@ -616,7 +616,7 @@ UGROUP "hitBuf_55" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.55.hit_mux_ch; LOCATE UGROUP "hitBuf_55" SITE "R36C133D" ; UGROUP "ff_en_55" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.55.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_55" SITE "R35C156D" ; # @@ -627,7 +627,7 @@ UGROUP "hitBuf_56" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.56.hit_mux_ch; LOCATE UGROUP "hitBuf_56" SITE "R38C133D" ; UGROUP "ff_en_56" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.56.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_56" SITE "R37C156D" ; # @@ -638,7 +638,7 @@ UGROUP "hitBuf_57" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.57.hit_mux_ch; LOCATE UGROUP "hitBuf_57" SITE "R49C133D" ; UGROUP "ff_en_57" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.57.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_57" SITE "R48C156D" ; # @@ -649,7 +649,7 @@ UGROUP "hitBuf_58" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.58.hit_mux_ch; LOCATE UGROUP "hitBuf_58" SITE "R51C133D" ; UGROUP "ff_en_58" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.58.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.58.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.58.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_58" SITE "R50C156D" ; # @@ -660,7 +660,7 @@ UGROUP "hitBuf_59" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.59.hit_mux_ch; LOCATE UGROUP "hitBuf_59" SITE "R54C133D" ; UGROUP "ff_en_59" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.59.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.59.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.59.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_59" SITE "R53C156D" ; # @@ -671,7 +671,7 @@ UGROUP "hitBuf_60" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.60.hit_mux_ch; LOCATE UGROUP "hitBuf_60" SITE "R56C133D" ; UGROUP "ff_en_60" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.60.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.60.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.60.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_60" SITE "R55C156D" ; # @@ -682,7 +682,7 @@ UGROUP "hitBuf_61" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.61.hit_mux_ch; LOCATE UGROUP "hitBuf_61" SITE "R67C133D" ; UGROUP "ff_en_61" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.61.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.61.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.61.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_61" SITE "R66C156D" ; # @@ -693,7 +693,7 @@ UGROUP "hitBuf_62" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.62.hit_mux_ch; LOCATE UGROUP "hitBuf_62" SITE "R69C133D" ; UGROUP "ff_en_62" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.62.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.62.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.62.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_62" SITE "R68C156D" ; # @@ -704,7 +704,7 @@ UGROUP "hitBuf_63" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.63.hit_mux_ch; LOCATE UGROUP "hitBuf_63" SITE "R87C60D" ; UGROUP "ff_en_63" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.63.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.63.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.63.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_63" SITE "R86C83D" ; # @@ -715,7 +715,7 @@ UGROUP "hitBuf_64" BBOX 1 1 BLKNAME THE_TDC/GEN_hit_mux.64.hit_mux_ch; LOCATE UGROUP "hitBuf_64" SITE "R85C60D" ; UGROUP "ff_en_64" BBOX 1 1 - BLKNAME THE_TDC/GEN_Channels.64.Channels/Channel200/ENCODER_START_OUT +# BLKNAME THE_TDC/GEN_Channels.64.Channels/Channel200/ENCODER_START_OUT BLKNAME THE_TDC/GEN_Channels.64.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_64" SITE "R84C83D" ; # diff --git a/releases/tdc_v2.1.2/trb3_periph_32PinAddOn.vhd b/releases/tdc_v2.1.2/trb3_periph_32PinAddOn.vhd index c16e5d0..056c81d 100644 --- a/releases/tdc_v2.1.2/trb3_periph_32PinAddOn.vhd +++ b/releases/tdc_v2.1.2/trb3_periph_32PinAddOn.vhd @@ -97,9 +97,6 @@ architecture trb3_periph_32PinAddOn_arch of trb3_periph_32PinAddOn is attribute syn_keep : boolean; attribute syn_preserve : boolean; - attribute NOM_FREQ : string; - attribute NOM_FREQ of OSCinst0 : label is "20.0"; - --Clock / Reset signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL @@ -313,20 +310,23 @@ begin THE_MAIN_PLL : pll_in200_out100 port map( CLK => CLK_GPLL_RIGHT, + RESET => '0', CLKOP => clk_100_i, CLKOK => clk_200_i, LOCK => pll_lock ); - -- internal oscillator with frequency of 2.5MHz for tdc calibration - OSCInst0: OSCF --- synthesis translate_off - generic map ( - NOM_FREQ => "20.0") --- synthesis translate_on - port map ( - OSC => osc_int); + --pll_calibration: entity work.pll_in125_out100 + -- port map ( + -- CLK => CLK_GPLL_LEFT, + -- CLKOP => osc_int, + -- LOCK => open); + pll_calibration: entity work.pll_in125_out33 + port map ( + CLK => CLK_GPLL_LEFT, + CLKOP => osc_int, + LOCK => open); --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) diff --git a/releases/tdc_v2.1.2/trb3_periph_ADA.vhd b/releases/tdc_v2.1.2/trb3_periph_ADA.vhd index 08de91b..62f1759 100644 --- a/releases/tdc_v2.1.2/trb3_periph_ADA.vhd +++ b/releases/tdc_v2.1.2/trb3_periph_ADA.vhd @@ -318,7 +318,7 @@ begin -- CLKOP => osc_int, -- LOCK => open); - pll_calibration: entity work.pll_in125_out333 + pll_calibration: entity work.pll_in125_out33 port map ( CLK => CLK_GPLL_LEFT, CLKOP => osc_int, diff --git a/releases/tdc_v2.1.2/trb3_periph_gpin.vhd b/releases/tdc_v2.1.2/trb3_periph_gpin.vhd index 123eb98..b58f162 100644 --- a/releases/tdc_v2.1.2/trb3_periph_gpin.vhd +++ b/releases/tdc_v2.1.2/trb3_periph_gpin.vhd @@ -8,7 +8,6 @@ use work.trb_net_components.all; use work.trb3_components.all; use work.tdc_components.all; use work.config.all; -use work.tdc_version.all; use work.version.all; @@ -244,7 +243,7 @@ architecture trb3_periph_gpin_arch of trb3_periph_gpin is signal tdc_ctrl_addr : std_logic_vector(2 downto 0); signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); - signal tdc_ctrl_reg : std_logic_vector(5*32+31 downto 0); + signal tdc_ctrl_reg : std_logic_vector(7*32+31 downto 0); signal spi_bram_addr : std_logic_vector(7 downto 0); signal spi_bram_wr_d : std_logic_vector(7 downto 0); @@ -315,15 +314,17 @@ begin THE_MAIN_PLL : pll_in200_out100 port map( CLK => CLK_GPLL_RIGHT, + RESET => '0', CLKOP => clk_100_i, CLKOK => clk_200_i, LOCK => pll_lock ); - -- internal oscillator with frequency of 2.5MHz for tdc calibration - OSCInst0 : OSCF + pll_calibration: entity work.pll_in125_out33 port map ( - OSC => osc_int); + CLK => CLK_GPLL_LEFT, + CLKOP => osc_int, + LOCK => open); --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) @@ -851,8 +852,7 @@ begin generic map ( CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of channels per module STATUS_REG_NR => 21, -- Number of status regs - CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr - TDC_VERSION => TDC_VERSION, -- TDC version number + CONTROL_REG_NR => 8, -- Number of control regs - higher than 8 check tdc_ctrl_addr DEBUG => c_YES, SIMULATION => c_NO) port map ( diff --git a/releases/tdc_v2.1.2/trb3_periph_padiwa.vhd b/releases/tdc_v2.1.2/trb3_periph_padiwa.vhd index 888d1df..48ec437 100644 --- a/releases/tdc_v2.1.2/trb3_periph_padiwa.vhd +++ b/releases/tdc_v2.1.2/trb3_periph_padiwa.vhd @@ -341,10 +341,11 @@ begin LOCK => pll_lock ); - -- internal oscillator with frequency of 2.5MHz for tdc calibration - OSCInst0 : OSCF + pll_calibration: entity work.pll_in125_out33 port map ( - OSC => osc_int); + CLK => CLK_GPLL_LEFT, + CLKOP => osc_int, + LOCK => open); gen_sync_clocks : if SYNC_MODE = c_YES generate clk_100_i <= rx_clock_100; diff --git a/releases/tdc_v2.1.2/unimportant_lines_constraints.lpf b/releases/tdc_v2.1.2/unimportant_lines_constraints.lpf index eb9b989..6064846 100644 --- a/releases/tdc_v2.1.2/unimportant_lines_constraints.lpf +++ b/releases/tdc_v2.1.2/unimportant_lines_constraints.lpf @@ -13,6 +13,8 @@ MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Cha MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_pre*" 4 x; MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_post*" 4 x; +MULTICYCLE FROM CELL "THE_TDC/hit_edge[*]" TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/memory[*]" 2.000000 X ; + MULTICYCLE TO CELL "THE_TDC/TheChannelDebugBus/data_out_reg[*]" 4 x; MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "CLK_OSC_c" 4.000000 X ;