From: Tobias Weber <toweber86@gmail.com>
Date: Fri, 22 Dec 2017 10:01:51 +0000 (+0100)
Subject: synchronisation and clock signals.
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=aaea22a680b492f3ae796efd6fc53441fc967676;p=trb3.git

synchronisation and clock signals.
---

diff --git a/base/trb3_periph_mupix8.lpf b/base/trb3_periph_mupix8.lpf
index 0a223ab..b152f7c 100644
--- a/base/trb3_periph_mupix8.lpf
+++ b/base/trb3_periph_mupix8.lpf
@@ -2,17 +2,6 @@ BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;
 BLOCK RD_DURING_WR_PATHS ;
 
-#################################################################
-# Basic Settings
-#################################################################
-
-  #SYSCONFIG MCCLK_FREQ = 2.5;
-
-  #FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-  #FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-  #FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-  #FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
-
 #################################################################
 # Clock I/O
 #################################################################
@@ -38,8 +27,6 @@ LOCATE COMP  "TRIGGER_LEFT"   SITE "V3";
 IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25 ;
 
 
-
-
 #################################################################
 # To central FPGA
 #################################################################
@@ -164,7 +151,12 @@ IOBUF PORT "spi_dout_dac" IO_TYPE=LVDS25 DIFFRESISTOR=100;
 LOCATE COMP "spi_dac4_dout" SITE "G26";
 IOBUF PORT "spi_dac4_dout" IO_TYPE=LVDS25 DIFFRESISTOR=100;
 
-
+LOCATE COMP "syncres" SITE "D1";
+IOBUF PORT "syncres" IO_TYPE=LVDS25;
+LOCATE COMP "clkref" SITE "T7";
+IOBUF PORT "clkref" IO_TYPE=LVDS25;
+LOCATE COMP "clkext" SITE "H6";
+IOBUF PORT "clkext" IO_TYPE=LVDS25;
 
 ###########################################################
 ##Relax some timing constraints
diff --git a/mupix/Mupix8/trb3_periph.vhd b/mupix/Mupix8/trb3_periph.vhd
index b01a1e8..ac9eb2b 100644
--- a/mupix/Mupix8/trb3_periph.vhd
+++ b/mupix/Mupix8/trb3_periph.vhd
@@ -52,16 +52,20 @@ entity trb3_periph is
     ctrl_clk2           :  out std_logic; --slow control clk2
     ctrl_ld             :  out std_logic; --slow control load latched data
     ctrl_dout           :  in  std_logic; --serial data from mupix
-    ctrl_rb             :  out std_logic; --slow control readback??
+    ctrl_rb             :  out std_logic; --slow control readback
     spi_dout_adc        :  in  std_logic; --adc serial data from board
     spi_dout_dac        :  in  std_logic; --dac serial data from board
     spi_ld_thres        :  out std_logic; --serial data load
     spi_clk             :  out std_logic; --serial clock
     spi_din             :  out std_logic; --serial data out
-    spi_ld_tmp_dac      :  out std_logic; --load temperature dac ??
-    spi_ld_adc          :  out std_logic; --load adc ??
-    spi_dac4_dout       :  in  std_logic; --serial data in from dac 4??
-    hitbus              :  in  std_logic;
+    spi_ld_tmp_dac      :  out std_logic; --load temperature dac 
+    spi_ld_adc          :  out std_logic; --load adc 
+    spi_dac4_dout       :  in  std_logic; --serial data in from dac 4
+    hitbus              :  in  std_logic; --hitbus
+    -- fast signals
+    clkext              :  out std_logic;
+    clkref              :  out std_logic;
+    syncres             :  out std_logic; --reset of mupix timestamps and counters
     --fast data comes in via serdes addon (see above)
     
     ---------------------------------------------------------------------------
@@ -338,7 +342,9 @@ architecture trb3_periph_arch of trb3_periph is
   signal resethandler_regio_ack_out_0          : std_logic;
   signal resethandler_regio_no_more_data_out_0 : std_logic;
   signal resethandler_regio_unknown_addr_out_0 : std_logic;
-
+  
+  --dummy
+  signal dummy_counter : integer range 0 to 7 := 0;
   
 begin
 
@@ -774,5 +780,25 @@ begin
       SLV_ACK_OUT           => resethandler_regio_ack_out_0,
       SLV_NO_MORE_DATA_OUT  => resethandler_regio_no_more_data_out_0,
       SLV_UNKNOWN_ADDR_OUT  => resethandler_regio_unknown_addr_out_0);
+      
+ clkext <= clk_100_i;
+ clkref <= clk_100_i;
+ 
+ --dummy process to test syncres
+ dummy_proc : process(clk_100_i)
+ begin
+    if rising_edge(clk_100_i) then
+        if reset_i = '0' then
+            dummy_counter <= 0;
+        else
+            syncres <= '0';
+            dummy_counter <= dummy_counter + 1;
+            if dummy_counter = 7 then
+                syncres <= '1';
+                dummy_counter <= 0;
+            end if;
+        end if;
+    end if;
+ end process dummy_proc;
 
 end architecture;
diff --git a/mupix/Mupix8/trb3_periph_constraints.lpf b/mupix/Mupix8/trb3_periph_constraints.lpf
index db33e6d..8d560a8 100644
--- a/mupix/Mupix8/trb3_periph_constraints.lpf
+++ b/mupix/Mupix8/trb3_periph_constraints.lpf
@@ -13,8 +13,6 @@
   FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
   #FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 
-  
-  
 #################################################################
 # Reset Nets
 #################################################################