From: Michael Boehmer Date: Tue, 28 Jun 2022 14:12:47 +0000 (+0200) Subject: changed directories for cores X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ab4445d05c500d5b8495531d824576ee330350e3;p=TOMcat.git changed directories for cores --- diff --git a/gbe/tomcat_gbe.prj b/gbe/tomcat_gbe.prj index 2e80990..d40a172 100644 --- a/gbe/tomcat_gbe.prj +++ b/gbe/tomcat_gbe.prj @@ -238,11 +238,9 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in12 #add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd" #GbE -#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper_5G.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper_single_5G.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper_single.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface_5G.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface_single_5G.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" @@ -266,12 +264,8 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" -add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v" -add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v" -add_file -vhdl -lib work "../../TOMcat/cores/serdes_gbe.vhd" -add_file -verilog -lib work "../../TOMcat/cores/serdes_gbe_softlogic.v" - - +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/serdes_gbe.vhd" +add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/serdes_gbe_softlogic.v" #add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd" diff --git a/gbe/tomcat_gbe.vhd b/gbe/tomcat_gbe.vhd index 7f97d12..d0eeb8e 100644 --- a/gbe/tomcat_gbe.vhd +++ b/gbe/tomcat_gbe.vhd @@ -144,8 +144,13 @@ architecture arch of tomcat_gbe is signal debug : std_logic_vector(127 downto 0); + signal status : std_logic_vector(15 downto 0); + begin +------------------------------------------------------------------------------- +-- Important pins +------------------------------------------------------------------------------- PROGRAMN <= '1'; ------------------------------------------------------------------------------- @@ -191,7 +196,7 @@ begin ------------------------------------------------------------------------------- -- GbE interface ------------------------------------------------------------------------------- - GBE : entity work.gbe_wrapper_single_5G + GBE : entity work.gbe_wrapper_single generic map( DO_SIMULATION => 0, INCLUDE_DEBUG => 0, @@ -268,10 +273,10 @@ begin BUS_REG_RX => open, --busgbereg_rx, -- registers inside GbE BUS_REG_TX => open, --busgbereg_tx, -- registers inside GbE -- Forwarder - FWD_DST_MAC_IN => (others => '0), - FWD_DST_IP_IN => (others => '0), - FWD_DST_UDP_IN => (others => '0), - FWD_DATA_IN => (others => '0), + FWD_DST_MAC_IN => (others => '0'), + FWD_DST_IP_IN => (others => '0'), + FWD_DST_UDP_IN => (others => '0'), + FWD_DATA_IN => (others => '0'), FWD_DATA_VALID_IN => '0', FWD_SOP_IN => '0', FWD_EOP_IN => '0', @@ -280,7 +285,7 @@ begin -- reset MAKE_RESET_OUT => reset_via_gbe, -- reset by GbE -- debug and status - STATUS_OUT => open, + STATUS_OUT => status, DEBUG_OUT => debug --open ); @@ -301,13 +306,13 @@ begin ------------------------------------------------------------------------------- -- LED ------------------------------------------------------------------------------- - LED_SFP_GREEN <= not '0'; --sd_led_green; - LED_SFP_RED <= not '0'; --sd_led_red; - LED_SFP_YELLOW <= not '0'; --sd_led_yellow; + LED_SFP_GREEN <= not (status(0) and status(1) and status(2)); --'0'; + LED_SFP_YELLOW <= not (status(3) and status(4)); --'0'; + LED_SFP_RED <= not '0'; LED(3) <= not '0'; LED(2) <= not '0'; LED(1) <= not '0'; - LED(0) <= not '0'; + LED(0) <= not status(8); --'0'; -- 0 red -- 1 orange @@ -318,88 +323,4 @@ begin ----------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------- --- type CTRLBUS_TX is record --- data : std_logic_vector(31 downto 0); --- ack : std_logic; --- wack,rack : std_logic; --for the old-fashioned guys --- unknown : std_logic; --- nack : std_logic; --- end record; - --- type CTRLBUS_RX is record --- data : std_logic_vector(31 downto 0); --- addr : std_logic_vector(15 downto 0); --- write : std_logic; --- read : std_logic; --- timeout : std_logic; --- end record; - -------------------------------------------------------------------------------- --- Bus Handler -------------------------------------------------------------------------------- --- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record --- generic map( --- PORT_NUMBER => 4, --- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", others => x"0000"), --- PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, others => 0), --- PORT_MASK_ENABLE => 1 --- ) --- port map( --- CLK => clk_sys, --- RESET => reset_i, --- REGIO_RX => ctrlbus_rx, --- REGIO_TX => ctrlbus_tx, --- BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED --- BUS_RX(1) => bussci_rx, --SCI Serdes --- BUS_RX(2) => bustc_rx, --Clock switch --- BUS_TX(0) => bustools_tx, --- BUS_TX(1) => bussci_tx, --- BUS_TX(2) => bustc_tx, --- STAT_DEBUG => open --- ); - -------------------------------------------------------------------------------- --- Control Tools -------------------------------------------------------------------------------- --- THE_TOOLS : entity work.tomcat_tools --- port map( --- CLK => clk_sys, --- RESET => reset_i, --- --Flash & Reload --- FLASH_CS => flash_ncs_i, --- FLASH_CLK => flash_sclk_i, --- FLASH_IN => flash_miso_i, --- FLASH_OUT => flash_mosi_i, --- PROGRAMN => PROGRAMN, --- REBOOT_IN => common_ctrl_reg(15), --- -- I2C --- SDA_INOUT => SFP_MOD_2, --open, --I2C_SDA, --- SCL_INOUT => SFP_MOD_1, --open, --SI2C_SCL, --- -- Additional register --- ADDITIONAL_REG => additional_reg, --- --Slowcontrol --- BUS_RX => bustools_rx, --- BUS_TX => bustools_tx, --- --Control master for default settings --- BUS_MASTER_IN => bus_master_in, --- BUS_MASTER_OUT => bus_master_out, --- BUS_MASTER_ACTIVE => bus_master_active, --- DEBUG_OUT => debug_tools --- );- --- --- led_off <= additional_reg(0); --- --- -- FlashROM external connections --- FLASH_OVERRIDE <= not additional_reg(1); --- FLASH_HOLD <= '1'; --- FLASH_WP <= '1'; --- FLASH_NCS <= flash_ncs_i; --- FLASH_SCLK <= flash_sclk_i; --- FLASH_MOSI <= flash_mosi_i; --- flash_miso_i <= FLASH_MISO; --- --- -- Jan's proposal --- -- led_off <= additional_reg(0); --- -- FLASH_OVERRIDE <= not additional_reg(1); - end architecture;