From: Michael Boehmer Date: Fri, 29 Jul 2022 12:41:25 +0000 (+0200) Subject: better timing now X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ab77353d38fb1a7b10a9503a145236053612c77e;p=trb3sc.git better timing now --- diff --git a/gbe_hub/trb3sc_gbe_hub.prj b/gbe_hub/trb3sc_gbe_hub.prj index b5aa41b..ef67a3c 100644 --- a/gbe_hub/trb3sc_gbe_hub.prj +++ b/gbe_hub/trb3sc_gbe_hub.prj @@ -55,7 +55,7 @@ add_file -vhdl -lib work "workdir/version.vhd" add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +#add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" @@ -107,11 +107,11 @@ add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" add_file -vhdl -lib work "../../trbnet/special/uart.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +#add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" -add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" -add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +#add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +#add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd" add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd" add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd" @@ -132,7 +132,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" @@ -162,23 +162,22 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +#add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +#add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +#add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_standalone_sctrl.vhd" #Hub -add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_accel.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_accel.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" -add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd" - +#add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_accel.vhd" +#add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_accel.vhd" +#add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" +#add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" +#add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" +#add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" +#add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd" #GbE #add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_med_interface_single.vhd" @@ -196,8 +195,8 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" #add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index 72d7f86..f23c779 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -8,7 +8,7 @@ use work.config.all; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; -use work.trb_net16_hub_func.all; +--use work.trb_net16_hub_func.all; use work.version.all; use work.trb_net_gbe_components.all; use work.med_sync_define_RS.all; @@ -145,6 +145,8 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal dl_rx_fifofull : std_logic_vector(9 downto 0); signal dl_tx_data : std_logic_vector(10 downto 0); -- 1:2 MUX to DL (TX) signal dl_tx_fifofull : std_logic_vector(9 downto 0); + + signal dl_rx_data_q : dl_rx_data_t; -- 10: frame_start -- 9 : fifo_wr @@ -174,7 +176,7 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal switch_rx_data : std_logic_vector(10 downto 0); -- 1:n MUX to 1:2 MUXes - signal dl_rx_port_sel : std_logic_vector(9 downto 0); + signal dl_rx_port_mux : std_logic_vector(3 downto 0); signal ul_tx_port_sel : std_logic; signal dl_tx_port_sel : std_logic; signal local_tx_port_sel : std_logic; @@ -259,8 +261,8 @@ begin LOCAL_FRAME_REQ_OUT => local_rx_frame_req, -- LOCAL RX request to send LOCAL_FRAME_ACK_IN => local_rx_frame_ack, -- LOCAL RX sent acknowledge -- - DL_RX_PORT_SEL_OUT(9 downto 0) => dl_rx_port_sel, - DL_RX_PORT_MUX_OUT => open, + DL_RX_PORT_SEL_OUT(9 downto 0) => open, + DL_RX_PORT_MUX_OUT => dl_rx_port_mux, DL_TX_PORT_SEL_OUT => dl_tx_port_sel, LOCAL_TX_PORT_SEL_OUT => local_tx_port_sel, UL_TX_PORT_SEL_OUT => ul_tx_port_sel, @@ -268,23 +270,28 @@ begin DEBUG => open ); + --------------------------------------------------------------------------- -- Multiplexers for data streams --------------------------------------------------------------------------- - THE_DL_RX_MUX: process( dl_rx_port_sel, dl_rx_data ) + THE_PIPELINING: for I in 0 to 9 generate + dl_rx_data_q(I) <= dl_rx_data(I) when rising_edge(clk_sys); + end generate THE_PIPELINING; + + THE_DL_RX_MUX: process( dl_rx_port_mux, dl_rx_data_q ) begin - case dl_rx_port_sel is - when b"0000000001" => switch_rx_data <= dl_rx_data(0); - when b"0000000010" => switch_rx_data <= dl_rx_data(1); - when b"0000000100" => switch_rx_data <= dl_rx_data(2); - when b"0000001000" => switch_rx_data <= dl_rx_data(3); - when b"0000010000" => switch_rx_data <= dl_rx_data(4); - when b"0000100000" => switch_rx_data <= dl_rx_data(5); - when b"0001000000" => switch_rx_data <= dl_rx_data(6); - when b"0010000000" => switch_rx_data <= dl_rx_data(7); - when b"0100000000" => switch_rx_data <= dl_rx_data(8); - when b"1000000000" => switch_rx_data <= dl_rx_data(9); - when others => switch_rx_data <= (others => '0'); + case dl_rx_port_mux is + when x"0" => switch_rx_data <= dl_rx_data_q(0); + when x"1" => switch_rx_data <= dl_rx_data_q(1); + when x"2" => switch_rx_data <= dl_rx_data_q(2); + when x"3" => switch_rx_data <= dl_rx_data_q(3); + when x"4" => switch_rx_data <= dl_rx_data_q(4); + when x"5" => switch_rx_data <= dl_rx_data_q(5); + when x"6" => switch_rx_data <= dl_rx_data_q(6); + when x"7" => switch_rx_data <= dl_rx_data_q(7); + when x"8" => switch_rx_data <= dl_rx_data_q(8); + when x"9" => switch_rx_data <= dl_rx_data_q(9); + when others => switch_rx_data <= (others => '0'); end case; end process THE_DL_RX_MUX; @@ -293,7 +300,10 @@ begin local_tx_data <= ul_rx_data when local_tx_port_sel = '1' else switch_rx_data; dl_tx_data <= ul_rx_data when dl_tx_port_sel = '1' else local_rx_data; - + + -- Multiplexer could be like this: + -- switch_rx_data <= dl_rx_data(DL_RX_PORT_MUX_OUT); + --------------------------------------------------------------------------- -- Debug pins --------------------------------------------------------------------------- @@ -303,20 +313,20 @@ begin -- 8 : fifo_eof -- 7..0: data --- DBG(3 downto 0) <= port_sel(3 downto 0); --- DBG(11 downto 4) <= ul_rx_data(7 downto 0); --- DBG(19 downto 12) <= dl_rx_data(0)(7 downto 0); --- DBG(20) <= ul_rx_frame_avail; --- DBG(21) <= ul_rx_frame_req; --- DBG(22) <= ul_rx_frame_ack; --- DBG(23) <= dl_rx_data(0)(9); --- DBG(27 downto 24) <= dl_tx_fifofull(3 downto 0); --- DBG(28) <= debug(0); --ul_rx_data(8); --- DBG(29) <= ul_rx_data(9); --- DBG(30) <= debug(1); --ul_rx_data(10); --- DBG(31) <= ul_rx_fifofull; --- DBG(32) <= debug(2); --dl_rx_data(0)(8); --- DBG(33) <= clk_sys; + DBG(3 downto 0) <= dl_rx_port_mux; + DBG(11 downto 4) <= ul_rx_data(7 downto 0); + DBG(19 downto 12) <= dl_rx_data(0)(7 downto 0); + DBG(20) <= ul_rx_frame_avail; + DBG(21) <= ul_rx_frame_req; + DBG(22) <= ul_rx_frame_ack; + DBG(23) <= dl_rx_data(0)(9); + DBG(27 downto 24) <= dl_tx_fifofull(3 downto 0); + DBG(28) <= ul_rx_data(8); + DBG(29) <= ul_rx_data(9); + DBG(30) <= ul_rx_data(10); + DBG(31) <= ul_rx_fifofull; + DBG(32) <= dl_rx_data(0)(8); + DBG(33) <= clk_sys; --------------------------------------------------------------------------- -- GbE wrapper without med interface