From: Cahit Date: Fri, 4 Apr 2014 14:28:32 +0000 (+0200) Subject: cbmtof project is adjusted for compile script and config package X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ab8f7b871c0f8928261938612fb0c1f77b0282c5;p=trb3.git cbmtof project is adjusted for compile script and config package --- diff --git a/32PinAddOn/nodes_lxhadeb07.txt b/32PinAddOn/nodes_lxhadeb07.txt deleted file mode 100644 index 60c088a..0000000 --- a/32PinAddOn/nodes_lxhadeb07.txt +++ /dev/null @@ -1,9 +0,0 @@ -// nodes file for parallel place&route - -[lxhadeb07] -SYSTEM = linux -CORENUM = 32 -ENV = /u/cugur/depc363/bin/diamond_setup_x64.sh -//ENV = /u/cugur/depc363/bin/diamond_setup.sh -WORKDIR = /u/cugur/depc363/Projects/TDC_on_TRB3/trb3/32PinAddOn/workdir - diff --git a/cbmtof/cbmtof.prj b/cbmtof/cbmtof.prj new file mode 100644 index 0000000..3865736 --- /dev/null +++ b/cbmtof/cbmtof.prj @@ -0,0 +1,175 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN672C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "cbmtof" +set_option -resource_sharing true + +# map options +set_option -frequency 200 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 0 +#set_option -force_gsr +set_option -force_gsr false +set_option -fixgatedclocks false #3 +set_option -fixgeneratedclocks false #3 +set_option -compiler_compatible true + + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/cbmtof.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#add_file options + +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib "work" "../base/trb3_components.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" + +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" + +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" + +add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" + + + + +############### +#Change path to tdc release also in compile script! +############### + +#add_file -vhdl -lib "work" "currentRelease/Adder_304.vhd" +add_file -vhdl -lib "work" "currentRelease/bit_sync.vhd" +add_file -vhdl -lib "work" "currentRelease/BusHandler.vhd" +add_file -vhdl -lib "work" "currentRelease/Channel.vhd" +add_file -vhdl -lib "work" "currentRelease/Channel_200.vhd" +add_file -vhdl -lib "work" "currentRelease/Encoder_304_Bit.vhd" +add_file -vhdl -lib "work" "currentRelease/LogicAnalyser.vhd" +add_file -vhdl -lib "work" "currentRelease/Readout.vhd" +#add_file -vhdl -lib "work" "currentRelease/ROM4_Encoder.vhd" +add_file -vhdl -lib "work" "currentRelease/ROM_encoder_3.vhd" +add_file -vhdl -lib "work" "currentRelease/ShiftRegisterSISO.vhd" +add_file -vhdl -lib "work" "currentRelease/TDC.vhd" +add_file -vhdl -lib "work" "currentRelease/TriggerHandler.vhd" +add_file -vhdl -lib "work" "currentRelease/up_counter.vhd" +add_file -vhdl -lib "work" "currentRelease/fallingEdgeDetect.vhd" +add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd" +add_file -vhdl -lib "work" "currentRelease/hit_mux.vhd" +add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd" +add_file -vhdl -lib "work" "../base/code/input_statistics.vhd" + + + +add_file -vhdl -lib "work" "cbmtof.vhd" + diff --git a/cbmtof/cbmtof.vhd b/cbmtof/cbmtof.vhd index 296f8c3..4d8e411 100644 --- a/cbmtof/cbmtof.vhd +++ b/cbmtof/cbmtof.vhd @@ -6,6 +6,7 @@ library work; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; +use work.config.all; use work.version.all; @@ -13,9 +14,9 @@ use work.version.all; entity cbmtof is port( --Clocks - CLK_OSC : in std_logic; --for tdc measurements --200MHz + CLK_OSC : in std_logic; --for tdc measurements --200MHz CLK_CM : in std_logic_vector(8 downto 0); --from clock manager --125MHz - CLK_EXT : in std_logic; --from CK_IN1 connection + CLK_EXT : in std_logic; --from CK_IN1 connection --Serdes --CLK_SERDES_INT_RIGHT : in std_logic; @@ -251,13 +252,31 @@ architecture cbmtof_arch of cbmtof is signal tdc_ctrl_addr : std_logic_vector(2 downto 0); signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); - signal tdc_ctrl_reg : std_logic_vector(5*32-1 downto 0); + signal tdc_ctrl_reg : std_logic_vector(6*32-1 downto 0); signal spi_bram_addr : std_logic_vector(7 downto 0); signal spi_bram_wr_d : std_logic_vector(7 downto 0); signal spi_bram_rd_d : std_logic_vector(7 downto 0); signal spi_bram_we : std_logic; + signal trig_out : std_logic_vector(3 downto 0); + signal trig_din : std_logic_vector(31 downto 0); + signal trig_dout : std_logic_vector(31 downto 0); + signal trig_write : std_logic := '0'; + signal trig_read : std_logic := '0'; + signal trig_ack : std_logic := '0'; + signal trig_nack : std_logic := '0'; + signal trig_addr : std_logic_vector(15 downto 0) := (others => '0'); + + signal stat_out : std_logic_vector(3 downto 0); + signal stat_din : std_logic_vector(31 downto 0); + signal stat_dout : std_logic_vector(31 downto 0); + signal stat_write : std_logic := '0'; + signal stat_read : std_logic := '0'; + signal stat_ack : std_logic := '0'; + signal stat_nack : std_logic := '0'; + signal stat_addr : std_logic_vector(15 downto 0) := (others => '0'); + --FPGA Test signal time_counter : unsigned(31 downto 0); @@ -297,7 +316,7 @@ begin THE_MAIN_PLL : pll_in200_out100 port map( - CLK => CLK_OSC, --CLK_CM(4), + CLK => CLK_OSC, --CLK_CM(4), CLKOP => clk_100_i, CLKOK => clk_200_i, CLKOS => open, @@ -309,7 +328,7 @@ begin port map ( CLK => CLK_CM(4), CLKOP => clk_20_i, - CLKOK => open, --clk_125_i, + CLKOK => open, --clk_125_i, LOCK => open); @@ -361,30 +380,19 @@ begin --------------------------------------------------------------------------- -- Endpoint --------------------------------------------------------------------------- - --regio_hardware_version_i <= x"9100" & addOn_type_i & edge_type_i & tdc_channel_no_i & x"0"; - - --addOn_type_i <= x"0"; -- x"0" - ADA AddOn version 1 - -- -- x"1" - ADA AddOn version 2 - -- -- x"2" - multi purpose test AddOn - -- -- x"3" - SFP hub AddOn - -- -- x"4" - Wasa AddOn - --edge_type_i <= x"0"; -- x"0" - single edge - -- -- x"1" - double edge - -- -- x"8" - double edge on consecutive channels - --tdc_channel_no_i <= x"6"; -- 2^n channels THE_ENDPOINT : trb_net16_endpoint_hades_full_handler generic map( - REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg - REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg + REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, + REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, ADDRESS_MASK => x"FFFF", BROADCAST_BITMASK => x"FF", - BROADCAST_SPECIAL_ADDR => x"50", + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => x"93000860", - REGIO_INIT_ADDRESS => x"f300", + REGIO_HARDWARE_VERSION => HARDWARE_INFO, + REGIO_INIT_ADDRESS => INIT_ADDRESS, REGIO_USE_VAR_ENDPOINT_ID => c_YES, - CLOCK_FREQUENCY => 100, + CLOCK_FREQUENCY => CLOCK_FREQUENCY, TIMING_TRIGGER_RAW => c_YES, --Configure data handler DATA_INTERFACE_NUMBER => 1, @@ -491,9 +499,13 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 9, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, others => 0) + PORT_NUMBER => 11, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", + 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", 9 => x"cf00", + 10 => x"cf80", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, + 5 => 7, 6 => 7, 7 => 7, 8 => 3, 9 => 6, + 10 => 7, others => 0) ) port map( CLK => clk_100_i, @@ -618,6 +630,28 @@ begin BUS_WRITE_ACK_IN(8) => tdc_ctrl_write, BUS_NO_MORE_DATA_IN(8) => '0', BUS_UNKNOWN_ADDR_IN(8) => '0', + --Trigger logic registers + BUS_READ_ENABLE_OUT(9) => trig_read, + BUS_WRITE_ENABLE_OUT(9) => trig_write, + BUS_DATA_OUT(9*32+31 downto 9*32) => trig_din, + BUS_ADDR_OUT(9*16+15 downto 9*16) => trig_addr, + BUS_TIMEOUT_OUT(9) => open, + BUS_DATA_IN(9*32+31 downto 9*32) => trig_dout, + BUS_DATAREADY_IN(9) => trig_ack, + BUS_WRITE_ACK_IN(9) => trig_ack, + BUS_NO_MORE_DATA_IN(9) => '0', + BUS_UNKNOWN_ADDR_IN(9) => trig_nack, + --Input statistics + BUS_READ_ENABLE_OUT(10) => stat_read, + BUS_WRITE_ENABLE_OUT(10) => stat_write, + BUS_DATA_OUT(10*32+31 downto 10*32) => stat_din, + BUS_ADDR_OUT(10*16+15 downto 10*16) => stat_addr, + BUS_TIMEOUT_OUT(10) => open, + BUS_DATA_IN(10*32+31 downto 10*32) => stat_dout, + BUS_DATAREADY_IN(10) => stat_ack, + BUS_WRITE_ACK_IN(10) => stat_ack, + BUS_NO_MORE_DATA_IN(10) => '0', + BUS_UNKNOWN_ADDR_IN(10) => stat_nack, STAT_DEBUG => open ); @@ -688,29 +722,81 @@ begin --------------------------------------------------------------------------- -- DAC --------------------------------------------------------------------------- - THE_DAC_SPI : spi_ltc2600 - generic map ( - BITS => 14, - WAITCYCLES => 15) - port map( - CLK_IN => clk_100_i, - RESET_IN => reset_i, - -- Slave bus - BUS_ADDR_IN => dac_addr, - BUS_READ_IN => dac_read_en, - BUS_WRITE_IN => dac_write_en, - BUS_ACK_OUT => dac_ack, - BUS_BUSY_OUT => dac_busy, - BUS_DATA_IN => dac_data_in, - BUS_DATA_OUT => dac_data_out, - -- SPI connections - SPI_CS_OUT(0) => DAC_CS, - SPI_SDI_IN => DAC_SDO, - SPI_SDO_OUT => DAC_SDI, - SPI_SCK_OUT => DAC_SCK, - SPI_CLR_OUT(0) => DAC_CLR - ); - + gen_SPI : if INCLUDE_SPI = 1 generate + THE_DAC_SPI : spi_ltc2600 + generic map ( + BITS => 14, + WAITCYCLES => 15) + port map( + CLK_IN => clk_100_i, + RESET_IN => reset_i, + -- Slave bus + BUS_ADDR_IN => dac_addr, + BUS_READ_IN => dac_read_en, + BUS_WRITE_IN => dac_write_en, + BUS_ACK_OUT => dac_ack, + BUS_BUSY_OUT => dac_busy, + BUS_DATA_IN => dac_data_in, + BUS_DATA_OUT => dac_data_out, + -- SPI connections + SPI_CS_OUT(0) => DAC_CS, + SPI_SDI_IN => DAC_SDO, + SPI_SDO_OUT => DAC_SDI, + SPI_SCK_OUT => DAC_SCK, + SPI_CLR_OUT(0) => DAC_CLR + ); + end generate; + +--------------------------------------------------------------------------- +-- Trigger logic +--------------------------------------------------------------------------- + gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate + THE_TRIG_LOGIC : input_to_trigger_logic + generic map( + INPUTS => 32, + OUTPUTS => 4 + ) + port map( + CLK => clk_100_i, + + INPUT => INPUT(32 downto 1), + OUTPUT => trig_out, + + DATA_IN => trig_din, + DATA_OUT => trig_dout, + WRITE_IN => trig_write, + READ_IN => trig_read, + ACK_OUT => trig_ack, + NACK_OUT => trig_nack, + ADDR_IN => trig_addr + ); +-- FPGA5_COMM(10 downto 7) <= trig_out; + end generate; + +--------------------------------------------------------------------------- +-- Input Statistics +--------------------------------------------------------------------------- + gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate + + THE_STAT_LOGIC : entity work.input_statistics + generic map( + INPUTS => PHYSICAL_INPUTS + ) + port map( + CLK => clk_100_i, + + INPUT => INPUT(PHYSICAL_INPUTS-1 downto 0), + + DATA_IN => stat_din, + DATA_OUT => stat_dout, + WRITE_IN => stat_write, + READ_IN => stat_read, + ACK_OUT => stat_ack, + NACK_OUT => stat_nack, + ADDR_IN => stat_addr + ); + end generate; + --------------------------------------------------------------------------- -- Reboot FPGA --------------------------------------------------------------------------- @@ -741,7 +827,7 @@ begin TEST_LINE(11 downto 10) <= SFP_MOD(2 downto 1); TEST_LINE(13 downto 12) <= SPARE_LINE(2 downto 1); TEST_LINE(31 downto 14) <= time_counter(31 downto 14); - + LVDS(1) <= or_all(INPUT); LVDS(2) <= SPARE_LINE(0); -- CLK_MNGR_USER(3 downto 0) <= (others => '0'); @@ -751,7 +837,7 @@ begin --------------------------------------------------------------------------- process begin - wait until rising_edge(CLK_EXT);--(clk_100_i); + wait until rising_edge(CLK_EXT); --(clk_100_i); time_counter <= time_counter + 1; end process; @@ -760,16 +846,19 @@ begin ------------------------------------------------------------------------------- THE_TDC : TDC generic map ( - CHANNEL_NUMBER => 65, -- Number of TDC channels - CONTROL_REG_NR => 5, -- Number of control regs - TDC_VERSION => "001" & x"51") -- TDC version numberTDC_VERSION => "001" & x"51") -- TDC version number + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels + STATUS_REG_NR => 20, -- Number of status regs + CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr + TDC_VERSION => TDC_VERSION, -- TDC version number + DEBUG => c_YES, + SIMULATION => c_NO) port map ( RESET => reset_i, CLK_TDC => CLK_OSC, -- Oscillator used for the time measurement -- CLK_TDC => CLK_EXT, -- External Clock used for the time measurement CLK_READOUT => clk_100_i, -- Clock for the readout - REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(64 downto 1), -- Channel start signals + REFERENCE_TIME => timing_trg_received_i, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals HIT_CALIBRATION => clk_20_i, -- Hits for calibrating the TDC TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width @@ -835,19 +924,17 @@ begin LOGIC_ANALYSER_OUT => logic_analyser_i, CONTROL_REG_IN => tdc_ctrl_reg); - - --- hit_in_i <= INPUT; - - -- to detect rising & falling edges - Gen_Hit_In_Signals : for i in 1 to 32 generate - hit_in_i(i*2-1) <= INPUT(i); - hit_in_i(i*2) <= not INPUT(i); - end generate Gen_Hit_In_Signals; - - --Gen_Hit_In_Signals : for i in 1 to 2 generate - -- hit_in_i(i*2-1) <= SPARE_LINE(i); - -- hit_in_i(i*2) <= not SPARE_LINE(i); - --end generate Gen_Hit_In_Signals; + -- For single edge measurements + gen_single : if USE_DOUBLE_EDGE = 0 generate + hit_in_i <= INPUT; + end generate; + + -- For ToT Measurements + gen_double : if USE_DOUBLE_EDGE = 1 generate + Gen_Hit_In_Signals : for i in 1 to 32 generate + hit_in_i(i*2-1) <= INPUT(i); + hit_in_i(i*2) <= not INPUT(i); + end generate Gen_Hit_In_Signals; + end generate; end architecture; diff --git a/cbmtof/compile_cbmtof_gsi.pl b/cbmtof/compile_cbmtof_gsi.pl new file mode 100755 index 0000000..a32db13 --- /dev/null +++ b/cbmtof/compile_cbmtof_gsi.pl @@ -0,0 +1,294 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; +use FileHandle; +use Getopt::Long; + +################################################################################### +#Settings for this project +my $TOPNAME = "cbmtof"; #Name of top-level entity +my $lattice_path = '/opt/lattice/diamond/3.0_x64/'; +my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed +my $synplify_path = '/opt/synplicity/I-2013.09-SP1'; +#my $lattice_path = '/opt/lattice/diamond/2.01/'; +#my $lattice_bin_path = "$lattice_path/bin/lin"; # note the lin/lin64 at the end, no isfgpa needed +#my $synplify_path = '/opt/synplicity/F-2012.03-SP1'; +my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; +my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; +################################################################################### + +################################################################################### +#Options for the script +my $help = ""; +my $isMultiPar = 0; # set it to zero for single par run on the local machine +my $nrNodes = 0; # set it to one for single par run on the local machine +my $all = 1; +my $syn = 0; +my $map = 0; +my $par = 0; +my $timing = 0; +my $bitgen = 0; + +my $result = GetOptions ( + "h|help" => \$help, + "m|mpar=i" => \$nrNodes, + "a|all" => \$all, + "s|syn" => \$syn, + "mp|map" => \$map, + "p|par" => \$par, + "t|timing" => \$timing, + "b|bitgen" => \$bitgen, + ); + +if($help) { + print "Usage: compile_priph_gsi.de \n\n"; + print "-h --help\tPrints the usage manual.\n"; + print "-a --all\tRun all compile script. By default the script is going to rung the whole process.\n"; + print "-s --syn\tRun synthesis part of the compile script.\n"; + print "-mp --map\tRun map part of the compile script.\n"; + print "-p --par\tRun par part of the compile script.\n"; + print "-t --timing\tRun timing analysis part of the compile script.\n"; + print "-b --bitgen\tRun bit generation part of the compile script.\n"; + print "-m --mpar\tSwitch for multi par. \"-m \" (Default = off)\n"; + print "\t\tThe node list file name has to be edited in the script. (Default = nodes_lxhadeb07.txt)\n"; + print "\n"; + exit; +} + +if ($nrNodes!=0){ + $isMultiPar=1; +} +if ($syn!=0 || $map!=0 || $par!=0 || $timing!=0 || $bitgen!=0){ + $all=0; +} +################################################################################### + + + +# source the standard lattice environment +$ENV{bindir}="$lattice_bin_path"; +open my $SOURCE, "bash -c '. $lattice_bin_path/diamond_env >& /dev/null; env'|" or + die "Can't fork: $!"; +while (<$SOURCE>) { + if (/^(.*)=(.*)/) { + $ENV{$1} = ${2} ; + } +} +close $SOURCE; + + +$ENV{'PAR_DESIGN_NAME'}=$TOPNAME; +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; + + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA672"; +my $SPEEDGRADE="8"; + +my $WORKDIR = "workdir"; +unless(-d $WORKDIR) { + mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!"; +} + +system("ln -sfT $lattice_path $WORKDIR/lattice-diamond"); + +#create full lpf file +system("cp ../base/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf"); +system("cat currentRelease/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); +system("cat currentRelease/tdc_constraints_64.lpf >> $WORKDIR/$TOPNAME.lpf"); + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; +my $c = ""; +my @a = (); +my $tpmap = $TOPNAME . "_map" ; + +if($syn==1 || $all==1){ + $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; + $r=execute($c, "do_not_exit" ); +} + +chdir $WORKDIR; + +if($syn==1 || $all==1){ + $fh = new FileHandle("<$TOPNAME".".srr"); + @a = <$fh>; + $fh -> close; + + foreach (@a) + { + if(/\@E:/) + { + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); + print "\n\n"; + exit 129; + } + } +} + +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + +if($map==1 || $all==1){ + $c=qq| edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; + execute($c); + + $c=qq|edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; + execute($c); + + $c=qq|ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; + execute($c); + + $c=qq|map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; + execute($c); + + $c=qq|htmlrpt -mrp $TOPNAME.mrp $TOPNAME|; + execute($c); + + $fh = new FileHandle("<$TOPNAME"."_mrp.html"); + @a = <$fh>; + $fh -> close; + foreach (@a) + { + if(/FC_|HitInvert|ff_en_/) + { + print "\n\n"; + print "#################################################\n"; + print "# !!!Possible Placement Errors!!! #\n"; + print "#################################################\n\n"; + + my $c="egrep 'WARNING.*hitBuf_|Channels/hit_buf_RNO|WARNING.*FC_|Channels/Channel200/SimAdderNo_FC|WARNING.*ff_en_|Channels/Channel200/ff_array_en_i_1_i' trb3_periph_padiwa_mrp.html"; + system($c); + last; + } + } +} + +if($par==1 || $all==1){ + system("rm $TOPNAME.ncd"); + #$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|; + #$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; + if ($isMultiPar) + { + #$c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -stopzero -w -l 5 -t 1 -e 100 -exp parDisablePgroup=0:parUseNBR=1:parCDP=1:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + #$c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -stopzero -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parDisablePgroup=0:parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + $c=qq|par -m ../nodes_lxhadeb07.txt -n $nrNodes -w -l 5 -t 1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + execute($c); + # find and copy the .ncd file which has met the timing constraints + $fh = new FileHandle("<$TOPNAME".".par"); + my @a = <$fh>; + my $isSuccess = 0; + $fh -> close; + foreach (@a) + { + my @line = split(' ', $_); + if(@line && ($line[2] =~ m/^[0-9]+$/) && ($line[3] =~ m/^[0-9]+$/)) + { + if(($line[2] == 0) && ($line[3] == 0)) + { + print "Copying $line[0].ncd file to workdir\n"; + my $c="cp $TOPNAME.dir/$line[0].ncd $TOPNAME.ncd"; + system($c); + print "\n\n"; + $isSuccess = 1; + last; + } + } + } + + if (!$isSuccess){ + print "\n\n"; + print "#################################################\n"; + print "# !!!PAR not succesfull!!! #\n"; + print "#################################################\n\n"; + exit 129; + } + } + else + { + $c=qq|par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=ON $tpmap.ncd $TOPNAME.dir $TOPNAME.prf|; + execute($c); + my $c="cp $TOPNAME.dir/5_1.ncd $TOPNAME.ncd"; + system($c); + } + my $c="cat $TOPNAME.par"; + system($c); + +} + + +if($timing==1){ + # IOR IO Timing Report + $c=qq|iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); + + # TWR Timing Report + $c=qq|trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); + + $c=qq|trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); + + $c=qq|ltxt2ptxt $TOPNAME.ncd|; + execute($c); + + my $c="cat $TOPNAME.par"; + system($c); + + $c=qq|htmlrpt -ptwr $TOPNAME.twr.setup $TOPNAME|; + execute($c); + + $c=qq|firefox $TOPNAME.html|; + execute($c); + +} + +if($bitgen==1 || $all==1){ + $c=qq|bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; + # $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; + execute($c); +} + +chdir ".."; +exit; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + $op = "" if(!$op); + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + return $r; +} diff --git a/cbmtof/config.vhd b/cbmtof/config.vhd new file mode 100644 index 0000000..a2d3212 --- /dev/null +++ b/cbmtof/config.vhd @@ -0,0 +1,77 @@ +library ieee; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + +--Include GbE logic + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 65; + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons + constant TDC_VERSION : std_logic_vector(11 downto 0) := x"160"; + constant USE_DOUBLE_EDGE : integer := c_YES; + +--Include SPI on AddOn connector + constant INCLUDE_SPI : integer := c_YES; + +--Add logic to generate configurable trigger signal from input signals. + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --not compatible with cbmtof! + +--Do histos of all inputs + constant INCLUDE_STATISTICS : integer := c_NO; + +--number of real inputs to the FPGA + constant PHYSICAL_INPUTS : integer := 32; + +--Run wih 125 MHz instead of 100 MHz + constant USE_125_MHZ : integer := c_NO; --not implemented yet! + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; --not implemented yet! + + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F300"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"50"; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"9300f000"; + constant HW_INFO_SPI : hw_info_t := (x"00000000", x"00000400", others => x"00000000"); + constant HW_INFO_DOUBLE_EDGE : hw_info_t := (x"00000000", x"00000800", others => x"00000000"); + constant HW_INFO_NUM_CHANS : hw_info_t := (x"00000000", x"00000010", x"00000020", x"00000030", + x"00000040", x"00000050", x"00000060", x"00000070", + others => x"00000000"); + constant CLOCK_FREQUENCY_ARR : intlist_t := (100, 125, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200, 125, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE + HW_INFO_SPI(INCLUDE_SPI) + HW_INFO_DOUBLE_EDGE(USE_DOUBLE_EDGE) + + HW_INFO_NUM_CHANS(NUM_TDC_CHANNELS_POWER2)); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ); + +end package body;