From: Adrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Date: Thu, 18 Nov 2021 13:27:14 +0000 (+0100)
Subject: add separate reset signal to DCA communication (DCA-Trbnet bridge)
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=abd929c0edf45ae8e63487fd3348f1d0a2f0dbcb;p=cri.git

add separate reset signal to DCA communication (DCA-Trbnet bridge)
---

diff --git a/src/cri_trbnet_dca_bridge.vhd b/src/cri_trbnet_dca_bridge.vhd
index b0c9d9f..662ced0 100644
--- a/src/cri_trbnet_dca_bridge.vhd
+++ b/src/cri_trbnet_dca_bridge.vhd
@@ -131,6 +131,9 @@ signal wait_dca, wait_dca_sync : std_logic := '0';
 
 signal reset_timeout           : std_logic_vector( 4 downto 0);
 
+signal dca_trb_reset           : std_logic;
+signal dca_trb_reset_nosync    : std_logic;
+
 begin
   reset_dca <= not RST_N_DCA;
 
@@ -157,6 +160,7 @@ begin
     TX_DATA_SIZE       => tx_data_size_dca,
     TX_READ_SIZE_ACK   => tx_rd_size_ack,
     
+    DCA_TRB_RESET      => dca_trb_reset_nosync,
     
     --WB_RESPONSE_READY_IN => WB_RESPONSE_READY,
 
@@ -209,6 +213,17 @@ THE_SYNC_RX_DATA : entity work.signal_sync
    PULSE_B_OUT => rx_data_wr_sync_i
  );
  
+ THE_SYNC_DCA_TRB_RESET_STB : entity work.pulse_sync
+ port map(
+   RESET_A_IN  => reset_dca,
+   CLK_A_IN    => CLK_DCA,
+   PULSE_A_IN  => dca_trb_reset_nosync,
+
+   RESET_B_IN  => RESET,
+   CLK_B_IN    => CLK,
+   PULSE_B_OUT => dca_trb_reset
+ );
+
  rx_data_wr_sync <= rx_data_wr_sync_i when reset_timeout(4) = '1'
                     else '0'; 
  
@@ -641,12 +656,16 @@ end process DISSECT_MACHINE;
 RESET_DETECTED_PROC : process(CLK)
 begin
   if rising_edge(CLK) then
-    if (dissect_current_state = IDLE) then
-      reset_detected <= '0';
-    elsif (rx_data_dca_sync(15 downto 8) = x"80" and rx_data_wr_sync = '1' and saved_hdr_ctr = "0010") then
+    if (dca_trb_reset = '1') then
       reset_detected <= '1';
     else
-      reset_detected <= reset_detected;
+      if (dissect_current_state = IDLE) then
+        reset_detected <= '0';
+      elsif (rx_data_dca_sync(15 downto 8) = x"80" and rx_data_wr_sync = '1' and saved_hdr_ctr = "0010") then
+        reset_detected <= '1';
+      else
+        reset_detected <= reset_detected;
+      end if;
     end if;
   end if;
 end process RESET_DETECTED_PROC;
@@ -656,6 +675,8 @@ begin
   if rising_edge(CLK) then
     if (dissect_current_state = IDLE) then
       make_reset <= '0';
+    elsif (dca_trb_reset = '1') then
+      make_reset <= '1';
     elsif (dissect_current_state = CLEANUP and reset_detected = '1') then
       make_reset <= '1';
     else
diff --git a/src/cri_trbnet_dca_bridge_handler.vhd b/src/cri_trbnet_dca_bridge_handler.vhd
index d95177d..dd24194 100644
--- a/src/cri_trbnet_dca_bridge_handler.vhd
+++ b/src/cri_trbnet_dca_bridge_handler.vhd
@@ -32,7 +32,9 @@ entity cri_trbnet_dca_bridge_handler is
     TX_DATA_IN       : in  std_logic_vector(31 downto 0);
     
     TX_DATA_SIZE     : in  std_logic_vector(15 downto 0); -- in byte
-    TX_READ_SIZE_ACK : out std_logic;   
+    TX_READ_SIZE_ACK : out std_logic;
+
+    DCA_TRB_RESET    : out std_logic;
 
     DEBUG_OUT        : out std_logic_vector(63 downto 0)
   );
@@ -108,6 +110,9 @@ GEN_AGWB_HANDLER_REAL: if SIMULATION = c_NO generate
     TX_SIZE_i(15 downto  0) => TX_DATA_SIZE,
     TX_SIZE_i_ack           => TX_READ_SIZE_ACK,
 
+    DCA_TRB_RESET_o         => open,
+    DCA_TRB_RESET_o_stb     => DCA_TRB_RESET,
+
     rst_n_i                 => RST_N,
     clk_sys_i               => CLK_DCA
   );