From: Jan Michel Date: Wed, 19 Sep 2018 11:37:02 +0000 (+0200) Subject: TDC doesn't repeat epoch markers for each channel, only when they changed. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ac143fb9e2e91acff7ec4cc6c97e9cff7c3cc16e;p=tdc.git TDC doesn't repeat epoch markers for each channel, only when they changed. --- diff --git a/releases/tdc_v2.3/Readout_record.vhd b/releases/tdc_v2.3/Readout_record.vhd index b7bfaab..4ad4e52 100644 --- a/releases/tdc_v2.3/Readout_record.vhd +++ b/releases/tdc_v2.3/Readout_record.vhd @@ -185,7 +185,7 @@ architecture behavioral of Readout_record is signal readout_time_up : std_logic; signal wait_time_up : std_logic; signal wrong_readout_up : std_logic; - signal finished : std_logic; +-- signal finished : std_logic; -- control signal sync_q : std_logic_vector((CHANNEL_NUMBER-2)*3+2 downto 0); signal isNoHit : std_logic := '1'; @@ -205,6 +205,9 @@ architecture behavioral of Readout_record is signal history_wr_fsm : std_logic_vector(31 downto 0) := (others => '0'); -- signal any_hit : std_logic := '0'; signal data_format_i : std_logic_vector(3 downto 0); + signal last_epoch : std_logic_vector(15 downto 0) := (others => '0'); + signal is_new_epoch : std_logic := '0'; + signal last_epoch_valid : std_logic := '0'; begin -- behavioral DATA_FORMAT_0 : if TDC_DATA_FORMAT = 0 generate @@ -667,9 +670,20 @@ begin -- behavioral wr_info <= wr_header or wr_status or wr_trailer when rising_edge(CLK_100); wr_time <= wr_ch_data_r and ch_data_4r(31) when rising_edge(CLK_100); - wr_epoch <= wr_ch_data_r and not data_out_r(31) and data_out_r(30) and data_out_r(29) and ch_data_4r(31); - + wr_epoch <= wr_ch_data_r and not data_out_r(31) and data_out_r(30) and data_out_r(29) and ch_data_4r(31) and is_new_epoch; + is_new_epoch <= not last_epoch_valid when data_out_r(15 downto 0) = last_epoch else '1'; + + PROC_LAST_EPCH : process begin + wait until rising_edge(CLK_100); + if wr_epoch = '1' then + last_epoch <= data_out_r(15 downto 0); + last_epoch_valid <= '1'; + elsif data_finished = '1' then + last_epoch_valid <= '0'; + end if; + end process; + READOUT_TX.data <= data_out_r when rising_edge(CLK_100); READOUT_TX.data_write <= wr_info or wr_time or wr_epoch when rising_edge(CLK_100); READOUT_TX.data_finished <= data_finished when rising_edge(CLK_100); @@ -680,7 +694,7 @@ begin -- behavioral READOUT_DEBUG(3 downto 0) <= rd_fsm_debug; READOUT_DEBUG(7 downto 4) <= wr_fsm_debug; READOUT_DEBUG(8) <= data_wr_r; - READOUT_DEBUG(9) <= finished; +-- READOUT_DEBUG(9) <= finished; READOUT_DEBUG(10) <= trg_release; READOUT_DEBUG(16 downto 11) <= data_out_r(27 downto 22); READOUT_DEBUG(31 downto 17) <= (others => '0');