From: Jan Michel Date: Wed, 27 May 2015 17:52:23 +0000 (+0200) Subject: added first information about TRB3sc X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=acb01680aac6ae60c0d35d3d3e1401f257109fdb;p=daqdocu.git added first information about TRB3sc --- diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex index 008125e..77acbd3 100644 --- a/trb3/Trb3GeneralRemarks.tex +++ b/trb3/Trb3GeneralRemarks.tex @@ -66,6 +66,7 @@ The TrbNet endpoint has a generic setting \signal{Regio\_Hardware\_Version} (reg \item[9140] design is for FPGA 4 only \item[9200] design for CBM Rich \item[9300] design for CBM Tof + \item[9500] design for Trb3sc \end{description*} The lower 16 Bit are used to identify the contents of the design and the AddOn boards they should be used with. Combine @@ -145,6 +146,7 @@ All boards of a given type are accessible by a broadcast address at the same tim \item 0x4d peripheral FPGA for MAPS read-out \item 0x4e peripheral FPGA for Hades Start detector \item 0x50 CBM-Rich + \item 0x60 Trb3sc \end{itemize*} The initial address set with \signal{Regio\_Init\_Address} can be chosen from the following set: @@ -153,6 +155,8 @@ The initial address set with \signal{Regio\_Init\_Address} can be chosen from th \item 0xF305 for the peripheral FPGA \item 0xF30n for a design for FPGA n only \item 0xF3C0 default for a design with CTS + \item 0xF350 default for master Trb3sc + \item 0xF351 default for slave TRB3sc \end{itemize*} diff --git a/trb3/Trb3scBasics.tex b/trb3/Trb3scBasics.tex new file mode 100644 index 0000000..ed9a83b --- /dev/null +++ b/trb3/Trb3scBasics.tex @@ -0,0 +1,109 @@ + \begin{figure} + \begin{center} + \includegraphics[width=0.7\textwidth]{figures/trb3scfrontpanel.png} + \caption[Trb3sc Front Panel]{Connections and LEDs on the Trb3sc front-panel} + \label{fig:trb3scfrontpanel} + \end{center} + \end{figure} + + +\subsubsection{Powering Schemes} +\begin{description*} + \item[External 5V] Connect a 1.5A power supply with not more than 5.5V to the black 3pin input. + \item[Backplane 5V] Connect a fitting power supply to the backplane. See the backplane description for further details. DC/DC converters are bypassed for lower noise. Power-LEDs will be off. + \item[External 3.5V/1.4V] Remove jumpers J12, J14 and J16. Connect a 1A power supply with 3.5-4.0V and 2A 1.4-1.7V to the black 4pin input. The 2.7V rail can be powered individually or connected to the 3.5V rail. + \item[Backplane 3.5V/1.4V] Remove jumpers J12, J14 and J16. Close fuses F1V2L, F3V3L and F2V5L. Connect a proper power supply to the backplane. DC/DC converters are bypassed for lower noise. Power-LEDs will be off. +\end{description*} + + +\subsubsection{Clock Inputs} +The current system clock configuration is shown on two LEDs on the front-panel. +\begin{itemize*} + \item The board has own 240 MHz and 125 MHz oscillators. The internal 240 MHz will be selected if there is no external clock available at power-up. + \item A external clock can be fed in via the RJ-45 connector (left, pair 2) or from the backplane. The source is selected with a switch. At power-up the board searches for an external clock on the selected input. If none is found, the internal is used. + \item The system clock can be recovered from the SFP1 input signal. This is selected at compile-time. +\end{itemize*} + +\subsubsection{Trigger Input/Output} +\begin{itemize*} + \item The default trigger input is pair 1 on the left RJ-45 on the front-panel + \item The front-panel trigger input can be rerouted to the second RJ-45 if separation of trigger and clock is required. + \item The trigger can be supplied from the backpanel, selected by the switch (same as clock setting) +\end{itemize*} + +\subsubsection{Other I/O} +JGPIO is available for any general purpose I/O. All lines are LVCMOS25. By default, SPI and UART are available: +\begin{center} + \begin{tabular}{|l|l|} + \hline + Pin & Usage \\ + \hline + 1 & UART TX\\ + 2 & UART RX\\ + 3 & SPI MOSI\\ + 4 & SPI MISO\\ + 5 & SPI CLK\\ + 6 & SPI CE\\ + 7 & \\ + 8 & \\ + 9 & \\ + 10 & 3.3V\\ + 11 & 3.3V\\ + 12 & GND\\ + 13 & GND\\ + \hline + \end{tabular} +\end{center} + +\subsubsection{Serial Links} +By default, SFP1 is used for GbE, SFP2 for TrbNet. SFP2 must be removed if the board is to be used on a backplane as slave module. Removing the SFP selects the backpanel as TrbNet input. + + + %--Serdes: Backplane + %--Backplane A2,A3,A0,A1 Slave 3,4,1,2, A0: TrbNet from backplane + %--AddOn C2,C3,C0,C1,B0,B1,B2,D1(B3) Slave --,--,5,9,8,7,6,-- + %--SFP D0,B3(D1) D0: GbE, B3: TrbNet + +By default, the use of Serdes channels is as follows: +\begin{center} + \begin{tabularx}{\textwidth}{|l|l|X|} + \hline + Block & Channel & Usage \\ + \hline + \multirow{4}{*}{A} + & 0 & Backplane, Master: TrbNet to Slave 1, Slaves: TrbNet input from backplane\\ + & 1 & Backplane, Master: TrbNet to Slave 2\\ + & 2 & Backplane, Master: TrbNet to Slave 3\\ + & 3 & Backplane, Master: TrbNet to Slave 4\\ + \hline + \multirow{4}{*}{B} + & 0 & AddOn Connector, Master: TrbNet to Slave 8\\ + & 1 & AddOn Connector, Master: TrbNet to Slave 7\\ + & 2 & AddOn Connector, Master: TrbNet to Slave 6\\ + & 3 & SFP2 (TrbNet), can be re-routed to AddOn-Connector\\ + \hline + \multirow{4}{*}{C} + & 0 & AddOn Connector, Master: TrbNet to Slave 5\\ + & 1 & AddOn Connector, Master: TrbNet to Slave 9\\ + & 2 & AddOn Connector\\ + & 3 & AddOn Connector\\ + \hline + \multirow{4}{*}{D} + & 0 & SFP1 (GbE)\\ + & 1 & AddOn Connector, can be re-routed to SFP2\\ + & 2 & not used\\ + & 3 & not used\\ + \hline + \end{tabularx} +% \caption[Trb3sc Serdes Mapping]{Mapping of Serdes channels} +\end{center} + + +\subsubsection{Modifications} +The following changes compared to the original schematics are to be made: +\begin{description*} + \item [R12, R14] 270 Ohm, LED is too dim + \item [R13, R15] 680 Ohm, LED is too dim + \item [R16, R17] 680 Ohm, LED is too bright + \item [Patchwire] Disconnect R14 from 2.5V (rotate by 90°), patchwire to Pin 2 of switch - green LED shows status of clock select +\end{description*} \ No newline at end of file diff --git a/trb3/figures/trb3scfrontpanel.png b/trb3/figures/trb3scfrontpanel.png new file mode 100755 index 0000000..6088042 Binary files /dev/null and b/trb3/figures/trb3scfrontpanel.png differ diff --git a/trb3/main.tex b/trb3/main.tex index bb57e4a..ad8564d 100644 --- a/trb3/main.tex +++ b/trb3/main.tex @@ -156,7 +156,10 @@ \subsection{Clock and Trigger Distribution} \input{Trb3ClockTriggerDistribution} \clearpage - + \section{Trb3sc} + \subsection{Basics} + \input{Trb3scBasics} + \clearpage \section{AddOns} \subsection{TDC AddOn} \input{TdcAddOn}