From: hadeshyp Date: Wed, 27 Mar 2013 23:31:35 +0000 (+0000) Subject: new nxyter data input stage, JM X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=acd66fc56d9eea82cf7bf034083bcaef423c8bdd;p=trb3.git new nxyter data input stage, JM --- diff --git a/nxyter/compile_frankfurt.pl b/nxyter/compile_frankfurt.pl index 9faac8a..05a3bd8 100755 --- a/nxyter/compile_frankfurt.pl +++ b/nxyter/compile_frankfurt.pl @@ -116,8 +116,8 @@ $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAM execute($c); # IOR IO Timing Report -# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -# execute($c); +$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); # TWR Timing Report $c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; diff --git a/nxyter/cores/nxyter_input_pll.ipx b/nxyter/cores/nxyter_input_pll.ipx new file mode 100644 index 0000000..d5412bc --- /dev/null +++ b/nxyter/cores/nxyter_input_pll.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/nxyter/cores/nxyter_input_pll.lpc b/nxyter/cores/nxyter_input_pll.lpc new file mode 100644 index 0000000..874962c --- /dev/null +++ b/nxyter/cores/nxyter_input_pll.lpc @@ -0,0 +1,66 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.3 +ModuleName=nxyter_input_pll +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/27/2013 +Time=23:26:48 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=125 +Div=1 +ClkOPBp=0 +Post=8 +U_OFrq=125 +OP_Tol=0.0 +OFrq=125.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=User Clock +Mult=1 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq= +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=1.485393 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 diff --git a/nxyter/cores/nxyter_input_pll.vhd b/nxyter/cores/nxyter_input_pll.vhd new file mode 100644 index 0000000..e0c92c3 --- /dev/null +++ b/nxyter/cores/nxyter_input_pll.vhd @@ -0,0 +1,98 @@ +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 5.3 +--/d/jspc29/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -n nxyter_input_pll -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 125 -fclkop_tol 0.0 -fb_mode USERCLOCK -noclkos -noclkok -norst -noclkok2 -bw -e + +-- Wed Mar 27 23:26:48 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity nxyter_input_pll is + port ( + CLK: in std_logic; + CLKFB: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of nxyter_input_pll : entity is true; +end nxyter_input_pll; + +architecture Structure of nxyter_input_pll is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "125.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "USERCLOCK", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 1, CLKI_DIV=> 1, + FIN=> "125.000000") + port map (CLKI=>CLK, CLKFB=>CLKFB, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of nxyter_input_pll is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/nxyter/source/nx_timestamp_fifo_read.vhd b/nxyter/source/nx_timestamp_fifo_read.vhd index fad71c7..8c87424 100644 --- a/nxyter/source/nx_timestamp_fifo_read.vhd +++ b/nxyter/source/nx_timestamp_fifo_read.vhd @@ -97,10 +97,14 @@ architecture Behavioral of nx_timestamp_fifo_read is signal fifo_delay_r : std_logic_vector(5 downto 0); signal fifo_reset_r : std_logic; + signal pll_lock : std_logic; + signal nx_clk_in_delayed : std_logic; + signal nx_timestamp_reg : std_logic_vector(7 downto 0); + begin - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= NX_TIMESTAMP_CLK_IN; + DEBUG_OUT(0) <= '0'; + DEBUG_OUT(1) <= '0'; DEBUG_OUT(2) <= fifo_empty; DEBUG_OUT(3) <= fifo_read_enable; DEBUG_OUT(4) <= fifo_data_valid; @@ -121,6 +125,16 @@ begin -- DEBUG_OUT(7 downto 4) <= fifo_out(3 downto 0); -- DEBUG_OUT(15 downto 8) <= fifo_out(34 downto 27); + THE_INPUT_PLL : entity work.nxyter_input_pll + port map( + CLK => NX_TIMESTAMP_CLK_IN, + CLKFB => nx_clk_in_delayed, + CLKOP => nx_clk_in_delayed, + LOCK => pll_lock --use this to generate FIFO reset! + ); + + nx_timestamp_reg <= NX_TIMESTAMP_IN when rising_edge(nx_clk_in_delayed); + ----------------------------------------------------------------------------- -- Dual Clock FIFO 9bit to 36bit ----------------------------------------------------------------------------- @@ -128,9 +142,9 @@ begin -- Send data to FIFO, depth is 256 fifo_dc_9to36_dyn_1: fifo_dc_9to36_dyn port map ( - Data(7 downto 0) => NX_TIMESTAMP_IN, + Data(7 downto 0) => nx_timestamp_reg, Data(8) => frame_tag_o, - WrClock => NX_TIMESTAMP_CLK_IN, + WrClock => nx_clk_in_delayed, RdClock => CLK_IN, WrEn => fifo_write_enable, RdEn => fifo_read_enable, @@ -143,8 +157,8 @@ begin AlmostEmpty => fifo_almost_empty ); - fifo_write_enable <= not RESET_IN; - fifo_reset <= RESET_IN or fifo_reset_r; + fifo_write_enable <= not RESET_IN and pll_lock; + fifo_reset <= (RESET_IN or fifo_reset_r) and not pll_lock; ----------------------------------------------------------------------------- -- FIFO Input Handler @@ -152,9 +166,9 @@ begin -- Cross ClockDomain CLK_IN --> NX_TIMESTAMP_CLK_IN for signal -- frame_clock_ctr_inc - PROC_FIFO_IN_HANDLER_SYNC: process(NX_TIMESTAMP_CLK_IN) + PROC_FIFO_IN_HANDLER_SYNC: process(nx_clk_in_delayed) begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if( rising_edge(nx_clk_in_delayed) ) then if( RESET_IN = '1' ) then frame_clock_ctr_inc_x <= '0'; frame_clock_ctr_inc_l <= '0'; @@ -168,15 +182,15 @@ begin -- Signal frame_tag_ctr_inc_l might be 2 clocks long --> I need 1 level_to_pulse_1: level_to_pulse port map ( - CLK_IN => NX_TIMESTAMP_CLK_IN, + CLK_IN => nx_clk_in_delayed, RESET_IN => RESET_IN, LEVEL_IN => frame_clock_ctr_inc_l, PULSE_OUT => frame_clock_ctr_inc ); - PROC_FRAME_CLOCK_GENERATOR: process(NX_TIMESTAMP_CLK_IN) + PROC_FRAME_CLOCK_GENERATOR: process(nx_clk_in_delayed) begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if( rising_edge(nx_clk_in_delayed) ) then if( RESET_IN = '1' ) then frame_clock_ctr <= (others => '0'); nx_frame_clock_o <= '0'; diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index 2b914bb..a7be974 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -137,6 +137,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.v add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" +add_file -vhdl -lib "work" "cores/nxyter_input_pll.vhd" add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib "work" "trb3_periph.vhd" diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index 096f3a9..51a39c1 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -13,13 +13,15 @@ FREQUENCY PORT CLK_GPLL_RIGHT 125 MHz; FREQUENCY PORT CLK_GPLL_LEFT 200 MHz; -#Put the names of your DCO inputs here: +#Put the names of your nxyter inputs here: FREQUENCY PORT NX1_ADC_DCLK_IN 192 MHz; FREQUENCY PORT NX2_ADC_DCLK_IN 192 MHz; - + FREQUENCY PORT NX1_CLK128_IN 128 MHz; + FREQUENCY PORT NX2_CLK128_IN 128 MHz; + #Change the next two lines to the clk_fast signal of the ADC - USE PRIMARY2EDGE NET "nXyter_FEE_board_1/adc_ad9222_1/clk_fast"; - USE PRIMARY NET "nXyter_FEE_board_1/adc_ad9222_1/clk_fast"; +# USE PRIMARY2EDGE NET "nXyter_FEE_board_1/adc_ad9222_1/clk_fast"; +# USE PRIMARY NET "nXyter_FEE_board_1/adc_ad9222_1/clk_fast"; USE PRIMARY NET "CLK_PCLK_LEFT"; USE PRIMARY NET "CLK_PCLK_LEFT_c"; @@ -46,3 +48,21 @@ LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; MULTICYCLE TO CELL "THE_ADC/restart_i" 20 ns; + + +################################################################# +# Constraints for nxyter inputs +################################################################# + +USE PRIMARY NET "*nx_clk_in_delayed"; +DEFINE PORT GROUP "NX_IN" "NX1_TIMESTAMP_*"; +INPUT_SETUP GROUP "NX_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN" ; + + + +#DEFINE PORT GROUP "ADC7_INPUTS" "PRE_IN_17" "PRE_IN_18" "PRE_IN_19" +# "PRE_IN_20" "PRE_IN_21" "PRE_IN_22" "PRE_IN_23" "PRE_IN_24" ; +#INPUT_SETUP GROUP "ADC7_INPUTS" 1.500000 ns HOLD 1.500000 ns CLKPORT "DCO_IN_7" ; + + +MULTICYCLE FROM CLKNET "NX1_CLK256A_OUT_c_c" 50 ns;