From: hadeshyp Date: Fri, 13 Aug 2010 09:32:23 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~194 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ad11bf61496d2e315ea4998a65326fc456dad190;p=trbnet.git *** empty log message *** --- diff --git a/basics/state_sync.vhd b/basics/state_sync.vhd new file mode 100644 index 0000000..8967100 --- /dev/null +++ b/basics/state_sync.vhd @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; +--use work.adcmv3_components.all; + +entity state_sync is +port( + STATE_A_IN : in std_logic; + RESET_B_IN : in std_logic; + CLK_B_IN : in std_logic; + STATE_B_OUT : out std_logic +); +end; + +architecture behavioral of state_sync is + +-- normal signals +signal sync_q : std_logic; +signal sync_qq : std_logic; + +begin + +-- synchronizing stage for clock domain B +THE_SYNC_STAGE_PROC: process( clk_b_in ) +begin + if( rising_edge(clk_b_in) ) then + if( reset_b_in = '1' ) then + sync_q <= '0'; sync_qq <= '0'; + else + sync_qq <= sync_q; + sync_q <= state_a_in; + end if; + end if; +end process THE_SYNC_STAGE_PROC; + +-- output signals +state_b_out <= sync_qq; + +end behavioral; diff --git a/lattice/ecp2m/lattice_ecp2m_fifo_16b_16b_dualport.lpc b/lattice/ecp2m/lattice_ecp2m_fifo_16b_16b_dualport.lpc new file mode 100644 index 0000000..09381ac --- /dev/null +++ b/lattice/ecp2m/lattice_ecp2m_fifo_16b_16b_dualport.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.3 +ModuleName=lattice_ecp2m_fifo_16b_16b_dualport +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/09/2010 +Time=13:03:06 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=512 +Width=16 +RDepth=512 +RWidth=16 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=1 +WDataCount=1 +EnECC=0 diff --git a/lattice/ecp2m/lattice_ecp2m_fifo_16b_16b_dualport.vhd b/lattice/ecp2m/lattice_ecp2m_fifo_16b_16b_dualport.vhd new file mode 100644 index 0000000..e8c5b59 --- /dev/null +++ b/lattice/ecp2m/lattice_ecp2m_fifo_16b_16b_dualport.vhd @@ -0,0 +1,1844 @@ +-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 5.3 +--C:\Programme\ispTOOLS8_0\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 16 -depth 512 -rdata_width 16 -no_enable -pe -1 -pf -1 -rfill -fill -e + +-- Mon Aug 09 13:03:06 2010 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity lattice_ecp2m_fifo_16b_16b_dualport is + port ( + Data: in std_logic_vector(15 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(15 downto 0); + WCNT: out std_logic_vector(9 downto 0); + RCNT: out std_logic_vector(9 downto 0); + Empty: out std_logic; + Full: out std_logic); +end lattice_ecp2m_fifo_16b_16b_dualport; + +architecture Structure of lattice_ecp2m_fifo_16b_16b_dualport is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal wptr_9: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal rptr_9: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co4: std_logic; + signal wcount_9: std_logic; + signal co3: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co4_1: std_logic; + signal rcount_9: std_logic; + signal co3_1: std_logic; + signal wfill_sub_0: std_logic; + signal wptr_0: std_logic; + signal wfill_sub_1: std_logic; + signal wfill_sub_2: std_logic; + signal co0_2: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wfill_sub_3: std_logic; + signal wfill_sub_4: std_logic; + signal co1_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wfill_sub_5: std_logic; + signal wfill_sub_6: std_logic; + signal co2_2: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wfill_sub_7: std_logic; + signal wfill_sub_8: std_logic; + signal co3_2: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wfill_sub_9: std_logic; + signal co4_2: std_logic; + signal wfill_sub_msb: std_logic; + signal rfill_sub_0: std_logic; + signal rptr_0: std_logic; + signal scuba_vhi: std_logic; + signal rfill_sub_1: std_logic; + signal rfill_sub_2: std_logic; + signal co0_3: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rfill_sub_3: std_logic; + signal rfill_sub_4: std_logic; + signal co1_3: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rfill_sub_5: std_logic; + signal rfill_sub_6: std_logic; + signal co2_3: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rfill_sub_7: std_logic; + signal rfill_sub_8: std_logic; + signal co3_3: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rfill_sub_9: std_logic; + signal co4_3: std_logic; + signal rfill_sub_msb: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_4: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_4: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_4: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_4: std_logic; + signal wcount_r8: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_8: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_5: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_5: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_5: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_5: std_logic; + signal rcount_w8: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_8: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KB + -- synopsys translate_off + generic (CSDECODE_R : in std_logic_vector(2 downto 0); + CSDECODE_W : in std_logic_vector(2 downto 0); + GSR : in String; RESETMODE : in String; + REGMODE : in String; DATA_WIDTH_R : in Integer; + DATA_WIDTH_W : in Integer); + -- synopsys translate_on + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_R : string; + attribute CSDECODE_W : string; + attribute RESETMODE : string; + attribute REGMODE : string; + attribute DATA_WIDTH_R : string; + attribute DATA_WIDTH_W : string; + attribute GSR : string; + attribute initval of LUT4_23 : label is "0x6996"; + attribute initval of LUT4_22 : label is "0x6996"; + attribute initval of LUT4_21 : label is "0x6996"; + attribute initval of LUT4_20 : label is "0x6996"; + attribute initval of LUT4_19 : label is "0x6996"; + attribute initval of LUT4_18 : label is "0x6996"; + attribute initval of LUT4_17 : label is "0x6996"; + attribute initval of LUT4_16 : label is "0x6996"; + attribute initval of LUT4_15 : label is "0x6996"; + attribute initval of LUT4_14 : label is "0x6996"; + attribute initval of LUT4_13 : label is "0x6996"; + attribute initval of LUT4_12 : label is "0x6996"; + attribute initval of LUT4_11 : label is "0x6996"; + attribute initval of LUT4_10 : label is "0x6996"; + attribute initval of LUT4_9 : label is "0x6996"; + attribute initval of LUT4_8 : label is "0x6996"; + attribute initval of LUT4_7 : label is "0x6996"; + attribute initval of LUT4_6 : label is "0x6996"; + attribute initval of LUT4_5 : label is "0x6996"; + attribute initval of LUT4_4 : label is "0x6996"; + attribute initval of LUT4_3 : label is "0x0410"; + attribute initval of LUT4_2 : label is "0x1004"; + attribute initval of LUT4_1 : label is "0x0140"; + attribute initval of LUT4_0 : label is "0x4001"; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "lattice_ecp2m_fifo_16b_16b_dualport.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b000"; + attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001"; + attribute GSR of pdp_ram_0_0_0 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC"; + attribute REGMODE of pdp_ram_0_0_0 : label is "NOREG"; + attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36"; + attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t22: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t21: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t20: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t19: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t18: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t17: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t16: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t15: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t14: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t13: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t12: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t11: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t10: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t9: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t8: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t7: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t6: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t5: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t4: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t3: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t2: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + LUT4_23: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_gcount_r29, + DO0=>w_g2b_xor_cluster_0); + + LUT4_22: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>w_gcount_r25, + DO0=>w_g2b_xor_cluster_1); + + LUT4_21: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_20: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_19: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5); + + LUT4_18: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); + + LUT4_17: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3); + + LUT4_16: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_15: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_14: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0); + + LUT4_13: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_gcount_w29, + DO0=>r_g2b_xor_cluster_0); + + LUT4_12: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>r_gcount_w25, + DO0=>r_g2b_xor_cluster_1); + + LUT4_11: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_10: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7); + + LUT4_9: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); + + LUT4_8: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4); + + LUT4_7: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3); + + LUT4_6: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_5: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0); + + XOR2_t1: XOR2 + port map (A=>wptr_9, B=>r_gcount_w29, Z=>wfill_sub_msb); + + XOR2_t0: XOR2 + port map (A=>w_gcount_r29, B=>rptr_9, Z=>rfill_sub_msb); + + LUT4_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0410") + -- synopsys translate_on + port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x1004") + -- synopsys translate_on + port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0140") + -- synopsys translate_on + port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4001") + -- synopsys translate_on + port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: PDPW16KB + -- synopsys translate_off + generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + -- synopsys translate_on + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>scuba_vlo, DI17=>scuba_vlo, + DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo, + DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo, + DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo, + DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo, + DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo, + DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, + ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, + ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, + ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, + ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, + ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>RdClock, + CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo, + RST=>Reset, DO0=>open, DO1=>open, DO2=>open, DO3=>open, + DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open, + DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open, + DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0), + DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), + DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), + DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), + DO33=>Q(15), DO34=>open, DO35=>open); + + FF_121: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_120: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_119: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_118: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_117: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_116: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_115: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_114: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_113: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_112: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_111: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_110: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_109: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_108: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_107: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_106: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_105: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_104: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_103: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_102: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_101: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_100: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_99: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_98: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_97: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_96: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_95: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_94: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_93: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_92: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_91: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_90: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_89: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_88: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_87: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_86: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_85: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_84: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_83: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_82: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_81: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_80: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_79: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_78: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_77: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_76: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_75: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_74: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_73: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_69: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_68: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_67: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_66: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_65: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_64: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_63: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_62: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_61: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_60: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_59: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_58: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_57: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_56: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_55: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_54: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_53: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_52: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_51: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_50: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_49: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_48: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_47: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_46: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_45: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_44: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_43: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_42: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_41: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_40: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_39: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_38: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_37: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_36: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_35: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_34: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_33: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_32: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_31: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_30: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_29: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_28: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_27: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_26: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_25: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_23: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0)); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1)); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2)); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3)); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4)); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5)); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6)); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7)); + + FF_3: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8)); + + FF_2: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9)); + + FF_1: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + wfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, + B1=>rcount_w0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, + S1=>wfill_sub_0); + + wfill_1: FSUB2B + port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w1, B1=>rcount_w2, + BI=>co0_2, BOUT=>co1_2, S0=>wfill_sub_1, S1=>wfill_sub_2); + + wfill_2: FSUB2B + port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w3, B1=>rcount_w4, + BI=>co1_2, BOUT=>co2_2, S0=>wfill_sub_3, S1=>wfill_sub_4); + + wfill_3: FSUB2B + port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w5, + B1=>r_g2b_xor_cluster_0, BI=>co2_2, BOUT=>co3_2, + S0=>wfill_sub_5, S1=>wfill_sub_6); + + wfill_4: FSUB2B + port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w7, B1=>rcount_w8, + BI=>co3_2, BOUT=>co4_2, S0=>wfill_sub_7, S1=>wfill_sub_8); + + wfill_5: FSUB2B + port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co4_2, BOUT=>open, S0=>wfill_sub_9, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + rfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wcount_r0, B0=>scuba_vlo, + B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_3, S0=>open, + S1=>rfill_sub_0); + + rfill_1: FSUB2B + port map (A0=>wcount_r1, A1=>wcount_r2, B0=>rptr_1, B1=>rptr_2, + BI=>co0_3, BOUT=>co1_3, S0=>rfill_sub_1, S1=>rfill_sub_2); + + rfill_2: FSUB2B + port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rptr_3, B1=>rptr_4, + BI=>co1_3, BOUT=>co2_3, S0=>rfill_sub_3, S1=>rfill_sub_4); + + rfill_3: FSUB2B + port map (A0=>wcount_r5, A1=>w_g2b_xor_cluster_0, B0=>rptr_5, + B1=>rptr_6, BI=>co2_3, BOUT=>co3_3, S0=>rfill_sub_5, + S1=>rfill_sub_6); + + rfill_4: FSUB2B + port map (A0=>wcount_r7, A1=>wcount_r8, B0=>rptr_7, B1=>rptr_8, + BI=>co3_3, BOUT=>co4_3, S0=>rfill_sub_7, S1=>rfill_sub_8); + + rfill_5: FSUB2B + port map (A0=>rfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co4_3, BOUT=>open, S0=>rfill_sub_9, + S1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_4); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_4, GE=>co1_4); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_4, GE=>co2_4); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r7, CI=>co2_4, GE=>co3_4); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8, + B1=>empty_cmp_clr, CI=>co3_4, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_5); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_5, GE=>co1_5); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_5, GE=>co2_5); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w7, CI=>co2_5, GE=>co3_5); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8, + B1=>full_cmp_clr, CI=>co3_5, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of lattice_ecp2m_fifo_16b_16b_dualport is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FSUB2B use entity ecp2m.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:OR2 use entity ecp2m.OR2(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/ecp2m/trb_net_fifo_16bit_16bit_bram_dualport.vhd b/lattice/ecp2m/trb_net_fifo_16bit_16bit_bram_dualport.vhd new file mode 100644 index 0000000..037aa72 --- /dev/null +++ b/lattice/ecp2m/trb_net_fifo_16bit_16bit_bram_dualport.vhd @@ -0,0 +1,62 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.numeric_std.all; + +library work; +use work.trb_net_std.all; + +entity trb_net_fifo_16bit_16bit_bram_dualport is +port( + READ_CLOCK_IN : in std_logic; + WRITE_CLOCK_IN : in std_logic; + READ_ENABLE_IN : in std_logic; + WRITE_ENABLE_IN : in std_logic; + FIFO_GSR_IN : in std_logic; + WRITE_DATA_IN : in std_logic_vector(15 downto 0); + READ_DATA_OUT : out std_logic_vector(15 downto 0); + FULL_OUT : out std_logic; + EMPTY_OUT : out std_logic; + WCNT_OUT : out std_logic_vector(9 downto 0); + RCNT_OUT : out std_logic_vector(9 downto 0) +); +end entity trb_net_fifo_16bit_16bit_bram_dualport; + +architecture trb_net_fifo_16bit_16bit_bram_dualport_arch of trb_net_fifo_16bit_16bit_bram_dualport is + +component lattice_ecp2m_fifo_16b_16b_dualport is +port( + Data : in std_logic_vector(15 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(15 downto 0); + WCNT : out std_logic_vector(9 downto 0); + RCNT : out std_logic_vector(9 downto 0); + Empty : out std_logic; + Full : out std_logic +); +end component lattice_ecp2m_fifo_16b_16b_dualport; + +begin + +FIFO_DP_BRAM: lattice_ecp2m_fifo_16b_16b_dualport +port map ( + Data => WRITE_DATA_IN, + WrClock => WRITE_CLOCK_IN, + RdClock => READ_CLOCK_IN, + WrEn => WRITE_ENABLE_IN, + RdEn => READ_ENABLE_IN, + Reset => FIFO_GSR_IN, + RPReset => '0', + Q => READ_DATA_OUT, + WCNT => WCNT_OUT, + RCNT => RCNT_OUT, + Empty => EMPTY_OUT, + Full => FULL_OUT +); + +end architecture trb_net_fifo_16bit_16bit_bram_dualport_arch; + diff --git a/media_interfaces/trb_net16_lsm_sfp.vhd b/media_interfaces/trb_net16_lsm_sfp.vhd index ef7f3ab..a325462 100644 --- a/media_interfaces/trb_net16_lsm_sfp.vhd +++ b/media_interfaces/trb_net16_lsm_sfp.vhd @@ -14,7 +14,11 @@ library work; use work.trb_net_std.all; entity trb_net16_lsm_sfp is -port( SYSCLK : in std_logic; -- fabric clock (100MHz) + generic( + CHECK_FOR_CV : integer := c_YES + ); + port( + SYSCLK : in std_logic; -- fabric clock (100MHz) RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset, connect to '0' if not needed / available -- status signals @@ -302,7 +306,7 @@ begin NEXT_STATE <= SLEEP; next_lane_rst <= '1'; next_rst_tctr <= '1'; - elsif( sd_cv_in /= "00" ) then + elsif( sd_cv_in /= "00" ) and CHECK_FOR_CV = c_YES then NEXT_STATE <= CVFND; next_ce_cctr <= '1'; -- increment CV counter next_rx_allow <= '1'; diff --git a/media_interfaces/trb_net16_med_ecp_fot.vhd b/media_interfaces/trb_net16_med_ecp_fot.vhd index 78c88a9..e0b0942 100644 --- a/media_interfaces/trb_net16_med_ecp_fot.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot.vhd @@ -33,18 +33,17 @@ entity trb_net16_med_ecp_fot is SD : in std_logic; -- Status and control port - STAT_OP : out std_logic_vector (15 downto 0); + STAT_OP : out std_logic_vector (15 downto 0); CTRL_OP : in std_logic_vector (15 downto 0); - STAT_DEBUG : out std_logic_vector (63 downto 0); + STAT_REG_OUT : out std_logic_vector (31 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); CTRL_DEBUG : in std_logic_vector (15 downto 0) ); end entity; architecture trb_net16_med_ecp_fot_arch of trb_net16_med_ecp_fot is --- Placer Directives attribute HGROUP : string; --- for whole architecture attribute HGROUP of trb_net16_med_ecp_fot_arch : architecture is "GROUP_PCS"; component serdes_fot_0 is @@ -92,575 +91,324 @@ attribute HGROUP of trb_net16_med_ecp_fot_arch : architecture is "GROUP_PCS"; ); end component; - --- --- component lattice_ecp2m_fifo_8x8_dualport --- port ( --- Data: in std_logic_vector(7 downto 0); --- WrClock: in std_logic; --- RdClock: in std_logic; --- WrEn: in std_logic; --- RdEn: in std_logic; --- Reset: in std_logic; --- RPReset: in std_logic; --- Q: out std_logic_vector(7 downto 0); --- Empty: out std_logic; --- Full: out std_logic --- ); --- end component; --- --- component lattice_ecp2m_fifo_16x8_dualport --- port ( --- Data: in std_logic_vector(15 downto 0); --- WrClock: in std_logic; --- RdClock: in std_logic; --- WrEn: in std_logic; --- RdEn: in std_logic; --- Reset: in std_logic; --- RPReset: in std_logic; --- Q: out std_logic_vector(15 downto 0); --- Empty: out std_logic; --- Full: out std_logic --- ); --- end component; - - signal link_error : std_logic_vector(7 downto 0); - signal link_error_q: std_logic_vector(7 downto 0); - signal reg_link_error : std_logic_vector(7 downto 0); - signal ffs_plol : std_logic; - signal link_ok : std_logic; - signal link_ok_q : std_logic; - signal tx_data : std_logic_vector(8-1 downto 0); - signal rx_data : std_logic_vector(8-1 downto 0); - signal ff_rxfullclk : std_logic; - signal ff_txfullclk : std_logic; - signal rx_k : std_logic; - signal tx_k : std_logic; - signal lane_rst : std_logic; - signal lane_rst_qtx : std_logic; - signal quad_rst : std_logic; - signal quad_rst_qtx : std_logic; - - signal byte_waiting : std_logic; - signal byte_buffer : std_logic_vector(8-1 downto 0); - signal fifo_reset : std_logic; - signal tx_fifo_dout : std_logic_vector(16-1 downto 0); - signal tx_fifo_data_in : std_logic_vector(16-1 downto 0); - signal tx_fifo_read_en : std_logic; - signal tx_fifo_write_en : std_logic; - signal tx_fifo_empty : std_logic; - signal tx_fifo_full : std_logic; - - signal tx_fifo_valid_read : std_logic; - signal tx_allow : std_logic; - signal tx_allow_del : std_logic; - signal tx_allow_qtx : std_logic; - - signal rx_data_reg : std_logic_vector(8-1 downto 0); - signal buf_rx_data_reg : std_logic_vector(8-1 downto 0); - signal buf_rx_data : std_logic_vector(8-1 downto 0); - signal buf_rx_k : std_logic; - signal rx_fifo_write_en : std_logic; - signal rx_fifo_read_en : std_logic; - signal rx_fifo_empty : std_logic; - signal rx_fifo_full : std_logic; - signal rx_fifo_dout : std_logic_vector(8-1 downto 0); - signal is_idle_word : std_logic; - signal rx_starting : std_logic; - signal rx_allow : std_logic; - signal rx_allow_del : std_logic; - signal rx_allow_qrx : std_logic; - signal sd_q : std_logic; - signal last_rx_fifo_read_en : std_logic; - signal last_rx_fifo_empty : std_logic; - signal last_last_rx_fifo_read_en : std_logic; - signal last_last_rx_fifo_empty : std_logic; - signal last_rx_fifo_dout : std_logic_vector(7 downto 0); - signal tx_fifo_valid_read_q : std_logic; - - signal buf_med_dataready_out : std_logic; - signal buf_med_read_out : std_logic; - signal buf_med_data_out : std_logic_vector(16-1 downto 0); - signal byte_select : std_logic; - signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal sfp_los : std_logic; - - signal led_counter : std_logic_vector(13 downto 0); - signal rx_led : std_logic; - signal tx_led : std_logic; - - signal FSM_STAT_OP : std_logic_vector(16-1 downto 0); - signal FSM_STAT_DEBUG : std_logic_vector(64-1 downto 0); - signal FSM_CTRL_OP : std_logic_vector(16-1 downto 0); - - signal send_reset_q : std_logic; - signal reset_word_cnt : std_logic_vector(4 downto 0); - signal send_reset_words : std_logic; - signal send_reset_words_q : std_logic; - signal make_trbnet_reset : std_logic; - signal make_trbnet_reset_q: std_logic; + signal buf_med_data_out : std_logic_vector(15 downto 0); + signal buf_med_dataready_out : std_logic; + signal buf_med_packet_num_out : std_logic_vector(2 downto 0); + + signal link_error : std_logic_vector(7 downto 0); + signal link_error_q : std_logic_vector(7 downto 0); + signal reg_link_error : std_logic_vector(7 downto 0); + signal ffs_plol : std_logic; + signal link_ok : std_logic; + signal link_ok_q : std_logic; + signal tx_data : std_logic_vector(8-1 downto 0); + signal rx_data : std_logic_vector(8-1 downto 0); + signal ff_rxfullclk : std_logic; + signal ff_txfullclk : std_logic; + signal rx_k : std_logic; + signal tx_k : std_logic; + signal lane_rst : std_logic; + signal lane_rst_qtx : std_logic; + signal quad_rst : std_logic; + signal quad_rst_qtx : std_logic; + + signal tx_allow : std_logic; + signal rx_allow : std_logic; + signal tx_allow_qtx : std_logic; + signal sd_q : std_logic; + signal sfp_los : std_logic; + + signal led_counter : std_logic_vector(11 downto 0); + signal rx_led : std_logic; + signal tx_led : std_logic; + + signal FSM_STAT_OP : std_logic_vector(16-1 downto 0); + signal FSM_STAT_DEBUG : std_logic_vector(64-1 downto 0); + signal FSM_CTRL_OP : std_logic_vector(16-1 downto 0); + + signal request_retransmit_i : std_logic; + signal request_position_i : std_logic_vector( 7 downto 0); + signal start_retransmit_i : std_logic; + signal start_position_i : std_logic_vector( 7 downto 0); + signal packet_timeout_i : std_logic; + signal debug_txcontrol_i : std_logic_vector(31 downto 0); + signal debug_rxcontrol_i : std_logic_vector(31 downto 0); + signal send_reset_words : std_logic; + signal make_trbnet_reset : std_logic; + + signal last_tx_k : std_logic; + signal request_cnt_i : unsigned(7 downto 0); + signal reset_rx_control : std_logic; begin - - --ff_rxfullclk <= clk_25; - --ff_rxfullclk <= ff_txfullclk; - +----------------------------------------------------------------------- +--Serdes +----------------------------------------------------------------------- THE_SERDES: serdes_fot_0 port map( - core_txrefclk => CLK_25, - core_rxrefclk => CLK_25, - hdinp0 => RXP, - hdinn0 => RXN, - hdoutp0 => TXP, - hdoutn0 => TXN, - ff_rxiclk_ch0 => ff_rxfullclk, - ff_txiclk_ch0 => ff_txfullclk, - ff_ebrd_clk_0 => ff_rxfullclk, - ff_txdata_ch0 => tx_data(7 downto 0), - ff_rxdata_ch0 => rx_data(7 downto 0), - ff_tx_k_cntrl_ch0 => tx_k, - ff_rx_k_cntrl_ch0 => rx_k, - ff_rxfullclk_ch0 => ff_rxfullclk, - ff_force_disp_ch0 => '0', - ff_disp_sel_ch0 => '0', - ff_correct_disp_ch0 => '0', - ff_disp_err_ch0 => link_error(0), - ff_cv_ch0 => link_error(1), - ffc_rrst_ch0 => '0', - ffc_lane_tx_rst_ch0 => lane_rst_qtx, --lane_rst(0), - ffc_lane_rx_rst_ch0 => lane_rst_qtx, - ffc_txpwdnb_ch0 => '1', - ffc_rxpwdnb_ch0 => '1', - ffs_rlos_lo_ch0 => link_error(2), + core_txrefclk => CLK_25, + core_rxrefclk => CLK_25, + hdinp0 => RXP, + hdinn0 => RXN, + hdoutp0 => TXP, + hdoutn0 => TXN, + ff_rxiclk_ch0 => ff_rxfullclk, + ff_txiclk_ch0 => ff_txfullclk, + ff_ebrd_clk_0 => ff_rxfullclk, + ff_txdata_ch0 => tx_data(7 downto 0), + ff_rxdata_ch0 => rx_data(7 downto 0), + ff_tx_k_cntrl_ch0 => tx_k, + ff_rx_k_cntrl_ch0 => rx_k, + ff_rxfullclk_ch0 => ff_rxfullclk, + ff_force_disp_ch0 => '0', + ff_disp_sel_ch0 => '0', + ff_correct_disp_ch0 => '0', + ff_disp_err_ch0 => link_error(0), + ff_cv_ch0 => link_error(1), + ffc_rrst_ch0 => '0', + ffc_lane_tx_rst_ch0 => lane_rst_qtx, --lane_rst(0), + ffc_lane_rx_rst_ch0 => lane_rst_qtx, + ffc_txpwdnb_ch0 => '1', + ffc_rxpwdnb_ch0 => '1', + ffs_rlos_lo_ch0 => link_error(2), ffs_ls_sync_status_ch0 => link_ok, - ffs_cc_underrun_ch0 => link_error(3), - ffs_cc_overrun_ch0 => link_error(4), + ffs_cc_underrun_ch0 => link_error(3), + ffs_cc_overrun_ch0 => link_error(4), ffs_txfbfifo_error_ch0 => link_error(5), ffs_rxfbfifo_error_ch0 => link_error(6), - ffs_rlol_ch0 => link_error(7), - oob_out_ch0 => open, - - ffc_macro_rst => '0', - ffc_quad_rst => quad_rst_qtx, - ffc_trst => '0', - ff_txfullclk => ff_txfullclk, - ffs_plol => ffs_plol + ffs_rlol_ch0 => link_error(7), + oob_out_ch0 => open, + + ffc_macro_rst => '0', + ffc_quad_rst => quad_rst_qtx, + ffc_trst => '0', + ff_txfullclk => ff_txfullclk, + ffs_plol => ffs_plol ); ---TX Control 25 ---------------- - - - THE_TX_FIFO: trb_net_fifo_16bit_bram_dualport - generic map( - USE_STATUS_FLAGS => c_NO - ) - port map( - read_clock_in => ff_txfullclk, - write_clock_in => CLK, - read_enable_in => tx_fifo_read_en, - write_enable_in => tx_fifo_write_en, - fifo_gsr_in => fifo_reset, - write_data_in => "00" & tx_fifo_data_in(15 downto 0), - read_data_out(15 downto 0) => tx_fifo_dout(15 downto 0), - full_out => tx_fifo_full, - empty_out => tx_fifo_empty - ); - --- THE_TX_FIFO: lattice_ecp2m_fifo_16x8_dualport --- port map( --- Data => tx_fifo_data_in(16-1 downto 0), --- WrClock => CLK, --- RdClock => ff_txfullclk, --- WrEn => tx_fifo_write_en, --- RdEn => tx_fifo_read_en, --- Reset => fifo_reset, --- RPReset => fifo_reset, --- Q => tx_fifo_dout(15 downto 0), --- Empty => tx_fifo_empty, --- Full => tx_fifo_full --- ); - - THE_READ_TX_FIFO_PROC: process( ff_txfullclk ) - begin - if( rising_edge(ff_txfullclk) ) then - if( reset = '1' ) then - byte_waiting <= '0'; - tx_fifo_read_en <= '0'; - tx_k <= '1'; - tx_data(7 downto 0) <= x"EE"; - tx_fifo_valid_read <= '0'; - else - tx_fifo_read_en <= tx_allow_qtx; - tx_fifo_valid_read <= tx_fifo_read_en and not tx_fifo_empty; - if( byte_waiting = '0' ) then - if( (tx_fifo_valid_read = '1')) then - byte_buffer(7 downto 0) <= tx_fifo_dout(15 downto 8); - byte_waiting <= '1'; - tx_k <= '0'; - tx_data(7 downto 0) <= tx_fifo_dout(7 downto 0); - tx_fifo_read_en <= tx_allow_qtx; - elsif send_reset_q = '1' then - byte_buffer(7 downto 0) <= x"FE"; - byte_waiting <= '1'; - tx_k <= '1'; - tx_data(7 downto 0) <= x"FE"; - tx_fifo_read_en <= '0'; - else - byte_buffer(7 downto 0) <= x"50"; - byte_waiting <= '1'; - tx_k <= '1'; - tx_data(7 downto 0) <= x"BC"; - tx_fifo_read_en <= tx_allow_qtx; - end if; - else --if byte_waiting = '1' then - tx_data(7 downto 0) <= byte_buffer(7 downto 0); - tx_k <= '0'; --second byte is always data - byte_waiting <= '0'; - tx_fifo_read_en <= '0'; - end if; - end if; - end if; - end process; - - fifo_reset <= reset or quad_rst or not rx_allow; --sync with SYSCLK - - --RX Control (25) - --------------------- - - THE_FIFO_RX: trb_net_fifo_16bit_bram_dualport - generic map( - USE_STATUS_FLAGS => c_NO - ) - port map( - read_clock_in => clk, - write_clock_in => ff_rxfullclk, - read_enable_in => rx_fifo_read_en, - write_enable_in => rx_fifo_write_en, - fifo_gsr_in => fifo_reset, - write_data_in => "00" & x"00" & rx_data_reg(7 downto 0), - read_data_out(7 downto 0) => rx_fifo_dout, - full_out => rx_fifo_full, - empty_out => rx_fifo_empty - ); - - --- THE_RX_FIFO: lattice_ecp2m_fifo_8x8_dualport --- port map( --- Data => rx_data_reg(7 downto 0), --- WrClock => ff_rxfullclk, --- RdClock => clk, --- WrEn => rx_fifo_write_en, --- RdEn => rx_fifo_read_en, --- Reset => fifo_reset, --- RPReset => fifo_reset, --- Q => rx_fifo_dout(7 downto 0), --- Empty => rx_fifo_empty, --- Full => rx_fifo_full --- ); - - THE_WRITE_RX_FIFO_PROC: process( ff_rxfullclk ) - begin - if( rising_edge(ff_rxfullclk) ) then - buf_rx_data(7 downto 0) <= rx_data(7 downto 0); - buf_rx_k <= rx_k; - if( (reset = '1') or (rx_allow_qrx = '0') ) then - rx_fifo_write_en <= '0'; - is_idle_word <= '1'; - rx_starting <= '1'; - else - rx_data_reg(7 downto 0) <= buf_rx_data(7 downto 0); - if( (buf_rx_k = '0') and (is_idle_word = '0') and (rx_starting = '0') ) then - rx_fifo_write_en <= '1'; - else - rx_fifo_write_en <= '0'; - end if; - if ( buf_rx_k = '1' ) then - is_idle_word <= '1'; - rx_starting <= '0'; - elsif( (buf_rx_k = '0') and (is_idle_word = '1') ) then - is_idle_word <= '0'; - end if; - end if; - end if; - end process THE_WRITE_RX_FIFO_PROC; - - - THE_CNT_RESET_PROC : process( ff_rxfullclk ) - begin - if rising_edge(ff_rxfullclk) then - if reset = '1' then - send_reset_words <= '0'; - make_trbnet_reset <= '0'; - reset_word_cnt(4 downto 0) <= (others => '0'); - else - send_reset_words <= '0'; - make_trbnet_reset <= '0'; - if buf_rx_data(7 downto 0) = x"FE" and buf_rx_k = '1' then - if reset_word_cnt(4) = '0' then - reset_word_cnt(4 downto 0) <= reset_word_cnt(4 downto 0) + 1; - else - send_reset_words <= '1'; - end if; - else - reset_word_cnt(4 downto 0) <= (others => '0'); - make_trbnet_reset <= reset_word_cnt(4); - end if; - end if; - end if; - end process; - - ---TX Control (100) ---------------------- - buf_med_read_out <= not tx_fifo_full and tx_allow_del; - tx_fifo_write_en <= buf_med_read_out and med_dataready_in; - tx_fifo_data_in(15 downto 0) <= med_data_in(15 downto 0); - med_read_out <= buf_med_read_out; - ---RX Control (100) ---------------------- - process( clk ) - begin - if( rising_edge(clk) ) then - if( reset = '1' ) then - buf_med_dataready_out <= '0'; - byte_select <= '0'; - last_rx_fifo_read_en <= '0'; - else - last_rx_fifo_read_en <= rx_fifo_read_en; - last_rx_fifo_empty <= rx_fifo_empty; - last_last_rx_fifo_read_en <= last_rx_fifo_read_en; - last_last_rx_fifo_empty <= last_rx_fifo_empty; - last_rx_fifo_dout <= rx_fifo_dout; - buf_med_dataready_out <= '0'; - if( (last_last_rx_fifo_empty = '0') and (last_last_rx_fifo_read_en = '1') ) then - if( byte_select = '1' ) then - buf_MED_DATA_OUT(15 downto 0) <= last_rx_fifo_dout(7 downto 0) - & buf_MED_DATA_OUT(7 downto 0); - buf_MED_DATAREADY_OUT <= '1'; - else - buf_MED_DATA_OUT(15 downto 0) <= x"00" & last_rx_fifo_dout(7 downto 0); - end if; - byte_select <= not byte_select; - end if; - end if; - end if; - end process; - - rx_fifo_read_en <= rx_allow_del and not rx_fifo_empty; - MED_DATA_OUT(15 downto 0) <= buf_MED_DATA_OUT(15 downto 0); - MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; - MED_PACKET_NUM_OUT <= rx_counter; - ---rx packet counter ---------------------- - THE_RX_PACKETS_PROC: process( clk ) - begin - if( rising_edge(clk) ) then - if( (reset = '1') or (rx_allow = '0') ) then - rx_counter <= c_H0; - else - if( buf_med_dataready_out = '1' ) then - if( rx_counter = c_max_word_number ) then - rx_counter <= (others => '0'); - else - rx_counter <= rx_counter + 1; - end if; - end if; - end if; - end if; - end process; - - - ---Link State machine ---------------------- - - - CLK_TO_TX_SYNC: signal_sync - generic map( - DEPTH => 2, - WIDTH => 3 - ) - port map( - RESET => reset, - D_IN(0) => tx_allow, - D_IN(1) => lane_rst, - D_IN(2) => quad_rst, - CLK0 => CLK, - CLK1 => ff_txfullclk, - D_OUT(0) => tx_allow_qtx, - D_OUT(1) => lane_rst_qtx, - D_OUT(2) => quad_rst_qtx - ); - - TX_TO_CLK_SYNC: signal_sync - generic map( - DEPTH => 2, - WIDTH => 1 - ) - port map( - RESET => reset, - D_IN(0) => tx_fifo_valid_read, - CLK0 => ff_txfullclk, - CLK1 => CLK, - D_OUT(0) => tx_fifo_valid_read_q - ); - - RX_TO_CLK_SYNC: signal_sync - generic map( - DEPTH => 2, - WIDTH => 9 - ) - port map( - RESET => reset, - D_IN(7 downto 0) => link_error, - D_IN(8) => link_ok, - CLK0 => ff_rxfullclk, - CLK1 => CLK, - D_OUT(7 downto 0) => link_error_q, - D_OUT(8) => link_ok_q - ); - - SYNC_INPUT_TO_CLK : signal_sync - generic map( - DEPTH => 2, - WIDTH => 3 - ) - port map( - RESET => reset, - D_IN(0) => sd, - D_IN(1) => tx_allow, - D_IN(2) => rx_allow, - CLK0 => CLK, - CLK1 => CLK, - D_OUT(0) => sd_q, - D_OUT(1) => tx_allow_del, - D_OUT(2) => rx_allow_del - ); - - THE_SFP_STATUS_SYNC: signal_sync - generic map( - DEPTH => 2, - WIDTH => 1 - ) - port map( - RESET => RESET, - D_IN(0) => rx_allow, - CLK0 => CLK, - CLK1 => ff_rxfullclk, - D_OUT(0) => rx_allow_qrx - ); - - - SYNC_RESET_DETECT_1 : signal_sync - generic map( - DEPTH => 2, - WIDTH => 1 - ) - port map( - RESET => reset, - D_IN(0) => send_reset_words, - CLK0 => CLK, - CLK1 => CLK, - D_OUT(0) => send_reset_words_q - ); - - SYNC_RESET_DETECT_2 : signal_sync - generic map( - DEPTH => 2, - WIDTH => 1 - ) - port map( - RESET => reset, - D_IN(0) => make_trbnet_reset, - CLK0 => CLK, - CLK1 => CLK, - D_OUT(0) => make_trbnet_reset_q - ); - +----------------------------------------------------------------------- +--TX Control +----------------------------------------------------------------------- + THE_TX_CONTROL : trb_net16_tx_control + port map( + TXCLK_IN => CLK_25, + RXCLK_IN => ff_rxfullclk, + SYSCLK_IN => CLK, + RESET_IN => lane_rst, + + TX_DATA_IN => MED_DATA_IN, + TX_WRITE_IN => MED_DATAREADY_IN, + TX_READ_OUT => MED_READ_OUT, + + TX_DATA_OUT => tx_data, + TX_K_OUT => tx_k, + + REQUEST_RETRANSMIT_IN => request_retransmit_i, + REQUEST_POSITION_IN => request_position_i, + START_RETRANSMIT_IN => start_retransmit_i, + START_POSITION_IN => start_position_i, + SEND_LINK_RESET_IN => send_reset_words, + TX_ALLOW_IN => tx_allow, + + DEBUG_OUT => debug_txcontrol_i + ); ---LED Signals ---------------------- - THE_TX_RX_LED_PROC: process( clk ) - begin - if( rising_edge(CLK) ) then - led_counter <= led_counter + 1; - if ( buf_med_dataready_out = '1' ) then - rx_led <= '1'; - elsif( led_counter = 0 ) then - rx_led <= '0'; - end if; - if( tx_fifo_valid_read_q = '1') then - tx_led <= '1'; - elsif led_counter = 0 then - tx_led <= '0'; - end if; - end if; - end process; +----------------------------------------------------------------------- +--RX Control +----------------------------------------------------------------------- + THE_RX_CONTROL : trb_net16_rx_control + port map( + RESET_IN => reset_rx_control, + QUAD_RST_IN => lane_rst, + -- raw data from SerDes receive path + CLK_IN => ff_rxfullclk, + RX_DATA_IN => rx_data, + RX_K_IN => rx_k, + RX_CV_IN => link_error(1), + RX_DISP_ERR_IN => link_error(0), + RX_ALLOW_IN => rx_allow, + -- media interface + SYSCLK_IN => CLK, + MED_DATA_OUT => buf_med_data_out, + MED_DATAREADY_OUT => buf_med_dataready_out, + MED_READ_IN => MED_READ_IN, + MED_PACKET_NUM_OUT => buf_med_packet_num_out, + -- request retransmission in case of error while receiving + REQUEST_RETRANSMIT_OUT => request_retransmit_i, + REQUEST_POSITION_OUT => request_position_i, + -- command decoding + START_RETRANSMIT_OUT => start_retransmit_i, + START_POSITION_OUT => start_position_i, + -- reset handling + SEND_RESET_WORDS_OUT => send_reset_words, + MAKE_TRBNET_RESET_OUT => make_trbnet_reset, + -- Status signals + PACKET_TIMEOUT_OUT => packet_timeout_i, + -- Debugging + DEBUG_OUT => debug_rxcontrol_i + ); +reset_rx_control <= RESET or lane_rst or link_error_q(2) or link_error_q(7); ------------------------------------------------------------ +----------------------------------------------------------------------- --Link State Machine ------------------------------------------------------------ - - THE_SFP_LSM: trb_net16_lsm_sfp - port map( - SYSCLK => CLK, - RESET => reset, - CLEAR => clear, - SFP_MISSING_IN => '0', - SFP_LOS_IN => sfp_los, - SD_LINK_OK_IN => link_ok_q, - SD_LOS_IN => link_error_q(2), - SD_TXCLK_BAD_IN => ffs_plol, - SD_RXCLK_BAD_IN => link_error_q(7), - SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope - SD_ALIGNMENT_IN => "10", - SD_CV_IN(0) => link_error_q(1), - SD_CV_IN(1) => '0', - FULL_RESET_OUT => quad_rst, - LANE_RESET_OUT => lane_rst, - TX_ALLOW_OUT => tx_allow, - RX_ALLOW_OUT => rx_allow, - SWAP_BYTES_OUT => open, - STAT_OP => FSM_STAT_OP(15 downto 0), - CTRL_OP => FSM_CTRL_OP(15 downto 0), - STAT_DEBUG => FSM_STAT_DEBUG(31 downto 0) - ); +----------------------------------------------------------------------- + + THE_SFP_LSM: trb_net16_lsm_sfp + generic map( + CHECK_FOR_CV => c_NO + ) + port map( + SYSCLK => CLK, + RESET => reset, + CLEAR => clear, + SFP_MISSING_IN => '0', + SFP_LOS_IN => sfp_los, + SD_LINK_OK_IN => link_ok_q, + SD_LOS_IN => link_error_q(2), + SD_TXCLK_BAD_IN => ffs_plol, + SD_RXCLK_BAD_IN => link_error_q(7), + SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope + SD_ALIGNMENT_IN => "10", + SD_CV_IN(0) => link_error_q(1), + SD_CV_IN(1) => '0', + FULL_RESET_OUT => quad_rst, + LANE_RESET_OUT => lane_rst, + TX_ALLOW_OUT => tx_allow, + RX_ALLOW_OUT => rx_allow, + SWAP_BYTES_OUT => open, + STAT_OP => FSM_STAT_OP(15 downto 0), + CTRL_OP => FSM_CTRL_OP(15 downto 0), + STAT_DEBUG => FSM_STAT_DEBUG(31 downto 0) + ); - sfp_los <= not sd_q; +----------------------------------------------------------------------- +--I/O +----------------------------------------------------------------------- + + MED_DATA_OUT <= buf_med_data_out; + MED_PACKET_NUM_OUT <= buf_med_packet_num_out; + MED_DATAREADY_OUT <= buf_med_dataready_out; + FSM_CTRL_OP <= CTRL_OP; +----------------------------------------------------------------------- +--Synchronizer +----------------------------------------------------------------------- ------------------------------------------------------------ ---Debugging ------------------------------------------------------------ + CLK_TO_TX_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 3 + ) + port map( + RESET => reset, + D_IN(0) => tx_allow, + D_IN(1) => lane_rst, + D_IN(2) => quad_rst, + CLK0 => CLK, + CLK1 => ff_txfullclk, + D_OUT(0) => tx_allow_qtx, + D_OUT(1) => lane_rst_qtx, + D_OUT(2) => quad_rst_qtx + ); - STAT_OP(9 downto 0) <= FSM_STAT_OP(9 downto 0); - STAT_OP(10) <= rx_led; - STAT_OP(11) <= tx_led; - STAT_OP(12) <= link_error(1) and not send_reset_words_q and tx_allow; - STAT_OP(13) <= make_trbnet_reset_q; - STAT_OP(14) <= FSM_STAT_OP(14); - STAT_OP(15) <= send_reset_words_q; + RX_TO_CLK_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 9 + ) + port map( + RESET => reset, + D_IN(7 downto 0) => link_error, + D_IN(8) => link_ok, + CLK0 => ff_rxfullclk, + CLK1 => CLK, + D_OUT(7 downto 0) => link_error_q, + D_OUT(8) => link_ok_q + ); - STAT_DEBUG(31 downto 0) <= FSM_STAT_DEBUG(31 downto 0); - STAT_DEBUG(39 downto 32) <= buf_rx_data_reg(7 downto 0); - STAT_DEBUG(40) <= rx_fifo_write_en; - STAT_DEBUG(48 downto 41) <= last_rx_fifo_dout; - STAT_DEBUG(63 downto 49) <= (others => '0'); + SYNC_INPUT_TO_CLK : signal_sync + generic map( + DEPTH => 2, + WIDTH => 1 + ) + port map( + RESET => reset, + D_IN(0) => sd, + CLK0 => CLK, + CLK1 => CLK, + D_OUT(0) => sd_q + ); + + sfp_los <= not sd_q; - PROC_LED : process(ff_rxfullclk) +----------------------------------------------------------------------- +--LED Signals +----------------------------------------------------------------------- + THE_TX_RX_LED_PROC: process( CLK_25 ) begin - if rising_edge(ff_rxfullclk) then - buf_rx_data_reg <= rx_data_reg; + if( rising_edge(CLK_25) ) then + led_counter <= led_counter + 1; + last_tx_k <= tx_k; + if ( buf_med_dataready_out = '1' ) then + rx_led <= '1'; + elsif( led_counter = 0 ) then + rx_led <= '0'; + end if; + if( tx_k = '0' and last_tx_k = '0') then + tx_led <= '1'; + elsif led_counter = 0 then + tx_led <= '0'; + end if; + end if; + end process; +----------------------------------------------------------------------- +--Statistics +----------------------------------------------------------------------- + + process(clk) + begin + if rising_edge(clk) then + if request_retransmit_i = '1' and send_reset_words = '0' then + request_cnt_i <= request_cnt_i + to_unsigned(1,1); + end if; end if; end process; +----------------------------------------------------------------------- +--Debugging +----------------------------------------------------------------------- + + STAT_REG_OUT(11 downto 0) <= (others => '0'); --reserved for trigger information + STAT_REG_OUT(23 downto 12) <= (others => '0'); + STAT_REG_OUT(31 downto 24) <= std_logic_vector(request_cnt_i); + + STAT_OP(7 downto 0) <= FSM_STAT_OP(7 downto 0); + STAT_OP(8) <= start_retransmit_i; + STAT_OP(9) <= FSM_STAT_OP(9); + STAT_OP(10) <= rx_led; + STAT_OP(11) <= tx_led; + STAT_OP(12) <= request_retransmit_i; + STAT_OP(13) <= make_trbnet_reset; + STAT_OP(14) <= FSM_STAT_OP(14); + STAT_OP(15) <= send_reset_words; + + STAT_DEBUG(15 downto 0) <= FSM_STAT_DEBUG(15 downto 0); + process(CLK) + begin + if rising_edge(CLK) then + STAT_DEBUG(16) <= request_retransmit_i; + STAT_DEBUG(17) <= start_retransmit_i; + STAT_DEBUG(25 downto 18) <= rx_data; + STAT_DEBUG(26) <= rx_k; + STAT_DEBUG(31 downto 27) <= (others => '0'); + end if; + end process; + STAT_DEBUG(47 downto 32) <= debug_txcontrol_i(15 downto 0); + STAT_DEBUG(63 downto 48) <= debug_rxcontrol_i(15 downto 0); end architecture; \ No newline at end of file diff --git a/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd b/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd index 4ec76b3..e111003 100644 --- a/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd @@ -10,7 +10,6 @@ use work.trb_net_components.all; entity trb_net16_med_ecp_fot_4_ctc is generic( REVERSE_ORDER : integer range 0 to 1 := c_NO --- USED_PORTS : std_logic-vector(3 downto 0) := "1111" ); port( CLK : in std_logic; @@ -38,6 +37,7 @@ port( -- Status and control port STAT_OP : out std_logic_vector (63 downto 0); CTRL_OP : in std_logic_vector (63 downto 0); + STAT_REG_OUT : out std_logic_vector(127 downto 0); STAT_DEBUG : out std_logic_vector (255 downto 0); CTRL_DEBUG : in std_logic_vector (63 downto 0) ); @@ -45,9 +45,7 @@ end entity; architecture trb_net16_med_ecp_fot_4_ctc_arch of trb_net16_med_ecp_fot_4_ctc is --- Placer Directives attribute HGROUP : string; --- for whole architecture attribute HGROUP of trb_net16_med_ecp_fot_4_ctc_arch : architecture is "GROUP_PCS"; attribute syn_sharing : string; attribute syn_sharing of trb_net16_med_ecp_fot_4_ctc_arch : architecture is "false"; @@ -188,65 +186,8 @@ PORT( end component; -component lattice_ecp2m_fifo_8x8_dualport -port( - Data : in std_logic_vector(7 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(7 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - - -component lattice_ecp2m_fifo_16x8_dualport -port( - Data : in std_logic_vector(15 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(15 downto 0); - Empty : out std_logic; - Full : out std_logic -); -end component; - -component trb_net16_rx_packets is -port( - -- Resets - RESET_IN : in std_logic; - QUAD_RST_IN : in std_logic; - -- data stream from SerDes - CLK_IN : in std_logic; -- SerDes RX clock - RX_ALLOW_IN : in std_logic; - RX_DATA_IN : in std_logic_vector(7 downto 0); - RX_K_IN : in std_logic; - -- media interface - SYSCLK_IN : in std_logic; -- 100MHz master clock - MED_DATA_OUT : out std_logic_vector(15 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - -- reset handling - SEND_RESET_WORDS_OUT : out std_logic; - MAKE_TRBNET_RESET_OUT : out std_logic; - -- Status signals - PACKET_TIMEOUT_OUT : out std_logic; - -- Debug signals - BSM_OUT : out std_logic_vector(3 downto 0); - DBG_OUT : out std_logic_vector(15 downto 0) -); -end component trb_net16_rx_packets; - type link_error_t is array(0 to 3) of std_logic_vector(7 downto 0); + signal link_error : link_error_t; signal link_error_q : link_error_t; signal reg_link_error : link_error_t; @@ -255,56 +196,27 @@ signal link_ok : std_logic_vector(3 downto 0); signal link_ok_q : std_logic_vector(3 downto 0); signal tx_data : std_logic_vector(8*4-1 downto 0); signal rx_data : std_logic_vector(8*4-1 downto 0); -signal buf_rx_data_reg : std_logic_vector(8*4-1 downto 0); signal ff_rxfullclk : std_logic_vector(3 downto 0); signal ff_txfullclk : std_logic; signal rx_k : std_logic_vector(3 downto 0); signal tx_k : std_logic_vector(3 downto 0); +signal last_tx_k : std_logic_vector(3 downto 0); signal lane_rst : std_logic_vector(3 downto 0); signal lane_rst_qtx : std_logic_vector(3 downto 0); signal quad_rst : std_logic_vector(3 downto 0); signal quad_rst_qtx : std_logic_vector(3 downto 0); -signal byte_waiting : std_logic_vector(3 downto 0); -signal byte_buffer : std_logic_vector(4*8-1 downto 0); -signal fifo_reset : std_logic_vector(3 downto 0); -signal tx_fifo_dout : std_logic_vector(4*16-1 downto 0); -signal tx_fifo_data_in : std_logic_vector(4*16-1 downto 0); -signal tx_fifo_read_en : std_logic_vector(3 downto 0); -signal tx_fifo_write_en : std_logic_vector(3 downto 0); -signal tx_fifo_empty : std_logic_vector(3 downto 0); -signal tx_fifo_full : std_logic_vector(3 downto 0); - -signal tx_fifo_valid_read : std_logic_vector(3 downto 0); signal tx_allow : std_logic_vector(3 downto 0); -signal tx_allow_del : std_logic_vector(3 downto 0); signal tx_allow_qtx : std_logic_vector(3 downto 0); -signal rx_data_reg : std_logic_vector(4*8-1 downto 0); -signal buf_rx_data : std_logic_vector(4*8-1 downto 0); -signal buf_rx_k : std_logic_vector(3 downto 0); -signal rx_fifo_write_en : std_logic_vector(3 downto 0); -signal rx_fifo_read_en : std_logic_vector(3 downto 0); -signal rx_fifo_empty : std_logic_vector(3 downto 0); -signal rx_fifo_full : std_logic_vector(3 downto 0); -signal rx_fifo_dout : std_logic_vector(4*8-1 downto 0); -signal is_idle_word : std_logic_vector(3 downto 0); -signal rx_starting : std_logic_vector(3 downto 0); + signal rx_allow : std_logic_vector(3 downto 0); -signal rx_allow_del : std_logic_vector(3 downto 0); -signal rx_allow_qrx : std_logic_vector(3 downto 0); signal sd_q : std_logic_vector(3 downto 0); -signal last_rx_fifo_read_en : std_logic_vector(3 downto 0); -signal last_rx_fifo_empty : std_logic_vector(3 downto 0); -signal last_last_rx_fifo_read_en : std_logic_vector(3 downto 0); -signal last_last_rx_fifo_empty : std_logic_vector(3 downto 0); -signal last_rx_fifo_dout : std_logic_vector(4*8-1 downto 0); -signal tx_fifo_valid_read_q : std_logic_vector(3 downto 0); signal buf_med_dataready_out : std_logic_vector(3 downto 0); signal buf_med_read_out : std_logic_vector(3 downto 0); signal buf_med_data_out : std_logic_vector(16*4-1 downto 0); -signal byte_select : std_logic_vector(3 downto 0); +signal buf_med_packet_num_out : std_logic_vector(3*4-1 downto 0); signal rx_counter : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); signal sfp_los : std_logic_vector(3 downto 0); @@ -316,21 +228,26 @@ signal FSM_STAT_OP : std_logic_vector(4*16-1 downto 0); signal FSM_STAT_DEBUG : std_logic_vector(4*32-1 downto 0); signal FSM_CTRL_OP : std_logic_vector(4*16-1 downto 0); -signal send_reset_q : std_logic_vector(3 downto 0); -signal reset_word_cnt : std_logic_vector(19 downto 0); +signal packet_timeout_i : std_logic_vector(3 downto 0); signal send_reset_words : std_logic_vector(3 downto 0); signal make_trbnet_reset : std_logic_vector(3 downto 0); +signal debug_txcontrol_i : std_logic_vector(127 downto 0); +signal debug_rxcontrol_i : std_logic_vector(127 downto 0); + +signal request_retransmit_i : std_logic_vector(3 downto 0); +signal start_retransmit_i : std_logic_vector(3 downto 0); +signal request_position_i : std_logic_vector(31 downto 0); +signal start_position_i : std_logic_vector(31 downto 0); +signal send_reset_words_ext : std_logic_vector(3 downto 0); +signal request_cnt_i : link_error_t; +signal reset_rx_control : std_logic_vector(3 downto 0); -signal packet_timeout : std_logic_vector(3 downto 0); -signal rx_bsm : std_logic_vector(15 downto 0); attribute syn_keep : boolean; attribute syn_preserve : boolean; attribute syn_keep of led_counter : signal is true; attribute syn_preserve of led_counter : signal is true; -attribute syn_keep of byte_waiting : signal is true; -attribute syn_preserve of byte_waiting : signal is true; begin gen_normal_serdes : if REVERSE_ORDER = c_NO generate @@ -593,373 +510,251 @@ THE_SERDES: serdes_fot_full_quad_ctc ); end generate; ---TX Control 25 ---------------- +gen_logic : for i in 0 to 3 generate -gen_tx_fifos: for i in 0 to 3 generate +----------------------------------------------------------------------- +--TX Control +----------------------------------------------------------------------- + THE_TX_CONTROL : trb_net16_tx_control + port map( + TXCLK_IN => CLK_25, + RXCLK_IN => CLK_25, + SYSCLK_IN => CLK, + RESET_IN => RESET, - THE_TX_FIFO: trb_net_fifo_16bit_bram_dualport - generic map( - USE_STATUS_FLAGS => c_NO - ) - port map( - read_clock_in => CLK_25,--ff_txfullclk, - write_clock_in => CLK, - read_enable_in => tx_fifo_read_en(i), - write_enable_in => tx_fifo_write_en(i), - fifo_gsr_in => fifo_reset(i), - write_data_in => "00" & tx_fifo_data_in((i+1)*16-1 downto i*16), - read_data_out(15 downto 0) => tx_fifo_dout((i+1)*16-1 downto i*16), - full_out => tx_fifo_full(i), - empty_out => tx_fifo_empty(i) - ); + TX_DATA_IN => MED_DATA_IN(i*16+15 downto i*16), + TX_WRITE_IN => MED_DATAREADY_IN(i), + TX_READ_OUT => MED_READ_OUT(i), + TX_DATA_OUT => tx_data(i*8+7 downto i*8), + TX_K_OUT => tx_k(i), - THE_READ_TX_FIFO_PROC: process( CLK_25 ) - begin - if( rising_edge(CLK_25) ) then - if( reset = '1' ) then - byte_waiting(i) <= '0'; - tx_fifo_read_en(i) <= '0'; - tx_k(i) <= '1'; - tx_data((i+1)*8-1 downto i*8) <= x"FE"; - tx_fifo_valid_read(i) <= '0'; - else - tx_fifo_read_en(i) <= tx_allow_qtx(i); - tx_fifo_valid_read(i) <= tx_fifo_read_en(i) and not tx_fifo_empty(i); - if( byte_waiting(i) = '0' ) then - if ( tx_fifo_valid_read(i) = '1' ) then - byte_buffer((i+1)*8-1 downto i*8) <= tx_fifo_dout((i)*16+15 downto i*16+8); - byte_waiting(i) <= '1'; - tx_k(i) <= '0'; - tx_data((i+1)*8-1 downto i*8) <= tx_fifo_dout(i*16+7 downto i*16+0); - tx_fifo_read_en(i) <= tx_allow_qtx(i); - elsif( send_reset_q(i) = '1' ) then - byte_buffer((i+1)*8-1 downto i*8) <= x"FE"; - byte_waiting(i) <= '1'; - tx_k(i) <= '1'; - tx_data((i+1)*8-1 downto i*8) <= x"FE"; - tx_fifo_read_en(i) <= '0'; - else - byte_buffer((i+1)*8-1 downto i*8) <= x"50"; - byte_waiting(i) <= '1'; - tx_k(i) <= '1'; - tx_data((i+1)*8-1 downto i*8) <= x"BC"; - tx_fifo_read_en(i) <= tx_allow_qtx(i); - end if; - else - tx_data((i+1)*8-1 downto i*8) <= byte_buffer((i+1)*8-1 downto i*8); - tx_k(i) <= send_reset_q(i); --second byte is always data - byte_waiting(i) <= '0'; - tx_fifo_read_en(i) <= '0'; - end if; - end if; - end if; - end process; - - fifo_reset(i) <= reset or quad_rst(0) or not rx_allow(i); --(sync with SYSCLK) - - --RX Control - --------------------- - - THE_RX_CONTROL : trb_net16_rx_packets + REQUEST_RETRANSMIT_IN => request_retransmit_i(i), + REQUEST_POSITION_IN => request_position_i(i*8+7 downto i*8), + START_RETRANSMIT_IN => start_retransmit_i(i), + START_POSITION_IN => start_position_i(i*8+7 downto i*8), + SEND_LINK_RESET_IN => send_reset_words_ext(i), + TX_ALLOW_IN => tx_allow(i), + + DEBUG_OUT => debug_txcontrol_i(i*32+31 downto i*32) + ); + + + +----------------------------------------------------------------------- +--RX Control +----------------------------------------------------------------------- + THE_RX_CONTROL : trb_net16_rx_control port map( - -- Resets - RESET_IN => fifo_reset(i), - QUAD_RST_IN => quad_rst(0), - -- data stream from SerDes - CLK_IN => CLK_25, - RX_ALLOW_IN => rx_allow(i), - RX_DATA_IN => rx_data(8*i+7 downto 8*i), - RX_K_IN => rx_k(i), + RESET_IN => reset_rx_control(i), + QUAD_RST_IN => quad_rst(0), + -- raw data from SerDes receive path + CLK_IN => CLK_25, + RX_DATA_IN => rx_data(i*8+7 downto i*8), + RX_K_IN => rx_k(i), + RX_CV_IN => link_error(i)(1), + RX_DISP_ERR_IN => link_error(i)(0), + RX_ALLOW_IN => rx_allow(i), -- media interface - SYSCLK_IN => CLK, - MED_DATA_OUT => MED_DATA_OUT(i*16+15 downto i*16), - MED_DATAREADY_OUT => MED_DATAREADY_OUT(i), - MED_READ_IN => MED_READ_IN(i), - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT(i*3+2 downto i*3), + SYSCLK_IN => CLK, + MED_DATA_OUT => buf_med_data_out(i*16+15 downto i*16), + MED_DATAREADY_OUT => buf_med_dataready_out(i), + MED_READ_IN => MED_READ_IN(i), + MED_PACKET_NUM_OUT => buf_med_packet_num_out(i*3+2 downto i*3), + -- request retransmission in case of error while receiving + REQUEST_RETRANSMIT_OUT => request_retransmit_i(i), + REQUEST_POSITION_OUT => request_position_i(i*8+7 downto i*8), + -- command decoding + START_RETRANSMIT_OUT => start_retransmit_i(i), + START_POSITION_OUT => start_position_i(i*8+7 downto i*8), -- reset handling - SEND_RESET_WORDS_OUT => send_reset_words(i), - MAKE_TRBNET_RESET_OUT => make_trbnet_reset(i), + SEND_RESET_WORDS_OUT => send_reset_words(i), + MAKE_TRBNET_RESET_OUT => make_trbnet_reset(i), -- Status signals - PACKET_TIMEOUT_OUT => packet_timeout(i), - -- Debug signals - BSM_OUT => rx_bsm(i*4+3 downto i*4), - DBG_OUT => open - ); + PACKET_TIMEOUT_OUT => packet_timeout_i(i), + -- Debugging + DEBUG_OUT => debug_rxcontrol_i(i*32+31 downto i*32) + ); - --TX Control (100) - --------------------- - buf_med_read_out(i) <= not tx_fifo_full(i) and tx_allow_del(i); - tx_fifo_write_en(i) <= buf_med_read_out(i) and med_dataready_in(i); - tx_fifo_data_in(i*16+15 downto i*16) <= med_data_in(i*16+15 downto i*16); - med_read_out(i) <= buf_med_read_out(i); +reset_rx_control(i) <= RESET or lane_rst(i) or link_error_q(i)(2) or link_error_q(i)(7); +----------------------------------------------------------------------- +--Link State Machine +----------------------------------------------------------------------- - --Link State machine - --------------------- - - CLK_TO_TX_SYNC: signal_sync - generic map( DEPTH => 2, WIDTH => 4 ) - port map( - RESET => reset, - D_IN(0) => tx_allow(i), - D_IN(1) => lane_rst(i), - D_IN(2) => quad_rst(i), - D_IN(3) => CTRL_OP(15+i*16), - CLK0 => CLK, - CLK1 => CLK_25, - D_OUT(0) => tx_allow_qtx(i), - D_OUT(1) => lane_rst_qtx(i), - D_OUT(2) => quad_rst_qtx(i), - D_OUT(3) => send_reset_q(i) - ); + THE_SFP_LSM: trb_net16_lsm_sfp + generic map( + CHECK_FOR_CV => c_NO + ) + port map( + SYSCLK => CLK, + RESET => reset, + CLEAR => reset, + SFP_MISSING_IN => '0', + SFP_LOS_IN => sfp_los(i), + SD_LINK_OK_IN => link_ok_q(i), + SD_LOS_IN => link_error_q(i)(2), + SD_TXCLK_BAD_IN => ffs_plol, + SD_RXCLK_BAD_IN => link_error_q(i)(7), + SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope + SD_ALIGNMENT_IN => "10", + SD_CV_IN(0) => link_error_q(i)(1), + SD_CV_IN(1) => '0', + FULL_RESET_OUT => quad_rst(i), + LANE_RESET_OUT => lane_rst(i), + TX_ALLOW_OUT => tx_allow(i), + RX_ALLOW_OUT => rx_allow(i), + SWAP_BYTES_OUT => open, + STAT_OP => FSM_STAT_OP(i*16+15 downto i*16), + CTRL_OP => FSM_CTRL_OP(i*16+15 downto i*16), + STAT_DEBUG => FSM_STAT_DEBUG(i*32+31 downto i*32) + ); - TX_TO_CLK_SYNC: signal_sync - generic map( DEPTH => 2, WIDTH => 1 ) - port map( - RESET => reset, - D_IN(0) => tx_fifo_valid_read(i), - CLK0 => CLK_25, - CLK1 => CLK, - D_OUT(0) => tx_fifo_valid_read_q(i) - ); - LINK_ERROR_SYNC: signal_sync - generic map( DEPTH => 2, WIDTH => 9 ) - port map( - RESET => reset, - D_IN(7 downto 0) => link_error(i), - D_IN(8) => link_ok(i), - CLK0 => CLK_25, - CLK1 => CLK, - D_OUT(7 downto 0) => link_error_q(i), - D_OUT(8) => link_ok_q(i) - ); - SYNC_INPUT_TO_CLK : signal_sync - generic map( DEPTH => 2, WIDTH => 3 ) - port map( - RESET => reset, - D_IN(0) => sd(i), - D_IN(1) => tx_allow(i), - D_IN(2) => rx_allow(i), - CLK0 => CLK, - CLK1 => CLK, - D_OUT(0) => sd_q(i), - D_OUT(1) => tx_allow_del(i), - D_OUT(2) => rx_allow_del(i) - ); +----------------------------------------------------------------------- +--Synchronizer +----------------------------------------------------------------------- - THE_SFP_STATUS_SYNC: signal_sync - generic map( DEPTH => 2, WIDTH => 1 ) - port map( - RESET => RESET, - D_IN(0) => rx_allow(i), - CLK0 => CLK, - CLK1 => CLK_25, - D_OUT(0) => rx_allow_qrx(i) - ); + CLK_TO_TX_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 4 + ) + port map( + RESET => reset, + D_IN(0) => tx_allow(i), + D_IN(1) => lane_rst(i), + D_IN(2) => quad_rst(i), + D_IN(3) => CTRL_OP(i*16+15), + CLK0 => CLK, + CLK1 => CLK_25, + D_OUT(0) => tx_allow_qtx(i), + D_OUT(1) => lane_rst_qtx(i), + D_OUT(2) => quad_rst_qtx(i), + D_OUT(3) => send_reset_words_ext(i) + ); + + RX_TO_CLK_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 9 + ) + port map( + RESET => reset, + D_IN(7 downto 0) => link_error(i), + D_IN(8) => link_ok(i), + CLK0 => CLK_25, + CLK1 => CLK, + D_OUT(7 downto 0) => link_error_q(i), + D_OUT(8) => link_ok_q(i) + ); + + SYNC_INPUT_TO_CLK : signal_sync + generic map( + DEPTH => 2, + WIDTH => 1 + ) + port map( + RESET => reset, + D_IN(0) => sd(i), + CLK0 => CLK, + CLK1 => CLK, + D_OUT(0) => sd_q(i) + ); + + sfp_los(i) <= not sd_q(i); + + + +----------------------------------------------------------------------- +--STAT & Debug +----------------------------------------------------------------------- + + + STAT_OP(i*16+7 downto i*16+0) <= FSM_STAT_OP(i*16+7 downto i*16+0); + STAT_OP(i*16+8) <= start_retransmit_i(i); + STAT_OP(i*16+9) <= FSM_STAT_OP(i*16+9); + STAT_OP(i*16+10) <= rx_led(i); + STAT_OP(i*16+11) <= tx_led(i); + STAT_OP(i*16+12) <= packet_timeout_i(i); --FSM_STAT_OP(i*16+12); + STAT_OP(i*16+13) <= make_trbnet_reset(i); + STAT_OP(i*16+14) <= FSM_STAT_OP(i*16+14); + STAT_OP(i*16+15) <= send_reset_words(i); + + STAT_DEBUG(i*64+15 downto i*64+0) <= FSM_STAT_DEBUG(i*32+15 downto i*32); + process(CLK) + begin + if rising_edge(CLK) then + STAT_DEBUG(i*64+16) <= request_retransmit_i(i); + STAT_DEBUG(i*64+17) <= start_retransmit_i(i); + STAT_DEBUG(i*64+25 downto i*64+18) <= rx_data(i*8+7 downto i*8); + STAT_DEBUG(i*64+26) <= rx_k(i); + STAT_DEBUG(i*64+31 downto i*64+27) <= (others => '0'); + end if; + end process; + STAT_DEBUG(i*64+47 downto i*64+32) <= debug_txcontrol_i(i*32+15 downto i*32); + STAT_DEBUG(i*64+63 downto i*64+48) <= debug_rxcontrol_i(i*32+15 downto i*32); + + +----------------------------------------------------------------------- +--Statistics +----------------------------------------------------------------------- + + process(clk) + begin + if rising_edge(clk) then + if request_retransmit_i(i) = '1' and CTRL_OP(i*16+15) = '0' then + request_cnt_i(i) <= request_cnt_i(i) + 1; + end if; + end if; + end process; + + + STAT_REG_OUT(i*32+11 downto i*32+0) <= (others => '0'); --reserved for trigger information + STAT_REG_OUT(i*32+23 downto i*32+12) <= (others => '0'); + STAT_REG_OUT(i*32+31 downto i*32+24) <= request_cnt_i(i); + +----------------------------------------------------------------------- +--LED Signals +----------------------------------------------------------------------- + THE_TX_RX_LED_PROC: process( clk_25 ) + begin + if( rising_edge(CLK_25) ) then + last_tx_k(i) <= tx_k(i); + if ( buf_med_dataready_out(i) = '1' ) then + rx_led(i) <= '1'; + elsif( led_counter = 0 ) then + rx_led(i) <= '0'; + end if; + if( tx_k(i) = '0' and last_tx_k(i) = '0') then + tx_led(i) <= '1'; + elsif led_counter = 0 then + tx_led(i) <= '0'; + end if; + end if; + end process; - --LED Signals - --------------------- - THE_TX_RX_LED_PROC: process( clk ) - begin - if( rising_edge(CLK) ) then - if ( buf_med_dataready_out(i) = '1' ) then - rx_led(i) <= '1'; - elsif( led_counter = 0 ) then - rx_led(i) <= '0'; - end if; - if ( tx_fifo_valid_read_q(i) = '1') then - tx_led(i) <= '1'; - elsif( led_counter = 0 ) then - tx_led(i) <= '0'; - end if; - end if; - end process THE_TX_RX_LED_PROC; - - STAT_OP(i*16+9 downto i*16+0) <= FSM_STAT_OP(i*16+9 downto i*16+0); - STAT_OP(i*16+10) <= rx_led(i); - STAT_OP(i*16+11) <= tx_led(i); - STAT_OP(i*16+12) <= packet_timeout(i); --FSM_STAT_OP(i*16+12); - STAT_OP(i*16+13) <= make_trbnet_reset(i); - STAT_OP(i*16+14) <= FSM_STAT_OP(i*16+14); - STAT_OP(i*16+15) <= send_reset_words(i); - - STAT_DEBUG(i*64+31 downto i*64+0) <= FSM_STAT_DEBUG(i*32+31 downto i*32); - STAT_DEBUG(i*64+39 downto i*64+32) <= buf_rx_data_reg(i*8+7 downto i*8); - STAT_DEBUG(i*64+40) <= rx_fifo_write_en(i); - STAT_DEBUG(i*64+48 downto i*64+41) <= last_rx_fifo_dout(i*8+7 downto i*8); - STAT_DEBUG(i*64+63 downto i*64+49) <= (others => '0'); - - PROC_DEBUG_OUT: process( CLK_25 ) - begin - if( rising_edge(CLK_25) ) then - buf_rx_data_reg <= rx_data_reg; - end if; - end process PROC_DEBUG_OUT; end generate; -PROC_LED_COUNTER: process(CLK) -begin - if( rising_edge(CLK) ) then - led_counter <= led_counter + 1; - end if; -end process PROC_LED_COUNTER; -gen_lsm : for i in 0 to 3 generate - THE_SFP_LSM: trb_net16_lsm_sfp - port map( - SYSCLK => CLK, - RESET => reset, - CLEAR => reset, - SFP_MISSING_IN => '0', - SFP_LOS_IN => sfp_los(i), - SD_LINK_OK_IN => link_ok_q(i), - SD_LOS_IN => link_error_q(i)(2), - SD_TXCLK_BAD_IN => ffs_plol, - SD_RXCLK_BAD_IN => link_error_q(i)(7), - SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope - SD_ALIGNMENT_IN => "10", - SD_CV_IN(0) => link_error_q(i)(1), - SD_CV_IN(1) => '0', - FULL_RESET_OUT => quad_rst(i), - LANE_RESET_OUT => lane_rst(i), - TX_ALLOW_OUT => tx_allow(i), - RX_ALLOW_OUT => rx_allow(i), - SWAP_BYTES_OUT => open, - STAT_OP => FSM_STAT_OP(i*16+15 downto i*16), - CTRL_OP => FSM_CTRL_OP(i*16+15 downto i*16), - STAT_DEBUG => FSM_STAT_DEBUG(i*32+31 downto i*32) - ); -end generate; + PROC_LED_COUNTER: process(CLK) + begin + if( rising_edge(CLK) ) then + led_counter <= led_counter + 1; + end if; + end process PROC_LED_COUNTER; + +----------------------------------------------------------------------- +--I/O +----------------------------------------------------------------------- + + MED_DATA_OUT <= buf_med_data_out; + MED_PACKET_NUM_OUT <= buf_med_packet_num_out; + MED_DATAREADY_OUT <= buf_med_dataready_out; + + FSM_CTRL_OP <= CTRL_OP; -SFP_LOS <= not sd_q; -FSM_CTRL_OP <= CTRL_OP; - -end architecture; - - - - --- THE_FIFO_RX: trb_net_fifo_16bit_bram_dualport --- generic map( --- USE_STATUS_FLAGS => c_NO --- ) --- port map( --- read_clock_in => clk, --- write_clock_in => CLK_25, --- read_enable_in => rx_fifo_read_en(i), --- write_enable_in => rx_fifo_write_en(i), --- fifo_gsr_in => fifo_reset(i), --- write_data_in => "00" & x"00" & rx_data_reg((i+1)*8-1 downto i*8), --- read_data_out(7 downto 0) => rx_fifo_dout((i+1)*8-1 downto i*8), --- full_out => rx_fifo_full(i), --- empty_out => rx_fifo_empty(i) --- ); - --- THE_WRITE_RX_FIFO_PROC: process( CLK_25 ) --- begin --- if( rising_edge(CLK_25) ) then --- buf_rx_data((i+1)*8-1 downto i*8) <= rx_data((i+1)*8-1 downto i*8); --- buf_rx_k(i) <= rx_k(i); --- if( (reset = '1') or (rx_allow_qrx(i) = '0') ) then --- rx_fifo_write_en(i) <= '0'; --- is_idle_word(i) <= '1'; --- rx_starting(i) <= '1'; --- else --- rx_data_reg((i+1)*8-1 downto i*8) <= buf_rx_data((i+1)*8-1 downto i*8); --- if( (buf_rx_k(i) = '0') and (is_idle_word(i) = '0') and (rx_starting(i) = '0') ) then --- rx_fifo_write_en(i) <= '1'; --- else --- rx_fifo_write_en(i) <= '0'; --- end if; --- if ( buf_rx_k(i) = '1' ) then --- is_idle_word(i) <= '1'; --- rx_starting(i) <= '0'; --- elsif( (buf_rx_k(i) = '0') and (is_idle_word(i) = '1') ) then --- is_idle_word(i) <= '0'; --- end if; --- end if; --- end if; --- end process THE_WRITE_RX_FIFO_PROC; - --- THE_CNT_RESET_PROC : process( CLK_25 ) --- begin --- if( rising_edge(CLK_25) ) then --- if( reset = '1' ) then --- send_reset_words(i) <= '0'; --- make_trbnet_reset(i) <= '0'; --- reset_word_cnt(i*5+4 downto i*5) <= (others => '0'); --- else --- send_reset_words(i) <= '0'; --- make_trbnet_reset(i) <= '0'; --- if( (buf_rx_data(i*8+7 downto i*8) = x"FE") and (buf_rx_k(i) = '1') ) then --- if( reset_word_cnt(i*5+4) = '0' ) then --- reset_word_cnt(i*5+4 downto i*5) <= reset_word_cnt(i*5+4 downto i*5) + 1; --- else --- send_reset_words(i) <= '1'; --- end if; --- else --- reset_word_cnt(i*5+4 downto i*5) <= (others => '0'); --- make_trbnet_reset(i) <= reset_word_cnt(i*5+4); --- end if; --- end if; --- end if; --- end process; - --RX Control (100) - --------------------- --- THE_RX_CTRL_PROC: process( clk ) --- begin --- if( rising_edge(clk) ) then --- if( reset = '1' ) then --- buf_med_dataready_out(i) <= '0'; --- byte_select(i) <= '0'; --- last_rx_fifo_read_en(i) <= '0'; --- else --- last_rx_fifo_read_en(i) <= rx_fifo_read_en(i); --- last_rx_fifo_empty(i) <= rx_fifo_empty(i); --- last_last_rx_fifo_read_en(i) <= last_rx_fifo_read_en(i); --- last_last_rx_fifo_empty(i) <= last_rx_fifo_empty(i); --- last_rx_fifo_dout(i*8+7 downto i*8) <= rx_fifo_dout(i*8+7 downto i*8); --- buf_med_dataready_out(i) <= '0'; --- if( (last_last_rx_fifo_empty(i) = '0') and (last_last_rx_fifo_read_en(i) = '1') ) then --- if( byte_select(i) = '1' ) then --- buf_MED_DATA_OUT((i+1)*16-1 downto i*16) <= last_rx_fifo_dout((i+1)*8-1 downto i*8) --- & buf_MED_DATA_OUT(i*16+7 downto i*16); --- buf_MED_DATAREADY_OUT(i) <= '1'; --- else --- buf_MED_DATA_OUT((i+1)*16-1 downto i*16) <= x"00" & last_rx_fifo_dout((i+1)*8-1 downto i*8); --- end if; --- byte_select(i) <= not byte_select(i); --- end if; --- end if; --- end if; --- end process THE_RX_CTRL_PROC; - --- rx_fifo_read_en(i) <= rx_allow_del(i) and not rx_fifo_empty(i); --- MED_DATA_OUT((i+1)*16-1 downto i*16) <= buf_MED_DATA_OUT((i+1)*16-1 downto i*16); --- MED_DATAREADY_OUT(i) <= buf_MED_DATAREADY_OUT(i); --- MED_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= rx_counter((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH); - --- --rx packet counter --- --------------------- --- THE_RX_PACKETS_PROC: process( clk ) --- begin --- if( rising_edge(clk) ) then --- if( (reset = '1') or (rx_allow(i) = '0') ) then --- rx_counter(i*3+2 downto i*3) <= c_H0; --- else --- if( buf_med_dataready_out(i) = '1' ) then --- if( rx_counter(i*3+2 downto i*3) = c_max_word_number ) then --- rx_counter(i*3+2 downto i*3) <= (others => '0'); --- else --- rx_counter(i*3+2 downto i*3) <= rx_counter(i*3+2 downto i*3) + 1; --- end if; --- end if; --- end if; --- end if; --- end process THE_RX_PACKETS_PROC; +end architecture; \ No newline at end of file diff --git a/media_interfaces/trb_net16_rx_checker.vhd b/media_interfaces/trb_net16_rx_checker.vhd new file mode 100644 index 0000000..4cefac7 --- /dev/null +++ b/media_interfaces/trb_net16_rx_checker.vhd @@ -0,0 +1,153 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +--use work.trb_net_components.all; + +entity trb_net16_rx_checker is +port( + -- Resets & clocks + SYSCLK_IN : in std_logic; + RESET_IN : in std_logic; + -- error detection and status signals + PKT_TOC_IN : in std_logic; -- full packet RX timeout + RX_IC_IN : in std_logic; -- illegal comma or CodeViolation on RX + STX_FND_IN : in std_logic; -- StartOfTransmission found on RX + PKT_IN_TRANS_IN : in std_logic; -- paket in transmission to media interface + -- control signals + FIFO_RST_OUT : out std_logic; -- clear RX FIFO + RESUME_OUT : out std_logic; -- full packet RX resume signal + REQ_RETRANS_OUT : out std_logic; -- request retransmission + -- Debug signals + BSM_OUT : out std_logic_vector(3 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) +); +end entity trb_net16_rx_checker; + + +architecture behavioral of trb_net16_rx_checker is + +-- state declarations +type STATES is (IDLE, CHK_PKT, RX_FAIL, WAIT_STX, DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; + +signal bsm_x : std_logic_vector(3 downto 0); +signal bsm : std_logic_vector(3 downto 0); + +signal fifo_rst_x : std_logic; +signal fifo_rst : std_logic; +signal resume_x : std_logic; +signal resume : std_logic; +signal request_x : std_logic; +signal request : std_logic; + +signal debug : std_logic_vector(15 downto 0); + +begin + +---------------------------------------------------------------------- +-- +---------------------------------------------------------------------- + +---------------------------------------------------------------------- +-- error checker state machine +---------------------------------------------------------------------- +-- state registers +STATE_MEM: process( SYSCLK_IN ) +begin + if( rising_edge(SYSCLK_IN) ) then + if( RESET_IN = '1' ) then + CURRENT_STATE <= IDLE; + fifo_rst <= '0'; + resume <= '0'; + request <= '0'; + bsm <= (others => '0'); + else + CURRENT_STATE <= NEXT_STATE; + fifo_rst <= fifo_rst_x; + resume <= resume_x; + request <= request_x; + bsm <= bsm_x; + end if; + end if; +end process STATE_MEM; + +-- state transitions +STATE_TRANSFORM: process( CURRENT_STATE, PKT_TOC_IN, RX_IC_IN, STX_FND_IN, PKT_IN_TRANS_IN ) +begin + NEXT_STATE <= IDLE; -- avoid latches + fifo_rst_x <= '0'; + resume_x <= '0'; + request_x <= '0'; + case CURRENT_STATE is + when IDLE => + if ( PKT_TOC_IN = '1' ) then + NEXT_STATE <= RX_FAIL; + fifo_rst_x <= '1'; + elsif( RX_IC_IN = '1' ) then + NEXT_STATE <= CHK_PKT; + else + NEXT_STATE <= IDLE; + end if; + when CHK_PKT => + if( PKT_IN_TRANS_IN = '1' ) then + NEXT_STATE <= CHK_PKT; + else + NEXT_STATE <= RX_FAIL; + fifo_rst_x <= '1'; + end if; + when RX_FAIL => + NEXT_STATE <= WAIT_STX; + fifo_rst_x <= '1'; + request_x <= '1'; + when WAIT_STX => + if( STX_FND_IN = '1' ) then + NEXT_STATE <= DONE; + resume_x <= '1'; + else + NEXT_STATE <= WAIT_STX; + fifo_rst_x <= '1'; + end if; + when DONE => + if( PKT_TOC_IN = '0' ) then + NEXT_STATE <= IDLE; + else + NEXT_STATE <= DONE; + end if; + when others => + NEXT_STATE <= IDLE; + end case; +end process STATE_TRANSFORM; + +-- just for debugging +THE_DECODE_PROC: process( NEXT_STATE ) +begin + case NEXT_STATE is + when IDLE => bsm_x <= x"0"; + when CHK_PKT => bsm_x <= x"1"; + when RX_FAIL => bsm_x <= x"2"; + when WAIT_STX => bsm_x <= x"3"; + when DONE => bsm_x <= x"4"; + when others => bsm_x <= x"f"; + end case; +end process THE_DECODE_PROC; + +---------------------------------------------------------------------- +-- Debug signals +---------------------------------------------------------------------- +debug(15 downto 12) <= bsm; +debug(11 downto 0) <= (others => '0'); + +---------------------------------------------------------------------- +-- Output signals +---------------------------------------------------------------------- +FIFO_RST_OUT <= fifo_rst; +RESUME_OUT <= resume; +REQ_RETRANS_OUT <= request; + +BSM_OUT <= bsm; +DBG_OUT <= debug; + +end behavioral; \ No newline at end of file diff --git a/media_interfaces/trb_net16_rx_comma_handler.vhd b/media_interfaces/trb_net16_rx_comma_handler.vhd new file mode 100644 index 0000000..6d5d4b4 --- /dev/null +++ b/media_interfaces/trb_net16_rx_comma_handler.vhd @@ -0,0 +1,270 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +--use work.trb_net_components.all; + +entity trb_net16_rx_comma_handler is +port( + RESET_IN : in std_logic; + QUAD_RST_IN : in std_logic; + -- raw data from SerDes receive path + CLK_IN : in std_logic; + RX_DATA_IN : in std_logic_vector(7 downto 0); + RX_K_IN : in std_logic; + RX_CV_IN : in std_logic; + RX_DISP_ERR_IN : in std_logic; + RX_ALLOW_IN : in std_logic; + -- FIFO interface + FIFO_DATA_OUT : out std_logic_vector(15 downto 0); + FIFO_WR_OUT : out std_logic; + FIFO_INHIBIT_OUT : out std_logic; + -- Special comma actions + LD_RX_POSITION_OUT : out std_logic; + RX_POSITION_OUT : out std_logic_vector(7 downto 0); + LD_START_POSITION_OUT : out std_logic; + START_POSITION_OUT : out std_logic_vector(7 downto 0); + -- Check + COMMA_LOCKED_OUT : out std_logic; + -- reset handling + SEND_RESET_WORDS_OUT : out std_logic; + MAKE_TRBNET_RESET_OUT : out std_logic; + -- Debugging + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end entity trb_net16_rx_comma_handler; + +architecture arch of trb_net16_rx_comma_handler is + +-- components + +-- normal signals +signal buf_rx_data : std_logic_vector(7 downto 0); +signal buf_rx_k : std_logic; +signal buf_rx_cv : std_logic; +signal buf_rx_disperr : std_logic; +signal buf2_rx_data : std_logic_vector(7 downto 0); +signal buf2_rx_k : std_logic; +signal buf2_rx_cv : std_logic; +signal buf2_rx_disperr : std_logic; +signal buf_data : std_logic_vector(15 downto 0); +signal buf2_data : std_logic_vector(15 downto 0); +signal buf_k : std_logic_vector(1 downto 0); +signal buf_cv : std_logic_vector(1 downto 0); +signal buf_disperr : std_logic_vector(1 downto 0); + +signal data_valid_x : std_logic; +signal comma_valid_x : std_logic; + +signal c_idle_x : std_logic; +signal c_idle : std_logic; -- 0xBC +signal c_reset_x : std_logic; +signal c_reset : std_logic; -- 0xFE +signal c_error_x : std_logic; +signal c_error : std_logic; -- 0xF7 +signal c_stx_x : std_logic; +signal c_stx : std_logic; -- 0xFB + +signal comma_idle : std_logic; -- correct IDLE comma (/I1/ or /I2/) received +signal comma_idle_x : std_logic; +signal comma_stx : std_logic; -- correct StartOfTransmission comma received +signal comma_stx_x : std_logic; +signal comma_error : std_logic; -- correct ErrorDetected comma received +signal comma_error_x : std_logic; + +signal comma_toggle : std_logic; +signal rst_toggle : std_logic; +signal ce_toggle : std_logic; + +signal comma_ctr : unsigned(3 downto 0); +signal comma_locked_x : std_logic; +signal comma_locked : std_logic; + +signal fifo_wr_x : std_logic; +signal fifo_wr : std_logic; + +signal ld_rx_position : std_logic; +signal rx_position : std_logic_vector(7 downto 0); +signal ld_start_position : std_logic; +signal start_position : std_logic_vector(7 downto 0); + +signal fifo_inhibit : std_logic; + +signal debug : std_logic_vector(15 downto 0); + +signal send_reset_words : std_logic; +signal make_trbnet_reset : std_logic; +signal reset_word_cnt : unsigned(4 downto 0); + +begin + +---------------------------------------------------------------------- +-- TRBnet reset handling (handles 0xFE comma) +---------------------------------------------------------------------- +THE_CNT_RESET_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + reset_word_cnt <= (others => '0'); + else + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + if( c_reset = '1' ) then + if( reset_word_cnt(4) = '0' ) then + reset_word_cnt <= reset_word_cnt + 1; + else + send_reset_words <= '1'; + end if; + else + reset_word_cnt <= (others => '0'); + make_trbnet_reset <= reset_word_cnt(4); + end if; + end if; + end if; +end process THE_CNT_RESET_PROC; + +---------------------------------------------------------------------- +-- sync the incoming data, check for commas +---------------------------------------------------------------------- +THE_SYNC_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + buf2_rx_data <= buf_rx_data; buf_rx_data <= RX_DATA_IN; + buf2_rx_k <= buf_rx_k; buf_rx_k <= RX_K_IN; + buf2_rx_cv <= buf_rx_cv; buf_rx_cv <= RX_CV_IN; + buf2_rx_disperr <= buf_rx_disperr; buf_rx_disperr <= RX_DISP_ERR_IN; + buf_data <= buf2_rx_data & buf_rx_data; + buf_k <= buf2_rx_k & buf_rx_k; + buf_cv <= buf2_rx_cv & buf_rx_cv; + buf_disperr <= buf2_rx_disperr & buf_rx_disperr; + c_idle <= c_idle_x; + c_reset <= c_reset_x; + c_error <= c_error_x; + c_stx <= c_stx_x; + comma_idle <= comma_idle_x; + comma_stx <= comma_stx_x; + comma_error <= comma_error_x; + comma_locked <= comma_locked_x; + fifo_wr <= fifo_wr_x; + ld_rx_position <= comma_stx; + ld_start_position <= comma_error; + if( comma_toggle = '1' ) then + buf2_data <= buf_data(7 downto 0) & buf_data(15 downto 8); + end if; + if( comma_stx = '1' ) then + rx_position <= buf_data(7 downto 0); + end if; + if( comma_error = '1' ) then + start_position <= buf_data(7 downto 0); + end if; + end if; +end process THE_SYNC_PROC; + +-- Comma recognition part I: K part of comma +c_idle_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"bc") ) else '0'; +c_reset_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"fe") ) else '0'; +c_error_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"f7") ) else '0'; +c_stx_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"fb") ) else '0'; + +-- Comma recognition part II: data part of comma +-- IDLE is allows any time +comma_idle_x <= '1' when ( (c_idle = '1') and (buf_rx_k = '0') and ((buf_rx_data = x"50") or (buf_rx_data = x"c5")) ) + else '0'; + +-- StartOfTransmission is only accepted in LOCKED state +comma_stx_x <= '1' when ( (c_stx = '1') and (buf_rx_k = '0') and (comma_locked_x = '1') ) else '0'; + +-- ErrorDetected is only accepted in LOCKED state +comma_error_x <= '1' when ( (c_error = '1') and (buf_rx_k = '0') and (comma_locked_x = '1') ) else '0'; + +-- reset toggle bit in case of mismatch during locking phase +rst_toggle <= '1' when ( ((comma_idle = '1') and (comma_toggle = '0') and (comma_locked_x = '0')) or + ((comma_idle = '0') and (comma_toggle = '1') and (comma_locked_x = '0')) or + (RX_ALLOW_IN = '0') ) + else '0'; + +-- count correctly received IDLE commas +ce_toggle <= '1' when ( (comma_idle = '1') and (comma_toggle = '1') and (comma_locked_x = '0') ) else '0'; + +-- reference toggle bit for 16bit reconstruction +THE_COMMA_TOGGLE_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( (RESET_IN = '1') or (rst_toggle = '1') ) then + comma_toggle <= '0'; + else + comma_toggle <= not comma_toggle; + end if; + end if; +end process THE_COMMA_TOGGLE_PROC; + +-- Lock counter: we require 16x correct IDLE commas to arrive in line. +-- After that we are locked till next reset starts the alignment again. +THE_LOCK_CTR_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if( (RESET_IN = '1') or (rst_toggle = '1') ) then + comma_ctr <= (others => '0'); + elsif( ce_toggle = '1' ) then + comma_ctr <= comma_ctr + 1; + end if; + end if; +end process THE_LOCK_CTR_PROC; + +comma_locked_x <= '1' when (comma_ctr = x"f") else '0'; + +---------------------------------------------------------------------- +-- check for correct data / comma values +---------------------------------------------------------------------- + +comma_valid_x <= comma_locked and (comma_idle or comma_error or comma_stx) + and not buf_cv(1) and not buf_cv(0) and not buf_disperr(0) and not buf_disperr(1); + +data_valid_x <= comma_locked and not buf_k(1) and not buf_k(0) + and not buf_cv(1) and not buf_cv(0) and not buf_disperr(0) and not buf_disperr(1); + +fifo_wr_x <= comma_toggle and data_valid_x and not fifo_inhibit; + +THE_FIFO_INHIBIT_PROC: process( CLK_IN ) +begin + if( rising_edge(CLK_IN) ) then + if ( (RESET_IN = '1') or (comma_stx = '1') ) then + fifo_inhibit <= '0'; + elsif( (comma_locked = '1') and (comma_toggle = '1') and (comma_valid_x = '0') and (data_valid_x = '0') ) then + fifo_inhibit <= '1'; + end if; + end if; +end process THE_FIFO_INHIBIT_PROC; + +---------------------------------------------------------------------- +-- Debug signals +---------------------------------------------------------------------- +debug(15) <= comma_valid_x; +debug(14) <= data_valid_x; +debug(13) <= fifo_inhibit; +debug(12 downto 0) <= (others => '0'); + +---------------------------------------------------------------------- +-- Output signals +---------------------------------------------------------------------- +FIFO_DATA_OUT <= buf2_data; +FIFO_WR_OUT <= fifo_wr; +FIFO_INHIBIT_OUT <= fifo_inhibit; + +LD_START_POSITION_OUT <= ld_start_position; +START_POSITION_OUT <= start_position; +LD_RX_POSITION_OUT <= ld_rx_position; +RX_POSITION_OUT <= rx_position; + +COMMA_LOCKED_OUT <= comma_locked; + +SEND_RESET_WORDS_OUT <= send_reset_words; +MAKE_TRBNET_RESET_OUT <= make_trbnet_reset; + +DEBUG_OUT <= debug; + +end architecture; \ No newline at end of file diff --git a/media_interfaces/trb_net16_rx_control.vhd b/media_interfaces/trb_net16_rx_control.vhd index d4b7d20..06c31fe 100644 --- a/media_interfaces/trb_net16_rx_control.vhd +++ b/media_interfaces/trb_net16_rx_control.vhd @@ -15,6 +15,7 @@ port( RX_DATA_IN : in std_logic_vector(7 downto 0); RX_K_IN : in std_logic; RX_CV_IN : in std_logic; + RX_DISP_ERR_IN : in std_logic; RX_ALLOW_IN : in std_logic; -- media interface SYSCLK_IN : in std_logic; -- 100MHz master clock @@ -33,6 +34,7 @@ port( MAKE_TRBNET_RESET_OUT : out std_logic; -- Status signals PACKET_TIMEOUT_OUT : out std_logic; + COMMA_LOCKED_OUT : out std_logic; -- Debugging DEBUG_OUT : out std_logic_vector(31 downto 0) ); @@ -43,6 +45,36 @@ end entity; architecture arch of trb_net16_rx_control is -- components +component trb_net16_rx_comma_handler is +port( + RESET_IN : in std_logic; + QUAD_RST_IN : in std_logic; + -- raw data from SerDes receive path + CLK_IN : in std_logic; + RX_DATA_IN : in std_logic_vector(7 downto 0); + RX_K_IN : in std_logic; + RX_CV_IN : in std_logic; + RX_DISP_ERR_IN : in std_logic; + RX_ALLOW_IN : in std_logic; + -- FIFO interface + FIFO_DATA_OUT : out std_logic_vector(15 downto 0); + FIFO_WR_OUT : out std_logic; + FIFO_INHIBIT_OUT : out std_logic; + -- Special comma actions + LD_RX_POSITION_OUT : out std_logic; + RX_POSITION_OUT : out std_logic_vector(7 downto 0); + LD_START_POSITION_OUT : out std_logic; + START_POSITION_OUT : out std_logic_vector(7 downto 0); + -- Check + COMMA_LOCKED_OUT : out std_logic; + -- reset handling + SEND_RESET_WORDS_OUT : out std_logic; + MAKE_TRBNET_RESET_OUT : out std_logic; + -- Debugging + DEBUG_OUT : out std_logic_vector(15 downto 0) +); +end component trb_net16_rx_comma_handler; + component trb_net16_rx_full_packets is port( -- Resets & clocks @@ -50,7 +82,7 @@ port( RESET_IN : in std_logic; -- FIFO signals FIFO_READ_OUT : out std_logic; - FIFO_RCNT_IN : in std_logic_vector(8 downto 0); + FIFO_RCNT_IN : in std_logic_vector(9 downto 0); FIFO_RESET_OUT : out std_logic; -- Media Interface MED_READ_IN : in std_logic; @@ -60,6 +92,7 @@ port( PKT_IN_TRANSIT_OUT : out std_logic; -- Status signals RX_ALLOW_IN : in std_logic; + RX_RESUME_IN : in std_logic; RX_LD_DATA_CTR_IN : in std_logic; RX_DATA_CTR_VAL_IN : in std_logic_vector(7 downto 0); RX_DATA_CTR_OUT : out std_logic_vector(7 downto 0); @@ -70,21 +103,41 @@ port( ); end component trb_net16_rx_full_packets; -component trb_net_fifo_8bit_16bit_bram_dualport is +component trb_net16_rx_checker is +port( + -- Resets & clocks + SYSCLK_IN : in std_logic; + RESET_IN : in std_logic; + -- error detection and status signals + PKT_TOC_IN : in std_logic; -- full packet RX timeout + RX_IC_IN : in std_logic; -- illegal comma or CodeViolation on RX + STX_FND_IN : in std_logic; -- StartOfTransmission found on RX + PKT_IN_TRANS_IN : in std_logic; -- paket in transmission to media interface + -- control signals + FIFO_RST_OUT : out std_logic; -- clear RX FIFO + RESUME_OUT : out std_logic; -- full packet RX resume signal + REQ_RETRANS_OUT : out std_logic; -- request retransmission + -- Debug signals + BSM_OUT : out std_logic_vector(3 downto 0); + DBG_OUT : out std_logic_vector(15 downto 0) +); +end component trb_net16_rx_checker; + +component trb_net_fifo_16bit_16bit_bram_dualport is port( READ_CLOCK_IN : in std_logic; WRITE_CLOCK_IN : in std_logic; READ_ENABLE_IN : in std_logic; WRITE_ENABLE_IN : in std_logic; FIFO_GSR_IN : in std_logic; - WRITE_DATA_IN : in std_logic_vector(7 downto 0); + WRITE_DATA_IN : in std_logic_vector(15 downto 0); READ_DATA_OUT : out std_logic_vector(15 downto 0); FULL_OUT : out std_logic; EMPTY_OUT : out std_logic; WCNT_OUT : out std_logic_vector(9 downto 0); - RCNT_OUT : out std_logic_vector(8 downto 0) + RCNT_OUT : out std_logic_vector(9 downto 0) ); -end component trb_net_fifo_8bit_16bit_bram_dualport; +end component trb_net_fifo_16bit_16bit_bram_dualport; component pulse_sync is port( @@ -97,9 +150,14 @@ port( ); end component pulse_sync; --- state declarations -type STATES is (IDLE, CHK_PKT, RX_FAIL); -signal CURRENT_STATE, NEXT_STATE: STATES; +component state_sync is +port( + STATE_A_IN : in std_logic; + RESET_B_IN : in std_logic; + CLK_B_IN : in std_logic; + STATE_B_OUT : out std_logic +); +end component state_sync; -- normal signals signal update : std_logic; @@ -108,45 +166,38 @@ signal med_data : std_logic_vector(15 downto 0); signal med_packet_num : std_logic_vector(2 downto 0); signal packet_timeout : std_logic; signal debug_rfp : std_logic_vector(15 downto 0); - -signal buf_rx_data : std_logic_vector(7 downto 0); -signal buf_rx_k : std_logic; -signal buf_rx_cv : std_logic; +signal debug_rxc : std_logic_vector(15 downto 0); +signal debug_rch : std_logic_vector(15 downto 0); signal fifo_wr_en : std_logic; signal fifo_rd_en : std_logic; -signal fifo_wr_data : std_logic_vector(7 downto 0); +signal fifo_wr_data : std_logic_vector(15 downto 0); signal fifo_rd_data : std_logic_vector(15 downto 0); signal fifo_reset : std_logic; -signal fifo_rcnt : std_logic_vector(8 downto 0); +signal fifo_rcnt : std_logic_vector(9 downto 0); signal fifo_rst : std_logic; -signal is_idle_word : std_logic; -signal rx_starting : std_logic; signal send_reset_words : std_logic; signal make_trbnet_reset : std_logic; -signal reset_word_cnt : unsigned(4 downto 0); - -signal comma_idle_x : std_logic; -signal comma_idle : std_logic; -- 0xBC -signal comma_reset_x : std_logic; -signal comma_reset : std_logic; -- 0xFE -signal comma_errordetd_x : std_logic; -signal comma_errordetd : std_logic; -- 0xF7 -signal comma_startoftx_x : std_logic; -signal comma_startoftx : std_logic; -- 0xFB -signal comma_invalid_x : std_logic; -signal comma_invalid : std_logic; -- all other commas are invalid! +signal request_retransmit : std_logic; signal request_position : std_logic_vector(7 downto 0); +signal start_retransmit_x : std_logic; signal start_retransmit : std_logic; signal start_position : std_logic_vector(7 downto 0); +signal ld_rx_position_x : std_logic; signal ld_rx_position : std_logic; signal rx_position : std_logic_vector(7 downto 0); signal pkt_in_transit : std_logic; +signal rx_resume : std_logic; + +signal rx_gone_wrong_x : std_logic; +signal rx_gone_wrong : std_logic; + +signal comma_locked : std_logic; signal debug : std_logic_vector(31 downto 0); @@ -155,132 +206,70 @@ begin ---------------------------------------------------------------------- -- decoding of raw commas ---------------------------------------------------------------------- -comma_idle_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"bc") ) else '0'; -comma_reset_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"fe") ) else '0'; -comma_errordetd_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"f7") ) else '0'; -comma_startoftx_x <= '1' when ( (buf_rx_k = '1') and (buf_rx_data = x"fb") ) else '0'; -comma_invalid_x <= '1' when ( ( (buf_rx_k = '1') and - (comma_idle ='0') and (comma_reset = '0') and - (comma_errordetd = '0') and (comma_startoftx = '0') ) or - (buf_rx_cv = '1') ) - else '0'; - ----------------------------------------------------------------------- --- StartOfTransmission comma handling ----------------------------------------------------------------------- --- store the RX position raw data -THE_RX_POSITION_PROC: process( CLK_IN ) -begin - if( rising_edge(CLK_IN) ) then - if( comma_startoftx = '1' ) then - rx_position <= buf_rx_data; - end if; - end if; -end process THE_RX_POSITION_PROC; +THE_COMMA_HANDLER: trb_net16_rx_comma_handler +port map( + RESET_IN => RESET_IN, + QUAD_RST_IN => QUAD_RST_IN, + -- raw data from SerDes receive path + CLK_IN => CLK_IN, + RX_DATA_IN => RX_DATA_IN, + RX_K_IN => RX_K_IN, + RX_CV_IN => RX_CV_IN, + RX_DISP_ERR_IN => RX_DISP_ERR_IN, + RX_ALLOW_IN => RX_ALLOW_IN, + -- FIFO interface + FIFO_DATA_OUT => fifo_wr_data, + FIFO_WR_OUT => fifo_wr_en, + FIFO_INHIBIT_OUT => rx_gone_wrong_x, -- BUG + -- Special comma actions + LD_RX_POSITION_OUT => ld_rx_position_x, + RX_POSITION_OUT => rx_position, + LD_START_POSITION_OUT => start_retransmit_x, + START_POSITION_OUT => start_position, + -- Check + COMMA_LOCKED_OUT => comma_locked, + -- reset handling + SEND_RESET_WORDS_OUT => send_reset_words, + MAKE_TRBNET_RESET_OUT => make_trbnet_reset, + -- Debugging + DEBUG_OUT => debug_rch +); -- clock domain transfer for internal RX data counter THE_LD_PULSE_SYNC: pulse_sync port map( CLK_A_IN => CLK_IN, RESET_A_IN => RESET_IN, - PULSE_A_IN => comma_startoftx, + PULSE_A_IN => ld_rx_position_x, CLK_B_IN => SYSCLK_IN, RESET_B_IN => RESET_IN, PULSE_B_OUT => ld_rx_position ); ----------------------------------------------------------------------- --- ErrorDetected comma handling ----------------------------------------------------------------------- - --- store the RX position raw data -THE_START_POSITION_PROC: process( CLK_IN ) -begin - if( rising_edge(CLK_IN) ) then - if( comma_errordetd = '1' ) then - start_position <= buf_rx_data; - end if; - end if; -end process THE_START_POSITION_PROC; - -- clock domain transfer for internal RX data counter THE_RT_PULSE_SYNC: pulse_sync port map( CLK_A_IN => CLK_IN, RESET_A_IN => RESET_IN, - PULSE_A_IN => comma_errordetd, + PULSE_A_IN => start_retransmit_x, CLK_B_IN => SYSCLK_IN, RESET_B_IN => RESET_IN, PULSE_B_OUT => start_retransmit ); ----------------------------------------------------------------------- --- FIFO write process, only data bytes are stored (Jan's work) ----------------------------------------------------------------------- -THE_WRITE_RX_FIFO_PROC: process( CLK_IN ) -begin - if( rising_edge(CLK_IN) ) then - -- pipeline comma detection - comma_idle <= comma_idle_x; - comma_reset <= comma_reset_x; - comma_errordetd <= comma_errordetd_x; - comma_startoftx <= comma_startoftx_x; - -- pipeline data - buf_rx_data <= RX_DATA_IN; - buf_rx_k <= RX_K_IN; - buf_rx_cv <= RX_CV_IN; - if( (RESET_IN = '1') or (RX_ALLOW_IN = '0') ) then - fifo_wr_en <= '0'; - is_idle_word <= '1'; - rx_starting <= '1'; - else - fifo_wr_data <= buf_rx_data; - if( (buf_rx_k = '0') and (is_idle_word = '0') and (rx_starting = '0') ) then - fifo_wr_en <= '1'; - else - fifo_wr_en <= '0'; - end if; - if ( buf_rx_k = '1' ) then - is_idle_word <= '1'; - rx_starting <= '0'; - elsif( (buf_rx_k = '0') and (is_idle_word = '1') ) then - is_idle_word <= '0'; - end if; - end if; - end if; -end process THE_WRITE_RX_FIFO_PROC; - ----------------------------------------------------------------------- --- TRBnet reset handling (handles 0xFE comma) ----------------------------------------------------------------------- -THE_CNT_RESET_PROC: process( CLK_IN ) -begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - send_reset_words <= '0'; - make_trbnet_reset <= '0'; - reset_word_cnt <= (others => '0'); - else - send_reset_words <= '0'; - make_trbnet_reset <= '0'; - if( comma_reset = '1' ) then - if( reset_word_cnt(4) = '0' ) then - reset_word_cnt <= reset_word_cnt + 1; - else - send_reset_words <= '1'; - end if; - else - reset_word_cnt <= (others => '0'); - make_trbnet_reset <= reset_word_cnt(4); - end if; - end if; - end if; -end process; +-- clock domain transfer for RX problems +THE_GONE_WRONG_SYNC: state_sync +port map( + STATE_A_IN => rx_gone_wrong_x, + RESET_B_IN => RESET_IN, + CLK_B_IN => SYSCLK_IN, + STATE_B_OUT => rx_gone_wrong +); ---------------------------------------------------------------------- -- the RX FIFO itself ---------------------------------------------------------------------- -THE_RX_FIFO: trb_net_fifo_8bit_16bit_bram_dualport +THE_RX_FIFO: trb_net_fifo_16bit_16bit_bram_dualport port map( READ_CLOCK_IN => SYSCLK_IN, WRITE_CLOCK_IN => CLK_IN, @@ -308,15 +297,16 @@ port map( -- FIFO signals FIFO_READ_OUT => fifo_rd_en, FIFO_RCNT_IN => fifo_rcnt, - FIFO_RESET_OUT => fifo_rst, + FIFO_RESET_OUT => open, -- not used anymore -- Media Interface MED_READ_IN => MED_READ_IN, MED_DATAREADY_OUT => med_dataready, MED_PACKET_NUM_OUT => med_packet_num, UPDATE_OUT => update, - PKT_IN_TRANSIT_OUT => pkt_in_transit, -- BUG + PKT_IN_TRANSIT_OUT => pkt_in_transit, -- Status signals RX_ALLOW_IN => RX_ALLOW_IN, + RX_RESUME_IN => rx_resume, RX_LD_DATA_CTR_IN => ld_rx_position, RX_DATA_CTR_VAL_IN => rx_position, RX_DATA_CTR_OUT => request_position, @@ -335,12 +325,39 @@ begin end if; end process THE_SYNC_SYSCLK_PROC; +---------------------------------------------------------------------- +-- RX checker state machine, does NOT include CRC checking! +---------------------------------------------------------------------- +THE_RX_CHECKER: trb_net16_rx_checker +port map( + -- Resets & clocks + SYSCLK_IN => SYSCLK_IN, + RESET_IN => RESET_IN, + -- error detection and status signals + PKT_TOC_IN => packet_timeout, + RX_IC_IN => rx_gone_wrong, + STX_FND_IN => ld_rx_position, + PKT_IN_TRANS_IN => pkt_in_transit, + -- control signals + FIFO_RST_OUT => fifo_rst, + RESUME_OUT => rx_resume, + REQ_RETRANS_OUT => request_retransmit, + -- Debug signals + BSM_OUT => open, + DBG_OUT => debug_rxc +); + ---------------------------------------------------------------------- -- Debug signals ---------------------------------------------------------------------- debug(31 downto 16) <= debug_rfp; -debug(15 downto 1) <= (others => '0'); -debug(0) <= pkt_in_transit; +-- debug(15 downto 0) <= debug_rch; --(others => '0'); + +debug(0) <= packet_timeout; +debug(1) <= rx_gone_wrong; +debug(2) <= pkt_in_transit; +debug(15 downto 3) <= debug_rch(15 downto 3); + ---------------------------------------------------------------------- -- Output signals @@ -348,13 +365,14 @@ debug(0) <= pkt_in_transit; SEND_RESET_WORDS_OUT <= send_reset_words; MAKE_TRBNET_RESET_OUT <= make_trbnet_reset; PACKET_TIMEOUT_OUT <= packet_timeout; +COMMA_LOCKED_OUT <= comma_locked; MED_DATAREADY_OUT <= med_dataready; MED_DATA_OUT <= med_data; MED_PACKET_NUM_OUT <= med_packet_num; -- used by internal logic -REQUEST_RETRANSMIT_OUT <= '0'; +REQUEST_RETRANSMIT_OUT <= request_retransmit; REQUEST_POSITION_OUT <= request_position; -- forwarding of retransmit request diff --git a/media_interfaces/trb_net16_rx_full_packets.vhd b/media_interfaces/trb_net16_rx_full_packets.vhd index 3d2de70..aca3bbf 100644 --- a/media_interfaces/trb_net16_rx_full_packets.vhd +++ b/media_interfaces/trb_net16_rx_full_packets.vhd @@ -13,7 +13,7 @@ port( RESET_IN : in std_logic; -- FIFO signals FIFO_READ_OUT : out std_logic; - FIFO_RCNT_IN : in std_logic_vector(8 downto 0); + FIFO_RCNT_IN : in std_logic_vector(9 downto 0); FIFO_RESET_OUT : out std_logic; -- Media Interface MED_READ_IN : in std_logic; @@ -23,6 +23,7 @@ port( PKT_IN_TRANSIT_OUT : out std_logic; -- full packet received and in transmission to media interface -- Status signals RX_ALLOW_IN : in std_logic; + RX_RESUME_IN : in std_logic; RX_LD_DATA_CTR_IN : in std_logic; RX_DATA_CTR_VAL_IN : in std_logic_vector(7 downto 0); RX_DATA_CTR_OUT : out std_logic_vector(7 downto 0); @@ -69,7 +70,7 @@ signal transit_x : std_logic; signal transit : std_logic; signal fifo_rd_en_x : std_logic; -signal fifo_rcnt : unsigned(8 downto 0); +signal fifo_rcnt : unsigned(9 downto 0); signal fifo_rst_x : std_logic; signal fifo_rst : std_logic; @@ -142,7 +143,7 @@ begin end process STATE_MEM; -- state transitions -STATE_TRANSFORM: process( CURRENT_STATE, fifo_rcnt, MED_READ_IN, med_dataready, toc_done ) +STATE_TRANSFORM: process( CURRENT_STATE, fifo_rcnt, RX_RESUME_IN, MED_READ_IN, med_dataready, toc_done ) begin NEXT_STATE <= IDLE; -- avoid latches fifo_rd_en_x <= '0'; @@ -177,6 +178,9 @@ begin pkt_timeout_x <= '1'; rst_toc_x <= '1'; fifo_rst_x <= '1'; + elsif( RX_RESUME_IN = '1' ) then -- NEW + NEXT_STATE <= IDLE; -- NEW + rst_toc_x <= '1'; -- NEW else NEXT_STATE <= RD1; ce_toc_x <= '1'; @@ -194,6 +198,9 @@ begin pkt_timeout_x <= '1'; rst_toc_x <= '1'; fifo_rst_x <= '1'; + elsif( RX_RESUME_IN = '1' ) then -- NEW + NEXT_STATE <= IDLE; -- NEW + rst_toc_x <= '1'; -- NEW else NEXT_STATE <= RD2; ce_toc_x <= '1'; @@ -282,11 +289,15 @@ begin med_dataready_x <= '1'; end if; when TOC => - NEXT_STATE <= CLEAN; - pkt_timeout_x <= '1'; - fifo_rst_x <= '1'; + if( RX_RESUME_IN = '1' ) then + NEXT_STATE <= CLEAN; + else + NEXT_STATE <= TOC; + pkt_timeout_x <= '1'; + fifo_rst_x <= '1'; + end if; when CLEAN => - NEXT_STATE <= IDLE; + NEXT_STATE <= IDLE; -- not really necessary? when others => NEXT_STATE <= IDLE; diff --git a/media_interfaces/trb_net16_tx_control.vhd b/media_interfaces/trb_net16_tx_control.vhd index 5b6eb2e..d74e3c9 100644 --- a/media_interfaces/trb_net16_tx_control.vhd +++ b/media_interfaces/trb_net16_tx_control.vhd @@ -190,9 +190,9 @@ THE_RAM_WR_PROC : process(TXCLK_IN) THE_DATA_CONTROL_FSM : process(TXCLK_IN) begin if rising_edge(TXCLK_IN) then - if RESET_IN = '1' then - null; - else +-- if RESET_IN = '1' then +-- null; +-- else ram_read <= '0'; case current_state is @@ -271,7 +271,7 @@ THE_RAM_WR_PROC : process(TXCLK_IN) end if; end if; - end if; +-- end if; end process; ---------------------------------------------------------------------- @@ -337,8 +337,9 @@ THE_RAM_WR_PROC : process(TXCLK_IN) elsif request_retransmit_i = '1' then make_request_i <= '1'; request_position_i <= request_position_q; - elsif current_state = SEND_REQUEST_H then + elsif current_state = SEND_REQUEST_L then make_request_i <= '0'; + elsif current_state = SEND_REQUEST_H then request_position_i <= (others => '0'); end if; end if; diff --git a/pinout/mdchub_fpga1234.lpf b/pinout/mdchub_fpga1234.lpf index 1c53675..570ee05 100644 --- a/pinout/mdchub_fpga1234.lpf +++ b/pinout/mdchub_fpga1234.lpf @@ -6,6 +6,7 @@ COMMERCIAL ; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; + BLOCK RD_DURING_WR_PATHS; ##################################################################### # Clocks & Resets diff --git a/testbenches/tb_trb_net16_rxtx_control.vhd b/testbenches/tb_trb_net16_rxtx_control.vhd new file mode 100644 index 0000000..57f19e2 --- /dev/null +++ b/testbenches/tb_trb_net16_rxtx_control.vhd @@ -0,0 +1,394 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +--use work.trb_net_components.all; + +entity rxtxtb is +end entity; + +architecture arch of rxtxtb is + + component trb_net16_tx_control is + port( + TXCLK_IN : in std_logic; + RXCLK_IN : in std_logic; + SYSCLK_IN : in std_logic; + RESET_IN : in std_logic; + + TX_DATA_IN : in std_logic_vector(15 downto 0); + TX_WRITE_IN : in std_logic; + TX_READ_OUT : out std_logic; + + TX_DATA_OUT : out std_logic_vector( 7 downto 0); + TX_K_OUT : out std_logic; + + REQUEST_RETRANSMIT_IN : in std_logic; + REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0); + + START_RETRANSMIT_IN : in std_logic; + START_POSITION_IN : in std_logic_vector( 7 downto 0); + + SEND_LINK_RESET_IN : in std_logic; + TX_ALLOW_IN : in std_logic; + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + end component; + + component trb_net16_rx_control is + port( + RESET_IN : in std_logic; + QUAD_RST_IN : in std_logic; + -- raw data from SerDes receive path + CLK_IN : in std_logic; + RX_DATA_IN : in std_logic_vector(7 downto 0); + RX_K_IN : in std_logic; + RX_CV_IN : in std_logic; + RX_ALLOW_IN : in std_logic; + -- media interface + SYSCLK_IN : in std_logic; -- 100MHz master clock + MED_DATA_OUT : out std_logic_vector(15 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + -- request retransmission in case of error while receiving + REQUEST_RETRANSMIT_OUT : out std_logic; -- one pulse + REQUEST_POSITION_OUT : out std_logic_vector( 7 downto 0); + -- command decoding + START_RETRANSMIT_OUT : out std_logic; + START_POSITION_OUT : out std_logic_vector( 7 downto 0); + -- reset handling + SEND_RESET_WORDS_OUT : out std_logic; + MAKE_TRBNET_RESET_OUT : out std_logic; + -- Status signals + PACKET_TIMEOUT_OUT : out std_logic; + -- Debugging + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + end component; + + + signal clk : std_logic := '1'; + signal clk251 : std_logic := '1'; + signal clk252 : std_logic := '1'; + signal reset : std_logic := '1'; + + signal tx1_data_in : std_logic_vector(15 downto 0) := (others => '0'); + signal tx1_write_in : std_logic := '0'; + signal tx1_read_out : std_logic := '0'; + signal tx2_data_in : std_logic_vector(15 downto 0) := (others => '0'); + signal tx2_write_in : std_logic := '0'; + signal tx2_read_out : std_logic := '0'; + + signal tx1_data_out : std_logic_vector( 7 downto 0) := (others => '0'); + signal tx1_k_out : std_logic := '0'; + signal tx2_data_out : std_logic_vector( 7 downto 0) := (others => '0'); + signal tx2_k_out : std_logic := '0'; + + signal rx1_data_in : std_logic_vector( 7 downto 0) := (others => '0'); + signal rx1_k_in : std_logic := '0'; + signal rx1_cv_in : std_logic := '0'; + signal rx1_allow_in : std_logic := '0'; + signal rx2_data_in : std_logic_vector( 7 downto 0) := (others => '0'); + signal rx2_k_in : std_logic := '0'; + signal rx2_cv_in : std_logic := '0'; + signal rx2_allow_in : std_logic := '0'; + + + signal tx1_request_retransmit_in : std_logic := '0'; + signal tx1_request_position_in : std_logic_vector( 7 downto 0) := (others => '0'); + signal tx1_start_retransmit_in : std_logic := '0'; + signal tx1_start_position_in : std_logic_vector( 7 downto 0) := (others => '0'); + signal tx1_send_link_reset_in : std_logic := '0'; + signal tx2_request_retransmit_in : std_logic := '0'; + signal tx2_request_position_in : std_logic_vector( 7 downto 0) := (others => '0'); + signal tx2_start_retransmit_in : std_logic := '0'; + signal tx2_start_position_in : std_logic_vector( 7 downto 0) := (others => '0'); + signal tx2_send_link_reset_in : std_logic := '0'; + + signal tx1_allow_in : std_logic := '0'; + signal tx2_allow_in : std_logic := '0'; + + +begin + + proc_clk251 : process + begin + wait for 20 ns; + clk251 <= not clk251; + end process; + + proc_clk252 : process + begin + wait for 5 ns; + while 1 = 1 loop + wait for 20 ns; + clk252 <= not clk252; + end loop; + end process; + + proc_clk : process + begin + wait for 5 ns; + clk <= not clk; + end process; + + proc_reset : process + begin + reset <= '1'; + wait for 105 ns; + reset <= '0'; + wait; + end process; + + uut_tx1 : trb_net16_tx_control + port map( + TXCLK_IN => clk251, + RXCLK_IN => clk252, + SYSCLK_IN => clk, + RESET_IN => reset, + + TX_DATA_IN => tx1_data_in, + TX_WRITE_IN => tx1_write_in, + TX_READ_OUT => tx1_read_out, + + TX_DATA_OUT => tx1_data_out, + TX_K_OUT => tx1_k_out, + + REQUEST_RETRANSMIT_IN => tx1_request_retransmit_in, + REQUEST_POSITION_IN => tx1_request_position_in, + + START_RETRANSMIT_IN => tx1_start_retransmit_in, + START_POSITION_IN => tx1_start_position_in, + + SEND_LINK_RESET_IN => tx1_send_link_reset_in, + TX_ALLOW_IN => tx1_allow_in, + + DEBUG_OUT => open + ); + + uut_tx2 : trb_net16_tx_control + port map( + TXCLK_IN => clk252, + RXCLK_IN => clk251, + SYSCLK_IN => clk, + RESET_IN => reset, + + TX_DATA_IN => tx2_data_in, + TX_WRITE_IN => tx2_write_in, + TX_READ_OUT => tx2_read_out, + + TX_DATA_OUT => tx2_data_out, + TX_K_OUT => tx2_k_out, + + REQUEST_RETRANSMIT_IN => tx2_request_retransmit_in, + REQUEST_POSITION_IN => tx2_request_position_in, + + START_RETRANSMIT_IN => tx2_start_retransmit_in, + START_POSITION_IN => tx2_start_position_in, + + SEND_LINK_RESET_IN => tx2_send_link_reset_in, + TX_ALLOW_IN => tx2_allow_in, + + DEBUG_OUT => open + ); + + uut_rx1 : trb_net16_rx_control + port map( + RESET_IN => reset, + QUAD_RST_IN => reset, + -- raw data from SerDes receive path + CLK_IN => clk252, + RX_DATA_IN => rx1_data_in, + RX_K_IN => rx1_k_in, + RX_CV_IN => rx1_cv_in, + RX_ALLOW_IN => rx1_allow_in, + -- media interface + SYSCLK_IN => clk, + MED_DATA_OUT => open, + MED_DATAREADY_OUT => open, + MED_READ_IN => '1', + MED_PACKET_NUM_OUT => open, + -- request retransmission in case of error while receiving + REQUEST_RETRANSMIT_OUT => tx1_request_retransmit_in, + REQUEST_POSITION_OUT => tx1_request_position_in, + -- command decoding + START_RETRANSMIT_OUT => tx1_start_retransmit_in, + START_POSITION_OUT => tx1_start_position_in, + -- reset handling + SEND_RESET_WORDS_OUT => open, + MAKE_TRBNET_RESET_OUT => open, + -- Status signals + PACKET_TIMEOUT_OUT => open, + -- Debugging + DEBUG_OUT => open + ); + + uut_rx2 : trb_net16_rx_control + port map( + RESET_IN => reset, + QUAD_RST_IN => reset, + -- raw data from SerDes receive path + CLK_IN => clk251, + RX_DATA_IN => rx2_data_in, + RX_K_IN => rx2_k_in, + RX_CV_IN => rx2_cv_in, + RX_ALLOW_IN => rx2_allow_in, + -- media interface + SYSCLK_IN => clk, + MED_DATA_OUT => open, + MED_DATAREADY_OUT => open, + MED_READ_IN => '1', + MED_PACKET_NUM_OUT => open, + -- request retransmission in case of error while receiving + REQUEST_RETRANSMIT_OUT => tx2_request_retransmit_in, + REQUEST_POSITION_OUT => tx2_request_position_in, + -- command decoding + START_RETRANSMIT_OUT => tx2_start_retransmit_in, + START_POSITION_OUT => tx2_start_position_in, + -- reset handling + SEND_RESET_WORDS_OUT => open, + MAKE_TRBNET_RESET_OUT => open, + -- Status signals + PACKET_TIMEOUT_OUT => open, + -- Debugging + DEBUG_OUT => open + ); + + +rx1_data_in <= transport tx2_data_out after 200 ns; +rx1_k_in <= transport tx2_k_out after 200 ns; +rx1_cv_in <= '0'; + +rx2_data_in <= transport tx1_data_out after 200 ns; +rx2_k_in <= transport tx1_k_out after 200 ns; +rx2_cv_in <= '0', '1' after 4400 ns, '0' after 4440 ns; + + +--Data 1 input + process + begin + tx1_data_in <= (others => '0'); + tx1_write_in <= '0'; + wait for 2300 ns; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"1001"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"2002"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_write_in <= '0'; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"3003"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"4004"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_write_in <= '0'; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"5005"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"6006"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"7007"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"8008"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"9009"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"a00a"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_write_in <= '0'; + wait for 1500 ns; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"b00b"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"c00c"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"d00d"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"e00e"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= x"f00f"; + tx1_write_in <= '1'; + if tx1_read_out = '0' then wait until tx1_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx1_data_in <= (others => '0'); + tx1_write_in <= '0'; + wait; + end process; + + + process + begin + tx2_data_in <= (others => '0'); + tx2_write_in <= '0'; + wait for 2300 ns; + wait until rising_edge(clk); wait for 1 ns; + tx2_data_in <= x"1001"; + tx2_write_in <= '1'; + if tx2_read_out = '0' then wait until tx2_read_out = '1'; end if; + wait until rising_edge(clk); wait for 1 ns; + tx2_data_in <= (others => '0'); + tx2_write_in <= '0'; + wait; + end process; + +--control from LSM + process + begin + tx1_allow_in <= '0'; + tx2_allow_in <= '0'; + rx1_allow_in <= '0'; + rx2_allow_in <= '0'; + tx1_send_link_reset_in<= '0'; + wait for 200 ns; + wait until rising_edge(clk); wait for 1 ns; + rx1_allow_in <= '1'; + rx2_allow_in <= '1'; + wait for 2050 ns; + wait until rising_edge(clk); wait for 1 ns; + tx1_allow_in <= '1'; + tx2_allow_in <= '1'; + wait for 15 us; + tx1_send_link_reset_in <= '1'; + wait for 1 us; + tx1_send_link_reset_in <= '0'; + end process; + + + + +end architecture; + + + diff --git a/testbenches/tb_trb_net16_tx_control.vhd b/testbenches/tb_trb_net16_tx_control.vhd index 07c90be..a4574b5 100644 --- a/testbenches/tb_trb_net16_tx_control.vhd +++ b/testbenches/tb_trb_net16_tx_control.vhd @@ -200,7 +200,7 @@ begin begin start_retransmit_in <= '0'; start_position_in <= (others => '0'); - wait for 650 ns; + wait for 630 ns; wait until rising_edge(clk); wait for 1 ns; start_retransmit_in <= '1'; start_position_in <= std_logic_vector(to_unsigned(5,8)); diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index 8a390f9..8d8e7fc 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -785,7 +785,8 @@ begin ------------------------------------------------- -- Common Status Register ------------------------------------------------- - proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, trigger_number_match, temperature, int_trigger_num) + proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, trigger_number_match, temperature, int_trigger_num, + link_error_i, link_and_reset_status, stat_lvl1_handler) begin buf_COMMON_STAT_REG_IN <= REGIO_COMMON_STAT_REG_IN; buf_COMMON_STAT_REG_IN(4) <= not trigger_number_match; @@ -796,7 +797,8 @@ begin end if; buf_COMMON_STAT_REG_IN(47 downto 32) <= int_trigger_num; buf_COMMON_STAT_REG_IN(127 downto 64) <= stat_lvl1_handler; - buf_COMMON_STAT_REG_IN(159 downto 128) <= link_and_reset_status; + buf_COMMON_STAT_REG_IN(131 downto 128) <= link_and_reset_status(3 downto 0); + buf_COMMON_STAT_REG_IN(136) <= link_error_i; end process; @@ -817,9 +819,6 @@ begin if make_trbnet_reset = '1' then link_and_reset_status(3 downto 0) <= link_and_reset_status(3 downto 0) + '1'; end if; - link_and_reset_status(7 downto 4) <= (others => '0'); - link_and_reset_status(8) <= link_error_i; - link_and_reset_status(31 downto 9) <= (others => '0'); end if; end process; diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd index 27193f0..482152b 100644 --- a/trb_net16_endpoint_hades_full_handler.vhd +++ b/trb_net16_endpoint_hades_full_handler.vhd @@ -569,6 +569,7 @@ begin common_stat_reg_i(9) <= debug_ipu_handler_i(12) or REGIO_COMMON_STAT_REG_IN(9); common_stat_reg_i(10) <= debug_ipu_handler_i(13) or REGIO_COMMON_STAT_REG_IN(10); common_stat_reg_i(11) <= debug_ipu_handler_i(14) or REGIO_COMMON_STAT_REG_IN(11); + common_stat_reg_i(159 downto 64) <= REGIO_COMMON_STAT_REG_IN(159 downto 64); end process; process(CLK) diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 470de94..c7d92e1 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -1421,6 +1421,9 @@ end component; component trb_net16_lsm_sfp is + generic( + CHECK_FOR_CV : integer := c_YES + ); port( SYSCLK : in std_logic; -- fabric clock RESET : in std_logic; -- synchronous reset @@ -1526,6 +1529,7 @@ end component; -- Status and control port STAT_OP : out std_logic_vector (15 downto 0); CTRL_OP : in std_logic_vector (15 downto 0); + STAT_REG_OUT : out std_logic_vector(127 downto 0); STAT_DEBUG : out std_logic_vector (63 downto 0); CTRL_DEBUG : in std_logic_vector (15 downto 0) ); @@ -1566,6 +1570,7 @@ end component; -- Status and control port STAT_OP : out std_logic_vector (63 downto 0); CTRL_OP : in std_logic_vector (63 downto 0); + STAT_REG_OUT : out std_logic_vector(127 downto 0); STAT_DEBUG : out std_logic_vector (255 downto 0); CTRL_DEBUG : in std_logic_vector (63 downto 0) ); @@ -2312,6 +2317,40 @@ end component; + component trb_net16_rx_control is + port( + RESET_IN : in std_logic; + QUAD_RST_IN : in std_logic; + -- raw data from SerDes receive path + CLK_IN : in std_logic; + RX_DATA_IN : in std_logic_vector(7 downto 0); + RX_K_IN : in std_logic; + RX_CV_IN : in std_logic; + RX_DISP_ERR_IN : in std_logic; + RX_ALLOW_IN : in std_logic; + -- media interface + SYSCLK_IN : in std_logic; -- 100MHz master clock + MED_DATA_OUT : out std_logic_vector(15 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + MED_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + -- request retransmission in case of error while receiving + REQUEST_RETRANSMIT_OUT : out std_logic; -- one pulse + REQUEST_POSITION_OUT : out std_logic_vector( 7 downto 0); + -- command decoding + START_RETRANSMIT_OUT : out std_logic; + START_POSITION_OUT : out std_logic_vector( 7 downto 0); + -- reset handling + SEND_RESET_WORDS_OUT : out std_logic; + MAKE_TRBNET_RESET_OUT : out std_logic; + -- Status signals + PACKET_TIMEOUT_OUT : out std_logic; + -- Debugging + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + end component; + + component trb_net16_sbuf is @@ -2771,6 +2810,33 @@ end component; + component trb_net16_tx_control is + port( + TXCLK_IN : in std_logic; + RXCLK_IN : in std_logic; + SYSCLK_IN : in std_logic; + RESET_IN : in std_logic; + + TX_DATA_IN : in std_logic_vector(15 downto 0); + TX_WRITE_IN : in std_logic; + TX_READ_OUT : out std_logic; + + TX_DATA_OUT : out std_logic_vector( 7 downto 0); + TX_K_OUT : out std_logic; + + REQUEST_RETRANSMIT_IN : in std_logic; + REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0); + + START_RETRANSMIT_IN : in std_logic; + START_POSITION_IN : in std_logic_vector( 7 downto 0); + + SEND_LINK_RESET_IN : in std_logic; + TX_ALLOW_IN : in std_logic; + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + end component; +