From: Jan Michel Date: Thu, 7 Sep 2017 13:15:44 +0000 (+0200) Subject: Add option to compile TDC with different pinout files. Not tested yet X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ad38ad866c10a4d82c78d7220a4b22b866ce3141;p=trb3sc.git Add option to compile TDC with different pinout files. Not tested yet --- diff --git a/pinout/trb3sc_32pin.lpf b/pinout/trb3sc_32pin.lpf index 0ac41ab..5095e2a 100644 --- a/pinout/trb3sc_32pin.lpf +++ b/pinout/trb3sc_32pin.lpf @@ -96,11 +96,11 @@ LOCATE COMP "INP_29" SITE "F3"; #was "DQUL2_1_P" 54 LOCATE COMP "INP_30" SITE "G2"; #was "DQUL2_2_P" 58 LOCATE COMP "INP_31" SITE "G3"; #was "DQSUL2_T" 62 -LOCATE COMP "DAC_IN_SDI" SITE "N9"; #was "DQSUL0_T" 86 -LOCATE COMP "DAC_OUT_SCK" SITE "K6"; #was "DQUL0_2_P" 82 -LOCATE COMP "DAC_OUT_CS" SITE "M7"; #was "DQUL0_4_P" 94 -LOCATE COMP "DAC_OUT_SDO" SITE "M4"; #was "DQUL0_1_P" 78 -LOCATE COMP "RES" SITE "Y34"; #was "DQLR2_3_P" 186 +LOCATE COMP "DAC_IN_SDI_1" SITE "N9"; #was "DQSUL0_T" 86 +LOCATE COMP "DAC_OUT_SCK_1" SITE "K6"; #was "DQUL0_2_P" 82 +LOCATE COMP "DAC_OUT_CS_1" SITE "M7"; #was "DQUL0_4_P" 94 +LOCATE COMP "DAC_OUT_SDO_1" SITE "M4"; #was "DQUL0_1_P" 78 +LOCATE COMP "RES" SITE "Y34"; #was "DQLR2_3_P" 186 DEFINE PORT GROUP "INP_group" "INP*" ; IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; diff --git a/tdctemplate/config.vhd b/tdctemplate/config.vhd index 0cea7b6..560ccad 100644 --- a/tdctemplate/config.vhd +++ b/tdctemplate/config.vhd @@ -10,6 +10,11 @@ package config is --Begin of design configuration ------------------------------------------------------------------------------ + --pinout to be used - don't forget to change config_compile.pl as well + -- 0: 32 Pin AddOn + -- 1: 4conn AddOn + constant PINOUT : integer := 1; + --TDC settings constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module @@ -49,9 +54,9 @@ package config is --input monitor and trigger generation logic constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; constant INCLUDE_STATISTICS : integer := c_YES; - constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_INPUT_NUM : integer := 48; constant TRIG_GEN_OUTPUT_NUM : integer := 4; - constant MONITOR_INPUT_NUM : integer := 36; + constant MONITOR_INPUT_NUM : integer := 52; ------------------------------------------------------------------------------ --End of design configuration diff --git a/tdctemplate/config_compile_frankfurt.pl b/tdctemplate/config_compile_frankfurt.pl index dd75c0a..a37b756 100644 --- a/tdctemplate/config_compile_frankfurt.pl +++ b/tdctemplate/config_compile_frankfurt.pl @@ -6,7 +6,8 @@ synplify_path => '/d/jspc29/lattice/synplify/M-2017.03/', nodelist_file => 'nodes_frankfurt.txt', # synplify_command => "ssh -p 52238 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/tdctemplate/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/L-2016.09-1/bin/synplify_premier_dp -batch ../trb3sc_tdctemplate.prj\" #", #Include only necessary lpf files -pinout_file => 'trb3sc_32pin', #name of pin-out file, if not equal TOPNAME +#pinout_file => 'trb3sc_32pin', #name of pin-out file, if not equal TOPNAME +pinout_file => 'trb3sc_padiwa', #name of pin-out file, if not equal TOPNAME include_TDC => 1, include_GBE => 0, diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index 3bc30fb..10248d3 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -19,30 +19,24 @@ entity trb3sc_tdctemplate is CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE CLK_CORE_PCLK : in std_logic; --Main Oscillator CLK_EXT_PLL_LEFT : in std_logic; --External Clock - --CLK_SUPPL_PLL_LEFT : in std_logic; --not used - --CLK_SUPPL_PLL_RIGHT : in std_logic; --not used - --CLK_CORE_PLL_LEFT : in std_logic; --not used - --CLK_CORE_PLL_RIGHT : in std_logic; --not used - --CLK_EXT_PCLK : in std_logic; --not used - --CLK_EXT_PLL_RIGHT : in std_logic; --not used + TRIG_LEFT : in std_logic; --Trigger Input - --TRIG_PLL : in std_logic; --not used - --TRIG_RIGHT : in std_logic; --not used --Backplane, all lines - BACK_GPIO : inout std_logic_vector(15 downto 0); - BACK_LVDS : inout std_logic_vector(1 downto 0); - BACK_3V3 : inout std_logic_vector(3 downto 0); +-- BACK_GPIO : inout std_logic_vector(15 downto 0); +-- BACK_LVDS : inout std_logic_vector(1 downto 0); +-- BACK_3V3 : inout std_logic_vector(3 downto 0); --Backplane for slaves on trbv3scbp1 --- BACK_GPIO : inout std_logic_vector(3 downto 0); + BACK_GPIO : inout std_logic_vector(3 downto 0); --AddOn Connector - 32 Pin AddOn - INP : in std_logic_vector(31 downto 0); - DAC_IN_SDI : in std_logic; - DAC_OUT_SCK : out std_logic; - DAC_OUT_CS : out std_logic; - DAC_OUT_SDO : out std_logic; + INP : in std_logic_vector(63 downto 0); + DAC_OUT_SDO : out std_logic_vector(4 downto 1); + DAC_OUT_SCK : out std_logic_vector(4 downto 1); + DAC_OUT_CS : out std_logic_vector(4 downto 1); + DAC_IN_SDI : in std_logic_vector(4 downto 1); + RES : out std_logic; --KEL Connector @@ -124,6 +118,7 @@ architecture trb3sc_arch of trb3sc_tdctemplate is signal time_counter : unsigned(31 downto 0) := (others => '0'); signal led : std_logic_vector(1 downto 0); signal debug_clock_reset : std_logic_vector(31 downto 0); + signal inputs : std_logic_vector(51 downto 0); --Media Interface signal med2int : med2int_array_t(0 to 0); @@ -360,12 +355,8 @@ begin ADC_MISO => ADC_DOUT, ADC_CLK => ADC_CLK, --Trigger & Monitor --- MONITOR_INPUTS(39 downto 0) => KEL(40 downto 1), --- MONITOR_INPUTS(43 downto 40) => trig_gen_out_i, --- TRIG_GEN_INPUTS => KEL(40 downto 1), - MONITOR_INPUTS(31 downto 0) => INP(31 downto 0), - MONITOR_INPUTS(35 downto 32) => trig_gen_out_i, - TRIG_GEN_INPUTS => INP(31 downto 0), + MONITOR_INPUTS => inputs(51 downto 0), + TRIG_GEN_INPUTS => inputs(47 downto 0), TRIG_GEN_OUTPUTS => trig_gen_out_i, --SED SED_ERROR_OUT => sed_error_i, @@ -379,6 +370,8 @@ begin DEBUG_OUT => open ); + + --------------------------------------------------------------------------- -- Switches --------------------------------------------------------------------------- @@ -398,15 +391,34 @@ begin BACK_GPIO(1 downto 0) <= (others => 'Z'); BACK_GPIO(3 downto 2) <= trig_gen_out_i(3 downto 2); - BACK_GPIO(15 downto 4) <= (others => 'Z'); BACK_LVDS <= (others => '0'); BACK_3V3 <= (others => 'Z'); - spi_miso(0) <= DAC_IN_SDI; - DAC_OUT_SCK <= spi_clk(0); - DAC_OUT_CS <= spi_cs(0); - DAC_OUT_SDO <= spi_mosi(0); + +gen_32pin : if PINOUT = 0 generate + inputs(31 downto 0) <= INP(31 downto 0); + inputs(47 downto 32) <= (others => '0'); + inputs(51 downto 48) <= trig_gen_out_i; + + spi_miso(0) <= DAC_IN_SDI(1); + DAC_OUT_SCK(1) <= spi_clk(0); + DAC_OUT_CS(1) <= spi_cs(0); + DAC_OUT_SDO(1) <= spi_mosi(0); + +end generate; +gen_4conn : if PINOUT = 1 generate + inputs(47 downto 0) <= INP(47 downto 0); + inputs(51 downto 48) <= trig_gen_out_i; + + spi_miso(3 downto 0) <= DAC_IN_SDI(4 downto 1); + DAC_OUT_SCK(4 downto 1) <= spi_clk(3 downto 0); + DAC_OUT_CS(4 downto 1) <= spi_cs(3 downto 0); + DAC_OUT_SDO(4 downto 1) <= spi_mosi(3 downto 0); + +end generate; + + --------------------------------------------------------------------------- -- LCD Data to display @@ -478,30 +490,18 @@ TEST_LINE <= med_stat_debug(15 downto 0); -- For single edge measurements gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate - hit_in_i(32 downto 1) <= INP(31 downto 0); + hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= inputs(NUM_TDC_CHANNELS-2 downto 0); end generate; -- For ToT Measurements gen_double : if DOUBLE_EDGE_TYPE = 2 generate - Gen_Hit_In_Signals : for i in 0 to 31 generate - hit_in_i(i*2+1) <= INP(i); - hit_in_i(i*2+2) <= not INP(i); + Gen_Hit_In_Signals : for i in 0 to NUM_TDC_CHANNELS-2 generate + hit_in_i(i*2+1) <= inputs(i); + hit_in_i(i*2+2) <= not inputs(i); end generate Gen_Hit_In_Signals; end generate; --- -- For single edge measurements --- gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate --- hit_in_i(40 downto 1) <= KEL(40 downto 1); --- end generate; --- --- -- For ToT Measurements --- gen_double : if DOUBLE_EDGE_TYPE = 2 generate --- Gen_Hit_In_Signals : for i in 1 to 20 generate --- hit_in_i(i*2-1) <= KEL(i); --- hit_in_i(i*2) <= not KEL(i); --- end generate Gen_Hit_In_Signals; --- end generate; - + end architecture;