From: Michael Boehmer Date: Fri, 4 Feb 2022 12:38:46 +0000 (+0100) Subject: SCI constraints considered harmful X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ade73ee38e8118c61e9641657fc195df6cd651f1;p=trb3sc.git SCI constraints considered harmful --- diff --git a/cts/trb3sc_cts.lpf b/cts/trb3sc_cts.lpf index 925ada1..42904d3 100644 --- a/cts/trb3sc_cts.lpf +++ b/cts/trb3sc_cts.lpf @@ -7,11 +7,10 @@ REGION "MEDIA_LEFT" "R102C17D" 13 75; # LEFT is for PCSD/PCSB REGION "MEDIA_RIGHT" "R102C92D" 13 75; # RIGHT is for PCSA/PCSC LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_LEFT"; -#LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/gen_control.3.gen_phaser.THE_PHASER/THE_PHASER_CORE/phaser_core_group" SITE "R113C61D"; # 181039 -#LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/gen_control.3.gen_phaser.THE_PHASER/THE_PHASER_CORE/phaser_core_group" SITE "R114C90D"; # 184235 -#LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/gen_control.3.gen_phaser.THE_PHASER/THE_PHASER_CORE/phaser_core_group" SITE "R107C74D"; # 191203 #LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/gen_control.3.gen_phaser.THE_PHASER/THE_PHASER_CORE/phaser_core_group" SITE "R111C77D"; # +LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/gen_control.3.gen_phaser.THE_PHASER/THE_PHASER_CORE/phaser_core_group" SITE "R111C77D"; # + BLOCK PATH FROM CELL THE_TDC/calibration_o*; BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*; BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/TheTriggerHandler/trg_in_r[0]; @@ -19,37 +18,37 @@ BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/TheTriggerHandle FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; FREQUENCY NET "GBE/clk_125_rx_from_pcs[3]" 125 MHz; -MULTICYCLE TO CELL "gen_PCSB.THE_MEDIA_PCSB/sci*" 20 ns; -MULTICYCLE FROM CELL "gen_PCSB.THE_MEDIA_PCSB/sci*" 20 ns; -MULTICYCLE TO CELL "gen_PCSB.THE_MEDIA_PCSB/PROC_SCI_CTRL.wa*" 20 ns; -BLOCK PATH TO CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_write_i"; -BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_write_i"; -BLOCK PATH TO CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i"; -BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i"; - -MULTICYCLE TO CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci*" 20 ns; -MULTICYCLE FROM CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci*" 20 ns; -MULTICYCLE TO CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/PROC_SCI_CTRL.wa*" 20 ns; -BLOCK PATH TO CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_write_i"; -BLOCK PATH FROM CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_write_i"; -BLOCK PATH TO CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_read_i"; -BLOCK PATH FROM CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_read_i"; - -MULTICYCLE TO CELL "gen_PCSC.THE_MEDIA_PCSC/sci*" 20 ns; -MULTICYCLE FROM CELL "gen_PCSC.THE_MEDIA_PCSC/sci*" 20 ns; -MULTICYCLE TO CELL "gen_PCSC.THE_MEDIA_PCSC/PROC_SCI_CTRL.wa*" 20 ns; -BLOCK PATH TO CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_write_i"; -BLOCK PATH FROM CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_write_i"; -BLOCK PATH TO CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_read_i"; -BLOCK PATH FROM CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_read_i"; - -MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; -MAXDELAY TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; - -MULTICYCLE TO ASIC gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; -MAXDELAY TO ASIC gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; - -MULTICYCLE TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; -MAXDELAY TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +#MULTICYCLE TO CELL "gen_PCSB.THE_MEDIA_PCSB/sci*" 20 ns; +#MULTICYCLE FROM CELL "gen_PCSB.THE_MEDIA_PCSB/sci*" 20 ns; +#MULTICYCLE TO CELL "gen_PCSB.THE_MEDIA_PCSB/PROC_SCI_CTRL.wa*" 20 ns; +#BLOCK PATH TO CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_write_i"; +#BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_write_i"; +#BLOCK PATH TO CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i"; +#BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i"; + +#MULTICYCLE TO CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci*" 20 ns; +#MULTICYCLE FROM CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci*" 20 ns; +#MULTICYCLE TO CELL "gen_PCSB_ADDON.THE_MEDIA_PCSB/PROC_SCI_CTRL.wa*" 20 ns; +#BLOCK PATH TO CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_write_i"; +#BLOCK PATH FROM CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_write_i"; +#BLOCK PATH TO CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_read_i"; +#BLOCK PATH FROM CLKNET "gen_PCSB_ADDON.THE_MEDIA_PCSB/sci_read_i"; + +#MULTICYCLE TO CELL "gen_PCSC.THE_MEDIA_PCSC/sci*" 20 ns; +#MULTICYCLE FROM CELL "gen_PCSC.THE_MEDIA_PCSC/sci*" 20 ns; +#MULTICYCLE TO CELL "gen_PCSC.THE_MEDIA_PCSC/PROC_SCI_CTRL.wa*" 20 ns; +#BLOCK PATH TO CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_write_i"; +#BLOCK PATH FROM CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_write_i"; +#BLOCK PATH TO CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_read_i"; +#BLOCK PATH FROM CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_read_i"; + +#MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +#MAXDELAY TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; + +#MULTICYCLE TO ASIC gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +#MAXDELAY TO ASIC gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; + +#MULTICYCLE TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +#MAXDELAY TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; PROHIBIT SECONDARY NET "THE_TOOLS/gen_STATISTICS.THE_STAT_LOGIC/reset_cnt" ; diff --git a/pinout/basic_constraints.lpf b/pinout/basic_constraints.lpf index 97dd583..84cdd83 100644 --- a/pinout/basic_constraints.lpf +++ b/pinout/basic_constraints.lpf @@ -37,14 +37,14 @@ BLOCK PATH FROM CELL "THE_TOOLS/gen_TRIG_LOGIC.THE_TRIG_LOGIC/inp_verylong*"; BLOCK PATH TO CELL "THE_TOOLS/gen_TRIG_LOGIC.THE_TRIG_LOGIC/out_reg*"; -BLOCK PATH FROM CLKNET "*/sci_read_i"; -BLOCK PATH FROM CLKNET "*/sci_write_i"; +#BLOCK PATH FROM CLKNET "*/sci_read_i"; +#BLOCK PATH FROM CLKNET "*/sci_write_i"; -MULTICYCLE TO CELL "*/sci*" 20 ns; -MULTICYCLE FROM CELL "*/sci*" 20 ns; -MULTICYCLE TO CELL "*/PROC_SCI_CTRL.wa*" 20 ns; -BLOCK PATH TO CELL "*/sci_addr_*"; +#MULTICYCLE TO CELL "*/sci*" 20 ns; +#MULTICYCLE FROM CELL "*/sci*" 20 ns; +#MULTICYCLE TO CELL "*/PROC_SCI_CTRL.wa*" 20 ns; +#BLOCK PATH TO CELL "*/sci_addr_*"; FREQUENCY NET "THE_MEDIA_INT*/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps FREQUENCY NET "THE_MEDIA_INT*/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps