From: Florian Marx <fmarx@jspc71.x-matter.uni-frankfurt.de>
Date: Tue, 7 Aug 2018 09:19:47 +0000 (+0200)
Subject: added triggerlogic to triggerlogic proj
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ae8ef4c1cedd2ece5280099106839b878cc4fe60;p=trb3sc.git

added triggerlogic to triggerlogic proj
---

diff --git a/pinout/trb3sc_basic.lpf b/pinout/trb3sc_basic.lpf
index aae022c..b10da16 100644
--- a/pinout/trb3sc_basic.lpf
+++ b/pinout/trb3sc_basic.lpf
@@ -415,6 +415,7 @@ LOCATE COMP "KEL_40"                        SITE "L28";
 DEFINE PORT GROUP "KEL_group" "KEL*" ;
 IOBUF GROUP  "KEL_group" IO_TYPE=LVDS25  DIFFRESISTOR=100;
 
+
 #################################################################
 # Many LED
 #################################################################
diff --git a/triggerlogic/config.vhd b/triggerlogic/config.vhd
index 698d9c0..08c6226 100644
--- a/triggerlogic/config.vhd
+++ b/triggerlogic/config.vhd
@@ -24,7 +24,7 @@ package config is
     constant USE_RXCLOCK            : integer := c_NO;
    
 --Address settings   
-    constant INIT_ADDRESS           : std_logic_vector := x"F3CC";
+    constant INIT_ADDRESS           : std_logic_vector := x"F369";
     constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"69";
    
 --set to 0 for backplane serdes, set to 3 for front SFP serdes
diff --git a/triggerlogic/trb3sc_trigger.prj b/triggerlogic/trb3sc_trigger.prj
index a8bd345..c9d457c 100644
--- a/triggerlogic/trb3sc_trigger.prj
+++ b/triggerlogic/trb3sc_trigger.prj
@@ -112,8 +112,8 @@ add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
-add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
-add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/code/uart_rec.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/code/uart_trans.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
@@ -139,6 +139,18 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.v
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
 
+#Triggerogic_flo
+#alle files einzeln adden 
+add_file -vhdl -lib work "../../triggerlogic/trigger_logic.vhd"
+add_file -vhdl -lib work "../../triggerlogic/trigger_enable.vhd"
+add_file -vhdl -lib work "../../triggerlogic/trigger_inverter.vhd"
+add_file -vhdl -lib work "../../triggerlogic/trigger_edgedetect.vhd"
+add_file -vhdl -lib work "../../triggerlogic/trigger_delay.vhd"
+add_file -vhdl -lib work "../../triggerlogic/trigger_stretch.vhd"
+add_file -vhdl -lib work "../../triggerlogic/trigger_coin.vhd"
+add_file -vhdl -lib work "../../triggerlogic/trigger_merge.vhd"
+add_file -vhdl -lib work "../../triggerlogic/cores/delay_shift_reg.vhd"
+
 #TrbNet Endpoint
 add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
diff --git a/triggerlogic/trb3sc_trigger.vhd b/triggerlogic/trb3sc_trigger.vhd
index f53720d..9df6a2f 100644
--- a/triggerlogic/trb3sc_trigger.vhd
+++ b/triggerlogic/trb3sc_trigger.vhd
@@ -346,7 +346,7 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
       SPI_MISO_IN => spi_miso,
       SPI_CLK_OUT => spi_clk,
       --Header
-      HEADER_IO   => HDR_IO,
+      HEADER_IO   => open,
       --LCD
       LCD_DATA_IN => lcd_data,
       --ADC
@@ -416,10 +416,24 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
     end if;
   end process;  
 
+---------------------------------------------------------------------------
+-- triggerlocig 
+---------------------------------------------------------------------------
+  THE_LOGIC : entity work.trigger_logic 
+  generic map(
+    INPUTS => 24,
+    OUTPUTS => 8
+    )
+  port map(
+    CLK           => clk_sys,
+    RESET         => reset_i,
+    BUS_RX        => bustrglogic_rx,
+    BUS_TX        => bustrglogic_tx,
+    INPUT         => KEL(24 downto 1),
+    OUTPUT        => HDR_IO(8 downto 1)
+    );
 
   
-  
-  
 
   
 end architecture;