From: Cahit Date: Fri, 20 Mar 2015 15:24:27 +0000 (+0100) Subject: IP cores for ecp5 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=aef5ea51c93a8d49ca0ce71769f023422a8a2067;p=trbnet.git IP cores for ecp5 --- diff --git a/lattice/ecp5/FIFO/FIFO.sbx b/lattice/ecp5/FIFO/FIFO.sbx index beca0a3..54df0df 100644 --- a/lattice/ecp5/FIFO/FIFO.sbx +++ b/lattice/ecp5/FIFO/FIFO.sbx @@ -20,1991 +20,12183 @@ - FIFO_36x128_OutReg_Clock - FIFO_36x128_OutReg_Clock + fifo_18x1k_oreg_AlmostFull + fifo_18x1k_oreg_AlmostFull + + out + + + + fifo_18x1k_oreg.AlmostFull + + + + + fifo_18x1k_oreg_Clock + fifo_18x1k_oreg_Clock in - FIFO_36x128_OutReg.Clock + fifo_18x1k_oreg.Clock - FIFO_36x128_OutReg_Empty - FIFO_36x128_OutReg_Empty + fifo_18x1k_oreg_Empty + fifo_18x1k_oreg_Empty out - FIFO_36x128_OutReg.Empty + fifo_18x1k_oreg.Empty - FIFO_36x128_OutReg_Full - FIFO_36x128_OutReg_Full + fifo_18x1k_oreg_Full + fifo_18x1k_oreg_Full out - FIFO_36x128_OutReg.Full + fifo_18x1k_oreg.Full - FIFO_36x128_OutReg_RdEn - FIFO_36x128_OutReg_RdEn + fifo_18x1k_oreg_RdEn + fifo_18x1k_oreg_RdEn in - FIFO_36x128_OutReg.RdEn + fifo_18x1k_oreg.RdEn - FIFO_36x128_OutReg_Reset - FIFO_36x128_OutReg_Reset + fifo_18x1k_oreg_Reset + fifo_18x1k_oreg_Reset in - FIFO_36x128_OutReg.Reset + fifo_18x1k_oreg.Reset - FIFO_36x128_OutReg_WrEn - FIFO_36x128_OutReg_WrEn + fifo_18x1k_oreg_WrEn + fifo_18x1k_oreg_WrEn in - FIFO_36x128_OutReg.WrEn + fifo_18x1k_oreg.WrEn - FIFO_DC_36x128_DynThr_OutReg_AlmostFull - FIFO_DC_36x128_DynThr_OutReg_AlmostFull + fifo_18x256_oreg_AlmostFull + fifo_18x256_oreg_AlmostFull out - FIFO_DC_36x128_DynThr_OutReg.AlmostFull + fifo_18x256_oreg.AlmostFull + + + + + fifo_18x256_oreg_Clock + fifo_18x256_oreg_Clock + + in + + + + fifo_18x256_oreg.Clock - FIFO_DC_36x128_DynThr_OutReg_Empty - FIFO_DC_36x128_DynThr_OutReg_Empty + fifo_18x256_oreg_Empty + fifo_18x256_oreg_Empty out - FIFO_DC_36x128_DynThr_OutReg.Empty + fifo_18x256_oreg.Empty - FIFO_DC_36x128_DynThr_OutReg_Full - FIFO_DC_36x128_DynThr_OutReg_Full + fifo_18x256_oreg_Full + fifo_18x256_oreg_Full out - FIFO_DC_36x128_DynThr_OutReg.Full + fifo_18x256_oreg.Full - FIFO_DC_36x128_DynThr_OutReg_RPReset - FIFO_DC_36x128_DynThr_OutReg_RPReset + fifo_18x256_oreg_RdEn + fifo_18x256_oreg_RdEn in - FIFO_DC_36x128_DynThr_OutReg.RPReset + fifo_18x256_oreg.RdEn - FIFO_DC_36x128_DynThr_OutReg_RdClock - FIFO_DC_36x128_DynThr_OutReg_RdClock + fifo_18x256_oreg_Reset + fifo_18x256_oreg_Reset in - FIFO_DC_36x128_DynThr_OutReg.RdClock + fifo_18x256_oreg.Reset - FIFO_DC_36x128_DynThr_OutReg_RdEn - FIFO_DC_36x128_DynThr_OutReg_RdEn + fifo_18x256_oreg_WrEn + fifo_18x256_oreg_WrEn in - FIFO_DC_36x128_DynThr_OutReg.RdEn + fifo_18x256_oreg.WrEn + + + + + fifo_18x512_oreg_AlmostFull + fifo_18x512_oreg_AlmostFull + + out + + + + fifo_18x512_oreg.AlmostFull - FIFO_DC_36x128_DynThr_OutReg_Reset - FIFO_DC_36x128_DynThr_OutReg_Reset + fifo_18x512_oreg_Clock + fifo_18x512_oreg_Clock in - FIFO_DC_36x128_DynThr_OutReg.Reset + fifo_18x512_oreg.Clock + + + + + fifo_18x512_oreg_Empty + fifo_18x512_oreg_Empty + + out + + + + fifo_18x512_oreg.Empty + + + + + fifo_18x512_oreg_Full + fifo_18x512_oreg_Full + + out + + + + fifo_18x512_oreg.Full - FIFO_DC_36x128_DynThr_OutReg_WrClock - FIFO_DC_36x128_DynThr_OutReg_WrClock + fifo_18x512_oreg_RdEn + fifo_18x512_oreg_RdEn in - FIFO_DC_36x128_DynThr_OutReg.WrClock + fifo_18x512_oreg.RdEn - FIFO_DC_36x128_DynThr_OutReg_WrEn - FIFO_DC_36x128_DynThr_OutReg_WrEn + fifo_18x512_oreg_Reset + fifo_18x512_oreg_Reset in - FIFO_DC_36x128_DynThr_OutReg.WrEn + fifo_18x512_oreg.Reset - FIFO_36x128_OutReg_Data - FIFO_36x128_OutReg_Data + fifo_18x512_oreg_WrEn + fifo_18x512_oreg_WrEn in - - 35 - 0 - - FIFO_36x128_OutReg.Data + fifo_18x512_oreg.WrEn - FIFO_36x128_OutReg_Q - FIFO_36x128_OutReg_Q + fifo_19x16_obuf_AlmostFull + fifo_19x16_obuf_AlmostFull out - - 35 - 0 - - FIFO_36x128_OutReg.Q + fifo_19x16_obuf.AlmostFull - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh + fifo_19x16_obuf_Clock + fifo_19x16_obuf_Clock in - - 6 - 0 - - FIFO_DC_36x128_DynThr_OutReg.AmFullThresh + fifo_19x16_obuf.Clock + + + + + fifo_19x16_obuf_Empty + fifo_19x16_obuf_Empty + + out + + + + fifo_19x16_obuf.Empty + + + + + fifo_19x16_obuf_Full + fifo_19x16_obuf_Full + + out + + + + fifo_19x16_obuf.Full - FIFO_DC_36x128_DynThr_OutReg_Data - FIFO_DC_36x128_DynThr_OutReg_Data + fifo_19x16_obuf_RdEn + fifo_19x16_obuf_RdEn + + in + + + + fifo_19x16_obuf.RdEn + + + + + fifo_19x16_obuf_Reset + fifo_19x16_obuf_Reset + + in + + + + fifo_19x16_obuf.Reset + + + + + fifo_19x16_obuf_WrEn + fifo_19x16_obuf_WrEn in - - 35 - 0 - - FIFO_DC_36x128_DynThr_OutReg.Data + fifo_19x16_obuf.WrEn - FIFO_DC_36x128_DynThr_OutReg_Q - FIFO_DC_36x128_DynThr_OutReg_Q + fifo_36x16k_oreg_AlmostFull + fifo_36x16k_oreg_AlmostFull out - - 35 - 0 - - FIFO_DC_36x128_DynThr_OutReg.Q + fifo_36x16k_oreg.AlmostFull - - - - LFE5UM-85F-8MG285C - synplify - 2015-03-17.15:26:04 - 2015-03-17.15:29:04 - 3.4.0.80 - VHDL - - true - false - false - true - false - false - false - false - false - false - false - - - - - - - - LATTICE - LOCAL - FIFO - 1.0 - - - FIFO_36x128_OutReg - - Lattice Semiconductor Corporation - LEGACY - FIFO - 5.0 - - - Diamond_Simulation - simulation - - ./FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd - vhdlSource - - - - Diamond_Synthesis - synthesis - - ./FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd - vhdlSource - - - - - - Configuration - none - ${sbp_path}/${instance}/generate_core.tcl - CONFIG - - - CreateNGD - none - ${sbp_path}/${instance}/generate_ngd.tcl - CONFIG - - - - - - - Clock - Clock - - in - - - - Empty - Empty - - out - - - - Full - Full - - out - - - - RdEn - RdEn - - in - - - - Reset - Reset - - in - - - - WrEn - WrEn - - in - - - - Data - Data - - in - - 35 - 0 - - - - - Q - Q - - out - - 35 - 0 - - - - - + + fifo_36x16k_oreg_Clock + fifo_36x16k_oreg_Clock + + in + - synplify - 2015-03-17.15:29:04 - false - false - false - false - false - false - false - false - false - false - LPM - PRIMARY - PRIMARY - false - false + fifo_36x16k_oreg.Clock - - - - - Family - ecp5um - - - OperatingCondition - COM - - - Package - CSFBGA285 - - - PartName - LFE5UM-85F-8MG285C - - - PartType - LFE5UM-85F - - - SpeedGrade - 8 - - - Status - C - - - - CoreName - FIFO - - - CoreRevision - 5.0 - - - CoreStatus - Demo - - - CoreType - LPM - - - Date - 03/17/2015 - - - ModuleName - FIFO_36x128_OutReg - - - ParameterFileVersion - 1.0 - - - SourceFormat - vhdl - - - Time - 15:27:43 - - - VendorName - Lattice Semiconductor Corporation - - - - CtrlByRdEn - 0 - - - Depth - 128 - - - Destination - Synplicity - - - EDIF - 1 - - - EmpFlg - 0 - - - EnECC - 0 - - - EnFWFT - 0 - - - Expression - BusA(0 to 7) - - - FIFOImp - EBR Based - - - FullFlg - 0 - - - IO - 0 - - - Order - Big Endian [MSB:LSB] - - - PeAssert - 10 - - - PeDeassert - 12 - - - PeMode - Static - Dual Threshold - - - PfAssert - 508 - - - PfDeassert - 506 - - - PfMode - Static - Dual Threshold - - - RDataCount - 0 - - - Reset - Sync - - - Reset1 - Sync - - - VHDL - 1 - - - Verilog - 0 - - - Width - 36 - - - regout - 1 - - - - cmd_line - -w -n FIFO_36x128_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 128 -width 36 -regout -no_enable -pe -1 -pf -1 -sync_reset - - - - - - - FIFO_DC_36x128_DynThr_OutReg - - Lattice Semiconductor Corporation - LEGACY - FIFO_DC - 5.7 - - - Diamond_Simulation - simulation - - ./FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd - vhdlSource - - - - Diamond_Synthesis - synthesis - - ./FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd - vhdlSource - - - - - - Configuration - none - ${sbp_path}/${instance}/generate_core.tcl - CONFIG - - - CreateNGD - none - ${sbp_path}/${instance}/generate_ngd.tcl - CONFIG - - - - - - - AlmostFull - AlmostFull - - out - - - - Empty - Empty - - out - - - - Full - Full - - out - - - - RPReset - RPReset - - in - - - - RdClock - RdClock - - in - - - - RdEn - RdEn - - in - - - - Reset - Reset - - in - - - - WrClock - WrClock - - in - - - - WrEn - WrEn - - in - - - - AmFullThresh - AmFullThresh - - in - - 6 - 0 - - - - - Data - Data - - in - - 35 - 0 - - - - - Q - Q - - out - - 35 - 0 - - - - - + + + fifo_36x16k_oreg_Empty + fifo_36x16k_oreg_Empty + + out + - synplify - 2015-03-17.15:29:04 - false - false - false - false - false - false - false - false - false - false - LPM - PRIMARY - PRIMARY - false - false + fifo_36x16k_oreg.Empty - - - - - Family - ecp5um - - - OperatingCondition - COM - - - Package - CSFBGA285 - - - PartName - LFE5UM-85F-8MG285C - - - PartType - LFE5UM-85F - - - SpeedGrade - 8 - - - Status - C - - - - CoreName - FIFO_DC - - - CoreRevision - 5.7 - - - CoreStatus - Demo - - - CoreType - LPM - - - Date - 03/17/2015 - - - ModuleName - FIFO_DC_36x128_DynThr_OutReg - - - ParameterFileVersion - 1.0 - - - SourceFormat - vhdl - - - Time - 15:27:13 - - - VendorName - Lattice Semiconductor Corporation - - - - ClockEn - 0 - - - CtrlByRdEn - 0 - - - Depth - 128 - - - Destination - Synplicity - - - EDIF - 1 - - - EmpFlg - 0 - - - EnECC - 0 - - - Expression - BusA(0 to 7) - - - FIFOImp - EBR Based - - - FullFlg - 1 - - - IO - 0 - - - Order - Big Endian [MSB:LSB] - - - PeAssert - 10 - - - PeDeassert - 12 - - - PeMode - Static - Dual Threshold - - - PfAssert - 508 - - - PfDeassert - 506 - - - PfMode - Dynamic - Single Threshold - - - RDataCount - 0 - - - RDepth - 128 - - - RWidth - 36 - - - Reset - Sync - - - Reset1 - Sync - - - VHDL - 1 - - - Verilog - 0 - - - WDataCount - 0 - - - Width - 36 - - - regout - 1 - - - - cmd_line - -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 128 -width 36 -rwidth 36 -regout -no_enable -sync_reset -pe -1 -pf 0 - - - - - - - + + + fifo_36x16k_oreg_Full + fifo_36x16k_oreg_Full + + out + + + + fifo_36x16k_oreg.Full + + + + + fifo_36x16k_oreg_RdEn + fifo_36x16k_oreg_RdEn + + in + + + + fifo_36x16k_oreg.RdEn + + + + + fifo_36x16k_oreg_Reset + fifo_36x16k_oreg_Reset + + in + + + + fifo_36x16k_oreg.Reset + + + + + fifo_36x16k_oreg_WrEn + fifo_36x16k_oreg_WrEn + + in + + + + fifo_36x16k_oreg.WrEn + + + + + fifo_36x1k_oreg_AlmostFull + fifo_36x1k_oreg_AlmostFull + + out + + + + fifo_36x1k_oreg.AlmostFull + + + + + fifo_36x1k_oreg_Clock + fifo_36x1k_oreg_Clock + + in + + + + fifo_36x1k_oreg.Clock + + + + + fifo_36x1k_oreg_Empty + fifo_36x1k_oreg_Empty + + out + + + + fifo_36x1k_oreg.Empty + + + + + fifo_36x1k_oreg_Full + fifo_36x1k_oreg_Full + + out + + + + fifo_36x1k_oreg.Full + + + + + fifo_36x1k_oreg_RdEn + fifo_36x1k_oreg_RdEn + + in + + + + fifo_36x1k_oreg.RdEn + + + + + fifo_36x1k_oreg_Reset + fifo_36x1k_oreg_Reset + + in + + + + fifo_36x1k_oreg.Reset + + + + + fifo_36x1k_oreg_WrEn + fifo_36x1k_oreg_WrEn + + in + + + + fifo_36x1k_oreg.WrEn + + + + + fifo_36x2k_oreg_AlmostFull + fifo_36x2k_oreg_AlmostFull + + out + + + + fifo_36x2k_oreg.AlmostFull + + + + + fifo_36x2k_oreg_Clock + fifo_36x2k_oreg_Clock + + in + + + + fifo_36x2k_oreg.Clock + + + + + fifo_36x2k_oreg_Empty + fifo_36x2k_oreg_Empty + + out + + + + fifo_36x2k_oreg.Empty + + + + + fifo_36x2k_oreg_Full + fifo_36x2k_oreg_Full + + out + + + + fifo_36x2k_oreg.Full + + + + + fifo_36x2k_oreg_RdEn + fifo_36x2k_oreg_RdEn + + in + + + + fifo_36x2k_oreg.RdEn + + + + + fifo_36x2k_oreg_Reset + fifo_36x2k_oreg_Reset + + in + + + + fifo_36x2k_oreg.Reset + + + + + fifo_36x2k_oreg_WrEn + fifo_36x2k_oreg_WrEn + + in + + + + fifo_36x2k_oreg.WrEn + + + + + fifo_36x32k_oreg_AlmostFull + fifo_36x32k_oreg_AlmostFull + + out + + + + fifo_36x32k_oreg.AlmostFull + + + + + fifo_36x32k_oreg_Clock + fifo_36x32k_oreg_Clock + + in + + + + fifo_36x32k_oreg.Clock + + + + + fifo_36x32k_oreg_Empty + fifo_36x32k_oreg_Empty + + out + + + + fifo_36x32k_oreg.Empty + + + + + fifo_36x32k_oreg_Full + fifo_36x32k_oreg_Full + + out + + + + fifo_36x32k_oreg.Full + + + + + fifo_36x32k_oreg_RdEn + fifo_36x32k_oreg_RdEn + + in + + + + fifo_36x32k_oreg.RdEn + + + + + fifo_36x32k_oreg_Reset + fifo_36x32k_oreg_Reset + + in + + + + fifo_36x32k_oreg.Reset + + + + + fifo_36x32k_oreg_WrEn + fifo_36x32k_oreg_WrEn + + in + + + + fifo_36x32k_oreg.WrEn + + + + + fifo_36x4k_oreg_AlmostFull + fifo_36x4k_oreg_AlmostFull + + out + + + + fifo_36x4k_oreg.AlmostFull + + + + + fifo_36x4k_oreg_Clock + fifo_36x4k_oreg_Clock + + in + + + + fifo_36x4k_oreg.Clock + + + + + fifo_36x4k_oreg_Empty + fifo_36x4k_oreg_Empty + + out + + + + fifo_36x4k_oreg.Empty + + + + + fifo_36x4k_oreg_Full + fifo_36x4k_oreg_Full + + out + + + + fifo_36x4k_oreg.Full + + + + + fifo_36x4k_oreg_RdEn + fifo_36x4k_oreg_RdEn + + in + + + + fifo_36x4k_oreg.RdEn + + + + + fifo_36x4k_oreg_Reset + fifo_36x4k_oreg_Reset + + in + + + + fifo_36x4k_oreg.Reset + + + + + fifo_36x4k_oreg_WrEn + fifo_36x4k_oreg_WrEn + + in + + + + fifo_36x4k_oreg.WrEn + + + + + fifo_36x512_oreg_AlmostFull + fifo_36x512_oreg_AlmostFull + + out + + + + fifo_36x512_oreg.AlmostFull + + + + + fifo_36x512_oreg_Clock + fifo_36x512_oreg_Clock + + in + + + + fifo_36x512_oreg.Clock + + + + + fifo_36x512_oreg_Empty + fifo_36x512_oreg_Empty + + out + + + + fifo_36x512_oreg.Empty + + + + + fifo_36x512_oreg_Full + fifo_36x512_oreg_Full + + out + + + + fifo_36x512_oreg.Full + + + + + fifo_36x512_oreg_RdEn + fifo_36x512_oreg_RdEn + + in + + + + fifo_36x512_oreg.RdEn + + + + + fifo_36x512_oreg_Reset + fifo_36x512_oreg_Reset + + in + + + + fifo_36x512_oreg.Reset + + + + + fifo_36x512_oreg_WrEn + fifo_36x512_oreg_WrEn + + in + + + + fifo_36x512_oreg.WrEn + + + + + fifo_36x8k_oreg_AlmostFull + fifo_36x8k_oreg_AlmostFull + + out + + + + fifo_36x8k_oreg.AlmostFull + + + + + fifo_36x8k_oreg_Clock + fifo_36x8k_oreg_Clock + + in + + + + fifo_36x8k_oreg.Clock + + + + + fifo_36x8k_oreg_Empty + fifo_36x8k_oreg_Empty + + out + + + + fifo_36x8k_oreg.Empty + + + + + fifo_36x8k_oreg_Full + fifo_36x8k_oreg_Full + + out + + + + fifo_36x8k_oreg.Full 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fifo_36x4k_oreg_Data[9] + fifo_36x4k_oreg_Data[9] + + + + + fifo_36x4k_oreg_Q + fifo_36x4k_oreg_Q + + + + + fifo_36x4k_oreg_Q[0] + fifo_36x4k_oreg_Q[0] + + + + + fifo_36x4k_oreg_Q[10] + fifo_36x4k_oreg_Q[10] + + + + + fifo_36x4k_oreg_Q[11] + fifo_36x4k_oreg_Q[11] + + + + + fifo_36x4k_oreg_Q[12] + fifo_36x4k_oreg_Q[12] + + + + + fifo_36x4k_oreg_Q[13] + fifo_36x4k_oreg_Q[13] + + + + + fifo_36x4k_oreg_Q[14] + fifo_36x4k_oreg_Q[14] + + + + + fifo_36x4k_oreg_Q[15] + fifo_36x4k_oreg_Q[15] + + + + + fifo_36x4k_oreg_Q[16] + fifo_36x4k_oreg_Q[16] + + + + + fifo_36x4k_oreg_Q[17] + fifo_36x4k_oreg_Q[17] + + + + + fifo_36x4k_oreg_Q[18] + fifo_36x4k_oreg_Q[18] + + + + + fifo_36x4k_oreg_Q[19] + fifo_36x4k_oreg_Q[19] + + + + + fifo_36x4k_oreg_Q[1] + fifo_36x4k_oreg_Q[1] + + + + + fifo_36x4k_oreg_Q[20] + fifo_36x4k_oreg_Q[20] + + + + + fifo_36x4k_oreg_Q[21] + fifo_36x4k_oreg_Q[21] + + + + + fifo_36x4k_oreg_Q[22] + fifo_36x4k_oreg_Q[22] + + + + + fifo_36x4k_oreg_Q[23] + fifo_36x4k_oreg_Q[23] + + + + + fifo_36x4k_oreg_Q[24] + fifo_36x4k_oreg_Q[24] + + + + + fifo_36x4k_oreg_Q[25] + fifo_36x4k_oreg_Q[25] + + + + + fifo_36x4k_oreg_Q[26] + fifo_36x4k_oreg_Q[26] + + + + + fifo_36x4k_oreg_Q[27] + fifo_36x4k_oreg_Q[27] + + + + + fifo_36x4k_oreg_Q[28] + fifo_36x4k_oreg_Q[28] + + + + + fifo_36x4k_oreg_Q[29] + fifo_36x4k_oreg_Q[29] + + + + + fifo_36x4k_oreg_Q[2] + fifo_36x4k_oreg_Q[2] + + + + + fifo_36x4k_oreg_Q[30] + fifo_36x4k_oreg_Q[30] + + + + + fifo_36x4k_oreg_Q[31] + fifo_36x4k_oreg_Q[31] + + + + + fifo_36x4k_oreg_Q[32] + fifo_36x4k_oreg_Q[32] + + + + + fifo_36x4k_oreg_Q[33] + fifo_36x4k_oreg_Q[33] + + + + + fifo_36x4k_oreg_Q[34] + fifo_36x4k_oreg_Q[34] + + + + + fifo_36x4k_oreg_Q[35] + fifo_36x4k_oreg_Q[35] + + + + + fifo_36x4k_oreg_Q[3] + fifo_36x4k_oreg_Q[3] + + + + + fifo_36x4k_oreg_Q[4] + fifo_36x4k_oreg_Q[4] + + + + + fifo_36x4k_oreg_Q[5] + fifo_36x4k_oreg_Q[5] + + + + + fifo_36x4k_oreg_Q[6] + fifo_36x4k_oreg_Q[6] + + + + + fifo_36x4k_oreg_Q[7] + fifo_36x4k_oreg_Q[7] + + + + + fifo_36x4k_oreg_Q[8] + fifo_36x4k_oreg_Q[8] + + + + + fifo_36x4k_oreg_Q[9] + fifo_36x4k_oreg_Q[9] + + + + + fifo_36x4k_oreg_WCNT + fifo_36x4k_oreg_WCNT + + + + + fifo_36x4k_oreg_WCNT[0] + fifo_36x4k_oreg_WCNT[0] + + + + + fifo_36x4k_oreg_WCNT[10] + fifo_36x4k_oreg_WCNT[10] + + + + + fifo_36x4k_oreg_WCNT[11] + fifo_36x4k_oreg_WCNT[11] + + + + + fifo_36x4k_oreg_WCNT[12] + fifo_36x4k_oreg_WCNT[12] + + + + + fifo_36x4k_oreg_WCNT[1] + fifo_36x4k_oreg_WCNT[1] + + + + + fifo_36x4k_oreg_WCNT[2] + fifo_36x4k_oreg_WCNT[2] + + + + + fifo_36x4k_oreg_WCNT[3] + fifo_36x4k_oreg_WCNT[3] + + + + + fifo_36x4k_oreg_WCNT[4] + fifo_36x4k_oreg_WCNT[4] + + + + + fifo_36x4k_oreg_WCNT[5] + fifo_36x4k_oreg_WCNT[5] + + + + + fifo_36x4k_oreg_WCNT[6] + fifo_36x4k_oreg_WCNT[6] + + + + + fifo_36x4k_oreg_WCNT[7] + fifo_36x4k_oreg_WCNT[7] + + + + + fifo_36x4k_oreg_WCNT[8] + fifo_36x4k_oreg_WCNT[8] + + + + + fifo_36x4k_oreg_WCNT[9] + fifo_36x4k_oreg_WCNT[9] + + + + + fifo_36x512_oreg_AmFullThresh + fifo_36x512_oreg_AmFullThresh + + + + + fifo_36x512_oreg_AmFullThresh[0] + fifo_36x512_oreg_AmFullThresh[0] + + + + + fifo_36x512_oreg_AmFullThresh[1] + fifo_36x512_oreg_AmFullThresh[1] + + + + + fifo_36x512_oreg_AmFullThresh[2] + fifo_36x512_oreg_AmFullThresh[2] + + + + + fifo_36x512_oreg_AmFullThresh[3] + fifo_36x512_oreg_AmFullThresh[3] + + + + + fifo_36x512_oreg_AmFullThresh[4] + fifo_36x512_oreg_AmFullThresh[4] + + + + + fifo_36x512_oreg_AmFullThresh[5] + fifo_36x512_oreg_AmFullThresh[5] + + + + + fifo_36x512_oreg_AmFullThresh[6] + fifo_36x512_oreg_AmFullThresh[6] + + + + + fifo_36x512_oreg_AmFullThresh[7] + fifo_36x512_oreg_AmFullThresh[7] + + + + + fifo_36x512_oreg_AmFullThresh[8] + fifo_36x512_oreg_AmFullThresh[8] + + + + + fifo_36x512_oreg_Data + fifo_36x512_oreg_Data + + + + + fifo_36x512_oreg_Data[0] + fifo_36x512_oreg_Data[0] + + + + + fifo_36x512_oreg_Data[10] + fifo_36x512_oreg_Data[10] + + + + + fifo_36x512_oreg_Data[11] + fifo_36x512_oreg_Data[11] + + + + + fifo_36x512_oreg_Data[12] + fifo_36x512_oreg_Data[12] + + + + + fifo_36x512_oreg_Data[13] + fifo_36x512_oreg_Data[13] + + + + + fifo_36x512_oreg_Data[14] + fifo_36x512_oreg_Data[14] + + + + + fifo_36x512_oreg_Data[15] + fifo_36x512_oreg_Data[15] + + + + + fifo_36x512_oreg_Data[16] + fifo_36x512_oreg_Data[16] + + + + + fifo_36x512_oreg_Data[17] + fifo_36x512_oreg_Data[17] + + + + + fifo_36x512_oreg_Data[18] + fifo_36x512_oreg_Data[18] + + + + + fifo_36x512_oreg_Data[19] + fifo_36x512_oreg_Data[19] + + + + + fifo_36x512_oreg_Data[1] + fifo_36x512_oreg_Data[1] + + + + + fifo_36x512_oreg_Data[20] + fifo_36x512_oreg_Data[20] + + + + + fifo_36x512_oreg_Data[21] + fifo_36x512_oreg_Data[21] + + + + + fifo_36x512_oreg_Data[22] + fifo_36x512_oreg_Data[22] + + + + + fifo_36x512_oreg_Data[23] + fifo_36x512_oreg_Data[23] + + + + + fifo_36x512_oreg_Data[24] + fifo_36x512_oreg_Data[24] + + + + + fifo_36x512_oreg_Data[25] + fifo_36x512_oreg_Data[25] + + + + + fifo_36x512_oreg_Data[26] + fifo_36x512_oreg_Data[26] + + + + + fifo_36x512_oreg_Data[27] + fifo_36x512_oreg_Data[27] + + + + + fifo_36x512_oreg_Data[28] + fifo_36x512_oreg_Data[28] + + + + + fifo_36x512_oreg_Data[29] + fifo_36x512_oreg_Data[29] + + + + + fifo_36x512_oreg_Data[2] + fifo_36x512_oreg_Data[2] + + + + + fifo_36x512_oreg_Data[30] + fifo_36x512_oreg_Data[30] + + + + + fifo_36x512_oreg_Data[31] + fifo_36x512_oreg_Data[31] + + + + + fifo_36x512_oreg_Data[32] + fifo_36x512_oreg_Data[32] + + + + + fifo_36x512_oreg_Data[33] + fifo_36x512_oreg_Data[33] + + + + + fifo_36x512_oreg_Data[34] + fifo_36x512_oreg_Data[34] + + + + + fifo_36x512_oreg_Data[35] + fifo_36x512_oreg_Data[35] + + + + + fifo_36x512_oreg_Data[3] + fifo_36x512_oreg_Data[3] + + + + + fifo_36x512_oreg_Data[4] + fifo_36x512_oreg_Data[4] + + + + + fifo_36x512_oreg_Data[5] + fifo_36x512_oreg_Data[5] + + + + + fifo_36x512_oreg_Data[6] + fifo_36x512_oreg_Data[6] + + + + + fifo_36x512_oreg_Data[7] + fifo_36x512_oreg_Data[7] + + + + + fifo_36x512_oreg_Data[8] + fifo_36x512_oreg_Data[8] + + + + + fifo_36x512_oreg_Data[9] + fifo_36x512_oreg_Data[9] + + + + + fifo_36x512_oreg_Q + fifo_36x512_oreg_Q + + + + + fifo_36x512_oreg_Q[0] + fifo_36x512_oreg_Q[0] + + + + + fifo_36x512_oreg_Q[10] + fifo_36x512_oreg_Q[10] + + + + + fifo_36x512_oreg_Q[11] + fifo_36x512_oreg_Q[11] + + + + + fifo_36x512_oreg_Q[12] + fifo_36x512_oreg_Q[12] + + + + + fifo_36x512_oreg_Q[13] + fifo_36x512_oreg_Q[13] + + + + + fifo_36x512_oreg_Q[14] + fifo_36x512_oreg_Q[14] + + + + + fifo_36x512_oreg_Q[15] + fifo_36x512_oreg_Q[15] + + + + + fifo_36x512_oreg_Q[16] + fifo_36x512_oreg_Q[16] + + + + + fifo_36x512_oreg_Q[17] + fifo_36x512_oreg_Q[17] + + + + + fifo_36x512_oreg_Q[18] + fifo_36x512_oreg_Q[18] + + + + + fifo_36x512_oreg_Q[19] + fifo_36x512_oreg_Q[19] + + + + + fifo_36x512_oreg_Q[1] + fifo_36x512_oreg_Q[1] + + + + + fifo_36x512_oreg_Q[20] + fifo_36x512_oreg_Q[20] + + + + + fifo_36x512_oreg_Q[21] + fifo_36x512_oreg_Q[21] + + + + + fifo_36x512_oreg_Q[22] + fifo_36x512_oreg_Q[22] + + + + + fifo_36x512_oreg_Q[23] + fifo_36x512_oreg_Q[23] + + + + + fifo_36x512_oreg_Q[24] + fifo_36x512_oreg_Q[24] + + + - FIFO_36x128_OutReg_Clock - FIFO_36x128_OutReg_Clock - - + fifo_36x512_oreg_Q[25] + fifo_36x512_oreg_Q[25] + + - FIFO_36x128_OutReg_Empty - FIFO_36x128_OutReg_Empty - - + fifo_36x512_oreg_Q[26] + fifo_36x512_oreg_Q[26] + + - FIFO_36x128_OutReg_Full - FIFO_36x128_OutReg_Full - - + fifo_36x512_oreg_Q[27] + fifo_36x512_oreg_Q[27] + + - FIFO_36x128_OutReg_RdEn - FIFO_36x128_OutReg_RdEn - - + fifo_36x512_oreg_Q[28] + fifo_36x512_oreg_Q[28] + + - FIFO_36x128_OutReg_Reset - FIFO_36x128_OutReg_Reset - - + fifo_36x512_oreg_Q[29] + fifo_36x512_oreg_Q[29] + + - FIFO_36x128_OutReg_WrEn - FIFO_36x128_OutReg_WrEn - - + fifo_36x512_oreg_Q[2] + fifo_36x512_oreg_Q[2] + + - FIFO_DC_36x128_DynThr_OutReg_AlmostFull - FIFO_DC_36x128_DynThr_OutReg_AlmostFull - - + fifo_36x512_oreg_Q[30] + fifo_36x512_oreg_Q[30] + + - FIFO_DC_36x128_DynThr_OutReg_Empty - FIFO_DC_36x128_DynThr_OutReg_Empty - - + fifo_36x512_oreg_Q[31] + fifo_36x512_oreg_Q[31] + + - FIFO_DC_36x128_DynThr_OutReg_Full - FIFO_DC_36x128_DynThr_OutReg_Full - - + fifo_36x512_oreg_Q[32] + fifo_36x512_oreg_Q[32] + + - FIFO_DC_36x128_DynThr_OutReg_RPReset - FIFO_DC_36x128_DynThr_OutReg_RPReset - - + fifo_36x512_oreg_Q[33] + fifo_36x512_oreg_Q[33] + + - FIFO_DC_36x128_DynThr_OutReg_RdClock - FIFO_DC_36x128_DynThr_OutReg_RdClock - - + fifo_36x512_oreg_Q[34] + fifo_36x512_oreg_Q[34] + + - FIFO_DC_36x128_DynThr_OutReg_RdEn - FIFO_DC_36x128_DynThr_OutReg_RdEn - - + fifo_36x512_oreg_Q[35] + fifo_36x512_oreg_Q[35] + + - FIFO_DC_36x128_DynThr_OutReg_Reset - FIFO_DC_36x128_DynThr_OutReg_Reset - - + fifo_36x512_oreg_Q[3] + fifo_36x512_oreg_Q[3] + + - FIFO_DC_36x128_DynThr_OutReg_WrClock - FIFO_DC_36x128_DynThr_OutReg_WrClock - - + fifo_36x512_oreg_Q[4] + fifo_36x512_oreg_Q[4] + + - FIFO_DC_36x128_DynThr_OutReg_WrEn - FIFO_DC_36x128_DynThr_OutReg_WrEn - - + fifo_36x512_oreg_Q[5] + fifo_36x512_oreg_Q[5] + + - FIFO_36x128_OutReg_Data - FIFO_36x128_OutReg_Data - - + fifo_36x512_oreg_Q[6] + fifo_36x512_oreg_Q[6] + + - FIFO_36x128_OutReg_Data[0] - FIFO_36x128_OutReg_Data[0] - - + fifo_36x512_oreg_Q[7] + fifo_36x512_oreg_Q[7] + + - FIFO_36x128_OutReg_Data[10] - FIFO_36x128_OutReg_Data[10] - - + fifo_36x512_oreg_Q[8] + fifo_36x512_oreg_Q[8] + + - FIFO_36x128_OutReg_Data[11] - FIFO_36x128_OutReg_Data[11] - - + fifo_36x512_oreg_Q[9] + fifo_36x512_oreg_Q[9] + + - FIFO_36x128_OutReg_Data[12] - FIFO_36x128_OutReg_Data[12] - - + fifo_36x512_oreg_WCNT + fifo_36x512_oreg_WCNT + + - FIFO_36x128_OutReg_Data[13] - FIFO_36x128_OutReg_Data[13] - - + fifo_36x512_oreg_WCNT[0] + fifo_36x512_oreg_WCNT[0] + + - FIFO_36x128_OutReg_Data[14] - FIFO_36x128_OutReg_Data[14] - - + fifo_36x512_oreg_WCNT[1] + fifo_36x512_oreg_WCNT[1] + + - FIFO_36x128_OutReg_Data[15] - FIFO_36x128_OutReg_Data[15] - - + fifo_36x512_oreg_WCNT[2] + fifo_36x512_oreg_WCNT[2] + + - FIFO_36x128_OutReg_Data[16] - FIFO_36x128_OutReg_Data[16] - - + fifo_36x512_oreg_WCNT[3] + fifo_36x512_oreg_WCNT[3] + + - FIFO_36x128_OutReg_Data[17] - FIFO_36x128_OutReg_Data[17] - - + fifo_36x512_oreg_WCNT[4] + fifo_36x512_oreg_WCNT[4] + + - FIFO_36x128_OutReg_Data[18] - FIFO_36x128_OutReg_Data[18] - - + fifo_36x512_oreg_WCNT[5] + fifo_36x512_oreg_WCNT[5] + + - FIFO_36x128_OutReg_Data[19] - FIFO_36x128_OutReg_Data[19] - - + fifo_36x512_oreg_WCNT[6] + fifo_36x512_oreg_WCNT[6] + + - FIFO_36x128_OutReg_Data[1] - FIFO_36x128_OutReg_Data[1] - - + fifo_36x512_oreg_WCNT[7] + fifo_36x512_oreg_WCNT[7] + + - FIFO_36x128_OutReg_Data[20] - FIFO_36x128_OutReg_Data[20] - - + fifo_36x512_oreg_WCNT[8] + fifo_36x512_oreg_WCNT[8] + + - FIFO_36x128_OutReg_Data[21] - FIFO_36x128_OutReg_Data[21] - - + fifo_36x512_oreg_WCNT[9] + fifo_36x512_oreg_WCNT[9] + + - FIFO_36x128_OutReg_Data[22] - FIFO_36x128_OutReg_Data[22] - - + fifo_36x8k_oreg_AmFullThresh + fifo_36x8k_oreg_AmFullThresh + + - FIFO_36x128_OutReg_Data[23] - FIFO_36x128_OutReg_Data[23] - - + fifo_36x8k_oreg_AmFullThresh[0] + fifo_36x8k_oreg_AmFullThresh[0] + + - FIFO_36x128_OutReg_Data[24] - FIFO_36x128_OutReg_Data[24] - - + fifo_36x8k_oreg_AmFullThresh[10] + fifo_36x8k_oreg_AmFullThresh[10] + + - FIFO_36x128_OutReg_Data[25] - FIFO_36x128_OutReg_Data[25] - - + fifo_36x8k_oreg_AmFullThresh[11] + fifo_36x8k_oreg_AmFullThresh[11] + + - FIFO_36x128_OutReg_Data[26] - FIFO_36x128_OutReg_Data[26] - - + fifo_36x8k_oreg_AmFullThresh[12] + fifo_36x8k_oreg_AmFullThresh[12] + + - FIFO_36x128_OutReg_Data[27] - FIFO_36x128_OutReg_Data[27] - - + fifo_36x8k_oreg_AmFullThresh[1] + fifo_36x8k_oreg_AmFullThresh[1] + + - FIFO_36x128_OutReg_Data[28] - FIFO_36x128_OutReg_Data[28] - - + fifo_36x8k_oreg_AmFullThresh[2] + fifo_36x8k_oreg_AmFullThresh[2] + + - FIFO_36x128_OutReg_Data[29] - FIFO_36x128_OutReg_Data[29] - - + fifo_36x8k_oreg_AmFullThresh[3] + fifo_36x8k_oreg_AmFullThresh[3] + + - FIFO_36x128_OutReg_Data[2] - FIFO_36x128_OutReg_Data[2] - - + fifo_36x8k_oreg_AmFullThresh[4] + fifo_36x8k_oreg_AmFullThresh[4] + + - FIFO_36x128_OutReg_Data[30] - FIFO_36x128_OutReg_Data[30] - - + fifo_36x8k_oreg_AmFullThresh[5] + fifo_36x8k_oreg_AmFullThresh[5] + + - FIFO_36x128_OutReg_Data[31] - FIFO_36x128_OutReg_Data[31] - - + fifo_36x8k_oreg_AmFullThresh[6] + fifo_36x8k_oreg_AmFullThresh[6] + + - FIFO_36x128_OutReg_Data[32] - FIFO_36x128_OutReg_Data[32] - - + fifo_36x8k_oreg_AmFullThresh[7] + fifo_36x8k_oreg_AmFullThresh[7] + + - FIFO_36x128_OutReg_Data[33] - FIFO_36x128_OutReg_Data[33] - - + fifo_36x8k_oreg_AmFullThresh[8] + fifo_36x8k_oreg_AmFullThresh[8] + + - FIFO_36x128_OutReg_Data[34] - FIFO_36x128_OutReg_Data[34] - - + fifo_36x8k_oreg_AmFullThresh[9] + fifo_36x8k_oreg_AmFullThresh[9] + + - FIFO_36x128_OutReg_Data[35] - FIFO_36x128_OutReg_Data[35] - - + fifo_36x8k_oreg_Data + fifo_36x8k_oreg_Data + + - FIFO_36x128_OutReg_Data[3] - FIFO_36x128_OutReg_Data[3] - - + fifo_36x8k_oreg_Data[0] + fifo_36x8k_oreg_Data[0] + + - FIFO_36x128_OutReg_Data[4] - FIFO_36x128_OutReg_Data[4] - - + fifo_36x8k_oreg_Data[10] + fifo_36x8k_oreg_Data[10] + + - FIFO_36x128_OutReg_Data[5] - FIFO_36x128_OutReg_Data[5] - - + fifo_36x8k_oreg_Data[11] + fifo_36x8k_oreg_Data[11] + + - FIFO_36x128_OutReg_Data[6] - FIFO_36x128_OutReg_Data[6] - - + fifo_36x8k_oreg_Data[12] + fifo_36x8k_oreg_Data[12] + + - FIFO_36x128_OutReg_Data[7] - FIFO_36x128_OutReg_Data[7] - - + fifo_36x8k_oreg_Data[13] + fifo_36x8k_oreg_Data[13] + + - FIFO_36x128_OutReg_Data[8] - FIFO_36x128_OutReg_Data[8] - - + fifo_36x8k_oreg_Data[14] + fifo_36x8k_oreg_Data[14] + + - FIFO_36x128_OutReg_Data[9] - FIFO_36x128_OutReg_Data[9] - - + fifo_36x8k_oreg_Data[15] + fifo_36x8k_oreg_Data[15] + + - FIFO_36x128_OutReg_Q - FIFO_36x128_OutReg_Q - - + fifo_36x8k_oreg_Data[16] + fifo_36x8k_oreg_Data[16] + + - FIFO_36x128_OutReg_Q[0] - FIFO_36x128_OutReg_Q[0] - - + fifo_36x8k_oreg_Data[17] + fifo_36x8k_oreg_Data[17] + + - FIFO_36x128_OutReg_Q[10] - FIFO_36x128_OutReg_Q[10] - - + fifo_36x8k_oreg_Data[18] + fifo_36x8k_oreg_Data[18] + + - FIFO_36x128_OutReg_Q[11] - FIFO_36x128_OutReg_Q[11] - - + fifo_36x8k_oreg_Data[19] + fifo_36x8k_oreg_Data[19] + + - FIFO_36x128_OutReg_Q[12] - FIFO_36x128_OutReg_Q[12] - - + fifo_36x8k_oreg_Data[1] + fifo_36x8k_oreg_Data[1] + + - FIFO_36x128_OutReg_Q[13] - FIFO_36x128_OutReg_Q[13] - - + fifo_36x8k_oreg_Data[20] + fifo_36x8k_oreg_Data[20] + + - FIFO_36x128_OutReg_Q[14] - FIFO_36x128_OutReg_Q[14] - - + fifo_36x8k_oreg_Data[21] + fifo_36x8k_oreg_Data[21] + + - FIFO_36x128_OutReg_Q[15] - FIFO_36x128_OutReg_Q[15] - - + fifo_36x8k_oreg_Data[22] + fifo_36x8k_oreg_Data[22] + + - FIFO_36x128_OutReg_Q[16] - FIFO_36x128_OutReg_Q[16] - - + fifo_36x8k_oreg_Data[23] + fifo_36x8k_oreg_Data[23] + + - FIFO_36x128_OutReg_Q[17] - FIFO_36x128_OutReg_Q[17] - - + fifo_36x8k_oreg_Data[24] + fifo_36x8k_oreg_Data[24] + + - FIFO_36x128_OutReg_Q[18] - FIFO_36x128_OutReg_Q[18] - - + fifo_36x8k_oreg_Data[25] + fifo_36x8k_oreg_Data[25] + + - FIFO_36x128_OutReg_Q[19] - FIFO_36x128_OutReg_Q[19] - - + fifo_36x8k_oreg_Data[26] + fifo_36x8k_oreg_Data[26] + + - FIFO_36x128_OutReg_Q[1] - FIFO_36x128_OutReg_Q[1] - - + fifo_36x8k_oreg_Data[27] + fifo_36x8k_oreg_Data[27] + + - FIFO_36x128_OutReg_Q[20] - FIFO_36x128_OutReg_Q[20] - - + fifo_36x8k_oreg_Data[28] + fifo_36x8k_oreg_Data[28] + + - FIFO_36x128_OutReg_Q[21] - FIFO_36x128_OutReg_Q[21] - - + fifo_36x8k_oreg_Data[29] + fifo_36x8k_oreg_Data[29] + + - FIFO_36x128_OutReg_Q[22] - FIFO_36x128_OutReg_Q[22] - - + fifo_36x8k_oreg_Data[2] + fifo_36x8k_oreg_Data[2] + + - FIFO_36x128_OutReg_Q[23] - FIFO_36x128_OutReg_Q[23] - - + fifo_36x8k_oreg_Data[30] + fifo_36x8k_oreg_Data[30] + + - FIFO_36x128_OutReg_Q[24] - FIFO_36x128_OutReg_Q[24] - - + fifo_36x8k_oreg_Data[31] + fifo_36x8k_oreg_Data[31] + + - FIFO_36x128_OutReg_Q[25] - FIFO_36x128_OutReg_Q[25] - - + fifo_36x8k_oreg_Data[32] + fifo_36x8k_oreg_Data[32] + + - FIFO_36x128_OutReg_Q[26] - FIFO_36x128_OutReg_Q[26] - - + fifo_36x8k_oreg_Data[33] + fifo_36x8k_oreg_Data[33] + + - FIFO_36x128_OutReg_Q[27] - FIFO_36x128_OutReg_Q[27] - - + fifo_36x8k_oreg_Data[34] + fifo_36x8k_oreg_Data[34] + + - FIFO_36x128_OutReg_Q[28] - FIFO_36x128_OutReg_Q[28] - - + fifo_36x8k_oreg_Data[35] + fifo_36x8k_oreg_Data[35] + + - FIFO_36x128_OutReg_Q[29] - FIFO_36x128_OutReg_Q[29] - - + fifo_36x8k_oreg_Data[3] + fifo_36x8k_oreg_Data[3] + + - FIFO_36x128_OutReg_Q[2] - FIFO_36x128_OutReg_Q[2] - - + fifo_36x8k_oreg_Data[4] + fifo_36x8k_oreg_Data[4] + + - FIFO_36x128_OutReg_Q[30] - FIFO_36x128_OutReg_Q[30] - - + fifo_36x8k_oreg_Data[5] + fifo_36x8k_oreg_Data[5] + + - FIFO_36x128_OutReg_Q[31] - FIFO_36x128_OutReg_Q[31] - - + fifo_36x8k_oreg_Data[6] + fifo_36x8k_oreg_Data[6] + + - FIFO_36x128_OutReg_Q[32] - FIFO_36x128_OutReg_Q[32] - - + fifo_36x8k_oreg_Data[7] + fifo_36x8k_oreg_Data[7] + + - FIFO_36x128_OutReg_Q[33] - FIFO_36x128_OutReg_Q[33] - - + fifo_36x8k_oreg_Data[8] + fifo_36x8k_oreg_Data[8] + + - FIFO_36x128_OutReg_Q[34] - FIFO_36x128_OutReg_Q[34] - - + fifo_36x8k_oreg_Data[9] + fifo_36x8k_oreg_Data[9] + + - FIFO_36x128_OutReg_Q[35] - FIFO_36x128_OutReg_Q[35] - - + fifo_36x8k_oreg_Q + fifo_36x8k_oreg_Q + + - FIFO_36x128_OutReg_Q[3] - FIFO_36x128_OutReg_Q[3] - - + fifo_36x8k_oreg_Q[0] + fifo_36x8k_oreg_Q[0] + + - FIFO_36x128_OutReg_Q[4] - FIFO_36x128_OutReg_Q[4] - - + fifo_36x8k_oreg_Q[10] + fifo_36x8k_oreg_Q[10] + + - FIFO_36x128_OutReg_Q[5] - FIFO_36x128_OutReg_Q[5] - - + fifo_36x8k_oreg_Q[11] + fifo_36x8k_oreg_Q[11] + + - FIFO_36x128_OutReg_Q[6] - FIFO_36x128_OutReg_Q[6] - - + fifo_36x8k_oreg_Q[12] + fifo_36x8k_oreg_Q[12] + + - FIFO_36x128_OutReg_Q[7] - FIFO_36x128_OutReg_Q[7] - - + fifo_36x8k_oreg_Q[13] + fifo_36x8k_oreg_Q[13] + + - FIFO_36x128_OutReg_Q[8] - FIFO_36x128_OutReg_Q[8] - - + fifo_36x8k_oreg_Q[14] + fifo_36x8k_oreg_Q[14] + + - FIFO_36x128_OutReg_Q[9] - FIFO_36x128_OutReg_Q[9] - - + fifo_36x8k_oreg_Q[15] + fifo_36x8k_oreg_Q[15] + + - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh - - + fifo_36x8k_oreg_Q[16] + fifo_36x8k_oreg_Q[16] + + - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh[0] - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh[0] - - + fifo_36x8k_oreg_Q[17] + fifo_36x8k_oreg_Q[17] + + - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh[1] - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh[1] - - + fifo_36x8k_oreg_Q[18] + fifo_36x8k_oreg_Q[18] + + - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh[2] - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh[2] - - + fifo_36x8k_oreg_Q[19] + fifo_36x8k_oreg_Q[19] + + - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh[3] - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh[3] - - + fifo_36x8k_oreg_Q[1] + fifo_36x8k_oreg_Q[1] + + - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh[4] - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh[4] - - + fifo_36x8k_oreg_Q[20] + fifo_36x8k_oreg_Q[20] + + - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh[5] - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh[5] - - + fifo_36x8k_oreg_Q[21] + fifo_36x8k_oreg_Q[21] + + - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh[6] - FIFO_DC_36x128_DynThr_OutReg_AmFullThresh[6] - - + fifo_36x8k_oreg_Q[22] + fifo_36x8k_oreg_Q[22] + + - FIFO_DC_36x128_DynThr_OutReg_Data - FIFO_DC_36x128_DynThr_OutReg_Data - - + fifo_36x8k_oreg_Q[23] + fifo_36x8k_oreg_Q[23] + + - FIFO_DC_36x128_DynThr_OutReg_Data[0] - FIFO_DC_36x128_DynThr_OutReg_Data[0] - - + fifo_36x8k_oreg_Q[24] + fifo_36x8k_oreg_Q[24] + + - FIFO_DC_36x128_DynThr_OutReg_Data[10] - FIFO_DC_36x128_DynThr_OutReg_Data[10] - - + fifo_36x8k_oreg_Q[25] + fifo_36x8k_oreg_Q[25] + + - FIFO_DC_36x128_DynThr_OutReg_Data[11] - FIFO_DC_36x128_DynThr_OutReg_Data[11] - - + fifo_36x8k_oreg_Q[26] + fifo_36x8k_oreg_Q[26] + + - FIFO_DC_36x128_DynThr_OutReg_Data[12] - FIFO_DC_36x128_DynThr_OutReg_Data[12] - - + fifo_36x8k_oreg_Q[27] + fifo_36x8k_oreg_Q[27] + + - FIFO_DC_36x128_DynThr_OutReg_Data[13] - FIFO_DC_36x128_DynThr_OutReg_Data[13] - - + fifo_36x8k_oreg_Q[28] + fifo_36x8k_oreg_Q[28] + + - FIFO_DC_36x128_DynThr_OutReg_Data[14] - FIFO_DC_36x128_DynThr_OutReg_Data[14] - - + fifo_36x8k_oreg_Q[29] + fifo_36x8k_oreg_Q[29] + + - FIFO_DC_36x128_DynThr_OutReg_Data[15] - FIFO_DC_36x128_DynThr_OutReg_Data[15] - - + fifo_36x8k_oreg_Q[2] + fifo_36x8k_oreg_Q[2] + + - FIFO_DC_36x128_DynThr_OutReg_Data[16] - FIFO_DC_36x128_DynThr_OutReg_Data[16] - - + fifo_36x8k_oreg_Q[30] + fifo_36x8k_oreg_Q[30] + + - FIFO_DC_36x128_DynThr_OutReg_Data[17] - FIFO_DC_36x128_DynThr_OutReg_Data[17] - - + fifo_36x8k_oreg_Q[31] + fifo_36x8k_oreg_Q[31] + + - FIFO_DC_36x128_DynThr_OutReg_Data[18] - FIFO_DC_36x128_DynThr_OutReg_Data[18] - - + fifo_36x8k_oreg_Q[32] + fifo_36x8k_oreg_Q[32] + + - FIFO_DC_36x128_DynThr_OutReg_Data[19] - FIFO_DC_36x128_DynThr_OutReg_Data[19] - - + fifo_36x8k_oreg_Q[33] + fifo_36x8k_oreg_Q[33] + + - FIFO_DC_36x128_DynThr_OutReg_Data[1] - FIFO_DC_36x128_DynThr_OutReg_Data[1] - - + fifo_36x8k_oreg_Q[34] + fifo_36x8k_oreg_Q[34] + + - FIFO_DC_36x128_DynThr_OutReg_Data[20] - FIFO_DC_36x128_DynThr_OutReg_Data[20] - - + fifo_36x8k_oreg_Q[35] + fifo_36x8k_oreg_Q[35] + + - FIFO_DC_36x128_DynThr_OutReg_Data[21] - FIFO_DC_36x128_DynThr_OutReg_Data[21] - - + fifo_36x8k_oreg_Q[3] + fifo_36x8k_oreg_Q[3] + + - FIFO_DC_36x128_DynThr_OutReg_Data[22] - FIFO_DC_36x128_DynThr_OutReg_Data[22] - - + fifo_36x8k_oreg_Q[4] + fifo_36x8k_oreg_Q[4] + + - FIFO_DC_36x128_DynThr_OutReg_Data[23] - FIFO_DC_36x128_DynThr_OutReg_Data[23] - - + fifo_36x8k_oreg_Q[5] + fifo_36x8k_oreg_Q[5] + + - FIFO_DC_36x128_DynThr_OutReg_Data[24] - FIFO_DC_36x128_DynThr_OutReg_Data[24] - - + fifo_36x8k_oreg_Q[6] + fifo_36x8k_oreg_Q[6] + + - FIFO_DC_36x128_DynThr_OutReg_Data[25] - FIFO_DC_36x128_DynThr_OutReg_Data[25] - - + fifo_36x8k_oreg_Q[7] + fifo_36x8k_oreg_Q[7] + + - FIFO_DC_36x128_DynThr_OutReg_Data[26] - FIFO_DC_36x128_DynThr_OutReg_Data[26] - - + fifo_36x8k_oreg_Q[8] + fifo_36x8k_oreg_Q[8] + + - FIFO_DC_36x128_DynThr_OutReg_Data[27] - FIFO_DC_36x128_DynThr_OutReg_Data[27] - - + fifo_36x8k_oreg_Q[9] + fifo_36x8k_oreg_Q[9] + + - FIFO_DC_36x128_DynThr_OutReg_Data[28] - FIFO_DC_36x128_DynThr_OutReg_Data[28] - - + fifo_36x8k_oreg_WCNT + fifo_36x8k_oreg_WCNT + + - FIFO_DC_36x128_DynThr_OutReg_Data[29] - FIFO_DC_36x128_DynThr_OutReg_Data[29] - - + fifo_36x8k_oreg_WCNT[0] + fifo_36x8k_oreg_WCNT[0] + + - FIFO_DC_36x128_DynThr_OutReg_Data[2] - FIFO_DC_36x128_DynThr_OutReg_Data[2] - - + fifo_36x8k_oreg_WCNT[10] + fifo_36x8k_oreg_WCNT[10] + + - FIFO_DC_36x128_DynThr_OutReg_Data[30] - FIFO_DC_36x128_DynThr_OutReg_Data[30] - - + fifo_36x8k_oreg_WCNT[11] + fifo_36x8k_oreg_WCNT[11] + + - FIFO_DC_36x128_DynThr_OutReg_Data[31] - FIFO_DC_36x128_DynThr_OutReg_Data[31] - - + fifo_36x8k_oreg_WCNT[12] + fifo_36x8k_oreg_WCNT[12] + + - FIFO_DC_36x128_DynThr_OutReg_Data[32] - FIFO_DC_36x128_DynThr_OutReg_Data[32] - - + fifo_36x8k_oreg_WCNT[13] + fifo_36x8k_oreg_WCNT[13] + + - FIFO_DC_36x128_DynThr_OutReg_Data[33] - FIFO_DC_36x128_DynThr_OutReg_Data[33] - - + fifo_36x8k_oreg_WCNT[1] + fifo_36x8k_oreg_WCNT[1] + + - FIFO_DC_36x128_DynThr_OutReg_Data[34] - FIFO_DC_36x128_DynThr_OutReg_Data[34] - - + fifo_36x8k_oreg_WCNT[2] + fifo_36x8k_oreg_WCNT[2] + + - FIFO_DC_36x128_DynThr_OutReg_Data[35] - FIFO_DC_36x128_DynThr_OutReg_Data[35] - - + fifo_36x8k_oreg_WCNT[3] + fifo_36x8k_oreg_WCNT[3] + + - FIFO_DC_36x128_DynThr_OutReg_Data[3] - FIFO_DC_36x128_DynThr_OutReg_Data[3] - - + fifo_36x8k_oreg_WCNT[4] + fifo_36x8k_oreg_WCNT[4] + + - FIFO_DC_36x128_DynThr_OutReg_Data[4] - FIFO_DC_36x128_DynThr_OutReg_Data[4] - - + fifo_36x8k_oreg_WCNT[5] + fifo_36x8k_oreg_WCNT[5] + + - FIFO_DC_36x128_DynThr_OutReg_Data[5] - FIFO_DC_36x128_DynThr_OutReg_Data[5] - - + fifo_36x8k_oreg_WCNT[6] + fifo_36x8k_oreg_WCNT[6] + + - FIFO_DC_36x128_DynThr_OutReg_Data[6] - FIFO_DC_36x128_DynThr_OutReg_Data[6] - - + fifo_36x8k_oreg_WCNT[7] + fifo_36x8k_oreg_WCNT[7] + + - FIFO_DC_36x128_DynThr_OutReg_Data[7] - FIFO_DC_36x128_DynThr_OutReg_Data[7] - - + fifo_36x8k_oreg_WCNT[8] + fifo_36x8k_oreg_WCNT[8] + + - FIFO_DC_36x128_DynThr_OutReg_Data[8] - FIFO_DC_36x128_DynThr_OutReg_Data[8] - - + fifo_36x8k_oreg_WCNT[9] + fifo_36x8k_oreg_WCNT[9] + + - FIFO_DC_36x128_DynThr_OutReg_Data[9] - FIFO_DC_36x128_DynThr_OutReg_Data[9] - - + lattice_ecp5_fifo_18x1k_Data + lattice_ecp5_fifo_18x1k_Data + + - FIFO_DC_36x128_DynThr_OutReg_Q - FIFO_DC_36x128_DynThr_OutReg_Q - - + lattice_ecp5_fifo_18x1k_Data[0] + lattice_ecp5_fifo_18x1k_Data[0] + + - FIFO_DC_36x128_DynThr_OutReg_Q[0] - FIFO_DC_36x128_DynThr_OutReg_Q[0] - - + lattice_ecp5_fifo_18x1k_Data[10] + lattice_ecp5_fifo_18x1k_Data[10] + + - FIFO_DC_36x128_DynThr_OutReg_Q[10] - FIFO_DC_36x128_DynThr_OutReg_Q[10] - - + lattice_ecp5_fifo_18x1k_Data[11] + lattice_ecp5_fifo_18x1k_Data[11] + + - FIFO_DC_36x128_DynThr_OutReg_Q[11] - FIFO_DC_36x128_DynThr_OutReg_Q[11] - - + lattice_ecp5_fifo_18x1k_Data[12] + lattice_ecp5_fifo_18x1k_Data[12] + + - FIFO_DC_36x128_DynThr_OutReg_Q[12] - FIFO_DC_36x128_DynThr_OutReg_Q[12] - - + lattice_ecp5_fifo_18x1k_Data[13] + lattice_ecp5_fifo_18x1k_Data[13] + + - FIFO_DC_36x128_DynThr_OutReg_Q[13] - FIFO_DC_36x128_DynThr_OutReg_Q[13] - - + lattice_ecp5_fifo_18x1k_Data[14] + lattice_ecp5_fifo_18x1k_Data[14] + + - FIFO_DC_36x128_DynThr_OutReg_Q[14] - FIFO_DC_36x128_DynThr_OutReg_Q[14] - - + lattice_ecp5_fifo_18x1k_Data[15] + lattice_ecp5_fifo_18x1k_Data[15] + + - FIFO_DC_36x128_DynThr_OutReg_Q[15] - FIFO_DC_36x128_DynThr_OutReg_Q[15] - - + lattice_ecp5_fifo_18x1k_Data[16] + lattice_ecp5_fifo_18x1k_Data[16] + + - FIFO_DC_36x128_DynThr_OutReg_Q[16] - FIFO_DC_36x128_DynThr_OutReg_Q[16] - - + lattice_ecp5_fifo_18x1k_Data[17] + lattice_ecp5_fifo_18x1k_Data[17] + + - FIFO_DC_36x128_DynThr_OutReg_Q[17] - FIFO_DC_36x128_DynThr_OutReg_Q[17] - - + lattice_ecp5_fifo_18x1k_Data[1] + lattice_ecp5_fifo_18x1k_Data[1] + + - FIFO_DC_36x128_DynThr_OutReg_Q[18] - FIFO_DC_36x128_DynThr_OutReg_Q[18] - - + lattice_ecp5_fifo_18x1k_Data[2] + lattice_ecp5_fifo_18x1k_Data[2] + + - FIFO_DC_36x128_DynThr_OutReg_Q[19] - FIFO_DC_36x128_DynThr_OutReg_Q[19] - - + lattice_ecp5_fifo_18x1k_Data[3] + lattice_ecp5_fifo_18x1k_Data[3] + + - FIFO_DC_36x128_DynThr_OutReg_Q[1] - FIFO_DC_36x128_DynThr_OutReg_Q[1] - - + lattice_ecp5_fifo_18x1k_Data[4] + lattice_ecp5_fifo_18x1k_Data[4] + + - FIFO_DC_36x128_DynThr_OutReg_Q[20] - FIFO_DC_36x128_DynThr_OutReg_Q[20] - - + lattice_ecp5_fifo_18x1k_Data[5] + lattice_ecp5_fifo_18x1k_Data[5] + + - FIFO_DC_36x128_DynThr_OutReg_Q[21] - FIFO_DC_36x128_DynThr_OutReg_Q[21] - - + lattice_ecp5_fifo_18x1k_Data[6] + lattice_ecp5_fifo_18x1k_Data[6] + + - FIFO_DC_36x128_DynThr_OutReg_Q[22] - FIFO_DC_36x128_DynThr_OutReg_Q[22] - - + lattice_ecp5_fifo_18x1k_Data[7] + lattice_ecp5_fifo_18x1k_Data[7] + + - FIFO_DC_36x128_DynThr_OutReg_Q[23] - FIFO_DC_36x128_DynThr_OutReg_Q[23] - - + lattice_ecp5_fifo_18x1k_Data[8] + lattice_ecp5_fifo_18x1k_Data[8] + + - FIFO_DC_36x128_DynThr_OutReg_Q[24] - FIFO_DC_36x128_DynThr_OutReg_Q[24] - - + lattice_ecp5_fifo_18x1k_Data[9] + lattice_ecp5_fifo_18x1k_Data[9] + + - FIFO_DC_36x128_DynThr_OutReg_Q[25] - FIFO_DC_36x128_DynThr_OutReg_Q[25] - - + lattice_ecp5_fifo_18x1k_Q + lattice_ecp5_fifo_18x1k_Q + + - FIFO_DC_36x128_DynThr_OutReg_Q[26] - FIFO_DC_36x128_DynThr_OutReg_Q[26] - - + lattice_ecp5_fifo_18x1k_Q[0] + lattice_ecp5_fifo_18x1k_Q[0] + + - FIFO_DC_36x128_DynThr_OutReg_Q[27] - FIFO_DC_36x128_DynThr_OutReg_Q[27] - - + lattice_ecp5_fifo_18x1k_Q[10] + lattice_ecp5_fifo_18x1k_Q[10] + + - FIFO_DC_36x128_DynThr_OutReg_Q[28] - FIFO_DC_36x128_DynThr_OutReg_Q[28] - - + lattice_ecp5_fifo_18x1k_Q[11] + lattice_ecp5_fifo_18x1k_Q[11] + + - FIFO_DC_36x128_DynThr_OutReg_Q[29] - FIFO_DC_36x128_DynThr_OutReg_Q[29] - - + lattice_ecp5_fifo_18x1k_Q[12] + lattice_ecp5_fifo_18x1k_Q[12] + + - FIFO_DC_36x128_DynThr_OutReg_Q[2] - FIFO_DC_36x128_DynThr_OutReg_Q[2] - - + lattice_ecp5_fifo_18x1k_Q[13] + lattice_ecp5_fifo_18x1k_Q[13] + + - FIFO_DC_36x128_DynThr_OutReg_Q[30] - FIFO_DC_36x128_DynThr_OutReg_Q[30] - - + lattice_ecp5_fifo_18x1k_Q[14] + lattice_ecp5_fifo_18x1k_Q[14] + + - FIFO_DC_36x128_DynThr_OutReg_Q[31] - FIFO_DC_36x128_DynThr_OutReg_Q[31] - - + lattice_ecp5_fifo_18x1k_Q[15] + lattice_ecp5_fifo_18x1k_Q[15] + + - FIFO_DC_36x128_DynThr_OutReg_Q[32] - FIFO_DC_36x128_DynThr_OutReg_Q[32] - - + lattice_ecp5_fifo_18x1k_Q[16] + lattice_ecp5_fifo_18x1k_Q[16] + + - FIFO_DC_36x128_DynThr_OutReg_Q[33] - FIFO_DC_36x128_DynThr_OutReg_Q[33] - - + lattice_ecp5_fifo_18x1k_Q[17] + lattice_ecp5_fifo_18x1k_Q[17] + + - FIFO_DC_36x128_DynThr_OutReg_Q[34] - FIFO_DC_36x128_DynThr_OutReg_Q[34] - - + lattice_ecp5_fifo_18x1k_Q[1] + lattice_ecp5_fifo_18x1k_Q[1] + + - FIFO_DC_36x128_DynThr_OutReg_Q[35] - FIFO_DC_36x128_DynThr_OutReg_Q[35] - - + lattice_ecp5_fifo_18x1k_Q[2] + lattice_ecp5_fifo_18x1k_Q[2] + + - FIFO_DC_36x128_DynThr_OutReg_Q[3] - FIFO_DC_36x128_DynThr_OutReg_Q[3] - - + lattice_ecp5_fifo_18x1k_Q[3] + lattice_ecp5_fifo_18x1k_Q[3] + + - FIFO_DC_36x128_DynThr_OutReg_Q[4] - FIFO_DC_36x128_DynThr_OutReg_Q[4] - - + lattice_ecp5_fifo_18x1k_Q[4] + lattice_ecp5_fifo_18x1k_Q[4] + + - FIFO_DC_36x128_DynThr_OutReg_Q[5] - FIFO_DC_36x128_DynThr_OutReg_Q[5] - - + lattice_ecp5_fifo_18x1k_Q[5] + lattice_ecp5_fifo_18x1k_Q[5] + + - FIFO_DC_36x128_DynThr_OutReg_Q[6] - FIFO_DC_36x128_DynThr_OutReg_Q[6] - - + lattice_ecp5_fifo_18x1k_Q[6] + lattice_ecp5_fifo_18x1k_Q[6] + + - FIFO_DC_36x128_DynThr_OutReg_Q[7] - FIFO_DC_36x128_DynThr_OutReg_Q[7] - - + lattice_ecp5_fifo_18x1k_Q[7] + lattice_ecp5_fifo_18x1k_Q[7] + + - FIFO_DC_36x128_DynThr_OutReg_Q[8] - FIFO_DC_36x128_DynThr_OutReg_Q[8] - - + lattice_ecp5_fifo_18x1k_Q[8] + lattice_ecp5_fifo_18x1k_Q[8] + + - FIFO_DC_36x128_DynThr_OutReg_Q[9] - FIFO_DC_36x128_DynThr_OutReg_Q[9] - - + lattice_ecp5_fifo_18x1k_Q[9] + lattice_ecp5_fifo_18x1k_Q[9] + + diff --git a/lattice/ecp5/FIFO/archv/FIFO_36x128_OutReg.zip b/lattice/ecp5/FIFO/archv/FIFO_36x128_OutReg.zip deleted file mode 100644 index 6e075d0..0000000 Binary files a/lattice/ecp5/FIFO/archv/FIFO_36x128_OutReg.zip and /dev/null differ diff --git a/lattice/ecp5/FIFO/archv/FIFO_DC_36x128_DynThr_OutReg.zip b/lattice/ecp5/FIFO/archv/FIFO_DC_36x128_DynThr_OutReg.zip deleted file mode 100644 index 0ac65d1..0000000 Binary files a/lattice/ecp5/FIFO/archv/FIFO_DC_36x128_DynThr_OutReg.zip and /dev/null differ diff --git a/lattice/ecp5/FIFO/archv/fifo_18x1k_oreg.zip b/lattice/ecp5/FIFO/archv/fifo_18x1k_oreg.zip new file mode 100644 index 0000000..77ac37d Binary files /dev/null and b/lattice/ecp5/FIFO/archv/fifo_18x1k_oreg.zip differ diff --git a/lattice/ecp5/FIFO/archv/fifo_18x256_oreg.zip b/lattice/ecp5/FIFO/archv/fifo_18x256_oreg.zip new file mode 100644 index 0000000..35cbcf4 Binary files /dev/null and b/lattice/ecp5/FIFO/archv/fifo_18x256_oreg.zip differ diff --git a/lattice/ecp5/FIFO/archv/fifo_18x512_oreg.zip b/lattice/ecp5/FIFO/archv/fifo_18x512_oreg.zip new file mode 100644 index 0000000..bb3c391 Binary files /dev/null and b/lattice/ecp5/FIFO/archv/fifo_18x512_oreg.zip differ diff --git a/lattice/ecp5/FIFO/archv/fifo_19x16_obuf.zip b/lattice/ecp5/FIFO/archv/fifo_19x16_obuf.zip new file mode 100644 index 0000000..78d1a86 Binary files /dev/null and b/lattice/ecp5/FIFO/archv/fifo_19x16_obuf.zip differ diff --git a/lattice/ecp5/FIFO/archv/fifo_36x16k_oreg.zip b/lattice/ecp5/FIFO/archv/fifo_36x16k_oreg.zip new file mode 100644 index 0000000..619a679 Binary files /dev/null and b/lattice/ecp5/FIFO/archv/fifo_36x16k_oreg.zip differ diff --git a/lattice/ecp5/FIFO/archv/fifo_36x1k_oreg.zip b/lattice/ecp5/FIFO/archv/fifo_36x1k_oreg.zip new file mode 100644 index 0000000..7e907e7 Binary files /dev/null and b/lattice/ecp5/FIFO/archv/fifo_36x1k_oreg.zip differ diff --git a/lattice/ecp5/FIFO/archv/fifo_36x2k_oreg.zip b/lattice/ecp5/FIFO/archv/fifo_36x2k_oreg.zip new file mode 100644 index 0000000..321057a Binary files /dev/null and b/lattice/ecp5/FIFO/archv/fifo_36x2k_oreg.zip differ diff --git a/lattice/ecp5/FIFO/archv/fifo_36x32k_oreg.zip b/lattice/ecp5/FIFO/archv/fifo_36x32k_oreg.zip new file mode 100644 index 0000000..c6ea84c Binary files /dev/null and b/lattice/ecp5/FIFO/archv/fifo_36x32k_oreg.zip differ diff --git a/lattice/ecp5/FIFO/archv/fifo_36x4k_oreg.zip b/lattice/ecp5/FIFO/archv/fifo_36x4k_oreg.zip new file mode 100644 index 0000000..60479b0 Binary files /dev/null and b/lattice/ecp5/FIFO/archv/fifo_36x4k_oreg.zip differ diff --git a/lattice/ecp5/FIFO/archv/fifo_36x512_oreg.zip b/lattice/ecp5/FIFO/archv/fifo_36x512_oreg.zip new file mode 100644 index 0000000..f465347 Binary files /dev/null and b/lattice/ecp5/FIFO/archv/fifo_36x512_oreg.zip differ diff --git a/lattice/ecp5/FIFO/archv/fifo_36x8k_oreg.zip b/lattice/ecp5/FIFO/archv/fifo_36x8k_oreg.zip new file mode 100644 index 0000000..17647cf Binary files /dev/null and b/lattice/ecp5/FIFO/archv/fifo_36x8k_oreg.zip differ diff --git a/lattice/ecp5/FIFO/archv/lattice_ecp5_fifo_18x1k.zip b/lattice/ecp5/FIFO/archv/lattice_ecp5_fifo_18x1k.zip new file mode 100644 index 0000000..dec6d68 Binary files /dev/null and b/lattice/ecp5/FIFO/archv/lattice_ecp5_fifo_18x1k.zip differ diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.cst b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.cst index bfbf105..3e61b19 100644 --- a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.cst +++ b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.cst @@ -1,3 +1,3 @@ -Date=03/18/2015 -Time=14:32:07 +Date=03/20/2015 +Time=11:37:48 diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.edn b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.edn index 6246675..4465628 100644 --- a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.edn +++ b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.edn @@ -4,9 +4,9 @@ (keywordMap (keywordLevel 0)) (status (written - (timestamp 2015 3 18 14 32 11) + (timestamp 2015 3 20 11 37 50) (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) - (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.fdc ") + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.fdc ") (library ORCLIB (edifLevel 0) (technology diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.lpc b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.lpc index aa9cf19..395bda1 100644 --- a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.lpc +++ b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.lpc @@ -16,8 +16,8 @@ CoreRevision=5.0 ModuleName=fifo_18x1k_oreg SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/18/2015 -Time=14:32:07 +Date=03/20/2015 +Time=11:37:48 [Parameters] Verilog=0 diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngd b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngd index 739970d..1b5006f 100644 Binary files a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngd and b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngd differ diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngo b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngo index ca80848..83c7d0f 100644 Binary files a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngo and b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.ngo differ diff --git a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd index 51a1398..aaac2e7 100644 --- a/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd +++ b/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 -- Module Version: 5.0 ---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.fdc +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.fdc --- Wed Mar 18 14:32:11 2015 +-- Fri Mar 20 11:37:50 2015 library IEEE; use IEEE.std_logic_1164.all; diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.cst b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.cst index 4b60fa4..c23c28e 100644 --- a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.cst +++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.cst @@ -1,3 +1,3 @@ -Date=03/18/2015 -Time=14:42:54 +Date=03/20/2015 +Time=11:38:15 diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.edn b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.edn index dbbee06..22ecc79 100644 --- a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.edn +++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.edn @@ -4,9 +4,9 @@ (keywordMap (keywordLevel 0)) (status (written - (timestamp 2015 3 18 14 42 55) + (timestamp 2015 3 20 11 38 17) (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) - (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x256_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 256 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.fdc ") + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x256_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 256 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.fdc ") (library ORCLIB (edifLevel 0) (technology diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.lpc b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.lpc index a889eae..3b858d7 100644 --- a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.lpc +++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.lpc @@ -16,8 +16,8 @@ CoreRevision=5.0 ModuleName=fifo_18x256_oreg SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/18/2015 -Time=14:42:54 +Date=03/20/2015 +Time=11:38:15 [Parameters] Verilog=0 diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.ngd b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.ngd index 97f9124..db6ef31 100644 Binary files a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.ngd and b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.ngd differ diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.ngo b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.ngo index f22854e..c91fe78 100644 Binary files a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.ngo and b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.ngo differ diff --git a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd index ba735fc..8aa100f 100644 --- a/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd +++ b/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 -- Module Version: 5.0 ---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x256_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 256 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.fdc +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x256_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 256 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.fdc --- Wed Mar 18 14:42:55 2015 +-- Fri Mar 20 11:38:17 2015 library IEEE; use IEEE.std_logic_1164.all; diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.cst b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.cst index d7afd32..cf3d01c 100644 --- a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.cst +++ b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.cst @@ -1,3 +1,3 @@ -Date=03/18/2015 -Time=14:43:13 +Date=03/20/2015 +Time=11:38:36 diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.edn b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.edn index d8b4bab..470f251 100644 --- a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.edn +++ b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.edn @@ -4,9 +4,9 @@ (keywordMap (keywordLevel 0)) (status (written - (timestamp 2015 3 18 14 43 18) + (timestamp 2015 3 20 11 38 38) (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) - (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.fdc ") + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.fdc ") (library ORCLIB (edifLevel 0) (technology diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.lpc b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.lpc index a92d8d4..b5f3c02 100644 --- a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.lpc +++ b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.lpc @@ -16,8 +16,8 @@ CoreRevision=5.0 ModuleName=fifo_18x512_oreg SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/18/2015 -Time=14:43:13 +Date=03/20/2015 +Time=11:38:36 [Parameters] Verilog=0 diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngd b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngd index ecd1e9a..d96cec1 100644 Binary files a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngd and b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngd differ diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngo b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngo index 25f8b97..8382d02 100644 Binary files a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngo and b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.ngo differ diff --git a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd index 0e3a077..e296f9d 100644 --- a/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd +++ b/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 -- Module Version: 5.0 ---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.fdc +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_18x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 18 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.fdc --- Wed Mar 18 14:43:18 2015 +-- Fri Mar 20 11:38:38 2015 library IEEE; use IEEE.std_logic_1164.all; diff --git a/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.cst b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.cst new file mode 100644 index 0000000..ffa99b5 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.cst @@ -0,0 +1,3 @@ +Date=03/20/2015 +Time=10:49:00 + diff --git a/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.edn b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.edn new file mode 100644 index 0000000..6a2902b --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.edn @@ -0,0 +1,1995 @@ +(edif fifo_19x16_obuf + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 3 20 10 49 2) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_19x16_obuf -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 16 -width 19 -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.fdc ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell CCU2C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port C0 + (direction INPUT)) + (port C1 + (direction INPUT)) + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port CIN + (direction INPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT)) + (port COUT + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell FD1P3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell PDPW16KD + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DI35 + (direction INPUT)) + (port DI34 + (direction INPUT)) + (port DI33 + (direction INPUT)) + (port DI32 + (direction INPUT)) + (port DI31 + (direction INPUT)) + (port DI30 + (direction INPUT)) + (port DI29 + (direction INPUT)) + (port DI28 + (direction INPUT)) + (port DI27 + (direction INPUT)) + (port DI26 + (direction INPUT)) + (port DI25 + (direction INPUT)) + (port DI24 + (direction INPUT)) + (port DI23 + (direction INPUT)) + (port DI22 + (direction INPUT)) + (port DI21 + (direction INPUT)) + (port DI20 + (direction INPUT)) + (port DI19 + (direction INPUT)) + (port DI18 + (direction INPUT)) + (port DI17 + (direction INPUT)) + (port DI16 + (direction INPUT)) + (port DI15 + (direction INPUT)) + (port DI14 + (direction INPUT)) + (port DI13 + (direction INPUT)) + (port DI12 + (direction INPUT)) + (port DI11 + (direction INPUT)) + (port DI10 + (direction INPUT)) + (port DI9 + (direction INPUT)) + (port DI8 + (direction INPUT)) + (port DI7 + (direction INPUT)) + (port DI6 + (direction INPUT)) + (port DI5 + (direction INPUT)) + (port DI4 + (direction INPUT)) + (port DI3 + (direction INPUT)) + (port DI2 + (direction INPUT)) + (port DI1 + (direction INPUT)) + (port DI0 + (direction INPUT)) + (port ADW8 + (direction INPUT)) + (port ADW7 + (direction INPUT)) + (port ADW6 + (direction INPUT)) + (port ADW5 + (direction INPUT)) + (port ADW4 + (direction INPUT)) + (port ADW3 + (direction INPUT)) + (port ADW2 + (direction INPUT)) + (port ADW1 + (direction INPUT)) + (port ADW0 + (direction INPUT)) + (port BE3 + (direction INPUT)) + (port BE2 + (direction INPUT)) + (port BE1 + (direction INPUT)) + (port BE0 + (direction INPUT)) + (port CEW + (direction INPUT)) + (port CLKW + (direction INPUT)) + (port CSW2 + (direction INPUT)) + (port CSW1 + (direction INPUT)) + (port CSW0 + (direction INPUT)) + (port ADR13 + (direction INPUT)) + (port ADR12 + (direction INPUT)) + (port ADR11 + (direction INPUT)) + (port ADR10 + (direction INPUT)) + (port ADR9 + (direction INPUT)) + (port ADR8 + (direction INPUT)) + (port ADR7 + (direction INPUT)) + (port ADR6 + (direction INPUT)) + (port ADR5 + (direction INPUT)) + (port ADR4 + (direction INPUT)) + (port ADR3 + (direction INPUT)) + (port ADR2 + (direction INPUT)) + (port ADR1 + (direction INPUT)) + (port ADR0 + (direction INPUT)) + (port CER + (direction INPUT)) + (port OCER + (direction INPUT)) + (port CLKR + (direction INPUT)) + (port CSR2 + (direction INPUT)) + (port CSR1 + (direction INPUT)) + (port CSR0 + (direction INPUT)) + (port RST + (direction INPUT)) + (port DO35 + (direction OUTPUT)) + (port DO34 + (direction OUTPUT)) + (port DO33 + (direction OUTPUT)) + (port DO32 + (direction OUTPUT)) + (port DO31 + (direction OUTPUT)) + (port DO30 + (direction OUTPUT)) + (port DO29 + (direction OUTPUT)) + (port DO28 + (direction OUTPUT)) + (port DO27 + (direction OUTPUT)) + (port DO26 + (direction OUTPUT)) + (port DO25 + (direction OUTPUT)) + (port DO24 + (direction OUTPUT)) + (port DO23 + (direction OUTPUT)) + (port DO22 + (direction OUTPUT)) + (port DO21 + (direction OUTPUT)) + (port DO20 + (direction OUTPUT)) + (port DO19 + (direction OUTPUT)) + (port DO18 + (direction OUTPUT)) + (port DO17 + (direction OUTPUT)) + (port DO16 + (direction OUTPUT)) + (port DO15 + (direction OUTPUT)) + (port DO14 + (direction OUTPUT)) + (port DO13 + (direction OUTPUT)) + (port DO12 + (direction OUTPUT)) + (port DO11 + (direction OUTPUT)) + (port DO10 + (direction OUTPUT)) + (port DO9 + (direction OUTPUT)) + (port DO8 + (direction OUTPUT)) + (port DO7 + (direction OUTPUT)) + (port DO6 + (direction OUTPUT)) + (port DO5 + (direction OUTPUT)) + (port DO4 + (direction OUTPUT)) + (port DO3 + (direction OUTPUT)) + (port DO2 + (direction OUTPUT)) + (port DO1 + (direction OUTPUT)) + (port DO0 + (direction OUTPUT))))) + (cell fifo_19x16_obuf + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port (array (rename Data "Data(18:0)") 19) + (direction INPUT)) + (port Clock + (direction INPUT)) + (port WrEn + (direction INPUT)) + (port RdEn + (direction INPUT)) + (port Reset + (direction INPUT)) + (port (array (rename AmFullThresh "AmFullThresh(3:0)") 4) + (direction INPUT)) + (port (array (rename Q "Q(18:0)") 19) + (direction OUTPUT)) + (port (array (rename WCNT "WCNT(4:0)") 5) + (direction OUTPUT)) + (port Empty + (direction OUTPUT)) + (port Full + (direction OUTPUT)) + (port AlmostFull + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance AND2_t5 + (viewRef view1 + (cellRef AND2))) + (instance INV_5 + (viewRef view1 + (cellRef INV))) + (instance AND2_t4 + (viewRef view1 + (cellRef AND2))) + (instance INV_4 + (viewRef view1 + (cellRef INV))) + (instance AND2_t3 + (viewRef view1 + (cellRef AND2))) + (instance XOR2_t2 + (viewRef view1 + (cellRef XOR2))) + (instance INV_3 + (viewRef view1 + (cellRef INV))) + (instance INV_2 + (viewRef view1 + (cellRef INV))) + (instance LUT4_1 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance LUT4_0 + (viewRef view1 + (cellRef ROM16X1A)) + (property initval + (string "0x3232"))) + (instance AND2_t1 + (viewRef view1 + (cellRef AND2))) + (instance INV_1 + (viewRef view1 + (cellRef INV))) + (instance XOR2_t0 + (viewRef view1 + (cellRef XOR2))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance pdp_ram_0_0_0 + (viewRef view1 + (cellRef PDPW16KD)) + (property INIT_DATA + (string "STATIC")) + (property ASYNC_RESET_RELEASE + (string "SYNC")) + (property MEM_LPC_FILE + (string "fifo_19x16_obuf.lpc")) + (property MEM_INIT_FILE + (string "")) + (property CSDECODE_R + (string "0b000")) + (property CSDECODE_W + (string "0b001")) + (property GSR + (string "ENABLED")) + (property RESETMODE + (string "ASYNC")) + (property REGMODE + (string "NOREG")) + (property DATA_WIDTH_R + (string "36")) + (property DATA_WIDTH_W + (string "36"))) + (instance FF_32 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_31 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_30 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_29 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_28 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_27 + (viewRef view1 + (cellRef FD1S3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_26 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_25 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_24 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_23 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_22 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_21 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_20 + (viewRef view1 + (cellRef FD1P3BX)) + (property GSR + (string "ENABLED"))) + (instance FF_19 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_18 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_17 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_16 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_15 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_14 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_13 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_12 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_11 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_10 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_9 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_8 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_7 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_6 + (viewRef view1 + (cellRef FD1P3DX)) + (property GSR + (string "ENABLED"))) + (instance FF_5 + (viewRef view1 + (cellRef FD1S3DX)) + (property GSR + (string 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5)) + (portRef DI13 (instanceRef pdp_ram_0_0_0)))) + (net datain12 + (joined + (portRef (member Data 6)) + (portRef DI12 (instanceRef pdp_ram_0_0_0)))) + (net datain11 + (joined + (portRef (member Data 7)) + (portRef DI11 (instanceRef pdp_ram_0_0_0)))) + (net datain10 + (joined + (portRef (member Data 8)) + (portRef DI10 (instanceRef pdp_ram_0_0_0)))) + (net datain9 + (joined + (portRef (member Data 9)) + (portRef DI9 (instanceRef pdp_ram_0_0_0)))) + (net datain8 + (joined + (portRef (member Data 10)) + (portRef DI8 (instanceRef pdp_ram_0_0_0)))) + (net datain7 + (joined + (portRef (member Data 11)) + (portRef DI7 (instanceRef pdp_ram_0_0_0)))) + (net datain6 + (joined + (portRef (member Data 12)) + (portRef DI6 (instanceRef pdp_ram_0_0_0)))) + (net datain5 + (joined + (portRef (member Data 13)) + (portRef DI5 (instanceRef pdp_ram_0_0_0)))) + (net datain4 + (joined + (portRef (member Data 14)) + (portRef DI4 (instanceRef pdp_ram_0_0_0)))) + (net datain3 + (joined + (portRef (member Data 15)) + (portRef DI3 (instanceRef pdp_ram_0_0_0)))) + (net datain2 + (joined + (portRef (member Data 16)) + (portRef DI2 (instanceRef pdp_ram_0_0_0)))) + (net datain1 + (joined + (portRef (member Data 17)) + (portRef DI1 (instanceRef pdp_ram_0_0_0)))) + (net datain0 + (joined + (portRef (member Data 18)) + (portRef DI0 (instanceRef pdp_ram_0_0_0)))))))) + (design fifo_19x16_obuf + (cellRef fifo_19x16_obuf + (libraryRef ORCLIB))) +) diff --git a/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.fdc b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.lpc b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.lpc new file mode 100644 index 0000000..1fd71eb --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8MG285C +SpeedGrade=8 +Package=CSFBGA285 +OperatingCondition=COM +Status=C + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.0 +ModuleName=fifo_19x16_obuf +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/20/2015 +Time=10:49:00 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=16 +Width=19 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Dynamic - Single Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=13 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=1 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_19x16_obuf -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 16 -width 19 -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill diff --git a/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.ngd b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.ngd new file mode 100644 index 0000000..a0ee205 Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.ngd differ diff --git a/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.ngo b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.ngo new file mode 100644 index 0000000..3d29cb2 Binary files /dev/null and b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.ngo differ diff --git a/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd new file mode 100644 index 0000000..af5ce56 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd @@ -0,0 +1,633 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.0 +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_19x16_obuf -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 16 -width 19 -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.fdc + +-- Fri Mar 20 10:49:02 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity fifo_19x16_obuf is + port ( + Data: in std_logic_vector(18 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + AmFullThresh: in std_logic_vector(3 downto 0); + Q: out std_logic_vector(18 downto 0); + WCNT: out std_logic_vector(4 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_19x16_obuf; + +architecture Structure of fifo_19x16_obuf is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal rptr_4: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal co2: std_logic; + signal co1: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_4: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal co2_1: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal co2_2: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal wcnt_sub_0: std_logic; + signal rptr_0: std_logic; + signal cnt_con_inv: std_logic; + signal wcount_0: std_logic; + signal cnt_con: std_logic; + signal precin: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; + signal rptr_2: std_logic; + signal rptr_1: std_logic; + signal wcount_2: std_logic; + signal wcount_1: std_logic; + signal co0_5: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; + signal rptr_3: std_logic; + signal wcnt_sub_msb: std_logic; + signal wcount_3: std_logic; + signal co1_5: std_logic; + signal co2_3d: std_logic; + signal co2_3: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; + signal co0_6: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; + signal co1_6: std_logic; + signal wcnt_reg_4: std_logic; + signal af_set: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal af_set_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_19x16_obuf.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t5: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_5: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t4: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_4: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t3: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t2: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_3: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_2: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t1: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_1: INV + port map (A=>wren_i, Z=>invout_0); + + XOR2_t0: XOR2 + port map (A=>wcount_4, B=>rptr_4, Z=>wcnt_sub_msb); + + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + pdp_ram_0_0_0: PDPW16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "ENABLED", + RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36, + DATA_WIDTH_W=> 36) + port map (DI35=>scuba_vlo, DI34=>scuba_vlo, DI33=>scuba_vlo, + DI32=>scuba_vlo, DI31=>scuba_vlo, DI30=>scuba_vlo, + DI29=>scuba_vlo, DI28=>scuba_vlo, DI27=>scuba_vlo, + DI26=>scuba_vlo, DI25=>scuba_vlo, DI24=>scuba_vlo, + DI23=>scuba_vlo, DI22=>scuba_vlo, DI21=>scuba_vlo, + DI20=>scuba_vlo, DI19=>scuba_vlo, DI18=>Data(18), + DI17=>Data(17), DI16=>Data(16), DI15=>Data(15), + DI14=>Data(14), DI13=>Data(13), DI12=>Data(12), + DI11=>Data(11), DI10=>Data(10), DI9=>Data(9), DI8=>Data(8), + DI7=>Data(7), DI6=>Data(6), DI5=>Data(5), DI4=>Data(4), + DI3=>Data(3), DI2=>Data(2), DI1=>Data(1), DI0=>Data(0), + ADW8=>scuba_vlo, ADW7=>scuba_vlo, ADW6=>scuba_vlo, + ADW5=>scuba_vlo, ADW4=>scuba_vlo, ADW3=>wptr_3, ADW2=>wptr_2, + ADW1=>wptr_1, ADW0=>wptr_0, BE3=>scuba_vhi, BE2=>scuba_vhi, + BE1=>scuba_vhi, BE0=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, + CSW2=>scuba_vlo, CSW1=>scuba_vlo, CSW0=>scuba_vhi, + ADR13=>scuba_vlo, ADR12=>scuba_vlo, ADR11=>scuba_vlo, + ADR10=>scuba_vlo, ADR9=>scuba_vlo, ADR8=>rptr_3, + ADR7=>rptr_2, ADR6=>rptr_1, ADR5=>rptr_0, ADR4=>scuba_vlo, + ADR3=>scuba_vlo, ADR2=>scuba_vlo, ADR1=>scuba_vlo, + ADR0=>scuba_vlo, CER=>rden_i, OCER=>rden_i, CLKR=>Clock, + CSR2=>scuba_vlo, CSR1=>scuba_vlo, CSR0=>scuba_vlo, + RST=>Reset, DO35=>Q(17), DO34=>Q(16), DO33=>Q(15), + DO32=>Q(14), DO31=>Q(13), DO30=>Q(12), DO29=>Q(11), + DO28=>Q(10), DO27=>Q(9), DO26=>Q(8), DO25=>Q(7), DO24=>Q(6), + DO23=>Q(5), DO22=>Q(4), DO21=>Q(3), DO20=>Q(2), DO19=>Q(1), + DO18=>Q(0), DO17=>open, DO16=>open, DO15=>open, DO14=>open, + DO13=>open, DO12=>open, DO11=>open, DO10=>open, DO9=>open, + DO8=>open, DO7=>open, DO6=>open, DO5=>open, DO4=>open, + DO3=>open, DO2=>open, DO1=>open, DO0=>Q(18)); + + FF_32: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_31: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_30: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_29: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_28: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_27: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_26: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_25: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + Q=>wcount_0); + + FF_24: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_23: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_22: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_21: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_20: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + Q=>rcount_0); + + FF_19: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_18: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_17: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_16: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_15: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_14: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_13: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_12: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_11: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_10: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_9: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_8: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_7: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_6: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_5: FD1S3DX + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_4: FD1S3DX + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_3: FD1S3DX + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_2: FD1S3DX + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_1: FD1S3DX + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>open, COUT=>co2); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_2, S0=>open, S1=>open, + COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>open, + COUT=>co2_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>open, + COUT=>co2_2); + + precin_inst137: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>precin, S0=>open, S1=>wcnt_sub_0, COUT=>co0_5); + + wcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2, COUT=>co1_5); + + wcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_3, A1=>wcnt_sub_msb, B0=>rptr_3, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4, + COUT=>co2_3); + + wcntd: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>co2_3d, S1=>open, COUT=>open); + + af_set_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_set_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, + S1=>open, COUT=>co0_6); + + af_set_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, + COUT=>co1_6); + + af_set_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, + COUT=>af_set_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_set_c, S0=>af_set, S1=>open, + COUT=>open); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf_ngd.asd b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.cst index 0fafcfe..26cc42c 100644 --- a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.cst +++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.cst @@ -1,3 +1,3 @@ -Date=03/18/2015 -Time=14:42:06 +Date=03/20/2015 +Time=11:40:01 diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.edn index f9adae0..9be3308 100644 --- a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.edn +++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.edn @@ -4,9 +4,9 @@ (keywordMap (keywordLevel 0)) (status (written - (timestamp 2015 3 18 14 42 8) + (timestamp 2015 3 20 11 40 3) (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) - (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x16k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 16384 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.fdc ") + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x16k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 16384 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.fdc ") (library ORCLIB (edifLevel 0) (technology diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.lpc index 0b5cbed..7ad390b 100644 --- a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.lpc +++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.lpc @@ -16,8 +16,8 @@ CoreRevision=5.0 ModuleName=fifo_36x16k_oreg SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/18/2015 -Time=14:42:06 +Date=03/20/2015 +Time=11:40:01 [Parameters] Verilog=0 diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.ngd index 46e0192..b51db87 100644 Binary files a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.ngd and b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.ngd differ diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.ngo b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.ngo index cbb3015..845c088 100644 Binary files a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.ngo and b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.ngo differ diff --git a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd index ab8fb13..4118aad 100644 --- a/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd +++ b/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 -- Module Version: 5.0 ---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x16k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 16384 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.fdc +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x16k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 16384 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.fdc --- Wed Mar 18 14:42:08 2015 +-- Fri Mar 20 11:40:03 2015 library IEEE; use IEEE.std_logic_1164.all; diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.cst index e2ce71a..ff669ea 100644 --- a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.cst +++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.cst @@ -1,3 +1,3 @@ -Date=03/18/2015 -Time=14:40:46 +Date=03/20/2015 +Time=11:39:06 diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.edn index a1e46fb..f8de5ea 100644 --- a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.edn +++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.edn @@ -4,9 +4,9 @@ (keywordMap (keywordLevel 0)) (status (written - (timestamp 2015 3 18 14 40 48) + (timestamp 2015 3 20 11 39 7) (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) - (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.fdc ") + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.fdc ") (library ORCLIB (edifLevel 0) (technology diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.lpc index 2dc804f..3518fc7 100644 --- a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.lpc +++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.lpc @@ -16,8 +16,8 @@ CoreRevision=5.0 ModuleName=fifo_36x1k_oreg SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/18/2015 -Time=14:40:46 +Date=03/20/2015 +Time=11:39:06 [Parameters] Verilog=0 diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngd index f9997bb..6d510d1 100644 Binary files a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngd and b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngd differ diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngo b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngo index f5480a0..b556a25 100644 Binary files a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngo and b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.ngo differ diff --git a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd index d861fe0..9ac63ab 100644 --- a/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd +++ b/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 -- Module Version: 5.0 ---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.fdc +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.fdc --- Wed Mar 18 14:40:48 2015 +-- Fri Mar 20 11:39:07 2015 library IEEE; use IEEE.std_logic_1164.all; diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.cst index 644f757..0614fb8 100644 --- a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.cst +++ b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.cst @@ -1,3 +1,3 @@ -Date=03/18/2015 -Time=14:41:09 +Date=03/20/2015 +Time=11:39:22 diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.edn index 7dc903a..26ba253 100644 --- a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.edn +++ b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.edn @@ -4,9 +4,9 @@ (keywordMap (keywordLevel 0)) (status (written - (timestamp 2015 3 18 14 41 11) + (timestamp 2015 3 20 11 39 23) (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) - (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.fdc ") + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.fdc ") (library ORCLIB (edifLevel 0) (technology diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.lpc index 9a49b8d..d12b80e 100644 --- a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.lpc +++ b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.lpc @@ -16,8 +16,8 @@ CoreRevision=5.0 ModuleName=fifo_36x2k_oreg SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/18/2015 -Time=14:41:09 +Date=03/20/2015 +Time=11:39:22 [Parameters] Verilog=0 diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngd index 7e0061e..395e133 100644 Binary files a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngd and b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngd differ diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngo b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngo index db3ed08..3a46a29 100644 Binary files a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngo and b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.ngo differ diff --git a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd index f8f1bfe..569c979 100644 --- a/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd +++ b/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 -- Module Version: 5.0 ---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.fdc +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 2048 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.fdc --- Wed Mar 18 14:41:11 2015 +-- Fri Mar 20 11:39:23 2015 library IEEE; use IEEE.std_logic_1164.all; diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.cst index 318c0e9..76e8864 100644 --- a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.cst +++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.cst @@ -1,3 +1,3 @@ -Date=03/18/2015 -Time=14:42:29 +Date=03/20/2015 +Time=11:40:22 diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.edn index c7477aa..d356664 100644 --- a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.edn +++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.edn @@ -4,9 +4,9 @@ (keywordMap (keywordLevel 0)) (status (written - (timestamp 2015 3 18 14 42 30) + (timestamp 2015 3 20 11 40 23) (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) - (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x32k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 32768 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.fdc ") + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x32k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 32768 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.fdc ") (library ORCLIB (edifLevel 0) (technology diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.lpc index 6a11f2a..cb959e0 100644 --- a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.lpc +++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.lpc @@ -16,8 +16,8 @@ CoreRevision=5.0 ModuleName=fifo_36x32k_oreg SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/18/2015 -Time=14:42:29 +Date=03/20/2015 +Time=11:40:22 [Parameters] Verilog=0 diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngd index 2c537bd..fb465d7 100644 Binary files a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngd and b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngd differ diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngo b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngo index 24133b2..91d39eb 100644 Binary files a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngo and b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.ngo differ diff --git a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd index 481cbdb..d98c841 100644 --- a/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd +++ b/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 -- Module Version: 5.0 ---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x32k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 32768 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.fdc +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x32k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 32768 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.fdc --- Wed Mar 18 14:42:30 2015 +-- Fri Mar 20 11:40:23 2015 library IEEE; use IEEE.std_logic_1164.all; diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.cst index 4204e1d..3b44fe7 100644 --- a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.cst +++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.cst @@ -1,3 +1,3 @@ -Date=03/18/2015 -Time=14:41:29 +Date=03/20/2015 +Time=11:39:33 diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.edn index 8bd1ced..206caf5 100644 --- a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.edn +++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.edn @@ -4,9 +4,9 @@ (keywordMap (keywordLevel 0)) (status (written - (timestamp 2015 3 18 14 41 31) + (timestamp 2015 3 20 11 39 36) (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) - (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x4k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 4096 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.fdc ") + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x4k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 4096 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.fdc ") (library ORCLIB (edifLevel 0) (technology diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.lpc index 86d40cd..2355028 100644 --- a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.lpc +++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.lpc @@ -16,8 +16,8 @@ CoreRevision=5.0 ModuleName=fifo_36x4k_oreg SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/18/2015 -Time=14:41:29 +Date=03/20/2015 +Time=11:39:33 [Parameters] Verilog=0 diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngd index 0d6ed61..541ceab 100644 Binary files a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngd and b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngd differ diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngo b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngo index 6df561d..afd7d37 100644 Binary files a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngo and b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.ngo differ diff --git a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd index bbb25a5..804c70c 100644 --- a/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd +++ b/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 -- Module Version: 5.0 ---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x4k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 4096 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.fdc +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x4k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 4096 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.fdc --- Wed Mar 18 14:41:31 2015 +-- Fri Mar 20 11:39:36 2015 library IEEE; use IEEE.std_logic_1164.all; diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.cst b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.cst index 5adc24e..1b6ba7d 100644 --- a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.cst +++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.cst @@ -1,3 +1,3 @@ -Date=03/18/2015 -Time=14:40:02 +Date=03/20/2015 +Time=11:40:56 diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.edn b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.edn index f005697..007172b 100644 --- a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.edn +++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.edn @@ -4,9 +4,9 @@ (keywordMap (keywordLevel 0)) (status (written - (timestamp 2015 3 18 14 40 4) + (timestamp 2015 3 20 11 40 58) (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) - (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.fdc ") + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.fdc ") (library ORCLIB (edifLevel 0) (technology diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.lpc index c0b44aa..0a5b386 100644 --- a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.lpc +++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.lpc @@ -16,8 +16,8 @@ CoreRevision=5.0 ModuleName=fifo_36x512_oreg SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/18/2015 -Time=14:40:02 +Date=03/20/2015 +Time=11:40:56 [Parameters] Verilog=0 diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.ngd index 22ea4f0..58aaf19 100644 Binary files a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.ngd and b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.ngd differ diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.ngo b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.ngo index 5360acc..1d1ab71 100644 Binary files a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.ngo and b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.ngo differ diff --git a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd index c76aa9d..aadf408 100644 --- a/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd +++ b/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 -- Module Version: 5.0 ---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.fdc +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 512 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.fdc --- Wed Mar 18 14:40:04 2015 +-- Fri Mar 20 11:40:58 2015 library IEEE; use IEEE.std_logic_1164.all; diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.cst b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.cst index a9a39ca..37e46fe 100644 --- a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.cst +++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.cst @@ -1,3 +1,3 @@ -Date=03/18/2015 -Time=14:41:45 +Date=03/20/2015 +Time=11:39:45 diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.edn b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.edn index 9a9857b..7223997 100644 --- a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.edn +++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.edn @@ -4,9 +4,9 @@ (keywordMap (keywordLevel 0)) (status (written - (timestamp 2015 3 18 14 41 46) + (timestamp 2015 3 20 11 39 47) (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) - (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x8k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 8192 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.fdc ") + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x8k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 8192 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.fdc ") (library ORCLIB (edifLevel 0) (technology diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.lpc b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.lpc index eac07d5..03671d9 100644 --- a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.lpc +++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.lpc @@ -16,8 +16,8 @@ CoreRevision=5.0 ModuleName=fifo_36x8k_oreg SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/18/2015 -Time=14:41:45 +Date=03/20/2015 +Time=11:39:45 [Parameters] Verilog=0 diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngd b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngd index ff7f458..62cc0c2 100644 Binary files a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngd and b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngd differ diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngo b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngo index 3d987c6..ef7f196 100644 Binary files a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngo and b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.ngo differ diff --git a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd index d5a618c..94f6126 100644 --- a/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd +++ b/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 -- Module Version: 5.0 ---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x8k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 8192 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.fdc +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n fifo_36x8k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 8192 -width 36 -regout -no_enable -pe -1 -pf 0 -reset_rel SYNC -fill -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.fdc --- Wed Mar 18 14:41:46 2015 +-- Fri Mar 20 11:39:47 2015 library IEEE; use IEEE.std_logic_1164.all; diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp3_fifo_18x1k.lpc b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp3_fifo_18x1k.lpc new file mode 100644 index 0000000..ef5cc11 --- /dev/null +++ b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp3_fifo_18x1k.lpc @@ -0,0 +1,45 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-6FN1156C +SpeedGrade=6 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=4.8 +ModuleName=lattice_ecp3_fifo_18x1k +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/13/2011 +Time=10:20:31 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=1024 +Width=18 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Single Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=1020 +PfDeassert=506 +RDataCount=0 +EnECC=0 +EnFWFT=0 diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.cst b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.cst new file mode 100644 index 0000000..1181bf1 --- /dev/null +++ b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.cst @@ -0,0 +1,3 @@ +Date=03/20/2015 +Time=10:58:50 + diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.edn b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.edn new file mode 100644 index 0000000..edcd6d7 --- /dev/null +++ b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.edn @@ -0,0 +1,2365 @@ +(edif lattice_ecp5_fifo_18x1k + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 3 20 10 58 53) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n lattice_ecp5_fifo_18x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 18 -no_enable -pe -1 -pf 1020 -reset_rel SYNC -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.fdc ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell CCU2C + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT)) + (port A1 + (direction INPUT)) + (port B0 + (direction INPUT)) + (port B1 + (direction INPUT)) + (port C0 + (direction INPUT)) + (port C1 + (direction INPUT)) + (port D0 + (direction INPUT)) + (port D1 + (direction INPUT)) + (port CIN + (direction INPUT)) + (port S0 + (direction OUTPUT)) + (port S1 + (direction OUTPUT)) + (port COUT + (direction OUTPUT))))) + (cell AND2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell FD1P3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port SP + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3BX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port PD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell FD1S3DX + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port D + (direction INPUT)) + (port CK + (direction INPUT)) + (port CD + (direction INPUT)) + (port Q + (direction OUTPUT))))) + (cell INV + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell ROM16X1A + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port AD3 + (direction INPUT)) + (port AD2 + (direction INPUT)) + (port AD1 + (direction INPUT)) + (port AD0 + (direction INPUT)) + (port DO0 + (direction OUTPUT))))) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell XOR2 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port A + (direction INPUT)) + (port B + (direction INPUT)) + (port Z + (direction OUTPUT))))) + (cell DP16KD + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA17 + (direction INPUT)) + (port DIA16 + (direction INPUT)) + (port DIA15 + (direction INPUT)) + (port DIA14 + (direction INPUT)) + (port DIA13 + (direction INPUT)) + (port DIA12 + (direction INPUT)) + (port DIA11 + (direction INPUT)) + (port DIA10 + (direction INPUT)) + (port DIA9 + (direction INPUT)) + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction INPUT)) + (port DIA6 + (direction INPUT)) + (port DIA5 + (direction INPUT)) + (port DIA4 + (direction INPUT)) + (port DIA3 + (direction INPUT)) + (port DIA2 + (direction INPUT)) + (port DIA1 + (direction INPUT)) + (port DIA0 + (direction INPUT)) + (port ADA13 + (direction INPUT)) + (port ADA12 + (direction INPUT)) + (port ADA11 + (direction INPUT)) + (port ADA10 + (direction INPUT)) + (port ADA9 + (direction INPUT)) + (port ADA8 + (direction INPUT)) + (port ADA7 + (direction INPUT)) + (port ADA6 + (direction INPUT)) + (port ADA5 + (direction INPUT)) + (port ADA4 + (direction INPUT)) + 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(design lattice_ecp5_fifo_18x1k + (cellRef lattice_ecp5_fifo_18x1k + (libraryRef ORCLIB))) +) diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.fdc b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.lpc b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.lpc new file mode 100644 index 0000000..4ca1435 --- /dev/null +++ b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.lpc @@ -0,0 +1,50 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8MG285C +SpeedGrade=8 +Package=CSFBGA285 +OperatingCondition=COM +Status=C + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.0 +ModuleName=lattice_ecp5_fifo_18x1k +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/20/2015 +Time=10:58:50 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=1024 +Width=18 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Single Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=1020 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=0 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n lattice_ecp5_fifo_18x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 18 -no_enable -pe -1 -pf 1020 -reset_rel SYNC diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.ngd b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.ngd new file mode 100644 index 0000000..36938bc Binary files /dev/null and b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.ngd differ diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.ngo b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.ngo new file mode 100644 index 0000000..c48ba2b Binary files /dev/null and b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.ngo differ diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd new file mode 100644 index 0000000..3e4db05 --- /dev/null +++ b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd @@ -0,0 +1,781 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 5.0 +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n lattice_ecp5_fifo_18x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 1024 -width 18 -no_enable -pe -1 -pf 1020 -reset_rel SYNC -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.fdc + +-- Fri Mar 20 10:58:53 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity lattice_ecp5_fifo_18x1k is + port ( + Data: in std_logic_vector(17 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end lattice_ecp5_fifo_18x1k; + +architecture Structure of lattice_ecp5_fifo_18x1k is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw_inv: std_logic; + signal r_nw: std_logic; + signal fcnt_en_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co3: std_logic; + signal ifcount_10: std_logic; + signal co5: std_logic; + signal co4: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal co4_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal co0_2: std_logic; + signal co1_2: std_logic; + signal co2_2: std_logic; + signal co3_2: std_logic; + signal wren_i: std_logic; + signal co4_2: std_logic; + signal wren_i_inv: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2_3: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3_3: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal iwcount_10: std_logic; + signal co5_1: std_logic; + signal co4_3: std_logic; + signal wcount_10: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_4: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_4: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal ircount_10: std_logic; + signal co5_2: std_logic; + signal co4_4: std_logic; + signal rcount_10: std_logic; + signal cmp_ci_2: std_logic; + signal fcnt_en_inv_inv: std_logic; + signal cnt_con: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_5: std_logic; + signal cnt_con_inv: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_5: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_5: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_5: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; + signal co4_5: std_logic; + signal fcount_10: std_logic; + signal af_d: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal af_d_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "lattice_ecp5_fifo_18x1k.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t4: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_8: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t3: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_7: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t1: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_6: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_5: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + AND2_t0: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_4: INV + port map (A=>wren_i, Z=>invout_0); + + INV_3: INV + port map (A=>fcnt_en, Z=>fcnt_en_inv); + + INV_2: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + INV_1: INV + port map (A=>r_nw, Z=>r_nw_inv); + + INV_0: INV + port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv); + + pdp_ram_0_0_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wcount_9, ADA12=>wcount_8, + ADA11=>wcount_7, ADA10=>wcount_6, ADA9=>wcount_5, + ADA8=>wcount_4, ADA7=>wcount_3, ADA6=>wcount_2, + ADA5=>wcount_1, ADA4=>wcount_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rcount_9, ADB12=>rcount_8, + ADB11=>rcount_7, ADB10=>rcount_6, ADB9=>rcount_5, + ADB8=>rcount_4, ADB7=>rcount_3, ADB6=>rcount_2, + ADB5=>rcount_1, ADB4=>rcount_0, ADB3=>scuba_vlo, + ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vlo, + CEB=>rden_i, OCEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>Q(17), DOB16=>Q(16), DOB15=>Q(15), + DOB14=>Q(14), DOB13=>Q(13), DOB12=>Q(12), DOB11=>Q(11), + DOB10=>Q(10), DOB9=>Q(9), DOB8=>Q(8), DOB7=>Q(7), DOB6=>Q(6), + DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3), DOB2=>Q(2), DOB1=>Q(1), + DOB0=>Q(0)); + + FF_35: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_34: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_33: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_32: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_31: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_30: FD1P3DX + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_29: FD1P3DX + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_28: FD1P3DX + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_27: FD1P3DX + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_26: FD1P3DX + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_25: FD1P3DX + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_24: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_23: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_22: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_21: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_20: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_19: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_18: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_17: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_16: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_15: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_14: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_13: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_12: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_11: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_10: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_9: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_8: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_7: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_6: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_5: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_4: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_3: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_2: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_1: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>bdcnt_bctr_ci); + + bdcnt_bctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>bdcnt_bctr_ci, S0=>ifcount_0, S1=>ifcount_1, COUT=>co0); + + bdcnt_bctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0, S0=>ifcount_2, S1=>ifcount_3, COUT=>co1); + + bdcnt_bctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1, S0=>ifcount_4, S1=>ifcount_5, COUT=>co2); + + bdcnt_bctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2, S0=>ifcount_6, S1=>ifcount_7, COUT=>co3); + + bdcnt_bctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3, S0=>ifcount_8, S1=>ifcount_9, COUT=>co4); + + bdcnt_bctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>scuba_vlo, B0=>cnt_con, B1=>cnt_con, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co4, S0=>ifcount_10, S1=>open, COUT=>co5); + + e_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + e_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rden_i, A1=>scuba_vlo, B0=>fcount_0, B1=>fcount_1, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_1); + + e_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_2, + B1=>fcount_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>open, S1=>open, COUT=>co1_1); + + e_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_4, + B1=>fcount_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>open, S1=>open, COUT=>co2_1); + + e_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_6, + B1=>fcount_7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>open, S1=>open, COUT=>co3_1); + + e_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_8, + B1=>fcount_9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>open, S1=>open, COUT=>co4_1); + + e_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>fcount_10, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_1, S0=>open, S1=>open, + COUT=>cmp_le_1_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_le_1_c, S0=>cmp_le_1, S1=>open, + COUT=>open); + + g_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + g_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>cmp_ci_1, S0=>open, S1=>open, COUT=>co0_2); + + g_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + g_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + g_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_2, S0=>open, S1=>open, COUT=>co3_2); + + g_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2); + + g_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_2, S0=>open, S1=>open, + COUT=>cmp_ge_d1_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ge_d1_c, S0=>cmp_ge_d1, S1=>open, + COUT=>open); + + w_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_ctr_ci); + + w_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_ctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0_3); + + w_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1_3); + + w_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2_3); + + w_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3_3); + + w_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4_3); + + w_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_10, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_3, S0=>iwcount_10, S1=>open, + COUT=>co5_1); + + r_ctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_ctr_ci); + + r_ctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_ctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_4); + + r_ctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_4); + + r_ctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_4); + + r_ctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_4); + + r_ctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_4, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_4); + + r_ctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_10, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_4, S0=>ircount_10, S1=>open, + COUT=>co5_2); + + af_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + af_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, S1=>open, + COUT=>co0_5); + + af_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con_inv, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_5, S0=>open, S1=>open, COUT=>co1_5); + + af_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_5, S0=>open, S1=>open, COUT=>co2_5); + + af_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_5, S0=>open, S1=>open, COUT=>co3_5); + + af_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_5, S0=>open, S1=>open, COUT=>co4_5); + + af_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_5, S0=>open, S1=>open, COUT=>af_d_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_d_c, S0=>af_d, S1=>open, COUT=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k_ngd.asd b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/lattice/ecp5/RAM/RAM.sbx b/lattice/ecp5/RAM/RAM.sbx new file mode 100644 index 0000000..a364f67 --- /dev/null +++ b/lattice/ecp5/RAM/RAM.sbx @@ -0,0 +1,1285 @@ + + + + LATTICE + LOCAL + RAM + 1.0 + + + Diamond_Synthesis + synthesis + + + Diamond_Simulation + simulation + + + + + + + + spi_dpram_32_to_8_ClockA + spi_dpram_32_to_8_ClockA + + in + + + + spi_dpram_32_to_8.ClockA + + + + + spi_dpram_32_to_8_ClockB + spi_dpram_32_to_8_ClockB + + in + + + + spi_dpram_32_to_8.ClockB + + + + + spi_dpram_32_to_8_ClockEnA + spi_dpram_32_to_8_ClockEnA + + in + + + + spi_dpram_32_to_8.ClockEnA + + + + + spi_dpram_32_to_8_ClockEnB + spi_dpram_32_to_8_ClockEnB + + in + + + + spi_dpram_32_to_8.ClockEnB + + + + + spi_dpram_32_to_8_ResetA + spi_dpram_32_to_8_ResetA + + in + + + + spi_dpram_32_to_8.ResetA + + + + + spi_dpram_32_to_8_ResetB + spi_dpram_32_to_8_ResetB + + in + + + + spi_dpram_32_to_8.ResetB + + + + + spi_dpram_32_to_8_WrA + spi_dpram_32_to_8_WrA + + in + + + + spi_dpram_32_to_8.WrA + + + + + spi_dpram_32_to_8_WrB + spi_dpram_32_to_8_WrB + + in + + + + spi_dpram_32_to_8.WrB + + + + + spi_dpram_32_to_8_AddressA + spi_dpram_32_to_8_AddressA + + in + + 5 + 0 + + + + + spi_dpram_32_to_8.AddressA + + + + + spi_dpram_32_to_8_AddressB + spi_dpram_32_to_8_AddressB + + in + + 7 + 0 + + + + + spi_dpram_32_to_8.AddressB + + + + + spi_dpram_32_to_8_DataInA + spi_dpram_32_to_8_DataInA + + in + + 31 + 0 + + + + + spi_dpram_32_to_8.DataInA + + + + + spi_dpram_32_to_8_DataInB + spi_dpram_32_to_8_DataInB + + in + + 7 + 0 + + + + + spi_dpram_32_to_8.DataInB + + + + + spi_dpram_32_to_8_QA + spi_dpram_32_to_8_QA + + out + + 31 + 0 + + + + + spi_dpram_32_to_8.QA + + + + + spi_dpram_32_to_8_QB + spi_dpram_32_to_8_QB + + out + + 7 + 0 + + + + + spi_dpram_32_to_8.QB + + + + + + + LFE5UM-85F-8MG285C + synplify + 2015-03-20.14:56:52 + 2015-03-20.15:25:17 + 3.4.0.80 + VHDL + + true + false + false + true + false + false + false + false + false + false + true + + + + + + + + LATTICE + LOCAL + RAM + 1.0 + + + spi_dpram_32_to_8 + + Lattice Semiconductor Corporation + LEGACY + RAM_DP_TRUE + 7.4 + + + Diamond_Simulation + simulation + + ./spi_dpram_32_to_8/spi_dpram_32_to_8.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./spi_dpram_32_to_8/spi_dpram_32_to_8.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/${instance}/generate_core.tcl + CONFIG + + + CreateNGD + none + ${sbp_path}/${instance}/generate_ngd.tcl + CONFIG + + + + + + + ClockA + ClockA + + in + + + + ClockB + ClockB + + in + + + + ClockEnA + ClockEnA + + in + + + + ClockEnB + ClockEnB + + in + + + + ResetA + ResetA + + in + + + + ResetB + ResetB + + in + + + + WrA + WrA + + in + + + + WrB + WrB + + in + + + + AddressA + AddressA + + in + + 5 + 0 + + + + + AddressB + AddressB + + in + + 7 + 0 + + + + + DataInA + DataInA + + in + + 31 + 0 + + + + + DataInB + DataInB + + in + + 7 + 0 + + + + + QA + QA + + out + + 31 + 0 + + + + + QB + QB + + out + + 7 + 0 + + + + + + + synplify + 2015-03-20.15:25:17 + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CSFBGA285 + + + PartName + LFE5UM-85F-8MG285C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + C + + + + CoreName + RAM_DP_TRUE + + + CoreRevision + 7.4 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 03/20/2015 + + + ModuleName + spi_dpram_32_to_8 + + + ParameterFileVersion + 1.0 + + + SourceFormat + VHDL + + + Time + 15:23:04 + + + VendorName + Lattice Semiconductor Corporation + + + + ByteSize + 9 + + + Destination + Synplicity + + + EDIF + 1 + + + EnECC + 0 + + + Expression + BusA(0 to 7) + + + IO + 0 + + + Init + 0 + + + MemFile + + + + MemFormat + bin + + + Optimization + Speed + + + Order + Big Endian [MSB:LSB] + + + Pipeline + 0 + + + RAddress + 64 + + + RClockEn + 0 + + + RData + 32 + + + ROutputEn + 1 + + + Reset + Sync + + + Reset1 + Sync + + + VHDL + 1 + + + Verilog + 0 + + + WAddress + 256 + + + WClockEn + 0 + + + WData + 8 + + + WOutputEn + 1 + + + WriteA + Normal + + + WriteB + Normal + + + enByte + 0 + + + init_data + 0 + + + + + mem + + + + cmd_line + -w -n spi_dpram_32_to_8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ramdp -device LFE5UM-85F -aaddr_width 6 -widtha 32 -baddr_width 8 -widthb 8 -anum_words 64 -bnum_words 256 -outdataA REGISTERED -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -mem_init0 -writemodeA NORMAL -writemodeB NORMAL + + + + + + + + + + spi_dpram_32_to_8_ClockA + spi_dpram_32_to_8_ClockA + + + + + spi_dpram_32_to_8_ClockB + spi_dpram_32_to_8_ClockB + + + + + spi_dpram_32_to_8_ClockEnA + spi_dpram_32_to_8_ClockEnA + + + + + spi_dpram_32_to_8_ClockEnB + spi_dpram_32_to_8_ClockEnB + + + + + spi_dpram_32_to_8_ResetA + spi_dpram_32_to_8_ResetA + + + + + spi_dpram_32_to_8_ResetB + spi_dpram_32_to_8_ResetB + + + + + spi_dpram_32_to_8_WrA + spi_dpram_32_to_8_WrA + + + + + spi_dpram_32_to_8_WrB + spi_dpram_32_to_8_WrB + + + + + spi_dpram_32_to_8_AddressA + spi_dpram_32_to_8_AddressA + + + + + spi_dpram_32_to_8_AddressA[0] + spi_dpram_32_to_8_AddressA[0] + + + + + spi_dpram_32_to_8_AddressA[1] + spi_dpram_32_to_8_AddressA[1] + + + + + spi_dpram_32_to_8_AddressA[2] + spi_dpram_32_to_8_AddressA[2] + + + + + spi_dpram_32_to_8_AddressA[3] + spi_dpram_32_to_8_AddressA[3] + + + + + spi_dpram_32_to_8_AddressA[4] + spi_dpram_32_to_8_AddressA[4] + + + + + spi_dpram_32_to_8_AddressA[5] + spi_dpram_32_to_8_AddressA[5] + + + + + spi_dpram_32_to_8_AddressB + spi_dpram_32_to_8_AddressB + + + + + spi_dpram_32_to_8_AddressB[0] + spi_dpram_32_to_8_AddressB[0] + + + + + spi_dpram_32_to_8_AddressB[1] + spi_dpram_32_to_8_AddressB[1] + + + + + spi_dpram_32_to_8_AddressB[2] + spi_dpram_32_to_8_AddressB[2] + + + + + spi_dpram_32_to_8_AddressB[3] + spi_dpram_32_to_8_AddressB[3] + + + + + spi_dpram_32_to_8_AddressB[4] + spi_dpram_32_to_8_AddressB[4] + + + + + spi_dpram_32_to_8_AddressB[5] + spi_dpram_32_to_8_AddressB[5] + + + + + spi_dpram_32_to_8_AddressB[6] + spi_dpram_32_to_8_AddressB[6] + + + + + spi_dpram_32_to_8_AddressB[7] + spi_dpram_32_to_8_AddressB[7] + + + + + spi_dpram_32_to_8_DataInA + spi_dpram_32_to_8_DataInA + + + + + spi_dpram_32_to_8_DataInA[0] + spi_dpram_32_to_8_DataInA[0] + + + + + spi_dpram_32_to_8_DataInA[10] + spi_dpram_32_to_8_DataInA[10] + + + + + spi_dpram_32_to_8_DataInA[11] + spi_dpram_32_to_8_DataInA[11] + + + + + spi_dpram_32_to_8_DataInA[12] + spi_dpram_32_to_8_DataInA[12] + + + + + spi_dpram_32_to_8_DataInA[13] + spi_dpram_32_to_8_DataInA[13] + + + + + spi_dpram_32_to_8_DataInA[14] + spi_dpram_32_to_8_DataInA[14] + + + + + spi_dpram_32_to_8_DataInA[15] + spi_dpram_32_to_8_DataInA[15] + + + + + spi_dpram_32_to_8_DataInA[16] + spi_dpram_32_to_8_DataInA[16] + + + + + spi_dpram_32_to_8_DataInA[17] + spi_dpram_32_to_8_DataInA[17] + + + + + spi_dpram_32_to_8_DataInA[18] + spi_dpram_32_to_8_DataInA[18] + + + + + spi_dpram_32_to_8_DataInA[19] + spi_dpram_32_to_8_DataInA[19] + + + + + spi_dpram_32_to_8_DataInA[1] + spi_dpram_32_to_8_DataInA[1] + + + + + spi_dpram_32_to_8_DataInA[20] + spi_dpram_32_to_8_DataInA[20] + + + + + spi_dpram_32_to_8_DataInA[21] + spi_dpram_32_to_8_DataInA[21] + + + + + spi_dpram_32_to_8_DataInA[22] + spi_dpram_32_to_8_DataInA[22] + + + + + spi_dpram_32_to_8_DataInA[23] + spi_dpram_32_to_8_DataInA[23] + + + + + spi_dpram_32_to_8_DataInA[24] + spi_dpram_32_to_8_DataInA[24] + + + + + spi_dpram_32_to_8_DataInA[25] + spi_dpram_32_to_8_DataInA[25] + + + + + spi_dpram_32_to_8_DataInA[26] + spi_dpram_32_to_8_DataInA[26] + + + + + spi_dpram_32_to_8_DataInA[27] + spi_dpram_32_to_8_DataInA[27] + + + + + spi_dpram_32_to_8_DataInA[28] + spi_dpram_32_to_8_DataInA[28] + + + + + spi_dpram_32_to_8_DataInA[29] + spi_dpram_32_to_8_DataInA[29] + + + + + spi_dpram_32_to_8_DataInA[2] + spi_dpram_32_to_8_DataInA[2] + + + + + spi_dpram_32_to_8_DataInA[30] + spi_dpram_32_to_8_DataInA[30] + + + + + spi_dpram_32_to_8_DataInA[31] + spi_dpram_32_to_8_DataInA[31] + + + + + spi_dpram_32_to_8_DataInA[3] + spi_dpram_32_to_8_DataInA[3] + + + + + spi_dpram_32_to_8_DataInA[4] + spi_dpram_32_to_8_DataInA[4] + + + + + spi_dpram_32_to_8_DataInA[5] + spi_dpram_32_to_8_DataInA[5] + + + + + spi_dpram_32_to_8_DataInA[6] + spi_dpram_32_to_8_DataInA[6] + + + + + spi_dpram_32_to_8_DataInA[7] + spi_dpram_32_to_8_DataInA[7] + + + + + spi_dpram_32_to_8_DataInA[8] + spi_dpram_32_to_8_DataInA[8] + + + + + spi_dpram_32_to_8_DataInA[9] + spi_dpram_32_to_8_DataInA[9] + + + + + spi_dpram_32_to_8_DataInB + spi_dpram_32_to_8_DataInB + + + + + spi_dpram_32_to_8_DataInB[0] + spi_dpram_32_to_8_DataInB[0] + + + + + spi_dpram_32_to_8_DataInB[1] + spi_dpram_32_to_8_DataInB[1] + + + + + spi_dpram_32_to_8_DataInB[2] + spi_dpram_32_to_8_DataInB[2] + + + + + spi_dpram_32_to_8_DataInB[3] + spi_dpram_32_to_8_DataInB[3] + + + + + spi_dpram_32_to_8_DataInB[4] + spi_dpram_32_to_8_DataInB[4] + + + + + spi_dpram_32_to_8_DataInB[5] + spi_dpram_32_to_8_DataInB[5] + + + + + spi_dpram_32_to_8_DataInB[6] + spi_dpram_32_to_8_DataInB[6] + + + + + spi_dpram_32_to_8_DataInB[7] + spi_dpram_32_to_8_DataInB[7] + + + + + spi_dpram_32_to_8_QA + spi_dpram_32_to_8_QA + + + + + spi_dpram_32_to_8_QA[0] + spi_dpram_32_to_8_QA[0] + + + + + spi_dpram_32_to_8_QA[10] + spi_dpram_32_to_8_QA[10] + + + + + spi_dpram_32_to_8_QA[11] + spi_dpram_32_to_8_QA[11] + + + + + spi_dpram_32_to_8_QA[12] + spi_dpram_32_to_8_QA[12] + + + + + spi_dpram_32_to_8_QA[13] + spi_dpram_32_to_8_QA[13] + + + + + spi_dpram_32_to_8_QA[14] + spi_dpram_32_to_8_QA[14] + + + + + spi_dpram_32_to_8_QA[15] + spi_dpram_32_to_8_QA[15] + + + + + spi_dpram_32_to_8_QA[16] + spi_dpram_32_to_8_QA[16] + + + + + spi_dpram_32_to_8_QA[17] + spi_dpram_32_to_8_QA[17] + + + + + spi_dpram_32_to_8_QA[18] + spi_dpram_32_to_8_QA[18] + + + + + spi_dpram_32_to_8_QA[19] + spi_dpram_32_to_8_QA[19] + + + + + spi_dpram_32_to_8_QA[1] + spi_dpram_32_to_8_QA[1] + + + + + spi_dpram_32_to_8_QA[20] + spi_dpram_32_to_8_QA[20] + + + + + spi_dpram_32_to_8_QA[21] + spi_dpram_32_to_8_QA[21] + + + + + spi_dpram_32_to_8_QA[22] + spi_dpram_32_to_8_QA[22] + + + + + spi_dpram_32_to_8_QA[23] + spi_dpram_32_to_8_QA[23] + + + + + spi_dpram_32_to_8_QA[24] + spi_dpram_32_to_8_QA[24] + + + + + spi_dpram_32_to_8_QA[25] + spi_dpram_32_to_8_QA[25] + + + + + spi_dpram_32_to_8_QA[26] + spi_dpram_32_to_8_QA[26] + + + + + spi_dpram_32_to_8_QA[27] + spi_dpram_32_to_8_QA[27] + + + + + spi_dpram_32_to_8_QA[28] + spi_dpram_32_to_8_QA[28] + + + + + spi_dpram_32_to_8_QA[29] + spi_dpram_32_to_8_QA[29] + + + + + spi_dpram_32_to_8_QA[2] + spi_dpram_32_to_8_QA[2] + + + + + spi_dpram_32_to_8_QA[30] + spi_dpram_32_to_8_QA[30] + + + + + spi_dpram_32_to_8_QA[31] + spi_dpram_32_to_8_QA[31] + + + + + spi_dpram_32_to_8_QA[3] + spi_dpram_32_to_8_QA[3] + + + + + spi_dpram_32_to_8_QA[4] + spi_dpram_32_to_8_QA[4] + + + + + spi_dpram_32_to_8_QA[5] + spi_dpram_32_to_8_QA[5] + + + + + spi_dpram_32_to_8_QA[6] + spi_dpram_32_to_8_QA[6] + + + + + spi_dpram_32_to_8_QA[7] + spi_dpram_32_to_8_QA[7] + + + + + spi_dpram_32_to_8_QA[8] + spi_dpram_32_to_8_QA[8] + + + + + spi_dpram_32_to_8_QA[9] + spi_dpram_32_to_8_QA[9] + + + + + spi_dpram_32_to_8_QB + spi_dpram_32_to_8_QB + + + + + spi_dpram_32_to_8_QB[0] + spi_dpram_32_to_8_QB[0] + + + + + spi_dpram_32_to_8_QB[1] + spi_dpram_32_to_8_QB[1] + + + + + spi_dpram_32_to_8_QB[2] + spi_dpram_32_to_8_QB[2] + + + + + spi_dpram_32_to_8_QB[3] + spi_dpram_32_to_8_QB[3] + + + + + spi_dpram_32_to_8_QB[4] + spi_dpram_32_to_8_QB[4] + + + + + spi_dpram_32_to_8_QB[5] + spi_dpram_32_to_8_QB[5] + + + + + spi_dpram_32_to_8_QB[6] + spi_dpram_32_to_8_QB[6] + + + + + spi_dpram_32_to_8_QB[7] + spi_dpram_32_to_8_QB[7] + + + + + + diff --git a/lattice/ecp5/RAM/archv/spi_dpram_32_to_8.zip b/lattice/ecp5/RAM/archv/spi_dpram_32_to_8.zip new file mode 100644 index 0000000..e26e2b7 Binary files /dev/null and b/lattice/ecp5/RAM/archv/spi_dpram_32_to_8.zip differ diff --git a/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.cst b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.cst new file mode 100644 index 0000000..9d90617 --- /dev/null +++ b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.cst @@ -0,0 +1,3 @@ +Date=03/20/2015 +Time=15:23:04 + diff --git a/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.edn b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.edn new file mode 100644 index 0000000..21a6730 --- /dev/null +++ b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.edn @@ -0,0 +1,1139 @@ +(edif spi_dpram_32_to_8 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2015 3 20 15 23 6) + (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) + (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n spi_dpram_32_to_8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 8 -num_rows 64 -outdataA REGISTERED -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -mem_init0 -writemodeA NORMAL -writemodeB NORMAL -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.fdc ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell DP16KD + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port DIA17 + (direction INPUT)) + (port DIA16 + (direction INPUT)) + (port DIA15 + (direction INPUT)) + (port DIA14 + (direction INPUT)) + (port DIA13 + (direction INPUT)) + (port DIA12 + (direction INPUT)) + (port DIA11 + (direction INPUT)) + (port DIA10 + (direction INPUT)) + (port DIA9 + (direction INPUT)) + (port DIA8 + (direction INPUT)) + (port DIA7 + (direction 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(port DIB17 + (direction INPUT)) + (port DIB16 + (direction INPUT)) + (port DIB15 + (direction INPUT)) + (port DIB14 + (direction INPUT)) + (port DIB13 + (direction INPUT)) + (port DIB12 + (direction INPUT)) + (port DIB11 + (direction INPUT)) + (port DIB10 + (direction INPUT)) + (port DIB9 + (direction INPUT)) + (port DIB8 + (direction INPUT)) + (port DIB7 + (direction INPUT)) + (port DIB6 + (direction INPUT)) + (port DIB5 + (direction INPUT)) + (port DIB4 + (direction INPUT)) + (port DIB3 + (direction INPUT)) + (port DIB2 + (direction INPUT)) + (port DIB1 + (direction INPUT)) + (port DIB0 + (direction INPUT)) + (port ADB13 + (direction INPUT)) + (port ADB12 + (direction INPUT)) + (port ADB11 + (direction INPUT)) + (port ADB10 + (direction INPUT)) + (port ADB9 + (direction INPUT)) + (port ADB8 + (direction INPUT)) + (port ADB7 + (direction INPUT)) + (port ADB6 + (direction INPUT)) + (port ADB5 + (direction INPUT)) + (port ADB4 + (direction INPUT)) + (port ADB3 + (direction INPUT)) + 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(portRef (member DataInA 31)) + (portRef DIA0 (instanceRef spi_dpram_32_to_8_0_0_1)))))))) + (design spi_dpram_32_to_8 + (cellRef spi_dpram_32_to_8 + (libraryRef ORCLIB))) +) diff --git a/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.fdc b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.fdc new file mode 100644 index 0000000..6fbcac9 --- /dev/null +++ b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.fdc @@ -0,0 +1,2 @@ +###==== Start Configuration + diff --git a/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.lpc b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.lpc new file mode 100644 index 0000000..0966399 --- /dev/null +++ b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.lpc @@ -0,0 +1,56 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8MG285C +SpeedGrade=8 +Package=CSFBGA285 +OperatingCondition=COM +Status=C + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_DP_TRUE +CoreRevision=7.4 +ModuleName=spi_dpram_32_to_8 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/20/2015 +Time=15:23:04 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +RAddress=64 +RData=32 +WAddress=256 +WData=8 +ROutputEn=1 +RClockEn=0 +WOutputEn=1 +WClockEn=0 +enByte=0 +ByteSize=9 +Optimization=Speed +Reset=Sync +Reset1=Sync +Init=0 +MemFile= +MemFormat=bin +EnECC=0 +Pipeline=0 +WriteA=Normal +WriteB=Normal +init_data=0 + +[FilesGenerated] +=mem + +[Command] +cmd_line= -w -n spi_dpram_32_to_8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ramdp -device LFE5UM-85F -aaddr_width 6 -widtha 32 -baddr_width 8 -widthb 8 -anum_words 64 -bnum_words 256 -outdataA REGISTERED -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -mem_init0 -writemodeA NORMAL -writemodeB NORMAL diff --git a/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.ngd b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.ngd new file mode 100644 index 0000000..0a9930e Binary files /dev/null and b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.ngd differ diff --git a/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.ngo b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.ngo new file mode 100644 index 0000000..d55611e Binary files /dev/null and b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.ngo differ diff --git a/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd new file mode 100644 index 0000000..4734b61 --- /dev/null +++ b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd @@ -0,0 +1,265 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- Module Version: 7.4 +--/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n spi_dpram_32_to_8 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 8 -num_rows 64 -outdataA REGISTERED -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -mem_init0 -writemodeA NORMAL -writemodeB NORMAL -fdc /home/cugur/Projects/TDC_on_TRB3/trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.fdc + +-- Fri Mar 20 15:23:06 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity spi_dpram_32_to_8 is + port ( + DataInA: in std_logic_vector(31 downto 0); + DataInB: in std_logic_vector(7 downto 0); + AddressA: in std_logic_vector(5 downto 0); + AddressB: in std_logic_vector(7 downto 0); + ClockA: in std_logic; + ClockB: in std_logic; + ClockEnA: in std_logic; + ClockEnB: in std_logic; + WrA: in std_logic; + WrB: in std_logic; + ResetA: in std_logic; + ResetB: in std_logic; + QA: out std_logic_vector(31 downto 0); + QB: out std_logic_vector(7 downto 0)); +end spi_dpram_32_to_8; + +architecture Structure of spi_dpram_32_to_8 is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute MEM_LPC_FILE of spi_dpram_32_to_8_0_0_1 : label is "spi_dpram_32_to_8.lpc"; + attribute MEM_INIT_FILE of spi_dpram_32_to_8_0_0_1 : label is "INIT_ALL_0s"; + attribute MEM_LPC_FILE of spi_dpram_32_to_8_0_1_0 : label is "spi_dpram_32_to_8.lpc"; + attribute MEM_INIT_FILE of spi_dpram_32_to_8_0_1_0 : label is "INIT_ALL_0s"; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + spi_dpram_32_to_8_0_0_1: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 18) + port map (DIA17=>scuba_vlo, DIA16=>DataInA(27), + DIA15=>DataInA(26), DIA14=>DataInA(25), DIA13=>DataInA(24), + DIA12=>DataInA(19), DIA11=>DataInA(18), DIA10=>DataInA(17), + DIA9=>DataInA(16), DIA8=>scuba_vlo, DIA7=>DataInA(11), + DIA6=>DataInA(10), DIA5=>DataInA(9), DIA4=>DataInA(8), + DIA3=>DataInA(3), DIA2=>DataInA(2), DIA1=>DataInA(1), + DIA0=>DataInA(0), ADA13=>scuba_vlo, ADA12=>scuba_vlo, + ADA11=>scuba_vlo, ADA10=>scuba_vlo, ADA9=>AddressA(5), + ADA8=>AddressA(4), ADA7=>AddressA(3), ADA6=>AddressA(2), + ADA5=>AddressA(1), ADA4=>AddressA(0), ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>ClockEnA, OCEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, + RSTA=>ResetA, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>DataInB(3), DIB2=>DataInB(2), DIB1=>DataInB(1), + DIB0=>DataInB(0), ADB13=>scuba_vlo, ADB12=>scuba_vlo, + ADB11=>scuba_vlo, ADB10=>scuba_vlo, ADB9=>AddressB(7), + ADB8=>AddressB(6), ADB7=>AddressB(5), ADB6=>AddressB(4), + ADB5=>AddressB(3), ADB4=>AddressB(2), ADB3=>AddressB(1), + ADB2=>AddressB(0), ADB1=>scuba_vlo, ADB0=>scuba_vlo, + CEB=>ClockEnB, OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, + RSTB=>ResetB, DOA17=>open, DOA16=>QA(27), DOA15=>QA(26), + DOA14=>QA(25), DOA13=>QA(24), DOA12=>QA(19), DOA11=>QA(18), + DOA10=>QA(17), DOA9=>QA(16), DOA8=>open, DOA7=>QA(11), + DOA6=>QA(10), DOA5=>QA(9), DOA4=>QA(8), DOA3=>QA(3), + DOA2=>QA(2), DOA1=>QA(1), DOA0=>QA(0), DOB17=>open, + DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, + DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, + DOB8=>open, DOB7=>open, DOB6=>open, DOB5=>open, DOB4=>open, + DOB3=>QB(3), DOB2=>QB(2), DOB1=>QB(1), DOB0=>QB(0)); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + spi_dpram_32_to_8_0_1_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 18) + port map (DIA17=>scuba_vlo, DIA16=>DataInA(31), + DIA15=>DataInA(30), DIA14=>DataInA(29), DIA13=>DataInA(28), + DIA12=>DataInA(23), DIA11=>DataInA(22), DIA10=>DataInA(21), + DIA9=>DataInA(20), DIA8=>scuba_vlo, DIA7=>DataInA(15), + DIA6=>DataInA(14), DIA5=>DataInA(13), DIA4=>DataInA(12), + DIA3=>DataInA(7), DIA2=>DataInA(6), DIA1=>DataInA(5), + DIA0=>DataInA(4), ADA13=>scuba_vlo, ADA12=>scuba_vlo, + ADA11=>scuba_vlo, ADA10=>scuba_vlo, ADA9=>AddressA(5), + ADA8=>AddressA(4), ADA7=>AddressA(3), ADA6=>AddressA(2), + ADA5=>AddressA(1), ADA4=>AddressA(0), ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>ClockEnA, OCEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, + RSTA=>ResetA, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>DataInB(7), DIB2=>DataInB(6), DIB1=>DataInB(5), + DIB0=>DataInB(4), ADB13=>scuba_vlo, ADB12=>scuba_vlo, + ADB11=>scuba_vlo, ADB10=>scuba_vlo, ADB9=>AddressB(7), + ADB8=>AddressB(6), ADB7=>AddressB(5), ADB6=>AddressB(4), + ADB5=>AddressB(3), ADB4=>AddressB(2), ADB3=>AddressB(1), + ADB2=>AddressB(0), ADB1=>scuba_vlo, ADB0=>scuba_vlo, + CEB=>ClockEnB, OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, + RSTB=>ResetB, DOA17=>open, DOA16=>QA(31), DOA15=>QA(30), + DOA14=>QA(29), DOA13=>QA(28), DOA12=>QA(23), DOA11=>QA(22), + DOA10=>QA(21), DOA9=>QA(20), DOA8=>open, DOA7=>QA(15), + DOA6=>QA(14), DOA5=>QA(13), DOA4=>QA(12), DOA3=>QA(7), + DOA2=>QA(6), DOA1=>QA(5), DOA0=>QA(4), DOB17=>open, + DOB16=>open, DOB15=>open, DOB14=>open, DOB13=>open, + DOB12=>open, DOB11=>open, DOB10=>open, DOB9=>open, + DOB8=>open, DOB7=>open, DOB6=>open, DOB5=>open, DOB4=>open, + DOB3=>QB(7), DOB2=>QB(6), DOB1=>QB(5), DOB0=>QB(4)); + +end Structure; diff --git a/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8_ngd.asd b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8_ngd.asd new file mode 100644 index 0000000..c265c78 --- /dev/null +++ b/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8_ngd.asd @@ -0,0 +1 @@ +[ActiveSupport NGD] diff --git a/lattice/ecp5/trb_net16_fifo_arch.vhd b/lattice/ecp5/trb_net16_fifo_arch.vhd new file mode 100644 index 0000000..aaf4d57 --- /dev/null +++ b/lattice/ecp5/trb_net16_fifo_arch.vhd @@ -0,0 +1,164 @@ +library ieee; + +use ieee.std_logic_1164.all; +USE ieee.std_logic_signed.ALL; +USE IEEE.numeric_std.ALL; +use work.trb_net_std.all; + +entity trb_net16_fifo is + generic ( + USE_VENDOR_CORES : integer range 0 to 1 := c_NO; + use_data_count : integer range 0 to 1 := c_NO; + DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(15 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(1 downto 0); -- Input data + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(15 downto 0); -- Output data + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); -- Input data + DATA_COUNT_OUT : out std_logic_vector(10 downto 0); + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; -- Full Flag + EMPTY_OUT : out std_logic + ); +end entity; + +architecture arch_trb_net16_fifo of trb_net16_fifo is +component lattice_ecp5_fifo_18x1k is + port ( + Data: in std_logic_vector(17 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic); +end component; + + +-- component lattice_ecp2m_fifo_18x16 is +-- port ( +-- Data: in std_logic_vector(17 downto 0); +-- WrClock: in std_logic; +-- RdClock: in std_logic; +-- WrEn: in std_logic; +-- RdEn: in std_logic; +-- Reset: in std_logic; +-- RPReset: in std_logic; +-- Q: out std_logic_vector(17 downto 0); +-- Empty: out std_logic; +-- Full: out std_logic); +-- end component; +-- +-- component lattice_ecp2m_fifo_18x32 is +-- port ( +-- Data: in std_logic_vector(17 downto 0); +-- WrClock: in std_logic; +-- RdClock: in std_logic; +-- WrEn: in std_logic; +-- RdEn: in std_logic; +-- Reset: in std_logic; +-- RPReset: in std_logic; +-- Q: out std_logic_vector(17 downto 0); +-- Empty: out std_logic; +-- Full: out std_logic); +-- end component; +-- +-- component lattice_ecp2m_fifo_18x64 is +-- port ( +-- Data: in std_logic_vector(17 downto 0); +-- WrClock: in std_logic; +-- RdClock: in std_logic; +-- WrEn: in std_logic; +-- RdEn: in std_logic; +-- Reset: in std_logic; +-- RPReset: in std_logic; +-- Q: out std_logic_vector(17 downto 0); +-- Empty: out std_logic; +-- Full: out std_logic); +-- end component; + + + signal din, dout : std_logic_vector(c_DATA_WIDTH +1 downto 0); + +begin + din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN; + din(c_DATA_WIDTH + 1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; + DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 1 downto c_DATA_WIDTH); + DATA_COUNT_OUT <= (others => '0'); + +-- gen_FIFO6 : if DEPTH = 6 generate + fifo:lattice_ecp5_fifo_18x1k + port map ( + Data => din, + Clock => CLK, + WrEn => WRITE_ENABLE_IN, + RdEn => READ_ENABLE_IN, + Reset => RESET, + Q => dout, + Empty => EMPTY_OUT, + Full => FULL_OUT + ); +-- end generate; + + +-- gen_FIFO1 : if DEPTH = 1 generate +-- fifo:lattice_ecp2m_fifo_18x16 +-- port map ( +-- Data => din, +-- WrClock => CLK, +-- RdClock => CLK, +-- WrEn => WRITE_ENABLE_IN, +-- RdEn => READ_ENABLE_IN, +-- Reset => RESET, +-- RPReset => RESET, +-- Q => dout, +-- Empty => EMPTY_OUT, +-- Full => FULL_OUT +-- ); +-- end generate; +-- +-- gen_FIFO2 : if DEPTH = 2 generate +-- fifo:lattice_ecp2m_fifo_18x32 +-- port map ( +-- Data => din, +-- WrClock => CLK, +-- RdClock => CLK, +-- WrEn => WRITE_ENABLE_IN, +-- RdEn => READ_ENABLE_IN, +-- Reset => RESET, +-- RPReset => RESET, +-- Q => dout, +-- Empty => EMPTY_OUT, +-- Full => FULL_OUT +-- ); +-- end generate; +-- +-- +-- gen_FIFO3 : if DEPTH = 3 generate +-- fifo:lattice_ecp2m_fifo_18x64 +-- port map ( +-- Data => din, +-- WrClock => CLK, +-- RdClock => CLK, +-- WrEn => WRITE_ENABLE_IN, +-- RdEn => READ_ENABLE_IN, +-- Reset => RESET, +-- RPReset => RESET, +-- Q => dout, +-- Empty => EMPTY_OUT, +-- Full => FULL_OUT +-- ); +-- end generate; + + +end architecture; + + +