From: local account Date: Tue, 13 Oct 2015 14:55:19 +0000 (+0200) Subject: updated gbe X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=af3079ca4c9c204c8042419b5880b374ad6f3d28;p=trbnet.git updated gbe --- diff --git a/gbe_trb/README.md b/gbe_trb/README.md new file mode 100644 index 0000000..7a04a3f --- /dev/null +++ b/gbe_trb/README.md @@ -0,0 +1,9 @@ +# gbe_trb +hello\as +as +df +asd +fas +d +f/S +F diff --git a/gbe_trb/base/gbe_ipu_dummy.vhd b/gbe_trb/base/gbe_ipu_dummy.vhd index 182adc4..87d23e7 100644 --- a/gbe_trb/base/gbe_ipu_dummy.vhd +++ b/gbe_trb/base/gbe_ipu_dummy.vhd @@ -13,96 +13,95 @@ use work.trb_net_gbe_components.all; use work.trb_net_gbe_protocols.all; entity gbe_ipu_dummy is - generic ( - DO_SIMULATION : integer range 0 to 1 := 0; - FIXED_SIZE_MODE : integer range 0 to 1 := 1; - FIXED_SIZE : integer range 0 to 65535 := 10; - INCREMENTAL_MODE : integer range 0 to 1 := 0; - UP_DOWN_MODE : integer range 0 to 1 := 0; - UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; - FIXED_DELAY_MODE : integer range 0 to 1 := 1; - FIXED_DELAY : integer range 0 to 16777215 := 16777215 + generic( + DO_SIMULATION : integer range 0 to 1 := 0; + FIXED_SIZE_MODE : integer range 0 to 1 := 1; + FIXED_SIZE : integer range 0 to 65535 := 10; + INCREMENTAL_MODE : integer range 0 to 1 := 0; + UP_DOWN_MODE : integer range 0 to 1 := 0; + UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; + FIXED_DELAY_MODE : integer range 0 to 1 := 1; + FIXED_DELAY : integer range 0 to 16777215 := 16777215 ); - port ( - clk : in std_logic; - rst : in std_logic; - GBE_READY_IN : in std_logic; - - CFG_EVENT_SIZE_IN : in std_logic_vector(15 downto 0); - CFG_TRIGGERED_MODE_IN : in std_logic; - TRIGGER_IN : in std_logic; - - CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); - CTS_CODE_OUT : out std_logic_vector (7 downto 0); - CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); - CTS_START_READOUT_OUT : out std_logic; - CTS_DATA_IN : in std_logic_vector (31 downto 0); - CTS_DATAREADY_IN : in std_logic; - CTS_READOUT_FINISHED_IN : in std_logic; - CTS_READ_OUT : out std_logic; - CTS_LENGTH_IN : in std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + port( + clk : in std_logic; + rst : in std_logic; + GBE_READY_IN : in std_logic; + + CFG_EVENT_SIZE_IN : in std_logic_vector(15 downto 0); + CFG_TRIGGERED_MODE_IN : in std_logic; + TRIGGER_IN : in std_logic; + + CTS_NUMBER_OUT : out std_logic_vector(15 downto 0); + CTS_CODE_OUT : out std_logic_vector(7 downto 0); + CTS_INFORMATION_OUT : out std_logic_vector(7 downto 0); + CTS_READOUT_TYPE_OUT : out std_logic_vector(3 downto 0); + CTS_START_READOUT_OUT : out std_logic; + CTS_DATA_IN : in std_logic_vector(31 downto 0); + CTS_DATAREADY_IN : in std_logic; + CTS_READOUT_FINISHED_IN : in std_logic; + CTS_READ_OUT : out std_logic; + CTS_LENGTH_IN : in std_logic_vector(15 downto 0); + CTS_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- Data payload interface - FEE_DATA_OUT : out std_logic_vector (15 downto 0); - FEE_DATAREADY_OUT : out std_logic; - FEE_READ_IN : in std_logic; - FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); - FEE_BUSY_OUT : out std_logic + FEE_DATA_OUT : out std_logic_vector(15 downto 0); + FEE_DATAREADY_OUT : out std_logic; + FEE_READ_IN : in std_logic; + FEE_STATUS_BITS_OUT : out std_logic_vector(31 downto 0); + FEE_BUSY_OUT : out std_logic ); end entity gbe_ipu_dummy; architecture RTL of gbe_ipu_dummy is - component random_size is - port ( - Clk: in std_logic; - Enb: in std_logic; - Rst: in std_logic; - Dout: out std_logic_vector(31 downto 0)); + port( + Clk : in std_logic; + Enb : in std_logic; + Rst : in std_logic; + Dout : out std_logic_vector(31 downto 0)); end component; - - type states is (IDLE, TIMEOUT, CTS_START, FEE_START, WAIT_FOR_READ_1, WAIT_A_SEC_1, WAIT_FOR_READ_2, WAIT_A_SEC_2, WAIT_FOR_READ_3, WAIT_A_SEC_3, - WAIT_FOR_READ_4, WAIT_A_SEC_4, WAIT_FOR_READ_5, WAIT_A_SEC_5, WAIT_FOR_READ_6, WAIT_A_SEC_6, CLOSE - , LOOP_OVER_DATA, SEND_ONE_WORD, WAIT_A_SEC_7, LOWER_BUSY, WAIT_A_SEC_8, WAIT_A_SEC_9, PULSE_WITH_READ); + + type states is (IDLE, TIMEOUT, CTS_START, FEE_START, WAIT_FOR_READ_1, WAIT_A_SEC_1, WAIT_FOR_READ_2, WAIT_A_SEC_2, WAIT_FOR_READ_3, WAIT_A_SEC_3, + WAIT_FOR_READ_4, WAIT_A_SEC_4, WAIT_FOR_READ_5, WAIT_A_SEC_5, WAIT_FOR_READ_6, WAIT_A_SEC_6, CLOSE, LOOP_OVER_DATA, SEND_ONE_WORD, WAIT_A_SEC_7, LOWER_BUSY, WAIT_A_SEC_8, WAIT_A_SEC_9, PULSE_WITH_READ); signal current_state, next_state : states; - - signal ctr : integer range 0 to 16777215 := 16777215; - signal timeout_stop : integer range 0 to 16777215 := 16777215; - signal pause_cts_fee : integer range 0 to 65535 := 8; - signal pause_dready : integer range 0 to 65535 := 3; - signal pause_wait_1, pause_wait_2, pause_wait_3, pause_wait_4, pause_wait_5, pause_wait_6, send_word_pause, pause_wait_7, pause_wait_8, pause_wait_9 : integer range 0 to 10 := 4; - signal cts_start_readout, fee_busy, fee_dready, cts_read : std_logic; - signal cts_number, fee_data, test_data_len : std_logic_vector(15 downto 0); - signal data_ctr : std_logic_vector(16 downto 0); - signal size_rand_en, delay_rand_en : std_logic; - signal delay_value : std_logic_vector(15 downto 0); - signal d, s : std_logic_vector(31 downto 0); - signal trigger_type, bank_select : std_logic_vector(3 downto 0) := x"0"; - signal constructed_events : std_logic_vector(15 downto 0) := x"0000"; - signal increment_flag : std_logic; - - + + signal ctr : integer range 0 to 16777215 := 16777215; + signal timeout_stop : integer range 0 to 16777215 := 16777215; + signal pause_cts_fee : integer range 0 to 65535 := 8; + signal pause_dready : integer range 0 to 65535 := 3; + signal pause_wait_1, pause_wait_2, pause_wait_3, pause_wait_4, pause_wait_5, pause_wait_6, send_word_pause, pause_wait_7, pause_wait_8, pause_wait_9 : integer range 0 to 10 := 4; + signal cts_start_readout, fee_busy, fee_dready, cts_read : std_logic; + signal cts_number, fee_data, test_data_len : std_logic_vector(15 downto 0); + signal data_ctr : std_logic_vector(16 downto 0); + signal size_rand_en, delay_rand_en : std_logic; + signal delay_value : std_logic_vector(15 downto 0); + signal d, s : std_logic_vector(31 downto 0); + signal trigger_type, bank_select : std_logic_vector(3 downto 0) := x"0"; + signal constructed_events : std_logic_vector(15 downto 0) := x"0000"; + signal increment_flag : std_logic; + signal local_trigger : std_logic; + signal evt_ctr : std_logic_vector(31 downto 0); + begin - send_word_pause <= 1; - + FEE_STATUS_BITS_OUT <= x"11223344"; + send_word_pause <= 1; + fixed_size_gen : if FIXED_SIZE_MODE = 1 generate test_data_len <= std_logic_vector(to_unsigned(FIXED_SIZE, 16)); --CFG_EVENT_SIZE_IN; --std_logic_vector(to_unsigned(FIXED_SIZE, 16)); end generate fixed_size_gen; - + random_size_gen : if FIXED_SIZE_MODE = 0 and INCREMENTAL_MODE = 0 generate - size_rand_inst : random_size - port map(Clk => clk, - Enb => size_rand_en, - Rst => rst, - Dout => s - ); - + port map(Clk => clk, + Enb => size_rand_en, + Rst => rst, + Dout => s + ); + test_data_len <= (x"00" & "00" & s(4 downto 0)) + x"0001"; - + process(clk) begin if rising_edge(clk) then @@ -113,34 +112,32 @@ begin end if; end if; end process; - + end generate random_size_gen; - + incremental_size_gen : if FIXED_SIZE_MODE = 0 and INCREMENTAL_MODE = 1 generate - process(clk) begin if rising_edge(clk) then test_data_len <= std_logic_vector(to_unsigned(FIXED_SIZE, 16)) + constructed_events; end if; end process; - + end generate incremental_size_gen; - + fixed_delay_gen : if FIXED_DELAY_MODE = 1 generate - timeout_stop <= FIXED_DELAY when DO_SIMULATION = 0 else 100; + timeout_stop <= FIXED_DELAY when DO_SIMULATION = 0 else 10; end generate fixed_delay_gen; - + variable_delay_gen : if FIXED_DELAY_MODE = 0 generate - delay_rand_inst : random_size - port map(Clk => clk, - Enb => delay_rand_en, - Rst => rst, - Dout => d); - - delay_value <= d(31 downto 16); - + port map(Clk => clk, + Enb => delay_rand_en, + Rst => rst, + Dout => d); + + delay_value <= d(31 downto 16); + process(clk) begin if rising_edge(clk) then @@ -151,22 +148,36 @@ begin end if; end if; end process; - + timeout_stop <= to_integer(unsigned(delay_value)); - + end generate variable_delay_gen; - - - CTS_INFORMATION_OUT <= x"d" & bank_select; - CTS_READOUT_TYPE_OUT <= trigger_type; --x"1"; - CTS_CODE_OUT <= x"aa"; + + CTS_INFORMATION_OUT <= x"d" & bank_select; + CTS_READOUT_TYPE_OUT <= trigger_type; --x"1"; + CTS_CODE_OUT <= x"aa"; CTS_START_READOUT_OUT <= cts_start_readout; - CTS_READ_OUT <= cts_read; - FEE_BUSY_OUT <= fee_busy; - FEE_DATAREADY_OUT <= fee_dready; - FEE_DATA_OUT <= fee_data; - - state_machine_proc : process (clk, rst) is + CTS_READ_OUT <= cts_read; + FEE_BUSY_OUT <= fee_busy; + FEE_DATAREADY_OUT <= fee_dready; + FEE_DATA_OUT <= fee_data; + + process(clk) + begin + if rising_edge(clk) then + if (CFG_TRIGGERED_MODE_IN = '0') then + if (ctr = timeout_stop) then + local_trigger <= '1'; + else + local_trigger <= '0'; + end if; + else + local_trigger <= TRIGGER_IN; + end if; + end if; + end process; + + state_machine_proc : process(clk, rst) is begin if rst = '1' then current_state <= IDLE; @@ -174,173 +185,177 @@ begin current_state <= next_state; end if; end process state_machine_proc; - - state_machine : process (current_state, GBE_READY_IN, ctr, timeout_stop, pause_dready, pause_cts_fee, FEE_READ_IN, pause_wait_6, pause_wait_5, - pause_wait_4, pause_wait_3, pause_wait_2, pause_wait_1, send_word_pause, TRIGGER_IN, data_ctr, test_data_len, pause_wait_7, pause_wait_8, pause_wait_9 - ) is + + state_machine : process(current_state, GBE_READY_IN, ctr, timeout_stop, CTS_READOUT_FINISHED_IN, pause_dready, pause_cts_fee, FEE_READ_IN, pause_wait_6, pause_wait_5, pause_wait_4, pause_wait_3, pause_wait_2, pause_wait_1, send_word_pause, local_trigger, data_ctr, test_data_len, pause_wait_7, pause_wait_8, pause_wait_9) + is begin - case current_state is - when IDLE => - if (GBE_READY_IN = '1') then - next_state <= TIMEOUT; - else - next_state <= IDLE; - end if; - - when TIMEOUT => - --if (ctr = timeout_stop) then - if (TRIGGER_IN = '1') then - next_state <= CTS_START; - else - next_state <= TIMEOUT; - end if; - - when CTS_START => - if (ctr = pause_cts_fee) then - next_state <= FEE_START; - else - next_state <= CTS_START; - end if; - - when FEE_START => - if (ctr = pause_dready) then - next_state <= WAIT_FOR_READ_1; - else - next_state <= FEE_START; - end if; - - when WAIT_FOR_READ_1 => - if (FEE_READ_IN = '1') then - next_state <= WAIT_A_SEC_1; - else - next_state <= WAIT_FOR_READ_1; - end if; - - when WAIT_A_SEC_1 => - if (ctr = pause_wait_1) then - next_state <= WAIT_FOR_READ_2; - else - next_state <= WAIT_A_SEC_1; - end if; - - when WAIT_FOR_READ_2 => - if (FEE_READ_IN = '1') then - next_state <= WAIT_A_SEC_2; - else - next_state <= WAIT_FOR_READ_2; - end if; - - when WAIT_A_SEC_2 => - if (ctr = pause_wait_2) then - next_state <= WAIT_FOR_READ_3; - else - next_state <= WAIT_A_SEC_2; - end if; - - when WAIT_FOR_READ_3 => - if (FEE_READ_IN = '1') then - next_state <= WAIT_A_SEC_3; - else - next_state <= WAIT_FOR_READ_3; - end if; - - when WAIT_A_SEC_3 => - if (ctr = pause_wait_3) then - next_state <= WAIT_FOR_READ_4; - else - next_state <= WAIT_A_SEC_3; - end if; - - when WAIT_FOR_READ_4 => - if (FEE_READ_IN = '1') then - next_state <= WAIT_A_SEC_4; - else - next_state <= WAIT_FOR_READ_4; - end if; - - when WAIT_A_SEC_4 => - if (ctr = pause_wait_4) then - next_state <= WAIT_FOR_READ_5; - else - next_state <= WAIT_A_SEC_4; - end if; - - when WAIT_FOR_READ_5 => - if (FEE_READ_IN = '1') then - next_state <= WAIT_A_SEC_5; - else - next_state <= WAIT_FOR_READ_5; - end if; - - when WAIT_A_SEC_5 => - if (ctr = pause_wait_5) then - next_state <= WAIT_FOR_READ_6; - else - next_state <= WAIT_A_SEC_5; - end if; - - when WAIT_FOR_READ_6 => - if (FEE_READ_IN = '1') then - next_state <= WAIT_A_SEC_6; - else - next_state <= WAIT_FOR_READ_6; - end if; - - when WAIT_A_SEC_6 => - if (ctr = pause_wait_6) then + case current_state is + when IDLE => + if (GBE_READY_IN = '1') then + next_state <= TIMEOUT; + else + next_state <= IDLE; + end if; + + when TIMEOUT => + --if (ctr = timeout_stop) then + --if (TRIGGER_IN = '1') then + if (local_trigger = '1') then + next_state <= CTS_START; + else + next_state <= TIMEOUT; + end if; + + when CTS_START => + if (ctr = pause_cts_fee) then + next_state <= FEE_START; + else + next_state <= CTS_START; + end if; + + when FEE_START => + if (ctr = pause_dready) then + next_state <= WAIT_FOR_READ_1; + else + next_state <= FEE_START; + end if; + + when WAIT_FOR_READ_1 => + if (FEE_READ_IN = '1') then + next_state <= WAIT_A_SEC_1; + else + next_state <= WAIT_FOR_READ_1; + end if; + + when WAIT_A_SEC_1 => + if (ctr = pause_wait_1) then + next_state <= WAIT_FOR_READ_2; + else + next_state <= WAIT_A_SEC_1; + end if; + + when WAIT_FOR_READ_2 => + if (FEE_READ_IN = '1') then + next_state <= WAIT_A_SEC_2; + else + next_state <= WAIT_FOR_READ_2; + end if; + + when WAIT_A_SEC_2 => + if (ctr = pause_wait_2) then + next_state <= WAIT_FOR_READ_3; + else + next_state <= WAIT_A_SEC_2; + end if; + + when WAIT_FOR_READ_3 => + if (FEE_READ_IN = '1') then + next_state <= WAIT_A_SEC_3; + else + next_state <= WAIT_FOR_READ_3; + end if; + + when WAIT_A_SEC_3 => + if (ctr = pause_wait_3) then + next_state <= WAIT_FOR_READ_4; + else + next_state <= WAIT_A_SEC_3; + end if; + + when WAIT_FOR_READ_4 => + if (FEE_READ_IN = '1') then + next_state <= WAIT_A_SEC_4; + else + next_state <= WAIT_FOR_READ_4; + end if; + + when WAIT_A_SEC_4 => + if (ctr = pause_wait_4) then + next_state <= WAIT_FOR_READ_5; + else + next_state <= WAIT_A_SEC_4; + end if; + + when WAIT_FOR_READ_5 => + if (FEE_READ_IN = '1') then + next_state <= WAIT_A_SEC_5; + else + next_state <= WAIT_FOR_READ_5; + end if; + + when WAIT_A_SEC_5 => + if (ctr = pause_wait_5) then + next_state <= WAIT_FOR_READ_6; + else + next_state <= WAIT_A_SEC_5; + end if; + + when WAIT_FOR_READ_6 => + if (FEE_READ_IN = '1') then + next_state <= WAIT_A_SEC_6; + else + next_state <= WAIT_FOR_READ_6; + end if; + + when WAIT_A_SEC_6 => + if (ctr = pause_wait_6) then + next_state <= LOOP_OVER_DATA; + else + next_state <= WAIT_A_SEC_6; + end if; + + when LOOP_OVER_DATA => + if (to_integer(unsigned(data_ctr)) = (2 * (to_integer(unsigned(test_data_len)) - 1)) and FEE_READ_IN = '1') then + next_state <= WAIT_A_SEC_7; + else + next_state <= SEND_ONE_WORD; --LOOP_OVER_DATA; + end if; + + when SEND_ONE_WORD => + -- if (ctr = send_word_pause) then + -- next_state <= LOOP_OVER_DATA; + -- else + -- next_state <= SEND_ONE_WORD; + -- end if; next_state <= LOOP_OVER_DATA; - else - next_state <= WAIT_A_SEC_6; - end if; - - when LOOP_OVER_DATA => - if (to_integer(unsigned(data_ctr)) = (2 * (to_integer(unsigned(test_data_len)) - 1))) then - next_state <= WAIT_A_SEC_7; - else - next_state <= LOOP_OVER_DATA; --SEND_ONE_WORD; - end if; - - when SEND_ONE_WORD => --- if (ctr = send_word_pause) then --- next_state <= LOOP_OVER_DATA; --- else --- next_state <= SEND_ONE_WORD; --- end if; - next_state <= LOOP_OVER_DATA; - - when WAIT_A_SEC_7 => - if (ctr = pause_wait_7) then - next_state <= LOWER_BUSY; - else - next_state <= WAIT_A_SEC_7; - end if; - - when LOWER_BUSY => - next_state <= WAIT_A_SEC_8; - - when WAIT_A_SEC_8 => - if (ctr = pause_wait_8) then - next_state <= PULSE_WITH_READ; - else + + when WAIT_A_SEC_7 => + if (ctr = pause_wait_7) then + next_state <= LOWER_BUSY; + else + next_state <= WAIT_A_SEC_7; + end if; + + when LOWER_BUSY => next_state <= WAIT_A_SEC_8; - end if; - - when PULSE_WITH_READ => - next_state <= WAIT_A_SEC_9; - - when WAIT_A_SEC_9 => - if (ctr = pause_wait_9) then - next_state <= CLOSE; - else + + when WAIT_A_SEC_8 => + if (ctr = pause_wait_8) then + next_state <= PULSE_WITH_READ; + else + next_state <= WAIT_A_SEC_8; + end if; + + when PULSE_WITH_READ => next_state <= WAIT_A_SEC_9; - end if; - - when CLOSE => - next_state <= IDLE; - - end case; + + when WAIT_A_SEC_9 => + if (ctr = pause_wait_9) then + next_state <= CLOSE; + else + next_state <= WAIT_A_SEC_9; + end if; + + when CLOSE => + if (CTS_READOUT_FINISHED_IN = '1') then + next_state <= IDLE; + else + next_state <= CLOSE; + end if; + + end case; end process state_machine; - + process(CLK) begin if rising_edge(CLK) then @@ -352,23 +367,22 @@ begin data_ctr <= data_ctr; end if; end if; - end process; - + end process; + ctr_proc : process(clk) begin if rising_edge(clk) then - ctr <= ctr; - - case current_state is + + case current_state is when IDLE => ctr <= 0; when TIMEOUT => --- if ctr /= timeout_stop then --- ctr <= ctr + 1; --- else + if ctr /= timeout_stop then + ctr <= ctr + 1; + else ctr <= 0; --- end if; + end if; when CTS_START => if (ctr /= pause_cts_fee) then ctr <= ctr + 1; @@ -417,7 +431,7 @@ begin else ctr <= 0; end if; - when SEND_ONE_WORD => + when SEND_ONE_WORD => if (ctr /= send_word_pause) then ctr <= ctr + 1; else @@ -441,20 +455,19 @@ begin else ctr <= 0; end if; - + when others => ctr <= ctr; end case; end if; - end process ctr_proc; - + end process ctr_proc; process(CLK) begin if rising_edge(CLK) then if (current_state = IDLE) then cts_start_readout <= '0'; - elsif (current_state = CTS_START and ctr = 0) then + elsif (current_state = CTS_START and ctr = 1) then cts_start_readout <= '1'; elsif (current_state = CLOSE) then cts_start_readout <= '0'; @@ -476,24 +489,24 @@ begin end if; end if; end process; - + process(rst, CLK) begin if rst = '1' then trigger_type <= x"1"; elsif rising_edge(CLK) then --- if (cts_number > x"0008" and cts_number < x"000b") then --- trigger_type <= x"2"; --- else --- trigger_type <= x"1"; --- end if; + -- if (cts_number > x"0008" and cts_number < x"000b") then + -- trigger_type <= x"2"; + -- else + -- trigger_type <= x"1"; + -- end if; --trigger_type <= cts_number(3 downto 0); trigger_type <= x"1"; end if; end process; - + bank_select <= trigger_type; - + process(CLK) begin if rising_edge(CLK) then @@ -502,13 +515,13 @@ begin elsif (current_state = FEE_START and ctr = 0) then fee_busy <= '1'; elsif (current_state = LOWER_BUSY) then - fee_busy <= '0'; + fee_busy <= '0'; else fee_busy <= fee_busy; end if; end if; end process; - + process(CLK) begin if rising_edge(CLK) then @@ -524,20 +537,20 @@ begin fee_dready <= '1'; elsif (current_state = WAIT_FOR_READ_6) then fee_dready <= '1'; - elsif (current_state = LOOP_OVER_DATA and FEE_READ_IN = '1') then - fee_dready <= '1'; +-- elsif (current_state = LOOP_OVER_DATA) then +-- fee_dready <= '1'; elsif (current_state = SEND_ONE_WORD) then -- and ctr = send_word_pause) then - fee_dready <= '1'; + fee_dready <= '1'; else fee_dready <= '0'; end if; end if; end process; - + process(CLK) begin if rising_edge(CLK) then - case current_state is + case current_state is when WAIT_FOR_READ_1 => fee_data <= x"00bb"; when WAIT_FOR_READ_2 => @@ -559,7 +572,7 @@ begin end case; end if; end process; - + process(CLK) begin if rising_edge(CLK) then @@ -572,55 +585,63 @@ begin end if; end if; end process; - - + static_incr_gen : if UP_DOWN_MODE = 0 generate - process(CLK) begin if rising_edge(CLK) then - if (current_state = CLOSE) then + if (current_state = CLOSE and CTS_READOUT_FINISHED_IN = '1') then constructed_events <= constructed_events + x"1"; else constructed_events <= constructed_events; end if; end if; end process; - + end generate static_incr_gen; - + up_down_gen : if UP_DOWN_MODE = 1 generate - process(CLK) begin if rising_edge(CLK) then - if (current_state = CLOSE) then + if (current_state = CLOSE and CTS_READOUT_FINISHED_IN = '1') then if (increment_flag = '1') then constructed_events <= constructed_events + x"1"; else constructed_events <= constructed_events - x"1"; - end if; + end if; else constructed_events <= constructed_events; end if; end if; end process; - + process(CLK) begin if rising_edge(CLK) then - if (current_state = CLOSE and test_data_len = UP_DOWN_LIMIT) then + if (current_state = CLOSE and CTS_READOUT_FINISHED_IN = '1' and test_data_len = UP_DOWN_LIMIT) then increment_flag <= '0'; - elsif (current_state = CLOSE and test_data_len = FIXED_SIZE) then + elsif (current_state = CLOSE and CTS_READOUT_FINISHED_IN = '1' and test_data_len = FIXED_SIZE) then increment_flag <= '1'; else increment_flag <= increment_flag; end if; end if; end process; - + end generate up_down_gen; - - + + process(CLK) + begin + if rising_edge(CLK) then + if rst = '1' then + evt_ctr <= (others => '0'); + elsif current_state = CLOSE and CTS_READOUT_FINISHED_IN = '1' then + evt_ctr <= evt_ctr + x"1"; + else + evt_ctr <= evt_ctr; + end if; + end if; + end process; end architecture RTL; diff --git a/gbe_trb/base/gbe_ipu_multiplexer.vhd b/gbe_trb/base/gbe_ipu_multiplexer.vhd index 3c73e48..bff7d1d 100644 --- a/gbe_trb/base/gbe_ipu_multiplexer.vhd +++ b/gbe_trb/base/gbe_ipu_multiplexer.vhd @@ -10,18 +10,6 @@ use work.trb_net_components.all; use work.trb_net_gbe_components.all; use work.trb_net_gbe_protocols.all; ---package vector_func is ---function find_next_active_link(v : std_logic_vector; s : integer) return integer is --- variable next_one : integer range 0 to v'length - 1; ---begin --- if (s) --- for i in s + 1 to v'length - 1 loop --- if (v(i) = '1') then next_one := i; end if; --- end loop; --- return next_one; --- end function find_next_active_link; ---end package; - entity gbe_ipu_multiplexer is generic( DO_SIMULATION : integer range 0 to 1 := 0; diff --git a/gbe_trb/base/gbe_logic_wrapper.vhd b/gbe_trb/base/gbe_logic_wrapper.vhd index 4d81fa8..55a9ec4 100644 --- a/gbe_trb/base/gbe_logic_wrapper.vhd +++ b/gbe_trb/base/gbe_logic_wrapper.vhd @@ -1,7 +1,7 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_ARITH.all; +use IEEE.std_logic_UNSIGNED.all; library work; use work.trb_net_std.all; @@ -11,905 +11,872 @@ use work.trb_net_gbe_components.all; use work.trb_net_gbe_protocols.all; entity gbe_logic_wrapper is - generic ( - DO_SIMULATION : integer range 0 to 1; - INCLUDE_DEBUG : integer range 0 to 1; + generic( + DO_SIMULATION : integer range 0 to 1; + INCLUDE_DEBUG : integer range 0 to 1; USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1; - RX_PATH_ENABLE : integer range 0 to 1; - - INCLUDE_READOUT : std_logic := '0'; - INCLUDE_SLOWCTRL : std_logic := '0'; - INCLUDE_DHCP : std_logic := '0'; - INCLUDE_ARP : std_logic := '0'; - INCLUDE_PING : std_logic := '0'; - - FRAME_BUFFER_SIZE : integer range 1 to 4 := 1; - READOUT_BUFFER_SIZE : integer range 1 to 4 := 1; - SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 := 1; - - FIXED_SIZE_MODE : integer range 0 to 1 := 1; - INCREMENTAL_MODE : integer range 0 to 1 := 0; - FIXED_SIZE : integer range 0 to 65535 := 10; - FIXED_DELAY_MODE : integer range 0 to 1 := 1; - UP_DOWN_MODE : integer range 0 to 1 := 0; - UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; - FIXED_DELAY : integer range 0 to 16777215 := 16777215 + RX_PATH_ENABLE : integer range 0 to 1; + + INCLUDE_READOUT : std_logic := '0'; + INCLUDE_SLOWCTRL : std_logic := '0'; + INCLUDE_DHCP : std_logic := '0'; + INCLUDE_ARP : std_logic := '0'; + INCLUDE_PING : std_logic := '0'; + + FRAME_BUFFER_SIZE : integer range 1 to 4 := 1; + READOUT_BUFFER_SIZE : integer range 1 to 4 := 1; + SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 := 1; + + FIXED_SIZE_MODE : integer range 0 to 1 := 1; + INCREMENTAL_MODE : integer range 0 to 1 := 0; + FIXED_SIZE : integer range 0 to 65535 := 10; + FIXED_DELAY_MODE : integer range 0 to 1 := 1; + UP_DOWN_MODE : integer range 0 to 1 := 0; + UP_DOWN_LIMIT : integer range 0 to 16777215 := 0; + FIXED_DELAY : integer range 0 to 16777215 := 16777215 ); - port ( - CLK_SYS_IN : in std_logic; - CLK_125_IN : in std_logic; - CLK_RX_125_IN : in std_logic; - RESET : in std_logic; - GSR_N : in std_logic; - - MY_MAC_OUT : out std_logic_vector(47 downto 0); - MY_MAC_IN : in std_logic_vector(47 downto 0); - DHCP_DONE_OUT : out std_logic; - - -- connection to MAC - MAC_READY_CONF_IN : in std_logic; - MAC_RECONF_OUT : out std_logic; - MAC_AN_READY_IN : in std_logic; - - MAC_FIFOAVAIL_OUT : out std_logic; - MAC_FIFOEOF_OUT : out std_logic; - MAC_FIFOEMPTY_OUT : out std_logic; - MAC_RX_FIFOFULL_OUT : out std_logic; - - MAC_TX_DATA_OUT : out std_logic_vector(7 downto 0); - MAC_TX_READ_IN : in std_logic; - MAC_TX_DISCRFRM_IN : in std_logic; - MAC_TX_STAT_EN_IN : in std_logic; - MAC_TX_STATS_IN : in std_logic_vector(30 downto 0); - MAC_TX_DONE_IN : in std_logic; - - MAC_RX_FIFO_ERR_IN : in std_logic; - MAC_RX_STATS_IN : in std_logic_vector(31 downto 0); - MAC_RX_DATA_IN : in std_logic_vector(7 downto 0); - MAC_RX_WRITE_IN : in std_logic; - MAC_RX_STAT_EN_IN : in std_logic; - MAC_RX_EOF_IN : in std_logic; - MAC_RX_ERROR_IN : in std_logic; - - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic; - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - FEE_BUSY_IN : in std_logic; - -- SlowControl - MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); - GSC_CLK_IN : in std_logic; + port( + CLK_SYS_IN : in std_logic; + CLK_125_IN : in std_logic; + CLK_RX_125_IN : in std_logic; + RESET : in std_logic; + GSR_N : in std_logic; + + MY_MAC_OUT : out std_logic_vector(47 downto 0); + MY_MAC_IN : in std_logic_vector(47 downto 0); + DHCP_DONE_OUT : out std_logic; + + -- connection to MAC + MAC_READY_CONF_IN : in std_logic; + MAC_RECONF_OUT : out std_logic; + MAC_AN_READY_IN : in std_logic; + + MAC_FIFOAVAIL_OUT : out std_logic; + MAC_FIFOEOF_OUT : out std_logic; + MAC_FIFOEMPTY_OUT : out std_logic; + MAC_RX_FIFOFULL_OUT : out std_logic; + + MAC_TX_DATA_OUT : out std_logic_vector(7 downto 0); + MAC_TX_READ_IN : in std_logic; + MAC_TX_DISCRFRM_IN : in std_logic; + MAC_TX_STAT_EN_IN : in std_logic; + MAC_TX_STATS_IN : in std_logic_vector(30 downto 0); + MAC_TX_DONE_IN : in std_logic; + + MAC_RX_FIFO_ERR_IN : in std_logic; + MAC_RX_STATS_IN : in std_logic_vector(31 downto 0); + MAC_RX_DATA_IN : in std_logic_vector(7 downto 0); + MAC_RX_WRITE_IN : in std_logic; + MAC_RX_STAT_EN_IN : in std_logic; + MAC_RX_EOF_IN : in std_logic; + MAC_RX_ERROR_IN : in std_logic; + + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector(15 downto 0); + CTS_CODE_IN : in std_logic_vector(7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector(7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector(31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector(15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector(15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0); + FEE_BUSY_IN : in std_logic; + -- SlowControl + MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); + GSC_CLK_IN : in std_logic; GSC_INIT_DATAREADY_OUT : out std_logic; GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_INIT_READ_IN : in std_logic; - GSC_REPLY_DATAREADY_IN : in std_logic; - GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + GSC_INIT_READ_IN : in std_logic; + GSC_REPLY_DATAREADY_IN : in std_logic; + GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); GSC_REPLY_READ_OUT : out std_logic; - GSC_BUSY_IN : in std_logic; - -- IP configuration - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- configuration of gbe core - CFG_GBE_ENABLE_IN : in std_logic; - CFG_IPU_ENABLE_IN : in std_logic; - CFG_MULT_ENABLE_IN : in std_logic; - CFG_MAX_FRAME_IN : in std_logic_vector(15 downto 0); - CFG_ALLOW_RX_IN : in std_logic; - CFG_SOFT_RESET_IN : in std_logic; - CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); - CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); - CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); - CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); - CFG_READOUT_CTR_VALID_IN : in std_logic; - CFG_INSERT_TTYPE_IN : in std_logic; - CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); - CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); - CFG_ADDITIONAL_HDR_IN : in std_logic; - CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0); - - MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0); - MONITOR_TX_BYTES_OUT : out std_logic_vector(31 downto 0); - MONITOR_TX_FRAMES_OUT : out std_logic_vector(31 downto 0); - MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0); - MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0); - - MAKE_RESET_OUT : out std_logic + GSC_BUSY_IN : in std_logic; + -- IP configuration + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- configuration of gbe core + CFG_GBE_ENABLE_IN : in std_logic; + CFG_IPU_ENABLE_IN : in std_logic; + CFG_MULT_ENABLE_IN : in std_logic; + CFG_MAX_FRAME_IN : in std_logic_vector(15 downto 0); + CFG_ALLOW_RX_IN : in std_logic; + CFG_SOFT_RESET_IN : in std_logic; + CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); + CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); + CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); + CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); + CFG_READOUT_CTR_VALID_IN : in std_logic; + CFG_INSERT_TTYPE_IN : in std_logic; + CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); + CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); + CFG_ADDITIONAL_HDR_IN : in std_logic; + CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0); + + MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0); + MONITOR_TX_BYTES_OUT : out std_logic_vector(31 downto 0); + MONITOR_TX_FRAMES_OUT : out std_logic_vector(31 downto 0); + MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0); + MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0); + MONITOR_GEN_DBG_OUT : out std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0); + + MAKE_RESET_OUT : out std_logic ); end entity gbe_logic_wrapper; architecture RTL of gbe_logic_wrapper is - - signal fr_q : std_logic_vector(8 downto 0); - signal fr_rd_en : std_logic; - signal fr_frame_valid : std_logic; - signal rc_rd_en : std_logic; - signal rc_q : std_logic_vector(8 downto 0); - signal rc_frames_rec_ctr : std_logic_vector(31 downto 0); - signal mc_data : std_logic_vector(8 downto 0); - signal mc_wr_en : std_logic; - signal fc_wr_en : std_logic; - signal fc_data : std_logic_vector(7 downto 0); - signal fc_ip_size : std_logic_vector(15 downto 0); - signal fc_udp_size : std_logic_vector(15 downto 0); - signal fc_ident : std_logic_vector(15 downto 0); - signal fc_flags_offset : std_logic_vector(15 downto 0); - signal fc_sod : std_logic; - signal fc_eod : std_logic; - signal fc_h_ready : std_logic; - signal fc_ready : std_logic; - signal rc_frame_ready : std_logic; - signal fr_frame_size : std_logic_vector(15 downto 0); - signal rc_frame_size : std_logic_vector(15 downto 0); - signal mc_frame_size : std_logic_vector(15 downto 0); - signal rc_bytes_rec : std_logic_vector(31 downto 0); - signal rc_debug : std_logic_vector(63 downto 0); - signal mc_transmit_ctrl : std_logic; - signal rc_loading_done : std_logic; - signal fr_get_frame : std_logic; - signal mc_transmit_done : std_logic; - - signal fr_frame_proto : std_logic_vector(15 downto 0); - signal rc_frame_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - - signal mc_type : std_logic_vector(15 downto 0); - signal fr_src_mac : std_logic_vector(47 downto 0); - signal fr_dest_mac : std_logic_vector(47 downto 0); - signal fr_src_ip : std_logic_vector(31 downto 0); - signal fr_dest_ip : std_logic_vector(31 downto 0); - signal fr_src_udp : std_logic_vector(15 downto 0); - signal fr_dest_udp : std_logic_vector(15 downto 0); - signal rc_src_mac : std_logic_vector(47 downto 0); - signal rc_dest_mac : std_logic_vector(47 downto 0); - signal rc_src_ip : std_logic_vector(31 downto 0); - signal rc_dest_ip : std_logic_vector(31 downto 0); - signal rc_src_udp : std_logic_vector(15 downto 0); - signal rc_dest_udp : std_logic_vector(15 downto 0); - - signal mc_dest_mac : std_logic_vector(47 downto 0); - signal mc_dest_ip : std_logic_vector(31 downto 0); - signal mc_dest_udp : std_logic_vector(15 downto 0); - signal mc_src_mac : std_logic_vector(47 downto 0); - signal mc_src_ip : std_logic_vector(31 downto 0); - signal mc_src_udp : std_logic_vector(15 downto 0); - - signal fc_dest_mac : std_logic_vector(47 downto 0); - signal fc_dest_ip : std_logic_vector(31 downto 0); - signal fc_dest_udp : std_logic_vector(15 downto 0); - signal fc_src_mac : std_logic_vector(47 downto 0); - signal fc_src_ip : std_logic_vector(31 downto 0); - signal fc_src_udp : std_logic_vector(15 downto 0); - signal fc_type : std_logic_vector(15 downto 0); - signal fc_ihl_version : std_logic_vector(7 downto 0); - signal fc_tos : std_logic_vector(7 downto 0); - signal fc_ttl : std_logic_vector(7 downto 0); - signal fc_protocol : std_logic_vector(7 downto 0); - - signal ft_data : std_logic_vector(8 downto 0); - signal ft_tx_empty : std_logic; - signal ft_start_of_packet : std_logic; - signal ft_bsm_init : std_logic_vector(3 downto 0); - signal ft_bsm_mac : std_logic_vector(3 downto 0); - signal ft_bsm_trans : std_logic_vector(3 downto 0); - - signal gbe_cts_number : std_logic_vector(15 downto 0); - signal gbe_cts_code : std_logic_vector(7 downto 0); - signal gbe_cts_information : std_logic_vector(7 downto 0); - signal gbe_cts_start_readout : std_logic; - signal gbe_cts_readout_type : std_logic_vector(3 downto 0); - signal gbe_cts_readout_finished : std_logic; - signal gbe_cts_status_bits : std_logic_vector(31 downto 0); - signal gbe_fee_data : std_logic_vector(15 downto 0); - signal gbe_fee_dataready : std_logic; - signal gbe_fee_read : std_logic; - signal gbe_fee_status_bits : std_logic_vector(31 downto 0); - signal gbe_fee_busy : std_logic; - - signal fr_ip_proto : std_logic_vector(7 downto 0); - signal mc_ip_proto : std_logic_vector(7 downto 0); - signal mc_ident : std_logic_vector(15 downto 0); - - signal dbg_select_rec : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - signal dbg_select_sent : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - signal dbg_select_rec_bytes : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - signal dbg_select_sent_bytes : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - signal dbg_select_drop_in : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - signal dbg_select_drop_out : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - signal dbg_select_gen : std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); - - signal global_reset, rst_n, ff : std_logic; - signal link_ok, dhcp_done : std_logic; - + signal fr_q : std_logic_vector(8 downto 0); + signal fr_rd_en : std_logic; + signal fr_frame_valid : std_logic; + signal rc_rd_en : std_logic; + signal rc_q : std_logic_vector(8 downto 0); + signal rc_frames_rec_ctr : std_logic_vector(31 downto 0); + signal mc_data : std_logic_vector(8 downto 0); + signal mc_wr_en : std_logic; + signal fc_wr_en : std_logic; + signal fc_data : std_logic_vector(7 downto 0); + signal fc_ip_size : std_logic_vector(15 downto 0); + signal fc_udp_size : std_logic_vector(15 downto 0); + signal fc_ident : std_logic_vector(15 downto 0); + signal fc_flags_offset : std_logic_vector(15 downto 0); + signal fc_sod : std_logic; + signal fc_eod : std_logic; + signal fc_h_ready : std_logic; + signal fc_ready : std_logic; + signal rc_frame_ready : std_logic; + signal fr_frame_size : std_logic_vector(15 downto 0); + signal rc_frame_size : std_logic_vector(15 downto 0); + signal mc_frame_size : std_logic_vector(15 downto 0); + signal rc_bytes_rec : std_logic_vector(31 downto 0); + signal rc_debug : std_logic_vector(63 downto 0); + signal mc_transmit_ctrl : std_logic; + signal rc_loading_done : std_logic; + signal fr_get_frame : std_logic; + signal mc_transmit_done : std_logic; + + signal fr_frame_proto : std_logic_vector(15 downto 0); + signal rc_frame_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + + signal mc_type : std_logic_vector(15 downto 0); + signal fr_src_mac : std_logic_vector(47 downto 0); + signal fr_dest_mac : std_logic_vector(47 downto 0); + signal fr_src_ip : std_logic_vector(31 downto 0); + signal fr_dest_ip : std_logic_vector(31 downto 0); + signal fr_src_udp : std_logic_vector(15 downto 0); + signal fr_dest_udp : std_logic_vector(15 downto 0); + signal rc_src_mac : std_logic_vector(47 downto 0); + signal rc_dest_mac : std_logic_vector(47 downto 0); + signal rc_src_ip : std_logic_vector(31 downto 0); + signal rc_dest_ip : std_logic_vector(31 downto 0); + signal rc_src_udp : std_logic_vector(15 downto 0); + signal rc_dest_udp : std_logic_vector(15 downto 0); + + signal mc_dest_mac : std_logic_vector(47 downto 0); + signal mc_dest_ip : std_logic_vector(31 downto 0); + signal mc_dest_udp : std_logic_vector(15 downto 0); + signal mc_src_mac : std_logic_vector(47 downto 0); + signal mc_src_ip : std_logic_vector(31 downto 0); + signal mc_src_udp : std_logic_vector(15 downto 0); + + signal fc_dest_mac : std_logic_vector(47 downto 0); + signal fc_dest_ip : std_logic_vector(31 downto 0); + signal fc_dest_udp : std_logic_vector(15 downto 0); + signal fc_src_mac : std_logic_vector(47 downto 0); + signal fc_src_ip : std_logic_vector(31 downto 0); + signal fc_src_udp : std_logic_vector(15 downto 0); + signal fc_type : std_logic_vector(15 downto 0); + signal fc_ihl_version : std_logic_vector(7 downto 0); + signal fc_tos : std_logic_vector(7 downto 0); + signal fc_ttl : std_logic_vector(7 downto 0); + signal fc_protocol : std_logic_vector(7 downto 0); + + signal ft_data : std_logic_vector(8 downto 0); + signal ft_tx_empty : std_logic; + signal ft_start_of_packet : std_logic; + signal ft_bsm_init : std_logic_vector(3 downto 0); + signal ft_bsm_mac : std_logic_vector(3 downto 0); + signal ft_bsm_trans : std_logic_vector(3 downto 0); + + signal gbe_cts_number : std_logic_vector(15 downto 0); + signal gbe_cts_code : std_logic_vector(7 downto 0); + signal gbe_cts_information : std_logic_vector(7 downto 0); + signal gbe_cts_start_readout : std_logic; + signal gbe_cts_readout_type : std_logic_vector(3 downto 0); + signal gbe_cts_readout_finished : std_logic; + signal gbe_cts_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_data : std_logic_vector(15 downto 0); + signal gbe_fee_dataready : std_logic; + signal gbe_fee_read : std_logic; + signal gbe_fee_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_busy : std_logic; + + signal fr_ip_proto : std_logic_vector(7 downto 0); + signal mc_ip_proto : std_logic_vector(7 downto 0); + signal mc_ident : std_logic_vector(15 downto 0); + + signal dbg_select_rec : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal dbg_select_sent : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal dbg_select_rec_bytes : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal dbg_select_sent_bytes : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal dbg_select_drop_in : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal dbg_select_drop_out : std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + signal dbg_select_gen : std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0); + + signal global_reset, rst_n, ff : std_logic; + signal link_ok, dhcp_done : std_logic; + signal dum_busy, dum_read, dum_dataready : std_logic; - signal dum_data : std_logic_vector(15 downto 0); - - signal monitor_tx_packets : std_logic_vector(31 downto 0); + signal dum_data : std_logic_vector(15 downto 0); + + signal monitor_tx_packets : std_logic_vector(31 downto 0); signal monitor_rx_bytes, monitor_rx_frames, monitor_tx_bytes, monitor_tx_frames : std_logic_vector(31 downto 0); - + signal dbg_hist, dbg_hist2 : hist_array; - signal monitor_dropped : std_logic_vector(31 downto 0); - signal dbg_ft : std_logic_vector(63 downto 0); - signal dbg_q : std_logic_vector(15 downto 0); - signal make_reset : std_logic; - signal my_mac : std_logic_vector(47 downto 0); - + signal monitor_dropped : std_logic_vector(31 downto 0); + signal dbg_ft : std_logic_vector(63 downto 0); + signal dbg_q : std_logic_vector(15 downto 0); + signal make_reset : std_logic; + signal my_mac : std_logic_vector(47 downto 0); + begin - reset_sync : process(GSR_N, CLK_SYS_IN) begin if (GSR_N = '0') then - ff <= '0'; + ff <= '0'; rst_n <= '0'; elsif rising_edge(CLK_SYS_IN) then - ff <= '1'; + ff <= '1'; rst_n <= ff; end if; end process reset_sync; - + global_reset <= not rst_n; - - fc_ihl_version <= x"45"; - fc_tos <= x"10"; - fc_ttl <= x"ff"; - - MY_MAC_OUT <= my_mac; - DHCP_DONE_OUT <= dhcp_done; + fc_ihl_version <= x"45"; + fc_tos <= x"10"; + fc_ttl <= x"ff"; + + MY_MAC_OUT <= my_mac; + DHCP_DONE_OUT <= dhcp_done; main_gen : if USE_INTERNAL_TRBNET_DUMMY = 0 generate - MAIN_CONTROL : trb_net16_gbe_main_control + MAIN_CONTROL : entity work.trb_net16_gbe_main_control generic map( - RX_PATH_ENABLE => RX_PATH_ENABLE, - DO_SIMULATION => DO_SIMULATION, - - INCLUDE_READOUT => INCLUDE_READOUT, - INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL, - INCLUDE_DHCP => INCLUDE_DHCP, - INCLUDE_ARP => INCLUDE_ARP, - INCLUDE_PING => INCLUDE_PING, - - READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE, + RX_PATH_ENABLE => RX_PATH_ENABLE, + DO_SIMULATION => DO_SIMULATION, + INCLUDE_READOUT => INCLUDE_READOUT, + INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL, + INCLUDE_DHCP => INCLUDE_DHCP, + INCLUDE_ARP => INCLUDE_ARP, + INCLUDE_PING => INCLUDE_PING, + READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE, SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE - ) - port map( - CLK => CLK_SYS_IN, - CLK_125 => CLK_125_IN, - RESET => RESET, - - MC_LINK_OK_OUT => link_ok, - MC_RESET_LINK_IN => global_reset, - MC_IDLE_TOO_LONG_OUT => open, - MC_DHCP_DONE_OUT => dhcp_done, - MC_MY_MAC_OUT => my_mac, - MC_MY_MAC_IN => MY_MAC_IN, - - -- signals to/from receive controller - RC_FRAME_WAITING_IN => rc_frame_ready, - RC_LOADING_DONE_OUT => rc_loading_done, - RC_DATA_IN => rc_q, - RC_RD_EN_OUT => rc_rd_en, - RC_FRAME_SIZE_IN => rc_frame_size, - RC_FRAME_PROTO_IN => rc_frame_proto, - - RC_SRC_MAC_ADDRESS_IN => rc_src_mac, - RC_DEST_MAC_ADDRESS_IN => rc_dest_mac, - RC_SRC_IP_ADDRESS_IN => rc_src_ip, - RC_DEST_IP_ADDRESS_IN => rc_dest_ip, - RC_SRC_UDP_PORT_IN => rc_src_udp, - RC_DEST_UDP_PORT_IN => rc_dest_udp, - - -- signals to/from transmit controller - TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl, - TC_DATA_OUT => mc_data, - TC_RD_EN_IN => mc_wr_en, - TC_FRAME_SIZE_OUT => mc_frame_size, - TC_FRAME_TYPE_OUT => mc_type, - TC_IP_PROTOCOL_OUT => mc_ip_proto, - TC_IDENT_OUT => mc_ident, - - TC_DEST_MAC_OUT => mc_dest_mac, - TC_DEST_IP_OUT => mc_dest_ip, - TC_DEST_UDP_OUT => mc_dest_udp, - TC_SRC_MAC_OUT => mc_src_mac, - TC_SRC_IP_OUT => mc_src_ip, - TC_SRC_UDP_OUT => mc_src_udp, - TC_TRANSMIT_DONE_IN => mc_transmit_done, - - -- signals to/from sgmii/gbe pcs_an_complete - PCS_AN_COMPLETE_IN => MAC_AN_READY_IN, - - -- signals to/from hub - MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN, - GSC_CLK_IN => GSC_CLK_IN, - GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, - GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, - GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, - GSC_INIT_READ_IN => GSC_INIT_READ_IN, - GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN, - GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN, - GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, - GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT, - GSC_BUSY_IN => GSC_BUSY_IN, - - MAKE_RESET_OUT => make_reset, --MAKE_RESET_OUT, - + ) + port map( + CLK => CLK_SYS_IN, + CLK_125 => CLK_125_IN, + RESET => RESET, + MC_LINK_OK_OUT => link_ok, + MC_RESET_LINK_IN => global_reset, + MC_IDLE_TOO_LONG_OUT => open, + MC_DHCP_DONE_OUT => dhcp_done, + MC_MY_MAC_OUT => my_mac, + MC_MY_MAC_IN => MY_MAC_IN, + + -- signals to/from receive controller + RC_FRAME_WAITING_IN => rc_frame_ready, + RC_LOADING_DONE_OUT => rc_loading_done, + RC_DATA_IN => rc_q, + RC_RD_EN_OUT => rc_rd_en, + RC_FRAME_SIZE_IN => rc_frame_size, + RC_FRAME_PROTO_IN => rc_frame_proto, + RC_SRC_MAC_ADDRESS_IN => rc_src_mac, + RC_DEST_MAC_ADDRESS_IN => rc_dest_mac, + RC_SRC_IP_ADDRESS_IN => rc_src_ip, + RC_DEST_IP_ADDRESS_IN => rc_dest_ip, + RC_SRC_UDP_PORT_IN => rc_src_udp, + RC_DEST_UDP_PORT_IN => rc_dest_udp, + + -- signals to/from transmit controller + TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl, + TC_DATA_OUT => mc_data, + TC_RD_EN_IN => mc_wr_en, + TC_FRAME_SIZE_OUT => mc_frame_size, + TC_FRAME_TYPE_OUT => mc_type, + TC_IP_PROTOCOL_OUT => mc_ip_proto, + TC_IDENT_OUT => mc_ident, + TC_DEST_MAC_OUT => mc_dest_mac, + TC_DEST_IP_OUT => mc_dest_ip, + TC_DEST_UDP_OUT => mc_dest_udp, + TC_SRC_MAC_OUT => mc_src_mac, + TC_SRC_IP_OUT => mc_src_ip, + TC_SRC_UDP_OUT => mc_src_udp, + TC_TRANSMIT_DONE_IN => mc_transmit_done, + + -- signals to/from sgmii/gbe pcs_an_complete + PCS_AN_COMPLETE_IN => MAC_AN_READY_IN, + + -- signals to/from hub + MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN, + GSC_CLK_IN => GSC_CLK_IN, + GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, + GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, + GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, + GSC_INIT_READ_IN => GSC_INIT_READ_IN, + GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN, + GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN, + GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, + GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT, + GSC_BUSY_IN => GSC_BUSY_IN, + MAKE_RESET_OUT => make_reset, --MAKE_RESET_OUT, + + RESET_TRBNET_IN => '0', + RESET_SCTRL_IN => '0', + -- CTS interface - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_READ_IN => CTS_READ_IN, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - -- Data payload interface - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - FEE_BUSY_IN => FEE_BUSY_IN, - -- ip configurator - SLV_ADDR_IN => SLV_ADDR_IN, - SLV_READ_IN => SLV_READ_IN, - SLV_WRITE_IN => SLV_WRITE_IN, - SLV_BUSY_OUT => SLV_BUSY_OUT, - SLV_ACK_OUT => SLV_ACK_OUT, - SLV_DATA_IN => SLV_DATA_IN, - SLV_DATA_OUT => SLV_DATA_OUT, - - CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN, - CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN, - CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN, - CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN, - CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN, - CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN, - CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN, - CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN, - CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN, - CFG_MAX_SUB_IN => CFG_MAX_SUB_IN, - CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN, - CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN, - CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN, - CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN, - CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN, - - TSM_HADDR_OUT => open, --mac_haddr, - TSM_HDATA_OUT => open, --mac_hdataout, - TSM_HCS_N_OUT => open, --mac_hcs, - TSM_HWRITE_N_OUT => open, --mac_hwrite, - TSM_HREAD_N_OUT => open, --mac_hread, - TSM_HREADY_N_IN => '0', --mac_hready, - TSM_HDATA_EN_N_IN => '1', --mac_hdata_en, - TSM_RX_STAT_VEC_IN => (others => '0'), --mac_rx_stat_vec, - TSM_RX_STAT_EN_IN => '0', --mac_rx_stat_en, - - MAC_READY_CONF_IN => MAC_READY_CONF_IN, - MAC_RECONF_OUT => MAC_RECONF_OUT, - - MONITOR_SELECT_REC_OUT => dbg_select_rec, - MONITOR_SELECT_REC_BYTES_OUT => dbg_select_rec_bytes, - MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes, - MONITOR_SELECT_SENT_OUT => dbg_select_sent, - MONITOR_SELECT_DROP_IN_OUT => dbg_select_drop_in, - MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out, - MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen, - - DATA_HIST_OUT => dbg_hist, - SCTRL_HIST_OUT => dbg_hist2 - ); + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_DATA_OUT => CTS_DATA_OUT, + CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_READ_IN => CTS_READ_IN, + CTS_LENGTH_OUT => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, + -- Data payload interface + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + FEE_BUSY_IN => FEE_BUSY_IN, + -- ip configurator + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => SLV_BUSY_OUT, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN, + CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN, + CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN, + CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN, + CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN, + CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN, + CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN, + CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN, + CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN, + CFG_MAX_SUB_IN => CFG_MAX_SUB_IN, + CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN, + CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN, + CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN, + CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN, + CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN, + TSM_HADDR_OUT => open, --mac_haddr, + TSM_HDATA_OUT => open, --mac_hdataout, + TSM_HCS_N_OUT => open, --mac_hcs, + TSM_HWRITE_N_OUT => open, --mac_hwrite, + TSM_HREAD_N_OUT => open, --mac_hread, + TSM_HREADY_N_IN => '0', --mac_hready, + TSM_HDATA_EN_N_IN => '1', --mac_hdata_en, + TSM_RX_STAT_VEC_IN => (others => '0'), --mac_rx_stat_vec, + TSM_RX_STAT_EN_IN => '0', --mac_rx_stat_en, + + MAC_READY_CONF_IN => MAC_READY_CONF_IN, + MAC_RECONF_OUT => MAC_RECONF_OUT, + MONITOR_SELECT_REC_OUT => dbg_select_rec, + MONITOR_SELECT_REC_BYTES_OUT => dbg_select_rec_bytes, + MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes, + MONITOR_SELECT_SENT_OUT => dbg_select_sent, + MONITOR_SELECT_DROP_IN_OUT => dbg_select_drop_in, + MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out, + MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen, + DATA_HIST_OUT => dbg_hist, + SCTRL_HIST_OUT => dbg_hist2 + ); end generate main_gen; - + main_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate - MAIN_CONTROL : trb_net16_gbe_main_control - generic map( - RX_PATH_ENABLE => RX_PATH_ENABLE, - DO_SIMULATION => DO_SIMULATION, - - INCLUDE_READOUT => INCLUDE_READOUT, - INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL, - INCLUDE_DHCP => INCLUDE_DHCP, - INCLUDE_ARP => INCLUDE_ARP, - INCLUDE_PING => INCLUDE_PING, - - READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE, - SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE + MAIN_CONTROL : entity work.trb_net16_gbe_main_control + generic map( + RX_PATH_ENABLE => RX_PATH_ENABLE, + DO_SIMULATION => DO_SIMULATION, + INCLUDE_READOUT => INCLUDE_READOUT, + INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL, + INCLUDE_DHCP => INCLUDE_DHCP, + INCLUDE_ARP => INCLUDE_ARP, + INCLUDE_PING => INCLUDE_PING, + READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE, + SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE ) - port map( - CLK => CLK_SYS_IN, - CLK_125 => CLK_125_IN, - RESET => RESET, - - MC_LINK_OK_OUT => link_ok, - MC_RESET_LINK_IN => global_reset, - MC_IDLE_TOO_LONG_OUT => open, - MC_DHCP_DONE_OUT => dhcp_done, - MC_MY_MAC_OUT => my_mac, - MC_MY_MAC_IN => MY_MAC_IN, - - -- signals to/from receive controller - RC_FRAME_WAITING_IN => rc_frame_ready, - RC_LOADING_DONE_OUT => rc_loading_done, - RC_DATA_IN => rc_q, - RC_RD_EN_OUT => rc_rd_en, - RC_FRAME_SIZE_IN => rc_frame_size, - RC_FRAME_PROTO_IN => rc_frame_proto, - - RC_SRC_MAC_ADDRESS_IN => rc_src_mac, - RC_DEST_MAC_ADDRESS_IN => rc_dest_mac, - RC_SRC_IP_ADDRESS_IN => rc_src_ip, - RC_DEST_IP_ADDRESS_IN => rc_dest_ip, - RC_SRC_UDP_PORT_IN => rc_src_udp, - RC_DEST_UDP_PORT_IN => rc_dest_udp, - - -- signals to/from transmit controller - TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl, - TC_DATA_OUT => mc_data, - TC_RD_EN_IN => mc_wr_en, - --TC_DATA_NOT_VALID_OUT => tc_data_not_valid, - TC_FRAME_SIZE_OUT => mc_frame_size, - TC_FRAME_TYPE_OUT => mc_type, - TC_IP_PROTOCOL_OUT => mc_ip_proto, - TC_IDENT_OUT => mc_ident, - - TC_DEST_MAC_OUT => mc_dest_mac, - TC_DEST_IP_OUT => mc_dest_ip, - TC_DEST_UDP_OUT => mc_dest_udp, - TC_SRC_MAC_OUT => mc_src_mac, - TC_SRC_IP_OUT => mc_src_ip, - TC_SRC_UDP_OUT => mc_src_udp, - TC_TRANSMIT_DONE_IN => mc_transmit_done, - - -- signals to/from sgmii/gbe pcs_an_complete - PCS_AN_COMPLETE_IN => MAC_AN_READY_IN, - - -- signals to/from hub - MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN, - GSC_CLK_IN => GSC_CLK_IN, - GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, - GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, - GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, - GSC_INIT_READ_IN => '1', - GSC_REPLY_DATAREADY_IN => dum_dataready, - GSC_REPLY_DATA_IN => dum_data, - GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, - GSC_REPLY_READ_OUT => dum_read, - GSC_BUSY_IN => dum_busy, - - MAKE_RESET_OUT => make_reset, - - -- CTS interface - CTS_NUMBER_IN => gbe_cts_number, - CTS_CODE_IN => gbe_cts_code, - CTS_INFORMATION_IN => gbe_cts_information, - CTS_READOUT_TYPE_IN => gbe_cts_readout_type, - CTS_START_READOUT_IN => gbe_cts_start_readout, - CTS_DATA_OUT => open, - CTS_DATAREADY_OUT => open, - CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished, - CTS_READ_IN => '1', - CTS_LENGTH_OUT => open, - CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits, - --Data payload interface - FEE_DATA_IN => gbe_fee_data, - FEE_DATAREADY_IN => gbe_fee_dataready, - FEE_READ_OUT => gbe_fee_read, - FEE_STATUS_BITS_IN => gbe_fee_status_bits, - FEE_BUSY_IN => gbe_fee_busy, - -- ip configurator - SLV_ADDR_IN => SLV_ADDR_IN, - SLV_READ_IN => SLV_READ_IN, - SLV_WRITE_IN => SLV_WRITE_IN, - SLV_BUSY_OUT => SLV_BUSY_OUT, - SLV_ACK_OUT => SLV_ACK_OUT, - SLV_DATA_IN => SLV_DATA_IN, - SLV_DATA_OUT => SLV_DATA_OUT, - - CFG_GBE_ENABLE_IN => '1', - CFG_IPU_ENABLE_IN => '0', - CFG_MULT_ENABLE_IN => '0', - CFG_SUBEVENT_ID_IN => x"0000_00cf", - CFG_SUBEVENT_DEC_IN => x"0002_0001", - CFG_QUEUE_DEC_IN => x"0003_0062", - CFG_READOUT_CTR_IN => x"00_0000", - CFG_READOUT_CTR_VALID_IN => '0', - CFG_INSERT_TTYPE_IN => '0', - CFG_MAX_SUB_IN => x"e998", -- 59800 - CFG_MAX_QUEUE_IN => x"ea60", -- 60000 - CFG_MAX_SUBS_IN_QUEUE_IN => x"00c8", -- 200 - CFG_MAX_SINGLE_SUB_IN => x"e998", --x"7d00", -- 32000 - - CFG_ADDITIONAL_HDR_IN => '0', - CFG_MAX_REPLY_SIZE_IN => x"0000_fa00", - - -- signal to/from Host interface of TriSpeed MAC - TSM_HADDR_OUT => open, --mac_haddr, - TSM_HDATA_OUT => open, --mac_hdataout, - TSM_HCS_N_OUT => open, --mac_hcs, - TSM_HWRITE_N_OUT => open, --mac_hwrite, - TSM_HREAD_N_OUT => open, --mac_hread, - TSM_HREADY_N_IN => '0', --mac_hready, - TSM_HDATA_EN_N_IN => '1', --mac_hdata_en, - TSM_RX_STAT_VEC_IN => (others => '0'), --mac_rx_stat_vec, - TSM_RX_STAT_EN_IN => '0', --mac_rx_stat_en, - - MAC_READY_CONF_IN => MAC_READY_CONF_IN, - MAC_RECONF_OUT => MAC_RECONF_OUT, - - MONITOR_SELECT_REC_OUT => dbg_select_rec, - MONITOR_SELECT_REC_BYTES_OUT => dbg_select_rec_bytes, - MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes, - MONITOR_SELECT_SENT_OUT => dbg_select_sent, - MONITOR_SELECT_DROP_IN_OUT => dbg_select_drop_in, - MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out, - MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen, - - DATA_HIST_OUT => dbg_hist, - SCTRL_HIST_OUT => dbg_hist2 - ); - - dummy : gbe_ipu_dummy - generic map( - DO_SIMULATION => DO_SIMULATION, - FIXED_SIZE_MODE => FIXED_SIZE_MODE, - INCREMENTAL_MODE => INCREMENTAL_MODE, - FIXED_SIZE => FIXED_SIZE, - UP_DOWN_MODE => UP_DOWN_MODE, - UP_DOWN_LIMIT => UP_DOWN_LIMIT, - FIXED_DELAY_MODE => FIXED_DELAY_MODE, - FIXED_DELAY => FIXED_DELAY - ) - port map( - clk => CLK_SYS_IN, - rst => RESET, - GBE_READY_IN => dhcp_done, - - CFG_EVENT_SIZE_IN => (others => '0'), - CFG_TRIGGERED_MODE_IN => '0', - TRIGGER_IN => '0', - - CTS_NUMBER_OUT => gbe_cts_number, - CTS_CODE_OUT => gbe_cts_code, - CTS_INFORMATION_OUT => gbe_cts_information, - CTS_READOUT_TYPE_OUT => gbe_cts_readout_type, - CTS_START_READOUT_OUT => gbe_cts_start_readout, - CTS_DATA_IN => (others => '0'), - CTS_DATAREADY_IN => '0', - CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished, - CTS_READ_OUT => open, - CTS_LENGTH_IN => (others => '0'), - CTS_ERROR_PATTERN_IN => gbe_cts_status_bits, - -- Data payload interfac => - FEE_DATA_OUT => gbe_fee_data, - FEE_DATAREADY_OUT => gbe_fee_dataready, - FEE_READ_IN => gbe_fee_read, - FEE_STATUS_BITS_OUT => gbe_fee_status_bits, - FEE_BUSY_OUT => gbe_fee_busy - ); + port map( + CLK => CLK_SYS_IN, + CLK_125 => CLK_125_IN, + RESET => RESET, + MC_LINK_OK_OUT => link_ok, + MC_RESET_LINK_IN => global_reset, + MC_IDLE_TOO_LONG_OUT => open, + MC_DHCP_DONE_OUT => dhcp_done, + MC_MY_MAC_OUT => my_mac, + MC_MY_MAC_IN => MY_MAC_IN, + + -- signals to/from receive controller + RC_FRAME_WAITING_IN => rc_frame_ready, + RC_LOADING_DONE_OUT => rc_loading_done, + RC_DATA_IN => rc_q, + RC_RD_EN_OUT => rc_rd_en, + RC_FRAME_SIZE_IN => rc_frame_size, + RC_FRAME_PROTO_IN => rc_frame_proto, + RC_SRC_MAC_ADDRESS_IN => rc_src_mac, + RC_DEST_MAC_ADDRESS_IN => rc_dest_mac, + RC_SRC_IP_ADDRESS_IN => rc_src_ip, + RC_DEST_IP_ADDRESS_IN => rc_dest_ip, + RC_SRC_UDP_PORT_IN => rc_src_udp, + RC_DEST_UDP_PORT_IN => rc_dest_udp, + + -- signals to/from transmit controller + TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl, + TC_DATA_OUT => mc_data, + TC_RD_EN_IN => mc_wr_en, + --TC_DATA_NOT_VALID_OUT => tc_data_not_valid, + TC_FRAME_SIZE_OUT => mc_frame_size, + TC_FRAME_TYPE_OUT => mc_type, + TC_IP_PROTOCOL_OUT => mc_ip_proto, + TC_IDENT_OUT => mc_ident, + TC_DEST_MAC_OUT => mc_dest_mac, + TC_DEST_IP_OUT => mc_dest_ip, + TC_DEST_UDP_OUT => mc_dest_udp, + TC_SRC_MAC_OUT => mc_src_mac, + TC_SRC_IP_OUT => mc_src_ip, + TC_SRC_UDP_OUT => mc_src_udp, + TC_TRANSMIT_DONE_IN => mc_transmit_done, + + -- signals to/from sgmii/gbe pcs_an_complete + PCS_AN_COMPLETE_IN => MAC_AN_READY_IN, + + -- signals to/from hub + MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN, + GSC_CLK_IN => GSC_CLK_IN, + GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, + GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, + GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, + GSC_INIT_READ_IN => '1', + GSC_REPLY_DATAREADY_IN => dum_dataready, + GSC_REPLY_DATA_IN => dum_data, + GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, + GSC_REPLY_READ_OUT => dum_read, + GSC_BUSY_IN => dum_busy, + MAKE_RESET_OUT => make_reset, + RESET_TRBNET_IN => '0', + RESET_SCTRL_IN => '0', + -- CTS interface + CTS_NUMBER_IN => gbe_cts_number, + CTS_CODE_IN => gbe_cts_code, + CTS_INFORMATION_IN => gbe_cts_information, + CTS_READOUT_TYPE_IN => gbe_cts_readout_type, + CTS_START_READOUT_IN => gbe_cts_start_readout, + CTS_DATA_OUT => open, + CTS_DATAREADY_OUT => open, + CTS_READOUT_FINISHED_OUT => gbe_cts_readout_finished, + CTS_READ_IN => '1', + CTS_LENGTH_OUT => open, + CTS_ERROR_PATTERN_OUT => gbe_cts_status_bits, + --Data payload interface + FEE_DATA_IN => gbe_fee_data, + FEE_DATAREADY_IN => gbe_fee_dataready, + FEE_READ_OUT => gbe_fee_read, + FEE_STATUS_BITS_IN => gbe_fee_status_bits, + FEE_BUSY_IN => gbe_fee_busy, + -- ip configurator + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => SLV_BUSY_OUT, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + CFG_GBE_ENABLE_IN => '1', + CFG_IPU_ENABLE_IN => '0', + CFG_MULT_ENABLE_IN => '0', + CFG_SUBEVENT_ID_IN => x"0000_00cf", + CFG_SUBEVENT_DEC_IN => x"0002_0001", + CFG_QUEUE_DEC_IN => x"0003_0062", + CFG_READOUT_CTR_IN => x"00_0000", + CFG_READOUT_CTR_VALID_IN => '0', + CFG_INSERT_TTYPE_IN => '0', + CFG_MAX_SUB_IN => x"e998", -- 59800 + CFG_MAX_QUEUE_IN => x"ea60", -- 60000 + CFG_MAX_SUBS_IN_QUEUE_IN => x"00c8", -- 200 + CFG_MAX_SINGLE_SUB_IN => x"e998", --x"7d00", -- 32000 + + CFG_ADDITIONAL_HDR_IN => '0', + CFG_MAX_REPLY_SIZE_IN => x"0000_fa00", + + -- signal to/from Host interface of TriSpeed MAC + TSM_HADDR_OUT => open, --mac_haddr, + TSM_HDATA_OUT => open, --mac_hdataout, + TSM_HCS_N_OUT => open, --mac_hcs, + TSM_HWRITE_N_OUT => open, --mac_hwrite, + TSM_HREAD_N_OUT => open, --mac_hread, + TSM_HREADY_N_IN => '0', --mac_hready, + TSM_HDATA_EN_N_IN => '1', --mac_hdata_en, + TSM_RX_STAT_VEC_IN => (others => '0'), --mac_rx_stat_vec, + TSM_RX_STAT_EN_IN => '0', --mac_rx_stat_en, + + MAC_READY_CONF_IN => MAC_READY_CONF_IN, + MAC_RECONF_OUT => MAC_RECONF_OUT, + MONITOR_SELECT_REC_OUT => dbg_select_rec, + MONITOR_SELECT_REC_BYTES_OUT => dbg_select_rec_bytes, + MONITOR_SELECT_SENT_BYTES_OUT => dbg_select_sent_bytes, + MONITOR_SELECT_SENT_OUT => dbg_select_sent, + MONITOR_SELECT_DROP_IN_OUT => dbg_select_drop_in, + MONITOR_SELECT_DROP_OUT_OUT => dbg_select_drop_out, + MONITOR_SELECT_GEN_DBG_OUT => dbg_select_gen, + DATA_HIST_OUT => dbg_hist, + SCTRL_HIST_OUT => dbg_hist2 + ); + + dummy : gbe_ipu_dummy + generic map( + DO_SIMULATION => DO_SIMULATION, + FIXED_SIZE_MODE => FIXED_SIZE_MODE, + INCREMENTAL_MODE => INCREMENTAL_MODE, + FIXED_SIZE => FIXED_SIZE, + UP_DOWN_MODE => UP_DOWN_MODE, + UP_DOWN_LIMIT => UP_DOWN_LIMIT, + FIXED_DELAY_MODE => FIXED_DELAY_MODE, + FIXED_DELAY => FIXED_DELAY + ) + port map( + clk => CLK_SYS_IN, + rst => RESET, + GBE_READY_IN => dhcp_done, + CFG_EVENT_SIZE_IN => (others => '0'), + CFG_TRIGGERED_MODE_IN => '0', + TRIGGER_IN => '0', + CTS_NUMBER_OUT => gbe_cts_number, + CTS_CODE_OUT => gbe_cts_code, + CTS_INFORMATION_OUT => gbe_cts_information, + CTS_READOUT_TYPE_OUT => gbe_cts_readout_type, + CTS_START_READOUT_OUT => gbe_cts_start_readout, + CTS_DATA_IN => (others => '0'), + CTS_DATAREADY_IN => '0', + CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished, + CTS_READ_OUT => open, + CTS_LENGTH_IN => (others => '0'), + CTS_ERROR_PATTERN_IN => gbe_cts_status_bits, + -- Data payload interfac => + FEE_DATA_OUT => gbe_fee_data, + FEE_DATAREADY_OUT => gbe_fee_dataready, + FEE_READ_IN => gbe_fee_read, + FEE_STATUS_BITS_OUT => gbe_fee_status_bits, + FEE_BUSY_OUT => gbe_fee_busy + ); end generate main_with_dummy_gen; - - MAKE_RESET_OUT <= make_reset; -- or idle_too_long; + + MAKE_RESET_OUT <= make_reset; -- or idle_too_long; transmit_gen : if USE_INTERNAL_TRBNET_DUMMY = 0 generate - TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2 - port map( - CLK => CLK_SYS_IN, - RESET => global_reset, --RESET, - - -- signal to/from main controller - TC_DATAREADY_IN => mc_transmit_ctrl, - TC_RD_EN_OUT => mc_wr_en, - TC_DATA_IN => mc_data(7 downto 0), - TC_FRAME_SIZE_IN => mc_frame_size, - TC_FRAME_TYPE_IN => mc_type, - TC_IP_PROTOCOL_IN => mc_ip_proto, - TC_DEST_MAC_IN => mc_dest_mac, - TC_DEST_IP_IN => mc_dest_ip, - TC_DEST_UDP_IN => mc_dest_udp, - TC_SRC_MAC_IN => mc_src_mac, - TC_SRC_IP_IN => mc_src_ip, - TC_SRC_UDP_IN => mc_src_udp, - TC_TRANSMISSION_DONE_OUT => mc_transmit_done, - TC_IDENT_IN => mc_ident, - TC_MAX_FRAME_IN => CFG_MAX_FRAME_IN, - - -- signal to/from frame constructor - FC_DATA_OUT => fc_data, - FC_WR_EN_OUT => fc_wr_en, - FC_READY_IN => fc_ready, - FC_H_READY_IN => fc_h_ready, - FC_FRAME_TYPE_OUT => fc_type, - FC_IP_SIZE_OUT => fc_ip_size, - FC_UDP_SIZE_OUT => fc_udp_size, - FC_IDENT_OUT => fc_ident, - FC_FLAGS_OFFSET_OUT => fc_flags_offset, - FC_SOD_OUT => fc_sod, - FC_EOD_OUT => fc_eod, - FC_IP_PROTOCOL_OUT => fc_protocol, - - DEST_MAC_ADDRESS_OUT => fc_dest_mac, - DEST_IP_ADDRESS_OUT => fc_dest_ip, - DEST_UDP_PORT_OUT => fc_dest_udp, - SRC_MAC_ADDRESS_OUT => fc_src_mac, - SRC_IP_ADDRESS_OUT => fc_src_ip, - SRC_UDP_PORT_OUT => fc_src_udp, - - MONITOR_TX_PACKETS_OUT => monitor_tx_packets - ); + port map( + CLK => CLK_SYS_IN, + RESET => global_reset, --RESET, + + -- signal to/from main controller + TC_DATAREADY_IN => mc_transmit_ctrl, + TC_RD_EN_OUT => mc_wr_en, + TC_DATA_IN => mc_data(7 downto 0), + TC_FRAME_SIZE_IN => mc_frame_size, + TC_FRAME_TYPE_IN => mc_type, + TC_IP_PROTOCOL_IN => mc_ip_proto, + TC_DEST_MAC_IN => mc_dest_mac, + TC_DEST_IP_IN => mc_dest_ip, + TC_DEST_UDP_IN => mc_dest_udp, + TC_SRC_MAC_IN => mc_src_mac, + TC_SRC_IP_IN => mc_src_ip, + TC_SRC_UDP_IN => mc_src_udp, + TC_TRANSMISSION_DONE_OUT => mc_transmit_done, + TC_IDENT_IN => mc_ident, + TC_MAX_FRAME_IN => CFG_MAX_FRAME_IN, + + -- signal to/from frame constructor + FC_DATA_OUT => fc_data, + FC_WR_EN_OUT => fc_wr_en, + FC_READY_IN => fc_ready, + FC_H_READY_IN => fc_h_ready, + FC_FRAME_TYPE_OUT => fc_type, + FC_IP_SIZE_OUT => fc_ip_size, + FC_UDP_SIZE_OUT => fc_udp_size, + FC_IDENT_OUT => fc_ident, + FC_FLAGS_OFFSET_OUT => fc_flags_offset, + FC_SOD_OUT => fc_sod, + FC_EOD_OUT => fc_eod, + FC_IP_PROTOCOL_OUT => fc_protocol, + DEST_MAC_ADDRESS_OUT => fc_dest_mac, + DEST_IP_ADDRESS_OUT => fc_dest_ip, + DEST_UDP_PORT_OUT => fc_dest_udp, + SRC_MAC_ADDRESS_OUT => fc_src_mac, + SRC_IP_ADDRESS_OUT => fc_src_ip, + SRC_UDP_PORT_OUT => fc_src_udp, + MONITOR_TX_PACKETS_OUT => monitor_tx_packets + ); end generate transmit_gen; - + transmit_with_dummy_gen : if USE_INTERNAL_TRBNET_DUMMY = 1 generate TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control2 - port map( - CLK => CLK_SYS_IN, - RESET => global_reset, --RESET, - - -- signal to/from main controller - TC_DATAREADY_IN => mc_transmit_ctrl, - TC_RD_EN_OUT => mc_wr_en, - TC_DATA_IN => mc_data(7 downto 0), - TC_FRAME_SIZE_IN => mc_frame_size, - TC_FRAME_TYPE_IN => mc_type, - TC_IP_PROTOCOL_IN => mc_ip_proto, - TC_DEST_MAC_IN => mc_dest_mac, - TC_DEST_IP_IN => mc_dest_ip, - TC_DEST_UDP_IN => mc_dest_udp, - TC_SRC_MAC_IN => mc_src_mac, - TC_SRC_IP_IN => mc_src_ip, - TC_SRC_UDP_IN => mc_src_udp, - TC_TRANSMISSION_DONE_OUT => mc_transmit_done, - TC_IDENT_IN => mc_ident, - TC_MAX_FRAME_IN => CFG_MAX_FRAME_IN, - - -- signal to/from frame constructor - FC_DATA_OUT => fc_data, - FC_WR_EN_OUT => fc_wr_en, - FC_READY_IN => fc_ready, - FC_H_READY_IN => fc_h_ready, - FC_FRAME_TYPE_OUT => fc_type, - FC_IP_SIZE_OUT => fc_ip_size, - FC_UDP_SIZE_OUT => fc_udp_size, - FC_IDENT_OUT => fc_ident, - FC_FLAGS_OFFSET_OUT => fc_flags_offset, - FC_SOD_OUT => fc_sod, - FC_EOD_OUT => fc_eod, - FC_IP_PROTOCOL_OUT => fc_protocol, - - DEST_MAC_ADDRESS_OUT => fc_dest_mac, - DEST_IP_ADDRESS_OUT => fc_dest_ip, - DEST_UDP_PORT_OUT => fc_dest_udp, - SRC_MAC_ADDRESS_OUT => fc_src_mac, - SRC_IP_ADDRESS_OUT => fc_src_ip, - SRC_UDP_PORT_OUT => fc_src_udp, - - MONITOR_TX_PACKETS_OUT => monitor_tx_packets - ); + port map( + CLK => CLK_SYS_IN, + RESET => global_reset, --RESET, + + -- signal to/from main controller + TC_DATAREADY_IN => mc_transmit_ctrl, + TC_RD_EN_OUT => mc_wr_en, + TC_DATA_IN => mc_data(7 downto 0), + TC_FRAME_SIZE_IN => mc_frame_size, + TC_FRAME_TYPE_IN => mc_type, + TC_IP_PROTOCOL_IN => mc_ip_proto, + TC_DEST_MAC_IN => mc_dest_mac, + TC_DEST_IP_IN => mc_dest_ip, + TC_DEST_UDP_IN => mc_dest_udp, + TC_SRC_MAC_IN => mc_src_mac, + TC_SRC_IP_IN => mc_src_ip, + TC_SRC_UDP_IN => mc_src_udp, + TC_TRANSMISSION_DONE_OUT => mc_transmit_done, + TC_IDENT_IN => mc_ident, + TC_MAX_FRAME_IN => CFG_MAX_FRAME_IN, + + -- signal to/from frame constructor + FC_DATA_OUT => fc_data, + FC_WR_EN_OUT => fc_wr_en, + FC_READY_IN => fc_ready, + FC_H_READY_IN => fc_h_ready, + FC_FRAME_TYPE_OUT => fc_type, + FC_IP_SIZE_OUT => fc_ip_size, + FC_UDP_SIZE_OUT => fc_udp_size, + FC_IDENT_OUT => fc_ident, + FC_FLAGS_OFFSET_OUT => fc_flags_offset, + FC_SOD_OUT => fc_sod, + FC_EOD_OUT => fc_eod, + FC_IP_PROTOCOL_OUT => fc_protocol, + DEST_MAC_ADDRESS_OUT => fc_dest_mac, + DEST_IP_ADDRESS_OUT => fc_dest_ip, + DEST_UDP_PORT_OUT => fc_dest_udp, + SRC_MAC_ADDRESS_OUT => fc_src_mac, + SRC_IP_ADDRESS_OUT => fc_src_ip, + SRC_UDP_PORT_OUT => fc_src_udp, + MONITOR_TX_PACKETS_OUT => monitor_tx_packets + ); end generate transmit_with_dummy_gen; - FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr - generic map ( - FRAME_BUFFER_SIZE => FRAME_BUFFER_SIZE - ) - port map( - -- ports for user logic - RESET => global_reset, - CLK => CLK_SYS_IN, - LINK_OK_IN => '1', - -- - WR_EN_IN => fc_wr_en, - DATA_IN => fc_data, - START_OF_DATA_IN => fc_sod, - END_OF_DATA_IN => fc_eod, - IP_F_SIZE_IN => fc_ip_size, - UDP_P_SIZE_IN => fc_udp_size, - HEADERS_READY_OUT => fc_h_ready, - READY_OUT => fc_ready, - DEST_MAC_ADDRESS_IN => fc_dest_mac, - DEST_IP_ADDRESS_IN => fc_dest_ip, - DEST_UDP_PORT_IN => fc_dest_udp, - SRC_MAC_ADDRESS_IN => fc_src_mac, - SRC_IP_ADDRESS_IN => fc_src_ip, - SRC_UDP_PORT_IN => fc_src_udp, - FRAME_TYPE_IN => fc_type, - IHL_VERSION_IN => fc_ihl_version, - TOS_IN => fc_tos, - IDENTIFICATION_IN => fc_ident, - FLAGS_OFFSET_IN => fc_flags_offset, - TTL_IN => fc_ttl, - PROTOCOL_IN => fc_protocol, - FRAME_DELAY_IN => (others => '0'), - - RD_CLK => CLK_125_IN, - FT_DATA_OUT => ft_data, - FT_TX_EMPTY_OUT => ft_tx_empty, - FT_TX_RD_EN_IN => MAC_TX_READ_IN, - FT_START_OF_PACKET_OUT => ft_start_of_packet, - FT_TX_DONE_IN => MAC_TX_DONE_IN, - FT_TX_DISCFRM_IN => MAC_TX_DISCRFRM_IN, - - MONITOR_TX_BYTES_OUT => monitor_tx_bytes, - MONITOR_TX_FRAMES_OUT => monitor_tx_frames - ); - + FRAME_CONSTRUCTOR : trb_net16_gbe_frame_constr + generic map( + FRAME_BUFFER_SIZE => FRAME_BUFFER_SIZE + ) + port map( + -- ports for user logic + RESET => global_reset, + CLK => CLK_SYS_IN, + LINK_OK_IN => '1', + -- + WR_EN_IN => fc_wr_en, + DATA_IN => fc_data, + START_OF_DATA_IN => fc_sod, + END_OF_DATA_IN => fc_eod, + IP_F_SIZE_IN => fc_ip_size, + UDP_P_SIZE_IN => fc_udp_size, + HEADERS_READY_OUT => fc_h_ready, + READY_OUT => fc_ready, + DEST_MAC_ADDRESS_IN => fc_dest_mac, + DEST_IP_ADDRESS_IN => fc_dest_ip, + DEST_UDP_PORT_IN => fc_dest_udp, + SRC_MAC_ADDRESS_IN => fc_src_mac, + SRC_IP_ADDRESS_IN => fc_src_ip, + SRC_UDP_PORT_IN => fc_src_udp, + FRAME_TYPE_IN => fc_type, + IHL_VERSION_IN => fc_ihl_version, + TOS_IN => fc_tos, + IDENTIFICATION_IN => fc_ident, + FLAGS_OFFSET_IN => fc_flags_offset, + TTL_IN => fc_ttl, + PROTOCOL_IN => fc_protocol, + FRAME_DELAY_IN => (others => '0'), + RD_CLK => CLK_125_IN, + FT_DATA_OUT => ft_data, + FT_TX_EMPTY_OUT => ft_tx_empty, + FT_TX_RD_EN_IN => MAC_TX_READ_IN, + FT_START_OF_PACKET_OUT => ft_start_of_packet, + FT_TX_DONE_IN => MAC_TX_DONE_IN, + FT_TX_DISCFRM_IN => MAC_TX_DISCRFRM_IN, + MONITOR_TX_BYTES_OUT => monitor_tx_bytes, + MONITOR_TX_FRAMES_OUT => monitor_tx_frames + ); + MAC_TX_DATA_OUT <= ft_data(7 downto 0); - - dbg_q(15 downto 9) <= (others => '0'); - - FRAME_TRANSMITTER: trb_net16_gbe_frame_trans - port map( - CLK => CLK_SYS_IN, - RESET => global_reset, - LINK_OK_IN => link_ok, - TX_MAC_CLK => CLK_125_IN, - TX_EMPTY_IN => ft_tx_empty, - START_OF_PACKET_IN => ft_start_of_packet, - DATA_ENDFLAG_IN => ft_data(8), - - TX_FIFOAVAIL_OUT => MAC_FIFOAVAIL_OUT, - TX_FIFOEOF_OUT => MAC_FIFOEOF_OUT, - TX_FIFOEMPTY_OUT => MAC_FIFOEMPTY_OUT, - TX_DONE_IN => MAC_TX_DONE_IN, - TX_STAT_EN_IN => MAC_TX_STAT_EN_IN, - TX_STATVEC_IN => MAC_TX_STATS_IN, - TX_DISCFRM_IN => MAC_TX_DISCRFRM_IN, - -- Debug - BSM_INIT_OUT => ft_bsm_init, - BSM_MAC_OUT => ft_bsm_mac, - BSM_TRANS_OUT => ft_bsm_trans, - DBG_RD_DONE_OUT => open, - DBG_INIT_DONE_OUT => open, - DBG_ENABLED_OUT => open, - DEBUG_OUT => dbg_ft - ); - + + dbg_q(15 downto 9) <= (others => '0'); + + FRAME_TRANSMITTER : trb_net16_gbe_frame_trans + port map( + CLK => CLK_SYS_IN, + RESET => global_reset, + LINK_OK_IN => link_ok, + TX_MAC_CLK => CLK_125_IN, + TX_EMPTY_IN => ft_tx_empty, + START_OF_PACKET_IN => ft_start_of_packet, + DATA_ENDFLAG_IN => ft_data(8), + TX_FIFOAVAIL_OUT => MAC_FIFOAVAIL_OUT, + TX_FIFOEOF_OUT => MAC_FIFOEOF_OUT, + TX_FIFOEMPTY_OUT => MAC_FIFOEMPTY_OUT, + TX_DONE_IN => MAC_TX_DONE_IN, + TX_STAT_EN_IN => MAC_TX_STAT_EN_IN, + TX_STATVEC_IN => MAC_TX_STATS_IN, + TX_DISCFRM_IN => MAC_TX_DISCRFRM_IN, + -- Debug + BSM_INIT_OUT => ft_bsm_init, + BSM_MAC_OUT => ft_bsm_mac, + BSM_TRANS_OUT => ft_bsm_trans, + DBG_RD_DONE_OUT => open, + DBG_INIT_DONE_OUT => open, + DBG_ENABLED_OUT => open, + DEBUG_OUT => dbg_ft + ); + rx_enable_gen : if (RX_PATH_ENABLE = 1) generate - RECEIVE_CONTROLLER : trb_net16_gbe_receive_control - port map( - CLK => CLK_SYS_IN, - RESET => global_reset, - + port map( + CLK => CLK_SYS_IN, + RESET => global_reset, + -- signals to/from frame_receiver - RC_DATA_IN => fr_q, - FR_RD_EN_OUT => fr_rd_en, - FR_FRAME_VALID_IN => fr_frame_valid, - FR_GET_FRAME_OUT => fr_get_frame, - FR_FRAME_SIZE_IN => fr_frame_size, - FR_FRAME_PROTO_IN => fr_frame_proto, - FR_IP_PROTOCOL_IN => fr_ip_proto, - - FR_SRC_MAC_ADDRESS_IN => fr_src_mac, - FR_DEST_MAC_ADDRESS_IN => fr_dest_mac, - FR_SRC_IP_ADDRESS_IN => fr_src_ip, - FR_DEST_IP_ADDRESS_IN => fr_dest_ip, - FR_SRC_UDP_PORT_IN => fr_src_udp, - FR_DEST_UDP_PORT_IN => fr_dest_udp, - + RC_DATA_IN => fr_q, + FR_RD_EN_OUT => fr_rd_en, + FR_FRAME_VALID_IN => fr_frame_valid, + FR_GET_FRAME_OUT => fr_get_frame, + FR_FRAME_SIZE_IN => fr_frame_size, + FR_FRAME_PROTO_IN => fr_frame_proto, + FR_IP_PROTOCOL_IN => fr_ip_proto, + FR_SRC_MAC_ADDRESS_IN => fr_src_mac, + FR_DEST_MAC_ADDRESS_IN => fr_dest_mac, + FR_SRC_IP_ADDRESS_IN => fr_src_ip, + FR_DEST_IP_ADDRESS_IN => fr_dest_ip, + FR_SRC_UDP_PORT_IN => fr_src_udp, + FR_DEST_UDP_PORT_IN => fr_dest_udp, + -- signals to/from main controller - RC_RD_EN_IN => rc_rd_en, - RC_Q_OUT => rc_q, - RC_FRAME_WAITING_OUT => rc_frame_ready, - RC_LOADING_DONE_IN => rc_loading_done, - RC_FRAME_SIZE_OUT => rc_frame_size, - RC_FRAME_PROTO_OUT => rc_frame_proto, - - RC_SRC_MAC_ADDRESS_OUT => rc_src_mac, - RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac, - RC_SRC_IP_ADDRESS_OUT => rc_src_ip, - RC_DEST_IP_ADDRESS_OUT => rc_dest_ip, - RC_SRC_UDP_PORT_OUT => rc_src_udp, - RC_DEST_UDP_PORT_OUT => rc_dest_udp, - + RC_RD_EN_IN => rc_rd_en, + RC_Q_OUT => rc_q, + RC_FRAME_WAITING_OUT => rc_frame_ready, + RC_LOADING_DONE_IN => rc_loading_done, + RC_FRAME_SIZE_OUT => rc_frame_size, + RC_FRAME_PROTO_OUT => rc_frame_proto, + RC_SRC_MAC_ADDRESS_OUT => rc_src_mac, + RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac, + RC_SRC_IP_ADDRESS_OUT => rc_src_ip, + RC_DEST_IP_ADDRESS_OUT => rc_dest_ip, + RC_SRC_UDP_PORT_OUT => rc_src_udp, + RC_DEST_UDP_PORT_OUT => rc_dest_udp, + -- statistics - FRAMES_RECEIVED_OUT => rc_frames_rec_ctr, - BYTES_RECEIVED_OUT => rc_bytes_rec, - - DEBUG_OUT => rc_debug - ); - - FRAME_RECEIVER : trb_net16_gbe_frame_receiver - port map( - CLK => CLK_SYS_IN, - RESET => global_reset, - LINK_OK_IN => link_ok, - ALLOW_RX_IN => CFG_ALLOW_RX_IN, - RX_MAC_CLK => CLK_RX_125_IN, - MY_MAC_IN => MY_MAC_IN, - - -- input signals from TS_MAC - MAC_RX_EOF_IN => MAC_RX_EOF_IN, - MAC_RX_ER_IN => MAC_RX_ERROR_IN, - MAC_RXD_IN => MAC_RX_DATA_IN, - MAC_RX_EN_IN => MAC_RX_WRITE_IN, - MAC_RX_FIFO_ERR_IN => MAC_RX_FIFO_ERR_IN, - MAC_RX_FIFO_FULL_OUT => MAC_RX_FIFOFULL_OUT, - MAC_RX_STAT_EN_IN => MAC_RX_STAT_EN_IN, - MAC_RX_STAT_VEC_IN => MAC_RX_STATS_IN, - -- output signal to control logic - FR_Q_OUT => fr_q, - FR_RD_EN_IN => fr_rd_en, - FR_FRAME_VALID_OUT => fr_frame_valid, - FR_GET_FRAME_IN => fr_get_frame, - FR_FRAME_SIZE_OUT => fr_frame_size, - FR_FRAME_PROTO_OUT => fr_frame_proto, - FR_IP_PROTOCOL_OUT => fr_ip_proto, - FR_ALLOWED_TYPES_IN => (others => '1'), --fr_allowed_types, - FR_ALLOWED_IP_IN => (others => '1'), --fr_allowed_ip, - FR_ALLOWED_UDP_IN => (others => '1'), --fr_allowed_udp, - FR_VLAN_ID_IN => (others => '0'), --vlan_id, - - FR_SRC_MAC_ADDRESS_OUT => fr_src_mac, - FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac, - FR_SRC_IP_ADDRESS_OUT => fr_src_ip, - FR_DEST_IP_ADDRESS_OUT => fr_dest_ip, - FR_SRC_UDP_PORT_OUT => fr_src_udp, - FR_DEST_UDP_PORT_OUT => fr_dest_udp, - - MONITOR_RX_BYTES_OUT => monitor_rx_bytes, - MONITOR_RX_FRAMES_OUT => monitor_rx_frames, - MONITOR_DROPPED_OUT => monitor_dropped - ); - + FRAMES_RECEIVED_OUT => rc_frames_rec_ctr, + BYTES_RECEIVED_OUT => rc_bytes_rec, + DEBUG_OUT => rc_debug + ); + + FRAME_RECEIVER : trb_net16_gbe_frame_receiver + port map( + CLK => CLK_SYS_IN, + RESET => global_reset, + LINK_OK_IN => link_ok, + ALLOW_RX_IN => CFG_ALLOW_RX_IN, + RX_MAC_CLK => CLK_RX_125_IN, + MY_MAC_IN => MY_MAC_IN, + + -- input signals from TS_MAC + MAC_RX_EOF_IN => MAC_RX_EOF_IN, + MAC_RX_ER_IN => MAC_RX_ERROR_IN, + MAC_RXD_IN => MAC_RX_DATA_IN, + MAC_RX_EN_IN => MAC_RX_WRITE_IN, + MAC_RX_FIFO_ERR_IN => MAC_RX_FIFO_ERR_IN, + MAC_RX_FIFO_FULL_OUT => MAC_RX_FIFOFULL_OUT, + MAC_RX_STAT_EN_IN => MAC_RX_STAT_EN_IN, + MAC_RX_STAT_VEC_IN => MAC_RX_STATS_IN, + -- output signal to control logic + FR_Q_OUT => fr_q, + FR_RD_EN_IN => fr_rd_en, + FR_FRAME_VALID_OUT => fr_frame_valid, + FR_GET_FRAME_IN => fr_get_frame, + FR_FRAME_SIZE_OUT => fr_frame_size, + FR_FRAME_PROTO_OUT => fr_frame_proto, + FR_IP_PROTOCOL_OUT => fr_ip_proto, + FR_ALLOWED_TYPES_IN => (others => '1'), --fr_allowed_types, + FR_ALLOWED_IP_IN => (others => '1'), --fr_allowed_ip, + FR_ALLOWED_UDP_IN => (others => '1'), --fr_allowed_udp, + FR_VLAN_ID_IN => (others => '0'), --vlan_id, + + FR_SRC_MAC_ADDRESS_OUT => fr_src_mac, + FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac, + FR_SRC_IP_ADDRESS_OUT => fr_src_ip, + FR_DEST_IP_ADDRESS_OUT => fr_dest_ip, + FR_SRC_UDP_PORT_OUT => fr_src_udp, + FR_DEST_UDP_PORT_OUT => fr_dest_udp, + MONITOR_RX_BYTES_OUT => monitor_rx_bytes, + MONITOR_RX_FRAMES_OUT => monitor_rx_frames, + MONITOR_DROPPED_OUT => monitor_dropped + ); + end generate rx_enable_gen; rx_disable_gen : if (RX_PATH_ENABLE = 0) generate - - rc_q <= (others => '0'); - rc_frame_ready <= '0'; - rc_frame_size <= (others => '0'); - rc_frame_proto <= (others => '0'); - - rc_src_mac <= (others => '0'); - rc_dest_mac <= (others => '0'); - rc_src_ip <= (others => '0'); - rc_dest_ip <= (others => '0'); - rc_src_udp <= (others => '0'); - rc_dest_udp <= (others => '0'); - - rc_frames_rec_ctr <= (others => '0'); - rc_bytes_rec <= (others => '0'); - rc_debug <= (others => '0'); - - monitor_rx_bytes <= (others => '0'); - monitor_rx_frames <= (others => '0'); - monitor_dropped <= (others => '0'); - + rc_q <= (others => '0'); + rc_frame_ready <= '0'; + rc_frame_size <= (others => '0'); + rc_frame_proto <= (others => '0'); + + rc_src_mac <= (others => '0'); + rc_dest_mac <= (others => '0'); + rc_src_ip <= (others => '0'); + rc_dest_ip <= (others => '0'); + rc_src_udp <= (others => '0'); + rc_dest_udp <= (others => '0'); + + rc_frames_rec_ctr <= (others => '0'); + rc_bytes_rec <= (others => '0'); + rc_debug <= (others => '0'); + + monitor_rx_bytes <= (others => '0'); + monitor_rx_frames <= (others => '0'); + monitor_dropped <= (others => '0'); + end generate rx_disable_gen; - - + MONITOR_RX_FRAMES_OUT <= monitor_rx_frames; MONITOR_RX_BYTES_OUT <= monitor_rx_bytes; MONITOR_TX_FRAMES_OUT <= monitor_tx_frames; MONITOR_TX_BYTES_OUT <= monitor_tx_bytes; MONITOR_TX_PACKETS_OUT <= monitor_tx_packets; MONITOR_DROPPED_OUT <= monitor_dropped; - - + + MONITOR_GEN_DBG_OUT <= dbg_select_gen; + -- MONITOR_RX_BYTES_OUT <= monitor_rx_bytes(4 * 32 - 1 downto 3 * 32) + monitor_rx_bytes(3 * 32 - 1 downto 2 * 32) + monitor_rx_bytes(2 * 32 - 1 downto 1 * 32) + monitor_rx_bytes(1 * 32 - 1 downto 0 * 32); -- MONITOR_RX_FRAMES_OUT <= monitor_rx_frames(4 * 32 - 1 downto 3 * 32) + monitor_rx_frames(3 * 32 - 1 downto 2 * 32) + monitor_rx_frames(2 * 32 - 1 downto 1 * 32) + monitor_rx_frames(1 * 32 - 1 downto 0 * 32); -- MONITOR_TX_BYTES_OUT <= monitor_tx_bytes(4 * 32 - 1 downto 3 * 32) + monitor_tx_bytes(3 * 32 - 1 downto 2 * 32) + monitor_tx_bytes(2 * 32 - 1 downto 1 * 32) + monitor_tx_bytes(1 * 32 - 1 downto 0 * 32); diff --git a/gbe_trb/base/gbe_med_interface.vhd b/gbe_trb/base/gbe_med_interface.vhd index 82f5fe2..dacb7c4 100644 --- a/gbe_trb/base/gbe_med_interface.vhd +++ b/gbe_trb/base/gbe_med_interface.vhd @@ -269,6 +269,8 @@ end component; signal synced_rst, ff : std_logic; + signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + begin rx_power <= "1111"; @@ -694,7 +696,12 @@ begin if rising_edge(CLK_125_IN) then MAC_TX_READ_OUT <= MAC_FIFOAVAIL_IN; - MAC_TX_DONE_OUT <= MAC_FIFOEOF_IN; + fifo_eof_q <= MAC_FIFOEOF_IN; + fifo_eof_qq <= fifo_eof_q; + fifo_eof_qqq <= fifo_eof_qq; + fifo_eof_qqqq <= fifo_eof_qqq; + + MAC_TX_DONE_OUT <= fifo_eof_qqqq; -- MAC_FIFOEOF_IN; end if; end process; diff --git a/gbe_trb/base/gbe_wrapper.vhd b/gbe_trb/base/gbe_wrapper.vhd index e280976..72f5ab2 100644 --- a/gbe_trb/base/gbe_wrapper.vhd +++ b/gbe_trb/base/gbe_wrapper.vhd @@ -202,6 +202,7 @@ architecture RTL of gbe_wrapper is signal dummy_event : std_logic_vector(15 downto 0); signal dummy_mode : std_logic; signal make_reset0, make_reset1, make_reset2, make_reset3 : std_logic := '0'; + signal monitor_gen_dbg : std_logic_vector(c_MAX_PROTOCOLS * 64 - 1 downto 0); begin @@ -279,7 +280,7 @@ begin INCLUDE_ARP => LINK_HAS_ARP(3), INCLUDE_PING => LINK_HAS_PING(3), FRAME_BUFFER_SIZE => 1, - READOUT_BUFFER_SIZE => 4, + READOUT_BUFFER_SIZE => 2, SLOWCTRL_BUFFER_SIZE => 2, FIXED_SIZE_MODE => FIXED_SIZE_MODE, INCREMENTAL_MODE => INCREMENTAL_MODE, @@ -375,9 +376,14 @@ begin MONITOR_TX_BYTES_OUT => monitor_tx_bytes(4 * 32 - 1 downto 3 * 32), MONITOR_TX_PACKETS_OUT => monitor_tx_packets(4 * 32 - 1 downto 3 * 32), MONITOR_DROPPED_OUT => monitor_dropped(4 * 32 - 1 downto 3 * 32), + MONITOR_GEN_DBG_OUT => monitor_gen_dbg, MAKE_RESET_OUT => make_reset3 ); end generate GEN_LINK_3; + + NO_LINK3_GEN : if (LINKS_ACTIVE(3) = '0') generate + make_reset3 <= '0'; + end generate NO_LINK3_GEN; -- sfp7 GEN_LINK_2 : if (LINKS_ACTIVE(2) = '1') generate @@ -496,9 +502,14 @@ begin MONITOR_TX_BYTES_OUT => monitor_tx_bytes(3 * 32 - 1 downto 2 * 32), MONITOR_TX_PACKETS_OUT => monitor_tx_packets(3 * 32 - 1 downto 2 * 32), MONITOR_DROPPED_OUT => monitor_dropped(3 * 32 - 1 downto 2 * 32), + MONITOR_GEN_DBG_OUT => open, MAKE_RESET_OUT => make_reset2 ); end generate GEN_LINK_2; + + NO_LINK2_GEN : if (LINKS_ACTIVE(2) = '0') generate + make_reset2 <= '0'; + end generate NO_LINK2_GEN; -- sfp6 GEN_LINK_1 : if (LINKS_ACTIVE(1) = '1') generate @@ -617,9 +628,14 @@ begin MONITOR_TX_BYTES_OUT => monitor_tx_bytes(2 * 32 - 1 downto 1 * 32), MONITOR_TX_PACKETS_OUT => monitor_tx_packets(2 * 32 - 1 downto 1 * 32), MONITOR_DROPPED_OUT => monitor_dropped(2 * 32 - 1 downto 1 * 32), + MONITOR_GEN_DBG_OUT => open, MAKE_RESET_OUT => make_reset1 ); end generate GEN_LINK_1; + + NO_LINK1_GEN : if (LINKS_ACTIVE(1) = '0') generate + make_reset1 <= '0'; + end generate NO_LINK1_GEN; -- sfp5 GEN_LINK_0 : if (LINKS_ACTIVE(0) = '1') generate @@ -738,9 +754,14 @@ begin MONITOR_TX_BYTES_OUT => monitor_tx_bytes(1 * 32 - 1 downto 0 * 32), MONITOR_TX_PACKETS_OUT => monitor_tx_packets(1 * 32 - 1 downto 0 * 32), MONITOR_DROPPED_OUT => monitor_dropped(1 * 32 - 1 downto 0 * 32), + MONITOR_GEN_DBG_OUT => open, MAKE_RESET_OUT => make_reset0 ); end generate GEN_LINK_0; + + NO_LINK0_GEN : if (LINKS_ACTIVE(0) = '0') generate + make_reset0 <= '0'; + end generate NO_LINK0_GEN; real_ipu_gen : if USE_EXTERNAL_TRBNET_DUMMY = 0 generate ipu_mult : entity work.gbe_ipu_multiplexer @@ -849,10 +870,10 @@ begin port map( clk => CLK_SYS_IN, rst => RESET, - GBE_READY_IN => '1', --all_links_ready, + GBE_READY_IN => all_links_ready, CFG_EVENT_SIZE_IN => dummy_event, - CFG_TRIGGERED_MODE_IN => dummy_mode, + CFG_TRIGGERED_MODE_IN => '0', TRIGGER_IN => TRIGGER_IN, CTS_NUMBER_OUT => local_cts_number, CTS_CODE_OUT => local_cts_code, @@ -972,7 +993,7 @@ begin MONITOR_SELECT_SENT_IN => (others => '0'), --dbg_select_sent, MONITOR_SELECT_DROP_IN_IN => (others => '0'), --dbg_select_drop_in, MONITOR_SELECT_DROP_OUT_IN => (others => '0'), --dbg_select_drop_out, - MONITOR_SELECT_GEN_DBG_IN => (others => '0'), --dbg_select_gen, + MONITOR_SELECT_GEN_DBG_IN => monitor_gen_dbg, --dbg_select_gen, DUMMY_EVENT_SIZE_OUT => dummy_event, DUMMY_TRIGGERED_MODE_OUT => dummy_mode, @@ -1038,12 +1059,15 @@ begin sum_dropped <= monitor_dropped(4 * 32 - 1 downto 3 * 32) + monitor_dropped(3 * 32 - 1 downto 2 * 32) + monitor_dropped(2 * 32 - 1 downto 1 * 32) + monitor_dropped(1 * 32 - 1 downto 0 * 32); include_debug_gen : if (INCLUDE_DEBUG = 1) generate - DEBUG_OUT(0) <= mac_an_ready(3); - DEBUG_OUT(1) <= clk_125_rx_from_pcs(3); - DEBUG_OUT(2) <= RESET; - DEBUG_OUT(3) <= CLK_125_IN; +-- DEBUG_OUT(0) <= mac_an_ready(3); +-- DEBUG_OUT(1) <= clk_125_rx_from_pcs(3); +-- DEBUG_OUT(2) <= RESET; +-- DEBUG_OUT(3) <= CLK_125_IN; +-- +-- DEBUG_OUT(127 downto 4) <= (others => '0'); - DEBUG_OUT(127 downto 4) <= (others => '0'); + DEBUG_OUT(63 downto 0) <= monitor_gen_dbg(4 * 64 - 1 downto 3 * 64); + DEBUG_OUT(127 downto 65) <= (others => '0'); end generate; @@ -1054,32 +1078,29 @@ begin clk_125_rx_from_pcs(2) <= CLK_125_IN; clk_125_rx_from_pcs(3) <= CLK_125_IN; - process - begin - mac_tx_done(0) <= '0'; - wait until rising_edge(mac_fifoeof(0)); - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_tx_done(0) <= '1'; - wait until rising_edge(clk_125_rx_from_pcs(0)); - end process; + done_generate : for i in 0 to 3 generate + process + begin + mac_tx_done(i) <= '0'; + wait until rising_edge(mac_fifoeof(i)); + wait until rising_edge(clk_125_rx_from_pcs(i)); + wait until rising_edge(clk_125_rx_from_pcs(i)); + wait until rising_edge(clk_125_rx_from_pcs(i)); + wait until rising_edge(clk_125_rx_from_pcs(i)); + wait until rising_edge(clk_125_rx_from_pcs(i)); + wait until rising_edge(clk_125_rx_from_pcs(i)); + mac_tx_done(i) <= '1'; + wait until rising_edge(clk_125_rx_from_pcs(i)); + end process; + end generate done_generate; process begin - mac_tx_done(1) <= '0'; - wait until rising_edge(mac_fifoeof(1)); - wait until rising_edge(clk_125_rx_from_pcs(0)); - mac_tx_done(1) <= '1'; - wait until rising_edge(clk_125_rx_from_pcs(0)); - end process; - - process(clk_125_rx_from_pcs(0)) - begin - if rising_edge(clk_125_rx_from_pcs(0)) then + wait until rising_edge(clk_125_rx_from_pcs(0)); mac_tx_read(0) <= mac_fifoavail(0); mac_tx_read(1) <= mac_fifoavail(1); mac_tx_read(2) <= mac_fifoavail(2); mac_tx_read(3) <= mac_fifoavail(3); - end if; end process; mac_rx_eof(1) <= mac_rx_eof(0); diff --git a/gbe_trb/base/trb_net16_gbe_event_constr.vhd b/gbe_trb/base/trb_net16_gbe_event_constr.vhd index df3cc90..f1c6323 100644 --- a/gbe_trb/base/trb_net16_gbe_event_constr.vhd +++ b/gbe_trb/base/trb_net16_gbe_event_constr.vhd @@ -9,6 +9,8 @@ use work.trb_net_std.all; use work.trb_net_components.all; use work.trb_net16_hub_func.all; +use ieee.math_real.all; + use work.trb_net_gbe_components.all; use work.trb_net_gbe_protocols.all; @@ -45,6 +47,15 @@ entity trb_net16_gbe_event_constr is end entity trb_net16_gbe_event_constr; architecture RTL of trb_net16_gbe_event_constr is + + component random_size is + port( + Clk : in std_logic; + Enb : in std_logic; + Rst : in std_logic; + Dout : out std_logic_vector(31 downto 0)); + end component; + attribute syn_encoding : string; type loadStates is (IDLE, GET_Q_SIZE, START_TRANSFER, LOAD_Q_HEADERS, LOAD_DATA, LOAD_SUB, LOAD_PADDING, LOAD_TERM, CLEANUP); @@ -87,7 +98,17 @@ architecture RTL of trb_net16_gbe_event_constr is signal shf_padding : std_logic; signal block_shf_after_divide, previous_tc_rd : std_logic; signal block_term_after_divide : std_logic; - signal df_full_real, df_afull : std_logic; + signal df_full_real, df_afull : std_logic; + signal df_wcnt : std_logic_vector(16 downto 0); + + attribute syn_keep : string; + attribute syn_keep of df_wcnt : signal is "true"; + signal load_state : std_logic_vector(3 downto 0); + signal evt_ctr : std_logic_vector(31 downto 0); + + signal s : std_logic_vector(31 downto 0); + signal df_afull_q : std_logic; + signal rand_vec : std_logic_vector(11 downto 0); begin @@ -126,7 +147,7 @@ begin end process DF_WR_EN_PROC; df_64k_gen : if READOUT_BUFFER_SIZE = 4 generate - DATA_FIFO : entity work.fifo_64kx9_af + DATA_FIFO : entity work.fifo_64kx9_af_cnt port map( Data(7 downto 0) => df_data, Data(8) => df_eos_q, @@ -140,12 +161,13 @@ begin Q(8) => load_eod, Empty => df_empty, Full => df_full_real, - AlmostFull => df_afull + AlmostFull => df_afull, + WCNT => df_wcnt ); end generate df_64k_gen; df_8k_gen : if READOUT_BUFFER_SIZE = 2 generate - DATA_FIFO : entity work.fifo_8kx9 + DATA_FIFO : entity work.fifo_8kx9_af_cnt port map( Data(7 downto 0) => df_data, Data(8) => df_eos_q, @@ -158,8 +180,11 @@ begin Q(7 downto 0) => df_q, Q(8) => load_eod, Empty => df_empty, - Full => df_full_real + Full => df_full_real, + AlmostFull => df_afull, + WCNT => df_wcnt(13 downto 0) ); + df_wcnt(16 downto 14) <= (others => '0'); end generate df_8k_gen; df_4k_gen : if READOUT_BUFFER_SIZE = 1 generate @@ -191,39 +216,72 @@ begin READY_PROC : process(CLK) begin if rising_edge(CLK) then - PC_READY_OUT <= not df_full; + --if (load_current_state = IDLE) then + PC_READY_OUT <= not df_full; + --else + -- PC_READY_OUT <= '0'; + --end if; end if; end process READY_PROC; - - df_full <= df_afull; --df_full_real; + + df_full <= df_afull; --df_full_real; end generate ready_impl_gen; ready_sim_gen : if DO_SIMULATION = 1 generate + + -- FULL_PROC : process + -- begin + -- df_full <= '0'; + -- + -- wait for 22000 ns; + -- wait until rising_edge(CLK); + -- df_full <= '1'; + -- wait until rising_edge(CLK); + -- wait until rising_edge(CLK); + -- wait until rising_edge(CLK); + -- df_full <= '0'; + -- + -- wait; + -- end process FULL_PROC; + afull_rand_inst : random_size + port map(Clk => CLK, + Enb => '1', + Rst => RESET, + Dout => s + ); --- FULL_PROC : process --- begin --- df_full <= '0'; --- --- wait for 22000 ns; --- wait until rising_edge(CLK); --- df_full <= '1'; --- wait until rising_edge(CLK); --- wait until rising_edge(CLK); --- wait until rising_edge(CLK); --- df_full <= '0'; --- --- wait; --- end process FULL_PROC; - - df_full <= df_afull; - - READY_PROC : process(CLK) - begin - if rising_edge(CLK) then - PC_READY_OUT <= not df_full; - end if; - end process READY_PROC; + process(clk) + variable seed1, seed2 : positive; + variable rand : real; + variable int_rand : integer; + variable stim : std_logic_vector(11 downto 0); + begin + if rising_edge(CLK) then + uniform(seed1, seed2, rand); + int_rand := integer(trunc(rand*4096.0)); + stim := std_logic_vector(to_unsigned(int_rand, stim'length)); + + rand_vec <= stim; + end if; + end process; + + + df_full <= df_afull; + + READY_PROC : process(CLK) + begin + if rising_edge(CLK) then + + df_afull_q <= df_afull; + + --if (load_current_state = IDLE) then + PC_READY_OUT <= not df_full and not qsf_full and not shf_full and not rand_vec(0); -- and not s(0); -- COMMENTED SIMULATED FIFO AFULL + --else + -- PC_READY_OUT <= '0'; + --end if; + end if; + end process READY_PROC; end generate ready_sim_gen; @@ -466,15 +524,15 @@ begin -- LOADING PART --******* - size_check_debug : if DO_SIMULATION = 1 generate - process(df_q, loaded_queue_bytes, load_current_state) - begin - if (loaded_queue_bytes > x"0021" and load_current_state = LOAD_DATA and loaded_queue_bytes(0) = '0') then - assert (df_q - x"0020" = loaded_queue_bytes(15 downto 1)) report "EVT_CONSTR: Mismatch between data and internal counters" severity warning; - end if; - end process; - - end generate size_check_debug; + -- size_check_debug : if DO_SIMULATION = 1 generate + -- process(df_q, loaded_queue_bytes, load_current_state) + -- begin + -- if (loaded_queue_bytes > x"0021" and load_current_state = LOAD_DATA and loaded_queue_bytes(0) = '0') then + -- assert (df_q - x"0020" = loaded_queue_bytes(15 downto 1)) report "EVT_CONSTR: Mismatch between data and internal counters" severity warning; + -- end if; + -- end process; + -- + -- end generate size_check_debug; LOAD_MACHINE_PROC : process(RESET, CLK) is begin @@ -487,8 +545,11 @@ begin LOAD_MACHINE : process(load_current_state, qsf_empty, header_ctr, load_eod_q, term_ctr, insert_padding, loaded_queue_bytes, actual_q_size) begin + load_state <= x"0"; + case (load_current_state) is when IDLE => + load_state <= x"1"; if (qsf_empty = '0') then -- something in queue sizes fifo means entire queue is waiting load_next_state <= GET_Q_SIZE; else @@ -496,6 +557,7 @@ begin end if; when GET_Q_SIZE => + load_state <= x"2"; if (header_ctr = 0) then load_next_state <= START_TRANSFER; else @@ -503,9 +565,11 @@ begin end if; when START_TRANSFER => + load_state <= x"3"; load_next_state <= LOAD_Q_HEADERS; when LOAD_Q_HEADERS => + load_state <= x"4"; if (header_ctr = 0) then load_next_state <= LOAD_SUB; else @@ -513,6 +577,7 @@ begin end if; when LOAD_SUB => + load_state <= x"5"; if (header_ctr = 0) then load_next_state <= LOAD_DATA; else @@ -520,6 +585,7 @@ begin end if; when LOAD_DATA => + load_state <= x"5"; if (load_eod_q = '1' and term_ctr = 33) then if (insert_padding = '1') then load_next_state <= LOAD_PADDING; @@ -535,6 +601,7 @@ begin end if; when LOAD_PADDING => + load_state <= x"6"; if (header_ctr = 0) then if (loaded_queue_bytes = actual_q_size) then load_next_state <= LOAD_TERM; @@ -546,6 +613,7 @@ begin end if; when LOAD_TERM => + load_state <= x"7"; if (header_ctr = 0) then load_next_state <= CLEANUP; else @@ -553,10 +621,29 @@ begin end if; when CLEANUP => + load_state <= x"8"; load_next_state <= IDLE; + when others => load_next_state <= IDLE; + end case; end process LOAD_MACHINE; + + evt_ctr_gen : if DO_SIMULATION = 1 generate + process(CLK) + begin + if rising_edge(CLK) then + if (RESET = '1') then + evt_ctr <= (others => '0'); + elsif (load_current_state = LOAD_SUB and header_ctr = 0) then + evt_ctr <= evt_ctr + x"1"; + else + evt_ctr <= evt_ctr; + end if; + end if; + end process; + end generate evt_ctr_gen; + process(CLK) begin @@ -775,6 +862,15 @@ begin -- outputs - DEBUG_OUT <= (others => '0'); + DEBUG_OUT(3 downto 0) <= load_state; + DEBUG_OUT(20 downto 4) <= df_wcnt; + DEBUG_OUT(23 downto 21) <= "000"; + DEBUG_OUT(24) <= df_afull; + DEBUG_OUT(25) <= df_full; + DEBUG_OUT(26) <= df_empty; + DEBUG_OUT(27) <= qsf_full; + DEBUG_OUT(28) <= shf_full; + + DEBUG_OUT(63 downto 29) <= (others => '0'); end architecture RTL; diff --git a/gbe_trb/base/trb_net16_gbe_frame_constr.vhd b/gbe_trb/base/trb_net16_gbe_frame_constr.vhd index 9db9170..bf65129 100755 --- a/gbe_trb/base/trb_net16_gbe_frame_constr.vhd +++ b/gbe_trb/base/trb_net16_gbe_frame_constr.vhd @@ -162,12 +162,8 @@ begin end if; end if; end process; ---ready <= '1' when (constructCurrentState = IDLE) --- else '0'; ---headers_ready <= '1' when (constructCurrentState = SAVE_DATA) --- else '0'; -sizeProc: process(CLK) -- put_udp_headers, IP_F_SIZE_IN, UDP_P_SIZE_IN, DEST_UDP_PORT_IN) +sizeProc: process(CLK) begin if rising_edge(CLK) then if( put_udp_headers = '1' ) and (DEST_UDP_PORT_IN /= x"0000") then @@ -488,7 +484,7 @@ end process readyFramesCtrProc; fpfResetProc : process(CLK) begin if rising_edge(CLK) then - if (LINK_OK_IN = '0') then + if (LINK_OK_IN = '0' or RESET = '1') then fpf_reset <= '1'; else fpf_reset <= '0'; @@ -532,7 +528,6 @@ fpf_8k_gen : if FRAME_BUFFER_SIZE = 2 generate ); end generate fpf_8k_gen; ---fpf_rd_en <= FT_TX_RD_EN_IN; fpf_rd_en <= '1' when ((link_ok_125 = '1') and (FT_TX_RD_EN_IN = '1')) or (link_ok_125 = '0') -- clear the fifo if link is down else '0'; diff --git a/gbe_trb/base/trb_net16_gbe_frame_trans.vhd b/gbe_trb/base/trb_net16_gbe_frame_trans.vhd index e0f1954..19dade8 100755 --- a/gbe_trb/base/trb_net16_gbe_frame_trans.vhd +++ b/gbe_trb/base/trb_net16_gbe_frame_trans.vhd @@ -124,7 +124,7 @@ begin end if; end process TransmitStatemachineProc; -TransmitStateMachine : process (transmitCurrentState, START_OF_PACKET_IN, DATA_ENDFLAG_IN, TX_DONE_IN) +TransmitStateMachine : process (transmitCurrentState, START_OF_PACKET_IN, DATA_ENDFLAG_IN, TX_DONE_IN, TX_DISCFRM_IN) begin case transmitCurrentState is when T_IDLE => @@ -143,7 +143,7 @@ begin end if; when T_WAITFORFIFO => bsm_trans <= x"2"; - if (TX_DONE_IN = '1') then + if (TX_DONE_IN = '1' or TX_DISCFRM_IN = '1') then transmitNextState <= T_IDLE; else transmitNextState <= T_WAITFORFIFO; diff --git a/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd b/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd index 56527d3..2a1eb9e 100644 --- a/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd +++ b/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd @@ -70,11 +70,11 @@ end entity trb_net16_gbe_ipu_interface; architecture RTL of trb_net16_gbe_ipu_interface is attribute syn_encoding : string; - type saveStates is (IDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, CLOSE, FINISH_4_WORDS, CLEANUP); + type saveStates is (IDLE, SAVE_EVT_ADDR, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, ADD_MISSING, TERMINATE, SEND_TERM_PULSE, CLOSE, FINISH_4_WORDS, CLEANUP); signal save_current_state, save_next_state : saveStates; attribute syn_encoding of save_current_state : signal is "onehot"; - type loadStates is (IDLE, WAIT_FOR_SUBS, REMOVE, WAIT_ONE, WAIT_TWO, DECIDE, PREPARE_TO_LOAD_SUB, WAIT_FOR_LOAD, LOAD, CLOSE_PACKET, CLOSE_SUB, CLOSE_QUEUE, CLOSE_QUEUE_IMMEDIATELY); + type loadStates is (IDLE, WAIT_FOR_SUBS, REMOVE, WAIT_ONE, WAIT_TWO, DECIDE, PREPARE_TO_LOAD_SUB, WAIT_FOR_LOAD, LOAD, FINISH_ONE, FINISH_TWO, CLOSE_SUB, CLOSE_QUEUE, CLOSE_QUEUE_IMMEDIATELY); signal load_current_state, load_next_state : loadStates; attribute syn_encoding of load_current_state : signal is "onehot"; @@ -85,7 +85,7 @@ architecture RTL of trb_net16_gbe_ipu_interface is signal cts_rnd, cts_trg : std_logic_vector(15 downto 0); signal save_ctr : std_logic_vector(15 downto 0); - signal saved_events_ctr, loaded_events_ctr, saved_events_ctr_gbe : std_logic_vector(7 downto 0); + signal saved_events_ctr, loaded_events_ctr, saved_events_ctr_gbe : std_logic_vector(31 downto 0); signal loaded_bytes_ctr : std_Logic_vector(15 downto 0); signal trigger_random : std_logic_vector(7 downto 0); @@ -96,7 +96,7 @@ architecture RTL of trb_net16_gbe_ipu_interface is signal bank_select : std_logic_vector(3 downto 0); signal readout_ctr : std_logic_vector(23 downto 0) := x"000000"; signal pc_ready_q : std_logic; - signal sf_afull_q,sf_afull_qq, sf_afull_qqq, sf_afull_qqqq, sf_afull_qqqqq : std_logic; + signal sf_afull_q, sf_afull_qq, sf_afull_qqq, sf_afull_qqqq, sf_afull_qqqqq : std_logic; signal sf_aempty : std_logic; signal rec_state, load_state : std_logic_vector(3 downto 0); signal queue_size : std_logic_vector(17 downto 0); @@ -108,7 +108,21 @@ architecture RTL of trb_net16_gbe_ipu_interface is signal sf_wr_qq, sf_wr_qqq, sf_wr_qqqq, sf_wr_qqqqq : std_logic; signal too_large_dropped : std_logic_vector(31 downto 0); signal previous_ttype, previous_bank : std_logic_vector(3 downto 0); - signal sf_afull_real : std_logic; + signal sf_afull_real : std_logic; + signal sf_cnt : std_logic_vector(15 downto 0); + + signal local_fee_busy, local_fee_busy_q, local_fee_busy_qq, local_fee_busy_qqq, local_fee_busy_qqqq, local_fee_busy_qqqqq, local_fee_busy_qqqqqq, local_fee_busy_qqqqqqq, local_fee_busy_qqqqqqqq : std_logic; + + attribute syn_keep : string; + attribute syn_keep of sf_cnt : signal is "true"; + signal saved_bytes_ctr : std_logic_vector(31 downto 0); + signal longer_busy_ctr : std_logic_vector(7 downto 0); + signal uneven_ctr : std_logic_vector(3 downto 0); + signal saved_size : std_logic_vector(16 downto 0); + signal overwrite_afull : std_logic; + signal last_three_bytes : std_logic_vector(3 downto 0); + signal sf_eos_q, sf_eos_qq : std_logic; + signal eos_ctr : std_logic_vector(3 downto 0); begin @@ -125,8 +139,9 @@ begin end if; end process SAVE_MACHINE_PROC; - SAVE_MACHINE : process(save_current_state, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN, size_check_ctr) + SAVE_MACHINE : process(save_current_state, CTS_START_READOUT_IN, local_fee_busy, saved_size, FEE_BUSY_IN, CTS_READ_IN, size_check_ctr) begin + rec_state <= x"0"; case (save_current_state) is when IDLE => rec_state <= x"1"; @@ -150,7 +165,8 @@ begin when SAVE_DATA => rec_state <= x"4"; - if (FEE_BUSY_IN = '0') then + --if (FEE_BUSY_IN = '0') then + if (local_fee_busy = '0') then save_next_state <= TERMINATE; else save_next_state <= SAVE_DATA; @@ -159,18 +175,33 @@ begin when TERMINATE => rec_state <= x"5"; if (CTS_READ_IN = '1') then - save_next_state <= CLOSE; + save_next_state <= SEND_TERM_PULSE; --CLOSE; else save_next_state <= TERMINATE; end if; + when SEND_TERM_PULSE => + rec_state <= x"6"; + save_next_state <= CLOSE; + when CLOSE => rec_state <= x"6"; if (CTS_START_READOUT_IN = '0') then - save_next_state <= ADD_SUBSUB1; + if (saved_size = x"0000" & "0") then + save_next_state <= ADD_SUBSUB1; + else + save_next_state <= ADD_MISSING; + end if; else save_next_state <= CLOSE; end if; + + when ADD_MISSING => + if (saved_size = x"0000" & "1") then + save_next_state <= ADD_SUBSUB1; + else + save_next_state <= ADD_MISSING; + end if; when ADD_SUBSUB1 => rec_state <= x"7"; @@ -200,20 +231,24 @@ begin rec_state <= x"c"; save_next_state <= IDLE; + when others => save_next_state <= IDLE; + end case; end process SAVE_MACHINE; SF_WR_EN_PROC : process(CLK_IPU) begin if rising_edge(CLK_IPU) then - sf_afull_q <= sf_afull; - sf_afull_qq <= sf_afull_q; - sf_afull_qqq <= sf_afull_qq; - sf_afull_qqqq <= sf_afull_qqq; + sf_afull_q <= sf_afull; + sf_afull_qq <= sf_afull_q; + sf_afull_qqq <= sf_afull_qq; + sf_afull_qqqq <= sf_afull_qqq; sf_afull_qqqqq <= sf_afull_qqqq; --if (sf_afull_q = '0' and save_current_state = SAVE_DATA and FEE_DATAREADY_IN = '1' and FEE_BUSY_IN = '1') then - if (sf_afull_qqqqq = '0' and save_current_state = SAVE_DATA and FEE_DATAREADY_IN = '1' and FEE_BUSY_IN = '1') then + --if (sf_afull_qqqqq = '0' and save_current_state = SAVE_DATA and FEE_DATAREADY_IN = '1' and FEE_BUSY_IN = '1') then + --if (sf_afull_qqqqq = '0' and save_current_state = SAVE_DATA and FEE_DATAREADY_IN = '1' and local_fee_busy = '1') then + if (sf_afull_qqqqq = '0' and save_current_state = SAVE_DATA and FEE_DATAREADY_IN = '1') then sf_wr_en <= '1'; elsif (save_current_state = SAVE_EVT_ADDR) then sf_wr_en <= '1'; @@ -221,12 +256,35 @@ begin sf_wr_en <= '1'; elsif (save_current_state = FINISH_4_WORDS) then sf_wr_en <= '1'; + elsif (save_current_state = ADD_MISSING) then + sf_wr_en <= '1'; else sf_wr_en <= '0'; end if; end if; end process SF_WR_EN_PROC; + LOCAL_BUSY_PROC : process(CLK_IPU) + begin + if rising_edge(CLK_IPU) then + if (save_current_state = IDLE) then + longer_busy_ctr <= x"14"; + elsif (save_current_state = SAVE_DATA and FEE_BUSY_IN = '0' and sf_afull_qqqqq = '0') then + longer_busy_ctr <= longer_busy_ctr - x"1"; + else + longer_busy_ctr <= longer_busy_ctr; + end if; + + if (FEE_BUSY_IN = '1') then + local_fee_busy <= '1'; + elsif (save_current_state = SAVE_DATA and longer_busy_ctr > x"00") then + local_fee_busy <= '1'; + else + local_fee_busy <= '0'; + end if; + end if; + end process LOCAL_BUSY_PROC; + SF_DATA_EOD_PROC : process(CLK_IPU) begin if rising_edge(CLK_IPU) then @@ -257,7 +315,7 @@ begin sf_data <= FEE_STATUS_BITS_IN(15 downto 0); save_eod <= '0'; - when others => sf_data <= (others => '0'); + when others => sf_data <= sf_data; save_eod <= '0'; end case; @@ -293,10 +351,10 @@ begin save_eod_qqqqq <= save_eod_qqqq; end if; - sf_wr_q <= sf_wr_en and (not sf_wr_lock) and DATA_GBE_ENABLE_IN; - sf_wr_qq <= sf_wr_q; - sf_wr_qqq <= sf_wr_qq; - sf_wr_qqqq <= sf_wr_qqq; + sf_wr_q <= sf_wr_en and (not sf_wr_lock) and DATA_GBE_ENABLE_IN; + sf_wr_qq <= sf_wr_q; + sf_wr_qqq <= sf_wr_qq; + sf_wr_qqqq <= sf_wr_qqq; sf_wr_qqqqq <= sf_wr_qqqq; end if; @@ -316,11 +374,18 @@ begin end if; if (save_current_state = IDLE) then - sf_wr_lock <= '1'; + sf_wr_lock <= '1'; + saved_size <= (others => '0'); elsif (save_current_state = SAVE_DATA and size_check_ctr = 2 and sf_wr_en = '1' and (sf_data & "00") < ("00" & MAX_SUBEVENT_SIZE_IN)) then -- condition to ALLOW an event to be passed forward sf_wr_lock <= '0'; + saved_size <= (sf_data & "0") + x"1"; + elsif (save_current_state = SAVE_DATA and sf_wr_q = '1') then + saved_size <= saved_size - x"1"; + elsif (save_current_state = ADD_MISSING) then + saved_size <= saved_size - x"1"; else sf_wr_lock <= sf_wr_lock; + saved_size <= saved_size; end if; end if; @@ -344,7 +409,8 @@ begin if (RESET = '1') then saved_events_ctr <= (others => '0'); elsif rising_edge(CLK_IPU) then - if (save_current_state = ADD_SUBSUB4 and sf_wr_lock = '0' and DATA_GBE_ENABLE_IN = '1') then + --if (save_current_state = ADD_SUBSUB4 and sf_wr_lock = '0' and DATA_GBE_ENABLE_IN = '1') then + if (save_current_state = SEND_TERM_PULSE and DATA_GBE_ENABLE_IN = '1') then saved_events_ctr <= saved_events_ctr + x"1"; else saved_events_ctr <= saved_events_ctr; @@ -355,7 +421,8 @@ begin CTS_DATAREADY_PROC : process(CLK_IPU) begin if rising_edge(CLK_IPU) then - if (save_current_state = SAVE_DATA and FEE_BUSY_IN = '0') then + --if (save_current_state = SAVE_DATA and FEE_BUSY_IN = '0') then + if (save_current_state = SAVE_DATA and local_fee_busy = '0') then CTS_DATAREADY_OUT <= '1'; elsif (save_current_state = TERMINATE) then CTS_DATAREADY_OUT <= '1'; @@ -368,7 +435,8 @@ begin CTS_READOUT_FINISHED_PROC : process(CLK_IPU) begin if rising_edge(CLK_IPU) then - if (save_current_state = CLOSE) then + --if (save_current_state = CLOSE) then + if (save_current_state = SEND_TERM_PULSE) then CTS_READOUT_FINISHED_OUT <= '1'; else CTS_READOUT_FINISHED_OUT <= '0'; @@ -416,54 +484,80 @@ begin end process SAVE_CTR_PROC; sf_afull_sim_gen : if DO_SIMULATION = 1 generate - --- process --- begin --- sf_afull <= '0'; --- wait for 20850 ns; --- sf_afull <= '1'; --- wait for 20 ns; --- sf_afull <= '0'; --- wait; --- end process; - + +-- process +-- begin +-- sf_afull <= '0'; +-- wait for 21310 ns; +-- sf_afull <= '1'; +-- wait for 10 ns; +-- sf_afull <= sf_afull_real; +-- wait; +-- end process; + sf_afull <= sf_afull_real; - + end generate sf_afull_sim_gen; - - sf_afull_impl_gen : if DO_SIMULATION = 0 generate + sf_afull_impl_gen : if DO_SIMULATION = 0 generate sf_afull <= sf_afull_real; - + end generate sf_afull_impl_gen; + + -- size_check_debug : if DO_SIMULATION = 1 generate + -- + -- process(save_ctr, sf_data_qqqqq, save_current_state) + -- begin + -- if (save_ctr > x"000c" and save_current_state = SAVE_DATA) then + -- assert (save_ctr - x"000c" = sf_data_qqqqq) report "IPU_INTERFACE: Mismatch between data and internal counters" severity warning; + -- end if; + -- end process; + -- + -- end generate size_check_debug; - size_check_debug : if DO_SIMULATION = 1 generate - - process(save_ctr, sf_data_qqqqq, save_current_state) - begin - if (save_ctr > x"000c" and save_current_state = SAVE_DATA) then - assert (save_ctr - x"000c" = sf_data_qqqqq) report "IPU_INTERFACE: Mismatch between data and internal counters" severity warning; + process(CLK_IPU) + begin + if rising_edge(CLK_IPU) then + if (save_current_state = IDLE) then + overwrite_afull <= '0'; + elsif (sf_wr_q = '1' and save_current_state /= SAVE_DATA) then + overwrite_afull <= '1'; + elsif (save_current_state = SAVE_DATA) then + overwrite_afull <= '0'; + else + overwrite_afull <= overwrite_afull; end if; - end process; + end if; + end process; - end generate size_check_debug; - + FEE_READ_PROC : process(CLK_IPU) begin if rising_edge(CLK_IPU) then - if (sf_afull = '0') then - if (save_current_state = IDLE or save_current_state = SAVE_EVT_ADDR or save_current_state = WAIT_FOR_DATA or save_current_state = SAVE_DATA) then + + if (save_current_state = SAVE_DATA) then + if (sf_afull = '0' or overwrite_afull = '1') then FEE_READ_OUT <= '1'; else FEE_READ_OUT <= '0'; end if; else - FEE_READ_OUT <= '0'; + FEE_READ_OUT <= '1'; end if; + +-- if (sf_afull = '0') then +-- --if (save_current_state = IDLE or save_current_state = SAVE_EVT_ADDR or save_current_state = WAIT_FOR_DATA or save_current_state = SAVE_DATA) then +-- FEE_READ_OUT <= '1'; +-- --else +-- -- FEE_READ_OUT <= '0'; +-- --end if; +-- else +-- FEE_READ_OUT <= '0'; +-- end if; end if; end process FEE_READ_PROC; - THE_SPLIT_FIFO : fifo_32kx16x8_mb2 --fifo_16kx18x9 + THE_SPLIT_FIFO : entity work.fifo_32kx18x9_wcnt -- fifo_32kx16x8_mb2 --fifo_16kx18x9 port map( -- Byte swapping for correct byte order on readout side of FIFO Data(7 downto 0) => sf_data_qqqqq(15 downto 8), @@ -480,7 +574,7 @@ begin AmFullThresh => b"111_1111_1110_1111", -- 0x7fef = 32751 -- b"001_0011_1000_1000" Q(7 downto 0) => sf_q, Q(8) => sf_eos, - --WCNT => open, + WCNT => sf_cnt, --RCNT => open, Empty => sf_empty, AlmostEmpty => sf_aempty, @@ -490,6 +584,23 @@ begin sf_reset <= RESET; + bytes_ctr_gen : if DO_SIMULATION = 1 generate + process(CLK_IPU) + begin + if rising_edge(CLK_IPU) then + if (RESET = '1') then + saved_bytes_ctr <= (others => '0'); + elsif (save_current_state = SAVE_DATA and sf_wr_q = '1') then + saved_bytes_ctr <= saved_bytes_ctr + x"2"; + elsif (save_current_state = CLEANUP) then + saved_bytes_ctr <= (others => '0'); + else + saved_bytes_ctr <= saved_bytes_ctr; + end if; + end if; + end process; + end generate bytes_ctr_gen; + --********* -- LOADING PART --********* @@ -510,8 +621,9 @@ begin end if; end process LOAD_MACHINE_PROC; - LOAD_MACHINE : process(load_current_state, saved_events_ctr_gbe, loaded_events_ctr, loaded_bytes_ctr, PC_READY_IN, sf_eos, queue_size, number_of_subs, subevent_size, MAX_QUEUE_SIZE_IN, MAX_SUBS_IN_QUEUE_IN, MAX_SINGLE_SUB_SIZE_IN, previous_bank, previous_ttype, trigger_type, bank_select, MULT_EVT_ENABLE_IN) + LOAD_MACHINE : process(load_current_state, saved_events_ctr_gbe, loaded_events_ctr, loaded_bytes_ctr, last_three_bytes, PC_READY_IN, sf_eos, sf_eos_q, sf_rd_en, eos_ctr, queue_size, number_of_subs, subevent_size, MAX_QUEUE_SIZE_IN, MAX_SUBS_IN_QUEUE_IN, MAX_SINGLE_SUB_SIZE_IN, previous_bank, previous_ttype, trigger_type, bank_select, MULT_EVT_ENABLE_IN) begin + load_state <= x"0"; case (load_current_state) is when IDLE => load_state <= x"1"; @@ -538,12 +650,12 @@ begin load_next_state <= WAIT_TWO; when WAIT_TWO => - load_state <= x"4"; + load_state <= x"5"; load_next_state <= DECIDE; --TODO: all queue split conditions here and also in the size process when DECIDE => - load_state <= x"5"; + load_state <= x"6"; if (queue_size > ("00" & MAX_QUEUE_SIZE_IN)) then -- max udp packet exceeded load_next_state <= CLOSE_QUEUE; elsif (MULT_EVT_ENABLE_IN = '1' and number_of_subs = MAX_SUBS_IN_QUEUE_IN) then @@ -559,11 +671,11 @@ begin end if; when PREPARE_TO_LOAD_SUB => - load_state <= x"6"; + load_state <= x"7"; load_next_state <= WAIT_FOR_LOAD; when WAIT_FOR_LOAD => - load_state <= x"7"; + load_state <= x"8"; if (PC_READY_IN = '1') then load_next_state <= LOAD; else @@ -571,37 +683,117 @@ begin end if; when LOAD => - load_state <= x"8"; - if (sf_eos = '1') then - load_next_state <= CLOSE_SUB; + load_state <= x"9"; + --if (sf_eos = '1') then + --if (eos_ctr = x"0") then + --if (sf_eos_q = '1') then + if (sf_eos = '1' and sf_rd_en = '1') then + load_next_state <= FINISH_ONE; + elsif (sf_eos = '1' and sf_rd_en = '0') then + load_next_state <= FINISH_TWO; else load_next_state <= LOAD; end if; - - when CLOSE_SUB => - load_state <= x"9"; - if (subevent_size > ("00" & MAX_SINGLE_SUB_SIZE_IN) and queue_size = (subevent_size + x"10" + x"8" + x"4")) then - load_next_state <= CLOSE_QUEUE_IMMEDIATELY; + + when FINISH_ONE => + load_state <= x"d"; + if (PC_READY_IN = '1') then + load_next_state <= CLOSE_SUB; else - load_next_state <= WAIT_FOR_SUBS; + load_next_state <= FINISH_ONE; + end if; + + when FINISH_TWO => + load_state <= x"e"; + if (PC_READY_IN = '1') then + load_next_state <= FINISH_ONE; + else + load_next_state <= FINISH_TWO; end if; + when CLOSE_SUB => + load_state <= x"a"; + --if (last_three_bytes = x"0") then + if (subevent_size > ("00" & MAX_SINGLE_SUB_SIZE_IN) and queue_size = (subevent_size + x"10" + x"8" + x"4")) then + load_next_state <= CLOSE_QUEUE_IMMEDIATELY; + else + load_next_state <= WAIT_FOR_SUBS; + end if; + --else + -- load_next_state <= CLOSE_SUB; + --end if; + when CLOSE_QUEUE => - load_state <= x"a"; + load_state <= x"b"; load_next_state <= PREPARE_TO_LOAD_SUB; when CLOSE_QUEUE_IMMEDIATELY => - load_state <= x"b"; + load_state <= x"c"; load_next_state <= WAIT_FOR_SUBS; when others => load_next_state <= IDLE; end case; end process LOAD_MACHINE; + + process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (load_current_state = LOAD) then + last_three_bytes <= x"1"; + elsif (load_current_state = CLOSE_SUB and PC_READY_IN = '1') then + last_three_bytes <= last_three_bytes - x"1"; + else + last_three_bytes <= last_three_bytes; + end if; + end if; + end process; + + + process(CLK_GBE) + begin + if rising_edge(CLK_GBE) then + if (load_current_state = REMOVE) then + sf_eos_q <= '0'; + elsif (load_current_state = LOAD and sf_eos = '1') then + sf_eos_q <= '1'; + else + sf_eos_q <= sf_eos_q; + end if; + + sf_eos_qq <= sf_eos_q; + +-- if (load_current_state = REMOVE) then +-- sf_eos_qq <= '0'; +-- elsif (PC_READY_IN = '1') then +-- if (load_current_state = LOAD and sf_eos_q = '1') then +-- sf_eos_qq <= '1'; +-- else +-- sf_eos_qq <= sf_eos_qq; +-- end if; +-- else +-- sf_eos_qq <= sf_eos_qq; +-- end if; + + if (load_current_state = REMOVE or load_current_state = IDLE) then + eos_ctr <= x"f"; + elsif (eos_ctr = x"f" and load_current_state = LOAD and sf_eos = '1' and sf_rd_en = '1') then + eos_ctr <= x"1"; + elsif (eos_ctr = x"f" and load_current_state = LOAD and sf_eos = '1' and sf_rd_en = '0') then + eos_ctr <= x"2"; + elsif (eos_ctr /= x"f" and load_current_state = LOAD and sf_rd_en = '1') then + eos_ctr <= eos_ctr - x"1"; + else + eos_ctr <= eos_ctr; + end if; + + end if; + end process; + saved_ctr_sync : signal_sync generic map( - WIDTH => 8, + WIDTH => 32, DEPTH => 2 ) port map( @@ -660,17 +852,57 @@ begin SF_RD_EN_PROC : process(CLK_GBE) begin if rising_edge(CLK_GBE) then - if (PC_READY_IN = '1') then - if (load_current_state = REMOVE) then - sf_rd_en <= '1'; - elsif (load_current_state = LOAD and PC_READY_IN = '1') then --pc_ready_q = '1') then - sf_rd_en <= '1'; + +-- if (PC_READY_IN = '1') then +-- if (load_current_state = REMOVE) then +-- sf_rd_en <= '1'; +-- elsif (load_current_state = LOAD and PC_READY_IN = '1') then --pc_ready_q = '1') then +-- sf_rd_en <= '1'; +-- else +-- sf_rd_en <= '0'; +-- end if; +-- else +-- sf_rd_en <= '0'; +-- end if; + +-- if (load_current_state = REMOVE) then +-- sf_rd_en <= '1'; +-- elsif (load_current_state = LOAD) then +-- if (sf_eos_q = '0') then +-- if (PC_READY_IN = '1') then +-- sf_rd_en <= '1'; +-- else +-- sf_rd_en <= '0'; +-- end if; +-- elsif (sf_eos_q = '1' or sf_eos_qq = '1') then +-- sf_rd_en <= '1'; +-- else +-- sf_rd_en <= '0'; +-- end if; +-- else +-- sf_rd_en <= '0'; +-- end if; + + if (load_current_state = REMOVE) then + sf_rd_en <= '1'; + --elsif (eos_ctr /= x"f" and eos_ctr /= x"0") then + else + if (PC_READY_IN = '1') then + if (load_current_state = LOAD and sf_eos = '0') then + sf_rd_en <= '1'; + elsif (load_current_state = FINISH_ONE or load_current_state = FINISH_TWO) then + sf_rd_en <= '1'; + --elsif (load_current_state = CLOSE_SUB and last_three_bytes /= x"0") then + -- sf_rd_en <= '1'; + else + sf_rd_en <= '0'; + end if; else sf_rd_en <= '0'; end if; - else - sf_rd_en <= '0'; end if; + + end if; end process SF_RD_EN_PROC; @@ -760,7 +992,7 @@ begin if (RESET = '1') then loaded_events_ctr <= (others => '0'); elsif rising_edge(CLK_GBE) then - if (load_current_state = CLOSE_SUB) then + if (load_current_state = CLOSE_SUB) then -- and PC_READY_IN = '1') then -- and last_three_bytes = x"0") then loaded_events_ctr <= loaded_events_ctr + x"1"; else loaded_events_ctr <= loaded_events_ctr; @@ -842,7 +1074,7 @@ begin if rising_edge(CLK_GBE) then --pc_ready_q <= PC_READY_IN; if (PC_READY_IN = '1') then - if (load_current_state = LOAD) then + if ( (load_current_state = LOAD and sf_eos = '0') or load_current_state = FINISH_ONE or load_current_state = FINISH_TWO) then PC_WR_EN_OUT <= '1'; else PC_WR_EN_OUT <= '0'; @@ -893,19 +1125,20 @@ begin PC_TRIGGER_TYPE_OUT <= trigger_type; - process(CLK_GBE) + process(CLK_IPU) begin - if rising_edge(CLK_GBE) then - DEBUG_OUT(3 downto 0) <= rec_state; - DEBUG_OUT(7 downto 4) <= load_state; - DEBUG_OUT(8) <= sf_empty; - DEBUG_OUT(9) <= sf_aempty; - DEBUG_OUT(10) <= sf_full; - DEBUG_OUT(11) <= sf_afull; + if rising_edge(CLK_IPU) then + DEBUG_OUT(3 downto 0) <= rec_state; + DEBUG_OUT(7 downto 4) <= load_state; + DEBUG_OUT(8) <= sf_empty; + DEBUG_OUT(9) <= sf_aempty; + DEBUG_OUT(10) <= sf_full; + DEBUG_OUT(11) <= sf_afull; + DEBUG_OUT(27 downto 12) <= sf_cnt; end if; end process; - DEBUG_OUT(383 downto 12) <= (others => '0'); + DEBUG_OUT(383 downto 28) <= (others => '0'); MONITOR_OUT(31 downto 0) <= too_large_dropped; MONITOR_OUT(223 downto 32) <= (others => '0'); diff --git a/gbe_trb/base/trb_net16_gbe_main_control.vhd b/gbe_trb/base/trb_net16_gbe_main_control.vhd index 1123e1f..0db36d5 100644 --- a/gbe_trb/base/trb_net16_gbe_main_control.vhd +++ b/gbe_trb/base/trb_net16_gbe_main_control.vhd @@ -1,7 +1,7 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IEEE.std_logic_UNSIGNED.all; library work; use work.trb_net_std.all; @@ -20,981 +20,995 @@ use work.trb_net_gbe_protocols.all; entity trb_net16_gbe_main_control is generic( - RX_PATH_ENABLE : integer range 0 to 1 := 1; - DO_SIMULATION : integer range 0 to 1 := 0; - - INCLUDE_READOUT : std_logic := '0'; - INCLUDE_SLOWCTRL : std_logic := '0'; - INCLUDE_DHCP : std_logic := '0'; - INCLUDE_ARP : std_logic := '0'; - INCLUDE_PING : std_logic := '0'; + RX_PATH_ENABLE : integer range 0 to 1 := 1; + DO_SIMULATION : integer range 0 to 1 := 0; + + INCLUDE_READOUT : std_logic := '0'; + INCLUDE_SLOWCTRL : std_logic := '0'; + INCLUDE_DHCP : std_logic := '0'; + INCLUDE_ARP : std_logic := '0'; + INCLUDE_PING : std_logic := '0'; + + READOUT_BUFFER_SIZE : integer range 1 to 4; + SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 + ); + port( + CLK : in std_logic; -- system clock + CLK_125 : in std_logic; + RESET : in std_logic; + + MC_LINK_OK_OUT : out std_logic; + MC_RESET_LINK_IN : in std_logic; + MC_IDLE_TOO_LONG_OUT : out std_logic; + MC_DHCP_DONE_OUT : out std_logic; + MC_MY_MAC_OUT : out std_logic_vector(47 downto 0); + MC_MY_MAC_IN : in std_logic_vector(47 downto 0); + + -- signals to/from receive controller + RC_FRAME_WAITING_IN : in std_logic; + RC_LOADING_DONE_OUT : out std_logic; + RC_DATA_IN : in std_logic_vector(8 downto 0); + RC_RD_EN_OUT : out std_logic; + RC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + RC_FRAME_PROTO_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + + RC_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + RC_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); + RC_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + RC_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); + RC_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); + RC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); + + -- signals to/from transmit controller + TC_TRANSMIT_CTRL_OUT : out std_logic; + TC_DATA_OUT : out std_logic_vector(8 downto 0); + TC_RD_EN_IN : in std_logic; + TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); + TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); + TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); + TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); + TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); + TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); + TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); + TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + TC_IDENT_OUT : out std_logic_vector(15 downto 0); + TC_TRANSMIT_DONE_IN : in std_logic; + + -- signals to/from sgmii/gbe pcs_an_complete + PCS_AN_COMPLETE_IN : in std_logic; + + -- signals to/from hub + MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); + + GSC_CLK_IN : in std_logic; + GSC_INIT_DATAREADY_OUT : out std_logic; + GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); + GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); + GSC_INIT_READ_IN : in std_logic; + GSC_REPLY_DATAREADY_IN : in std_logic; + GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); + GSC_REPLY_READ_OUT : out std_logic; + GSC_BUSY_IN : in std_logic; + + RESET_TRBNET_IN : in std_logic; + RESET_SCTRL_IN : in std_logic; + -- signal for data readout + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector(15 downto 0); + CTS_CODE_IN : in std_logic_vector(7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector(7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector(31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector(15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector(15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0); + FEE_BUSY_IN : in std_logic; + -- ip configurator + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + + CFG_GBE_ENABLE_IN : in std_logic; + CFG_IPU_ENABLE_IN : in std_logic; + CFG_MULT_ENABLE_IN : in std_logic; + CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); + CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); + CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); + CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); + CFG_READOUT_CTR_VALID_IN : in std_logic; + CFG_INSERT_TTYPE_IN : in std_logic; + CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); + CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); + CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); + + CFG_ADDITIONAL_HDR_IN : in std_logic; + CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0); + + MAKE_RESET_OUT : out std_logic; + + -- signal to/from Host interface of TriSpeed MAC + TSM_HADDR_OUT : out std_logic_vector(7 downto 0); + TSM_HDATA_OUT : out std_logic_vector(7 downto 0); + TSM_HCS_N_OUT : out std_logic; + TSM_HWRITE_N_OUT : out std_logic; + TSM_HREAD_N_OUT : out std_logic; + TSM_HREADY_N_IN : in std_logic; + TSM_HDATA_EN_N_IN : in std_logic; + TSM_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0); + TSM_RX_STAT_EN_IN : in std_logic; + + MAC_READY_CONF_IN : in std_logic; + MAC_RECONF_OUT : out std_logic; + + MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); + MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2 * c_MAX_PROTOCOLS * 32 - 1 downto 0); + + DATA_HIST_OUT : out hist_array; + SCTRL_HIST_OUT : out hist_array; - READOUT_BUFFER_SIZE : integer range 1 to 4; - SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 + DEBUG_OUT : out std_logic_vector(63 downto 0) ); -port ( - CLK : in std_logic; -- system clock - CLK_125 : in std_logic; - RESET : in std_logic; - - MC_LINK_OK_OUT : out std_logic; - MC_RESET_LINK_IN : in std_logic; - MC_IDLE_TOO_LONG_OUT : out std_logic; - MC_DHCP_DONE_OUT : out std_logic; - MC_MY_MAC_OUT : out std_logic_vector(47 downto 0); - MC_MY_MAC_IN : in std_logic_vector(47 downto 0); - --- signals to/from receive controller - RC_FRAME_WAITING_IN : in std_logic; - RC_LOADING_DONE_OUT : out std_logic; - RC_DATA_IN : in std_logic_vector(8 downto 0); - RC_RD_EN_OUT : out std_logic; - RC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - RC_FRAME_PROTO_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - - RC_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - RC_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - RC_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - RC_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - RC_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - RC_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - --- signals to/from transmit controller - TC_TRANSMIT_CTRL_OUT : out std_logic; - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_RD_EN_IN : in std_logic; - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - TC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_TRANSMIT_DONE_IN : in std_logic; - --- signals to/from sgmii/gbe pcs_an_complete - PCS_AN_COMPLETE_IN : in std_logic; - --- signals to/from hub - MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0); - - GSC_CLK_IN : in std_logic; - GSC_INIT_DATAREADY_OUT : out std_logic; - GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_INIT_READ_IN : in std_logic; - GSC_REPLY_DATAREADY_IN : in std_logic; - GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); - GSC_REPLY_READ_OUT : out std_logic; - GSC_BUSY_IN : in std_logic; - - -- signal for data readout - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic; - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - FEE_BUSY_IN : in std_logic; - -- ip configurator - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - - CFG_GBE_ENABLE_IN : in std_logic; - CFG_IPU_ENABLE_IN : in std_logic; - CFG_MULT_ENABLE_IN : in std_logic; - CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); - CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); - CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); - CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); - CFG_READOUT_CTR_VALID_IN : in std_logic; - CFG_INSERT_TTYPE_IN : in std_logic; - CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); - CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); - - CFG_ADDITIONAL_HDR_IN : in std_logic; - CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0); - - MAKE_RESET_OUT : out std_logic; - --- signal to/from Host interface of TriSpeed MAC - TSM_HADDR_OUT : out std_logic_vector(7 downto 0); - TSM_HDATA_OUT : out std_logic_vector(7 downto 0); - TSM_HCS_N_OUT : out std_logic; - TSM_HWRITE_N_OUT : out std_logic; - TSM_HREAD_N_OUT : out std_logic; - TSM_HREADY_N_IN : in std_logic; - TSM_HDATA_EN_N_IN : in std_logic; - TSM_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0); - TSM_RX_STAT_EN_IN : in std_logic; - - MAC_READY_CONF_IN : in std_logic; - MAC_RECONF_OUT : out std_logic; - - - MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); - - DATA_HIST_OUT : out hist_array; - SCTRL_HIST_OUT : out hist_array -); end trb_net16_gbe_main_control; - architecture trb_net16_gbe_main_control of trb_net16_gbe_main_control is ---attribute HGROUP : string; ---attribute HGROUP of trb_net16_gbe_main_control : architecture is "GBE_MAIN_group"; - -attribute syn_encoding : string; + --attribute HGROUP : string; + --attribute HGROUP of trb_net16_gbe_main_control : architecture is "GBE_MAIN_group"; -signal tsm_ready : std_logic; -signal tsm_reconf : std_logic; -signal tsm_haddr : std_logic_vector(7 downto 0); -signal tsm_hdata : std_logic_vector(7 downto 0); -signal tsm_hcs_n : std_logic; -signal tsm_hwrite_n : std_logic; -signal tsm_hread_n : std_logic; + attribute syn_encoding : string; -type link_states is (INACTIVE, ACTIVE, ENABLE_MAC, TIMEOUT, FINALIZE, WAIT_FOR_BOOT, GET_ADDRESS); -signal link_current_state, link_next_state : link_states; -attribute syn_encoding of link_current_state : signal is "onehot"; + signal tsm_ready : std_logic; + signal tsm_reconf : std_logic; + signal tsm_haddr : std_logic_vector(7 downto 0); + signal tsm_hdata : std_logic_vector(7 downto 0); + signal tsm_hcs_n : std_logic; + signal tsm_hwrite_n : std_logic; + signal tsm_hread_n : std_logic; -signal link_down_ctr : std_logic_vector(15 downto 0); -signal link_down_ctr_lock : std_logic; -signal link_ok : std_logic; -signal link_ok_timeout_ctr : std_logic_vector(15 downto 0); + type link_states is (INACTIVE, ACTIVE, ENABLE_MAC, TIMEOUT, FINALIZE, WAIT_FOR_BOOT, GET_ADDRESS); + signal link_current_state, link_next_state : link_states; + attribute syn_encoding of link_current_state : signal is "onehot"; -signal mac_control_debug : std_logic_vector(63 downto 0); + signal link_down_ctr : std_logic_vector(15 downto 0); + signal link_down_ctr_lock : std_logic; + signal link_ok : std_logic; + signal link_ok_timeout_ctr : std_logic_vector(15 downto 0); -type flow_states is (IDLE, TRANSMIT_CTRL, WAIT_FOR_FC, CLEANUP); -signal flow_current_state, flow_next_state : flow_states; -attribute syn_encoding of flow_current_state : signal is "onehot"; + signal mac_control_debug : std_logic_vector(63 downto 0); -signal state : std_logic_vector(3 downto 0); -signal link_state : std_logic_vector(3 downto 0); -signal redirect_state : std_logic_vector(3 downto 0); + type flow_states is (IDLE, TRANSMIT_CTRL, WAIT_FOR_FC, CLEANUP); + signal flow_current_state, flow_next_state : flow_states; + attribute syn_encoding of flow_current_state : signal is "onehot"; -signal ps_wr_en : std_logic; -signal ps_response_ready : std_logic; -signal ps_busy : std_logic_vector(c_MAX_PROTOCOLS -1 downto 0); -signal rc_rd_en : std_logic; -signal first_byte : std_logic; -signal first_byte_q : std_logic; -signal first_byte_qq : std_logic; -signal proto_select : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -signal loaded_bytes_ctr : std_Logic_vector(15 downto 0); + signal state : std_logic_vector(3 downto 0); + signal link_state : std_logic_vector(3 downto 0); + signal redirect_state : std_logic_vector(3 downto 0); -signal dhcp_start : std_logic; -signal dhcp_done : std_logic; -signal wait_ctr : std_logic_vector(31 downto 0); + signal ps_wr_en : std_logic; + signal ps_response_ready : std_logic; + signal ps_busy : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal rc_rd_en : std_logic; + signal first_byte : std_logic; + signal first_byte_q : std_logic; + signal first_byte_qq : std_logic; + signal proto_select : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal loaded_bytes_ctr : std_Logic_vector(15 downto 0); -signal rc_data_local : std_logic_vector(8 downto 0); + signal dhcp_start : std_logic; + signal dhcp_done : std_logic; + signal wait_ctr : std_logic_vector(31 downto 0); --- debug -signal frame_waiting_ctr : std_logic_vector(15 downto 0); -signal ps_busy_q : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -signal rc_frame_proto_q : std_Logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal rc_data_local : std_logic_vector(8 downto 0); -type redirect_states is (IDLE, CHECK_TYPE, DROP, CHECK_BUSY, LOAD, BUSY, WAIT_ONE, FINISH, CLEANUP); -signal redirect_current_state, redirect_next_state : redirect_states; -attribute syn_encoding of redirect_current_state : signal is "onehot"; + -- debug + signal frame_waiting_ctr : std_logic_vector(15 downto 0); + signal ps_busy_q : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); + signal rc_frame_proto_q : std_Logic_vector(c_MAX_PROTOCOLS - 1 downto 0); -signal disable_redirect, ps_wr_en_q, ps_wr_en_qq : std_logic; + type redirect_states is (IDLE, CHECK_TYPE, DROP, CHECK_BUSY, LOAD, BUSY, WAIT_ONE, FINISH, CLEANUP); + signal redirect_current_state, redirect_next_state : redirect_states; + attribute syn_encoding of redirect_current_state : signal is "onehot"; -type stats_states is (IDLE, LOAD_VECTOR, CLEANUP); -signal stats_current_state, stats_next_state : stats_states; + signal disable_redirect, ps_wr_en_q, ps_wr_en_qq : std_logic; -signal stat_rdy, stat_ack : std_logic; -signal rx_stat_en_q : std_logic; -signal rx_stat_vec_q : std_logic_vector(31 downto 0); + type stats_states is (IDLE, LOAD_VECTOR, CLEANUP); + signal stats_current_state, stats_next_state : stats_states; -type array_of_ctrs is array(15 downto 0) of std_logic_vector(31 downto 0); -signal arr : array_of_ctrs; -signal stats_ctr : integer range 0 to 15; -signal stat_data : std_logic_vector(31 downto 0); -signal stat_addr : std_logic_vector(7 downto 0); + signal stat_rdy, stat_ack : std_logic; + signal rx_stat_en_q : std_logic; + signal rx_stat_vec_q : std_logic_vector(31 downto 0); -signal unique_id : std_logic_vector(63 downto 0); + type array_of_ctrs is array (15 downto 0) of std_logic_vector(31 downto 0); + signal arr : array_of_ctrs; + signal stats_ctr : integer range 0 to 15; + signal stat_data : std_logic_vector(31 downto 0); + signal stat_addr : std_logic_vector(7 downto 0); + signal unique_id : std_logic_vector(63 downto 0); -signal nothing_sent : std_logic; -signal nothing_sent_ctr : std_logic_vector(31 downto 0); + signal nothing_sent : std_logic; + signal nothing_sent_ctr : std_logic_vector(31 downto 0); -signal dbg_ps : std_Logic_vector(63 downto 0); + signal dbg_ps : std_Logic_vector(63 downto 0); -signal tc_data : std_logic_vector(8 downto 0); + signal tc_data : std_logic_vector(8 downto 0); -attribute syn_preserve : boolean; -attribute syn_keep : boolean; -attribute syn_keep of unique_id, nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true; -attribute syn_preserve of unique_id, nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true; + attribute syn_preserve : boolean; + attribute syn_keep : boolean; + attribute syn_keep of unique_id, nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true; + attribute syn_preserve of unique_id, nothing_sent, link_state, state, redirect_state, dhcp_done : signal is true; -signal mc_busy : std_logic; -signal incl_dhcp : std_logic; + signal mc_busy : std_logic; + signal incl_dhcp : std_logic; + signal flow_state : std_logic_vector(3 downto 0); + signal selector_debug : std_logic_vector(63 downto 0); begin - -unique_id <= MC_UNIQUE_ID_IN; - -protocol_selector : trb_net16_gbe_protocol_selector -generic map( - RX_PATH_ENABLE => RX_PATH_ENABLE, - DO_SIMULATION => DO_SIMULATION, - - INCLUDE_READOUT => INCLUDE_READOUT, - INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL, - INCLUDE_DHCP => INCLUDE_DHCP, - INCLUDE_ARP => INCLUDE_ARP, - INCLUDE_PING => INCLUDE_PING, - - READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE, - SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE + unique_id <= MC_UNIQUE_ID_IN; + + protocol_selector : entity work.trb_net16_gbe_protocol_selector + generic map( + RX_PATH_ENABLE => RX_PATH_ENABLE, + DO_SIMULATION => DO_SIMULATION, + INCLUDE_READOUT => INCLUDE_READOUT, + INCLUDE_SLOWCTRL => INCLUDE_SLOWCTRL, + INCLUDE_DHCP => INCLUDE_DHCP, + INCLUDE_ARP => INCLUDE_ARP, + INCLUDE_PING => INCLUDE_PING, + READOUT_BUFFER_SIZE => READOUT_BUFFER_SIZE, + SLOWCTRL_BUFFER_SIZE => SLOWCTRL_BUFFER_SIZE ) -port map( - CLK => CLK, - RESET => RESET, - RESET_FOR_DHCP => MC_RESET_LINK_IN, - - PS_DATA_IN => rc_data_local, -- RC_DATA_IN, - PS_WR_EN_IN => ps_wr_en_qq, --ps_wr_en, - PS_PROTO_SELECT_IN => proto_select, - PS_BUSY_OUT => ps_busy, - PS_FRAME_SIZE_IN => RC_FRAME_SIZE_IN, - PS_RESPONSE_READY_OUT => ps_response_ready, - - PS_SRC_MAC_ADDRESS_IN => RC_SRC_MAC_ADDRESS_IN, - PS_DEST_MAC_ADDRESS_IN => RC_DEST_MAC_ADDRESS_IN, - PS_SRC_IP_ADDRESS_IN => RC_SRC_IP_ADDRESS_IN, - PS_DEST_IP_ADDRESS_IN => RC_DEST_IP_ADDRESS_IN, - PS_SRC_UDP_PORT_IN => RC_SRC_UDP_PORT_IN, - PS_DEST_UDP_PORT_IN => RC_DEST_UDP_PORT_IN, - - TC_DATA_OUT => tc_data, - TC_RD_EN_IN => TC_RD_EN_IN, - TC_FRAME_SIZE_OUT => TC_FRAME_SIZE_OUT, - TC_FRAME_TYPE_OUT => TC_FRAME_TYPE_OUT, - TC_IP_PROTOCOL_OUT => TC_IP_PROTOCOL_OUT, - TC_IDENT_OUT => TC_IDENT_OUT, - TC_DEST_MAC_OUT => TC_DEST_MAC_OUT, - TC_DEST_IP_OUT => TC_DEST_IP_OUT, - TC_DEST_UDP_OUT => TC_DEST_UDP_OUT, - TC_SRC_MAC_OUT => TC_SRC_MAC_OUT, - TC_SRC_IP_OUT => TC_SRC_IP_OUT, - TC_SRC_UDP_OUT => TC_SRC_UDP_OUT, - - MC_BUSY_IN => mc_busy, - - MY_MAC_IN => MC_MY_MAC_IN, - MY_IP_OUT => open, - DHCP_START_IN => dhcp_start, - DHCP_DONE_OUT => dhcp_done, - - GSC_CLK_IN => GSC_CLK_IN, - GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, - GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, - GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, - GSC_INIT_READ_IN => GSC_INIT_READ_IN, - GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN, - GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN, - GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, - GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT, - GSC_BUSY_IN => GSC_BUSY_IN, - - MAKE_RESET_OUT => MAKE_RESET_OUT, - - -- CTS interface - CTS_NUMBER_IN => CTS_NUMBER_IN, - CTS_CODE_IN => CTS_CODE_IN, - CTS_INFORMATION_IN => CTS_INFORMATION_IN, - CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, - CTS_START_READOUT_IN => CTS_START_READOUT_IN, - CTS_DATA_OUT => CTS_DATA_OUT, - CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, - CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, - CTS_READ_IN => CTS_READ_IN, - CTS_LENGTH_OUT => CTS_LENGTH_OUT, - CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, - -- Data payload interface - FEE_DATA_IN => FEE_DATA_IN, - FEE_DATAREADY_IN => FEE_DATAREADY_IN, - FEE_READ_OUT => FEE_READ_OUT, - FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, - FEE_BUSY_IN => FEE_BUSY_IN, - -- ip configurator - SLV_ADDR_IN => SLV_ADDR_IN, - SLV_READ_IN => SLV_READ_IN, - SLV_WRITE_IN => SLV_WRITE_IN, - SLV_BUSY_OUT => SLV_BUSY_OUT, - SLV_ACK_OUT => SLV_ACK_OUT, - SLV_DATA_IN => SLV_DATA_IN, - SLV_DATA_OUT => SLV_DATA_OUT, - - CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN, - CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN, - CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN, - CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN, - CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN, - CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN, - CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN, - CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN, - CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN, - CFG_MAX_SUB_IN => CFG_MAX_SUB_IN, - CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN, - CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN, - CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN, - - CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN, - CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN, - - -- input for statistics from outside - STAT_DATA_IN => stat_data, - STAT_ADDR_IN => stat_addr, - STAT_DATA_RDY_IN => stat_rdy, - STAT_DATA_ACK_OUT => stat_ack, - - MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT, - MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT, - MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT, - MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT, - MONITOR_SELECT_DROP_OUT_OUT => MONITOR_SELECT_DROP_OUT_OUT, - MONITOR_SELECT_DROP_IN_OUT => MONITOR_SELECT_DROP_IN_OUT, - MONITOR_SELECT_GEN_DBG_OUT => MONITOR_SELECT_GEN_DBG_OUT, - - DATA_HIST_OUT => DATA_HIST_OUT, - SCTRL_HIST_OUT => SCTRL_HIST_OUT -); - -TC_DATA_OUT <= tc_data; - --- gk 07.11.11 --- do not select any response constructors when dropping a frame -proto_select <= RC_FRAME_PROTO_IN when disable_redirect = '0' else (others => '0'); - --- gk 07.11.11 -DISABLE_REDIRECT_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RESET = '1') then - disable_redirect <= '0'; - elsif (redirect_current_state = CHECK_TYPE) then - if (link_current_state /= ACTIVE and link_current_state /= GET_ADDRESS) then - disable_redirect <= '1'; - elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN /= "10") then - disable_redirect <= '1'; - else + port map( + CLK => CLK, + RESET => RESET, + RESET_FOR_DHCP => MC_RESET_LINK_IN, + PS_DATA_IN => rc_data_local, -- RC_DATA_IN, + PS_WR_EN_IN => ps_wr_en_qq, --ps_wr_en, + PS_PROTO_SELECT_IN => proto_select, + PS_BUSY_OUT => ps_busy, + PS_FRAME_SIZE_IN => RC_FRAME_SIZE_IN, + PS_RESPONSE_READY_OUT => ps_response_ready, + PS_SRC_MAC_ADDRESS_IN => RC_SRC_MAC_ADDRESS_IN, + PS_DEST_MAC_ADDRESS_IN => RC_DEST_MAC_ADDRESS_IN, + PS_SRC_IP_ADDRESS_IN => RC_SRC_IP_ADDRESS_IN, + PS_DEST_IP_ADDRESS_IN => RC_DEST_IP_ADDRESS_IN, + PS_SRC_UDP_PORT_IN => RC_SRC_UDP_PORT_IN, + PS_DEST_UDP_PORT_IN => RC_DEST_UDP_PORT_IN, + TC_DATA_OUT => tc_data, + TC_RD_EN_IN => TC_RD_EN_IN, + TC_FRAME_SIZE_OUT => TC_FRAME_SIZE_OUT, + TC_FRAME_TYPE_OUT => TC_FRAME_TYPE_OUT, + TC_IP_PROTOCOL_OUT => TC_IP_PROTOCOL_OUT, + TC_IDENT_OUT => TC_IDENT_OUT, + TC_DEST_MAC_OUT => TC_DEST_MAC_OUT, + TC_DEST_IP_OUT => TC_DEST_IP_OUT, + TC_DEST_UDP_OUT => TC_DEST_UDP_OUT, + TC_SRC_MAC_OUT => TC_SRC_MAC_OUT, + TC_SRC_IP_OUT => TC_SRC_IP_OUT, + TC_SRC_UDP_OUT => TC_SRC_UDP_OUT, + MC_BUSY_IN => mc_busy, + MY_MAC_IN => MC_MY_MAC_IN, + MY_IP_OUT => open, + DHCP_START_IN => dhcp_start, + DHCP_DONE_OUT => dhcp_done, + GSC_CLK_IN => GSC_CLK_IN, + GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, + GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT, + GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, + GSC_INIT_READ_IN => GSC_INIT_READ_IN, + GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN, + GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN, + GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, + GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT, + GSC_BUSY_IN => GSC_BUSY_IN, + MAKE_RESET_OUT => MAKE_RESET_OUT, + + -- CTS interface + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_DATA_OUT => CTS_DATA_OUT, + CTS_DATAREADY_OUT => CTS_DATAREADY_OUT, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_READ_IN => CTS_READ_IN, + CTS_LENGTH_OUT => CTS_LENGTH_OUT, + CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT, + -- Data payload interface + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + FEE_BUSY_IN => FEE_BUSY_IN, + -- ip configurator + SLV_ADDR_IN => SLV_ADDR_IN, + SLV_READ_IN => SLV_READ_IN, + SLV_WRITE_IN => SLV_WRITE_IN, + SLV_BUSY_OUT => SLV_BUSY_OUT, + SLV_ACK_OUT => SLV_ACK_OUT, + SLV_DATA_IN => SLV_DATA_IN, + SLV_DATA_OUT => SLV_DATA_OUT, + CFG_GBE_ENABLE_IN => CFG_GBE_ENABLE_IN, + CFG_IPU_ENABLE_IN => CFG_IPU_ENABLE_IN, + CFG_MULT_ENABLE_IN => CFG_MULT_ENABLE_IN, + CFG_SUBEVENT_ID_IN => CFG_SUBEVENT_ID_IN, + CFG_SUBEVENT_DEC_IN => CFG_SUBEVENT_DEC_IN, + CFG_QUEUE_DEC_IN => CFG_QUEUE_DEC_IN, + CFG_READOUT_CTR_IN => CFG_READOUT_CTR_IN, + CFG_READOUT_CTR_VALID_IN => CFG_READOUT_CTR_VALID_IN, + CFG_INSERT_TTYPE_IN => CFG_INSERT_TTYPE_IN, + CFG_MAX_SUB_IN => CFG_MAX_SUB_IN, + CFG_MAX_QUEUE_IN => CFG_MAX_QUEUE_IN, + CFG_MAX_SUBS_IN_QUEUE_IN => CFG_MAX_SUBS_IN_QUEUE_IN, + CFG_MAX_SINGLE_SUB_IN => CFG_MAX_SINGLE_SUB_IN, + CFG_ADDITIONAL_HDR_IN => CFG_ADDITIONAL_HDR_IN, + CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN, + + -- input for statistics from outside + STAT_DATA_IN => stat_data, + STAT_ADDR_IN => stat_addr, + STAT_DATA_RDY_IN => stat_rdy, + STAT_DATA_ACK_OUT => stat_ack, + MONITOR_SELECT_REC_OUT => MONITOR_SELECT_REC_OUT, + MONITOR_SELECT_REC_BYTES_OUT => MONITOR_SELECT_REC_BYTES_OUT, + MONITOR_SELECT_SENT_BYTES_OUT => MONITOR_SELECT_SENT_BYTES_OUT, + MONITOR_SELECT_SENT_OUT => MONITOR_SELECT_SENT_OUT, + MONITOR_SELECT_DROP_OUT_OUT => MONITOR_SELECT_DROP_OUT_OUT, + MONITOR_SELECT_DROP_IN_OUT => MONITOR_SELECT_DROP_IN_OUT, + MONITOR_SELECT_GEN_DBG_OUT => MONITOR_SELECT_GEN_DBG_OUT, + DATA_HIST_OUT => DATA_HIST_OUT, + SCTRL_HIST_OUT => SCTRL_HIST_OUT, + DEBUG_OUT => selector_debug + ); + + TC_DATA_OUT <= tc_data; + + -- gk 07.11.11 + -- do not select any response constructors when dropping a frame + proto_select <= RC_FRAME_PROTO_IN when disable_redirect = '0' else (others => '0'); + + -- gk 07.11.11 + DISABLE_REDIRECT_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (RESET = '1') then disable_redirect <= '0'; + elsif (redirect_current_state = CHECK_TYPE) then + if (link_current_state /= ACTIVE and link_current_state /= GET_ADDRESS) then + disable_redirect <= '1'; + elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN /= "10") then + disable_redirect <= '1'; + else + disable_redirect <= '0'; + end if; + else + disable_redirect <= disable_redirect; end if; - else - disable_redirect <= disable_redirect; end if; - end if; -end process DISABLE_REDIRECT_PROC; + end process DISABLE_REDIRECT_PROC; --- warning -SYNC_PROC : process(CLK) -begin - if rising_edge(CLK) then - rc_data_local <= RC_DATA_IN; - end if; -end process SYNC_PROC; + -- warning + SYNC_PROC : process(CLK) + begin + if rising_edge(CLK) then + rc_data_local <= RC_DATA_IN; + end if; + end process SYNC_PROC; -REDIRECT_MACHINE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - redirect_current_state <= IDLE; - elsif rising_edge(CLK) then - if RX_PATH_ENABLE = 1 then - redirect_current_state <= redirect_next_state; - else + REDIRECT_MACHINE_PROC : process(RESET, CLK) + begin + if RESET = '1' then redirect_current_state <= IDLE; + elsif rising_edge(CLK) then + if RX_PATH_ENABLE = 1 then + redirect_current_state <= redirect_next_state; + else + redirect_current_state <= IDLE; + end if; end if; - end if; -end process REDIRECT_MACHINE_PROC; + end process REDIRECT_MACHINE_PROC; -REDIRECT_MACHINE : process(redirect_current_state, link_current_state, RC_FRAME_WAITING_IN, ps_busy, RC_FRAME_PROTO_IN, loaded_bytes_ctr, RC_FRAME_SIZE_IN) -begin - case redirect_current_state is - - when IDLE => - redirect_state <= x"1"; - if (RC_FRAME_WAITING_IN = '1') then - redirect_next_state <= CHECK_TYPE; - else + REDIRECT_MACHINE : process(redirect_current_state, link_current_state, RC_FRAME_WAITING_IN, ps_busy, RC_FRAME_PROTO_IN, loaded_bytes_ctr, RC_FRAME_SIZE_IN) + begin + redirect_state <= x"0"; + + case redirect_current_state is + when IDLE => + redirect_state <= x"1"; + if (RC_FRAME_WAITING_IN = '1') then + redirect_next_state <= CHECK_TYPE; + else + redirect_next_state <= IDLE; + end if; + + when CHECK_TYPE => + redirect_state <= x"2"; + if (link_current_state = ACTIVE) then + redirect_next_state <= CHECK_BUSY; + elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN = "10") then + redirect_next_state <= CHECK_BUSY; + else + redirect_next_state <= DROP; + end if; + + when DROP => + redirect_state <= x"3"; + if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then + redirect_next_state <= WAIT_ONE; + else + redirect_next_state <= DROP; + end if; + + when CHECK_BUSY => + redirect_state <= x"4"; + if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then + redirect_next_state <= LOAD; + else + redirect_next_state <= BUSY; + end if; + + when LOAD => + redirect_state <= x"5"; + if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then + redirect_next_state <= WAIT_ONE; + else + redirect_next_state <= LOAD; + end if; + + when BUSY => + redirect_state <= x"6"; + if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then + redirect_next_state <= LOAD; + else + redirect_next_state <= BUSY; + end if; + + when WAIT_ONE => + redirect_state <= x"7"; + redirect_next_state <= FINISH; + + when FINISH => + redirect_state <= x"8"; + redirect_next_state <= CLEANUP; + + when CLEANUP => + redirect_state <= x"9"; redirect_next_state <= IDLE; - end if; - - when CHECK_TYPE => - if (link_current_state = ACTIVE) then - redirect_next_state <= CHECK_BUSY; - elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN = "10") then - redirect_next_state <= CHECK_BUSY; - else - redirect_next_state <= DROP; - end if; - - when DROP => - redirect_state <= x"7"; - if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then - redirect_next_state <= WAIT_ONE; - else - redirect_next_state <= DROP; - end if; - - when CHECK_BUSY => - redirect_state <= x"6"; - if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then - redirect_next_state <= LOAD; - else - redirect_next_state <= BUSY; - end if; - - when LOAD => - redirect_state <= x"2"; - if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then - redirect_next_state <= WAIT_ONE; + + when others => redirect_next_state <= IDLE; + + end case; + end process REDIRECT_MACHINE; + + rc_rd_en <= '1' when redirect_current_state = LOAD or redirect_current_state = DROP else '0'; + RC_RD_EN_OUT <= rc_rd_en; + + LOADING_DONE_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (RC_DATA_IN(8) = '1' and ps_wr_en_q = '1') then + RC_LOADING_DONE_OUT <= '1'; else - redirect_next_state <= LOAD; + RC_LOADING_DONE_OUT <= '0'; end if; - - when BUSY => - redirect_state <= x"3"; - if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then - redirect_next_state <= LOAD; + end if; + end process LOADING_DONE_PROC; + + PS_WR_EN_PROC : process(CLK) + begin + if rising_edge(CLK) then + ps_wr_en <= rc_rd_en; + ps_wr_en_q <= ps_wr_en; + ps_wr_en_qq <= ps_wr_en_q; + end if; + end process PS_WR_EN_PROC; + + LOADED_BYTES_CTR_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (redirect_current_state = IDLE) then + loaded_bytes_ctr <= (others => '0'); + elsif (redirect_current_state = LOAD or redirect_current_state = DROP) and (rc_rd_en = '1') then + loaded_bytes_ctr <= loaded_bytes_ctr + x"1"; else - redirect_next_state <= BUSY; + loaded_bytes_ctr <= loaded_bytes_ctr; end if; - - when WAIT_ONE => - redirect_state <= x"f"; - redirect_next_state <= FINISH; - - when FINISH => - redirect_state <= x"4"; - redirect_next_state <= CLEANUP; - - when CLEANUP => - redirect_state <= x"5"; - redirect_next_state <= IDLE; - - end case; -end process REDIRECT_MACHINE; + end if; + end process LOADED_BYTES_CTR_PROC; -rc_rd_en <= '1' when redirect_current_state = LOAD or redirect_current_state = DROP else '0'; -RC_RD_EN_OUT <= rc_rd_en; + FIRST_BYTE_PROC : process(CLK) + begin + if rising_edge(CLK) then + first_byte_q <= first_byte; + first_byte_qq <= first_byte_q; -LOADING_DONE_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (RC_DATA_IN(8) = '1' and ps_wr_en_q = '1') then - RC_LOADING_DONE_OUT <= '1'; - else - RC_LOADING_DONE_OUT <= '0'; + if (redirect_current_state = IDLE) then + first_byte <= '1'; + else + first_byte <= '0'; + end if; end if; - end if; -end process LOADING_DONE_PROC; + end process FIRST_BYTE_PROC; -PS_WR_EN_PROC : process(CLK) -begin - if rising_edge(CLK) then - ps_wr_en <= rc_rd_en; - ps_wr_en_q <= ps_wr_en; - ps_wr_en_qq <= ps_wr_en_q; - end if; -end process PS_WR_EN_PROC; - -LOADED_BYTES_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (redirect_current_state = IDLE) then - loaded_bytes_ctr <= (others => '0'); - elsif (redirect_current_state = LOAD or redirect_current_state = DROP) and (rc_rd_en = '1') then - loaded_bytes_ctr <= loaded_bytes_ctr + x"1"; - else - loaded_bytes_ctr <= loaded_bytes_ctr; - end if; - end if; -end process LOADED_BYTES_CTR_PROC; + --********************* + -- DATA FLOW CONTROL -FIRST_BYTE_PROC : process(CLK) -begin - if rising_edge(CLK) then - first_byte_q <= first_byte; - first_byte_qq <= first_byte_q; - - if (redirect_current_state = IDLE) then - first_byte <= '1'; - else - first_byte <= '0'; + FLOW_MACHINE_PROC : process(RESET, CLK) + begin + if RESET = '1' then + flow_current_state <= IDLE; + elsif rising_edge(CLK) then + flow_current_state <= flow_next_state; end if; - end if; -end process FIRST_BYTE_PROC; + end process FLOW_MACHINE_PROC; ---********************* --- DATA FLOW CONTROL + FLOW_MACHINE : process(flow_current_state, TC_TRANSMIT_DONE_IN, ps_response_ready, tc_data) + begin + flow_state <= x"0"; -FLOW_MACHINE_PROC : process(RESET, CLK) -begin - if RESET = '1' then - flow_current_state <= IDLE; - elsif rising_edge(CLK) then - flow_current_state <= flow_next_state; - end if; -end process FLOW_MACHINE_PROC; - -FLOW_MACHINE : process(flow_current_state, TC_TRANSMIT_DONE_IN, ps_response_ready, tc_data) -begin - case flow_current_state is + case flow_current_state is + when IDLE => + flow_state <= x"1"; + if (ps_response_ready = '1') then + flow_next_state <= TRANSMIT_CTRL; + else + flow_next_state <= IDLE; + end if; - when IDLE => - if (ps_response_ready = '1') then - flow_next_state <= TRANSMIT_CTRL; - else - flow_next_state <= IDLE; - end if; - - when TRANSMIT_CTRL => - if (tc_data(8) = '1') then - flow_next_state <= WAIT_FOR_FC; - else - flow_next_state <= TRANSMIT_CTRL; - end if; - - when WAIT_FOR_FC => - if (TC_TRANSMIT_DONE_IN = '1') then - flow_next_state <= CLEANUP; - else - flow_next_state <= WAIT_FOR_FC; - end if; + when TRANSMIT_CTRL => + flow_state <= x"2"; + if (tc_data(8) = '1') then + flow_next_state <= WAIT_FOR_FC; + else + flow_next_state <= TRANSMIT_CTRL; + end if; - when CLEANUP => - flow_next_state <= IDLE; + when WAIT_FOR_FC => + flow_state <= x"3"; + if (TC_TRANSMIT_DONE_IN = '1') then + flow_next_state <= CLEANUP; + else + flow_next_state <= WAIT_FOR_FC; + end if; - end case; -end process FLOW_MACHINE; + when CLEANUP => + flow_state <= x"4"; + flow_next_state <= IDLE; -process(CLK) -begin - if rising_edge(CLK) then - if (flow_current_state = IDLE and ps_response_ready = '1') then - TC_TRANSMIT_CTRL_OUT <= '1'; - else - TC_TRANSMIT_CTRL_OUT <= '0'; - end if; - - if (flow_current_state = TRANSMIT_CTRL or flow_current_state = WAIT_FOR_FC) then - mc_busy <= '1'; - else - mc_busy <= '0'; - end if; - end if; -end process; + when others => flow_next_state <= IDLE; ---*********************** --- LINK STATE CONTROL + end case; + end process FLOW_MACHINE; -lsm_impl_gen : if DO_SIMULATION = 0 generate - LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK) + process(CLK) begin - if MC_RESET_LINK_IN = '1' then - link_current_state <= INACTIVE; - elsif rising_edge(CLK) then - if RX_PATH_ENABLE = 1 then - link_current_state <= link_next_state; + if rising_edge(CLK) then + if (flow_current_state = IDLE and ps_response_ready = '1') then + TC_TRANSMIT_CTRL_OUT <= '1'; else - link_current_state <= INACTIVE; + TC_TRANSMIT_CTRL_OUT <= '0'; end if; - end if; - end process; -end generate lsm_impl_gen; -lsm_sim_gen : if DO_SIMULATION = 1 generate - LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK) - begin - if MC_RESET_LINK_IN = '1' then - link_current_state <= GET_ADDRESS; - elsif rising_edge(CLK) then - if RX_PATH_ENABLE = 1 then - link_current_state <= link_next_state; + if (flow_current_state = TRANSMIT_CTRL or flow_current_state = WAIT_FOR_FC) then + mc_busy <= '1'; else - link_current_state <= ACTIVE; + mc_busy <= '0'; end if; end if; end process; -end generate lsm_sim_gen; -incl_dhcp_gen : if (INCLUDE_DHCP = '1') generate - incl_dhcp <= '1'; -end generate incl_dhcp_gen; -noincl_dhcp_gen : if (INCLUDE_DHCP = '0') generate - incl_dhcp <= '0'; -end generate noincl_dhcp_gen; + --*********************** + -- LINK STATE CONTROL -LINK_STATE_MACHINE : process(link_current_state, dhcp_done, wait_ctr, PCS_AN_COMPLETE_IN, incl_dhcp, MAC_READY_CONF_IN, link_ok_timeout_ctr) -begin - case link_current_state is - - when INACTIVE => - link_state <= x"2"; - if (PCS_AN_COMPLETE_IN = '1') then - link_next_state <= TIMEOUT; - else - link_next_state <= INACTIVE; + lsm_impl_gen : if DO_SIMULATION = 0 generate + LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK) + begin + if MC_RESET_LINK_IN = '1' then + link_current_state <= INACTIVE; + elsif rising_edge(CLK) then + if RX_PATH_ENABLE = 1 then + link_current_state <= link_next_state; + else + link_current_state <= INACTIVE; + end if; end if; - - when TIMEOUT => - link_state <= x"3"; - if (PCS_AN_COMPLETE_IN = '0') then - link_next_state <= INACTIVE; - else - if (link_ok_timeout_ctr = x"ffff") then - link_next_state <= ENABLE_MAC; --FINALIZE; + end process; + end generate lsm_impl_gen; + + lsm_sim_gen : if DO_SIMULATION = 1 generate + LINK_STATE_MACHINE_PROC : process(MC_RESET_LINK_IN, CLK) + begin + if MC_RESET_LINK_IN = '1' then + link_current_state <= GET_ADDRESS; + elsif rising_edge(CLK) then + if RX_PATH_ENABLE = 1 then + link_current_state <= link_next_state; else - link_next_state <= TIMEOUT; + link_current_state <= ACTIVE; end if; end if; + end process; + end generate lsm_sim_gen; - when ENABLE_MAC => - link_state <= x"4"; - if (PCS_AN_COMPLETE_IN = '0') then - link_next_state <= INACTIVE; - --elsif (tsm_ready = '1') then - elsif (MAC_READY_CONF_IN = '1') then - link_next_state <= FINALIZE; --INACTIVE; - else - link_next_state <= ENABLE_MAC; - end if; + incl_dhcp_gen : if (INCLUDE_DHCP = '1') generate + incl_dhcp <= '1'; + end generate incl_dhcp_gen; + noincl_dhcp_gen : if (INCLUDE_DHCP = '0') generate + incl_dhcp <= '0'; + end generate noincl_dhcp_gen; - when FINALIZE => - link_state <= x"5"; - if (PCS_AN_COMPLETE_IN = '0') then - link_next_state <= INACTIVE; - else - link_next_state <= WAIT_FOR_BOOT; --ACTIVE; - end if; - - when WAIT_FOR_BOOT => - link_state <= x"6"; - if (PCS_AN_COMPLETE_IN = '0') then - link_next_state <= INACTIVE; - else - if (wait_ctr = x"0000_1000") then - if (incl_dhcp = '1') then - link_next_state <= GET_ADDRESS; + LINK_STATE_MACHINE : process(link_current_state, dhcp_done, wait_ctr, PCS_AN_COMPLETE_IN, incl_dhcp, MAC_READY_CONF_IN, link_ok_timeout_ctr) + begin + link_state <= x"0"; + + case link_current_state is + when INACTIVE => + link_state <= x"1"; + if (PCS_AN_COMPLETE_IN = '1') then + link_next_state <= TIMEOUT; + else + link_next_state <= INACTIVE; + end if; + + when TIMEOUT => + link_state <= x"2"; + if (PCS_AN_COMPLETE_IN = '0') then + link_next_state <= INACTIVE; + else + if (link_ok_timeout_ctr = x"ffff") then + link_next_state <= ENABLE_MAC; --FINALIZE; else - link_next_state <= ACTIVE; + link_next_state <= TIMEOUT; end if; + end if; + + when ENABLE_MAC => + link_state <= x"3"; + if (PCS_AN_COMPLETE_IN = '0') then + link_next_state <= INACTIVE; + --elsif (tsm_ready = '1') then + elsif (MAC_READY_CONF_IN = '1') then + link_next_state <= FINALIZE; --INACTIVE; else - link_next_state <= WAIT_FOR_BOOT; + link_next_state <= ENABLE_MAC; end if; - end if; - - when GET_ADDRESS => - link_state <= x"7"; - if (PCS_AN_COMPLETE_IN = '0') then - link_next_state <= INACTIVE; - else - if (dhcp_done = '1') then - link_next_state <= ACTIVE; + + when FINALIZE => + link_state <= x"4"; + if (PCS_AN_COMPLETE_IN = '0') then + link_next_state <= INACTIVE; else - link_next_state <= GET_ADDRESS; + link_next_state <= WAIT_FOR_BOOT; --ACTIVE; end if; - end if; - - when ACTIVE => - link_state <= x"1"; - if (PCS_AN_COMPLETE_IN = '0') then - link_next_state <= INACTIVE; - else - link_next_state <= ACTIVE; - end if; - end case; -end process LINK_STATE_MACHINE; + when WAIT_FOR_BOOT => + link_state <= x"5"; + if (PCS_AN_COMPLETE_IN = '0') then + link_next_state <= INACTIVE; + else + if (wait_ctr = x"0000_1000") then + if (incl_dhcp = '1') then + link_next_state <= GET_ADDRESS; + else + link_next_state <= ACTIVE; + end if; + else + link_next_state <= WAIT_FOR_BOOT; + end if; + end if; -MC_DHCP_DONE_OUT <= '1' when link_current_state = ACTIVE else '0'; + when GET_ADDRESS => + link_state <= x"6"; + if (PCS_AN_COMPLETE_IN = '0') then + link_next_state <= INACTIVE; + else + if (dhcp_done = '1') then + link_next_state <= ACTIVE; + else + link_next_state <= GET_ADDRESS; + end if; + end if; -LINK_OK_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - --if (RESET = '1') or (link_current_state /= TIMEOUT) then - if (link_current_state /= TIMEOUT) then - link_ok_timeout_ctr <= (others => '0'); - elsif (link_current_state = TIMEOUT) then - link_ok_timeout_ctr <= link_ok_timeout_ctr + x"1"; - end if; - --- if (link_current_state = ACTIVE or link_current_state = GET_ADDRESS) then --- link_ok <= '1'; --- else --- link_ok <= '0'; --- end if; - - if (link_current_state = GET_ADDRESS) then - dhcp_start <= '1'; - else - dhcp_start <= '0'; - end if; - end if; -end process LINK_OK_CTR_PROC; + when ACTIVE => + link_state <= x"7"; + if (PCS_AN_COMPLETE_IN = '0') then + link_next_state <= INACTIVE; + else + link_next_state <= ACTIVE; + end if; ---link_ok <= '1' when (link_current_state = ACTIVE) or (link_current_state = GET_ADDRESS) else '0'; -link_ok <= '1'; + when others => link_next_state <= INACTIVE; -WAIT_CTR_PROC : process(CLK) -begin - if rising_edge(CLK) then - if (link_current_state = WAIT_FOR_BOOT) then - wait_ctr <= wait_ctr + x"1"; - else - wait_ctr <= (others => '0'); - end if; - end if; -end process WAIT_CTR_PROC; - ---dhcp_start <= '1' when link_current_state = GET_ADDRESS else '0'; - ---LINK_DOWN_CTR_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- link_down_ctr <= (others => '0'); --- link_down_ctr_lock <= '0'; --- elsif (PCS_AN_COMPLETE_IN = '1') then --- link_down_ctr_lock <= '0'; --- elsif ((PCS_AN_COMPLETE_IN = '0') and (link_down_ctr_lock = '0')) then --- link_down_ctr <= link_down_ctr + x"1"; --- link_down_ctr_lock <= '1'; --- end if; --- end if; ---end process LINK_DOWN_CTR_PROC; - -MC_LINK_OK_OUT <= link_ok; -- or nothing_sent; - --- END OF LINK STATE CONTROL ---************* - ---************* --- GENERATE MAC_ADDRESS ---g_MY_MAC <= unique_id(31 downto 8) & x"be0002"; -MC_MY_MAC_OUT <= unique_id(31 downto 8) & x"be0002"; - ---************* - ---**************** --- TRI SPEED MAC CONTROLLER - ---TSMAC_CONTROLLER : trb_net16_gbe_mac_control ---port map( --- CLK => CLK, --- RESET => MC_RESET_LINK_IN, --- ----- signals to/from main controller --- MC_TSMAC_READY_OUT => tsm_ready, --- MC_RECONF_IN => tsm_reconf, --- MC_GBE_EN_IN => '1', --- MC_RX_DISCARD_FCS => '0', --- MC_PROMISC_IN => '1', --- MC_MAC_ADDR_IN => g_MY_MAC, --x"001122334455", --- ----- signal to/from Host interface of TriSpeed MAC --- TSM_HADDR_OUT => tsm_haddr, --- TSM_HDATA_OUT => tsm_hdata, --- TSM_HCS_N_OUT => tsm_hcs_n, --- TSM_HWRITE_N_OUT => tsm_hwrite_n, --- TSM_HREAD_N_OUT => tsm_hread_n, --- TSM_HREADY_N_IN => TSM_HREADY_N_IN, --- TSM_HDATA_EN_N_IN => TSM_HDATA_EN_N_IN, --- --- DEBUG_OUT => open ---); - ---DEBUG_OUT <= mac_control_debug; -process(CLK) -begin - if rising_edge(CLK) then - if link_current_state = INACTIVE and PCS_AN_COMPLETE_IN = '1' then - tsm_reconf <= '1'; - else - tsm_reconf <= '0'; + end case; + end process LINK_STATE_MACHINE; + + MC_DHCP_DONE_OUT <= '1' when link_current_state = ACTIVE else '0'; + + LINK_OK_CTR_PROC : process(CLK) + begin + if rising_edge(CLK) then + --if (RESET = '1') or (link_current_state /= TIMEOUT) then + if (link_current_state /= TIMEOUT) then + link_ok_timeout_ctr <= (others => '0'); + elsif (link_current_state = TIMEOUT) then + link_ok_timeout_ctr <= link_ok_timeout_ctr + x"1"; + end if; + + -- if (link_current_state = ACTIVE or link_current_state = GET_ADDRESS) then + -- link_ok <= '1'; + -- else + -- link_ok <= '0'; + -- end if; + + if (link_current_state = GET_ADDRESS) then + dhcp_start <= '1'; + else + dhcp_start <= '0'; + end if; end if; - end if; -end process; -MAC_RECONF_OUT <= tsm_reconf; ---tsm_reconf <= '1' when (link_current_state = INACTIVE) and (PCS_AN_COMPLETE_IN = '0') else '0'; - -TSM_HADDR_OUT <= tsm_haddr; -TSM_HCS_N_OUT <= tsm_hcs_n; -TSM_HDATA_OUT <= tsm_hdata; -TSM_HREAD_N_OUT <= tsm_hread_n; -TSM_HWRITE_N_OUT <= tsm_hwrite_n; - --- END OF TRI SPEED MAC CONTROLLER ---*************** - - --- ***** --- STATISTICS --- ***** - --- ---CTRS_GEN : for n in 0 to 15 generate --- --- CTR_PROC : process(CLK) --- begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- arr(n) <= (others => '0'); --- elsif (rx_stat_en_q = '1' and rx_stat_vec_q(16 + n) = '1') then --- arr(n) <= arr(n) + x"1"; --- end if; --- end if; --- end process CTR_PROC; --- ---end generate CTRS_GEN; --- ---STAT_VEC_SYNC : signal_sync ---generic map ( --- WIDTH => 32, --- DEPTH => 2 ---) ---port map ( --- RESET => RESET, --- CLK0 => CLK, --- CLK1 => CLK, --- D_IN => TSM_RX_STAT_VEC_IN, --- D_OUT => rx_stat_vec_q ---); --- --- ---STAT_VEC_EN_SYNC : pulse_sync ---port map( --- CLK_A_IN => CLK_125, --- RESET_A_IN => RESET, --- PULSE_A_IN => TSM_RX_STAT_EN_IN, --- CLK_B_IN => CLK, --- RESET_B_IN => RESET, --- PULSE_B_OUT => rx_stat_en_q ---); --- --- ---STATS_MACHINE_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- stats_current_state <= IDLE; --- else --- stats_current_state <= stats_next_state; --- end if; --- end if; ---end process STATS_MACHINE_PROC; --- ---STATS_MACHINE : process(stats_current_state, rx_stat_en_q, stats_ctr) ---begin --- --- case (stats_current_state) is --- --- when IDLE => --- if (rx_stat_en_q = '1') then --- stats_next_state <= LOAD_VECTOR; --- else --- stats_next_state <= IDLE; --- end if; --- --- when LOAD_VECTOR => --- --if (stat_ack = '1') then --- if (stats_ctr = 15) then --- stats_next_state <= CLEANUP; --- else --- stats_next_state <= LOAD_VECTOR; --- end if; --- --- when CLEANUP => --- stats_next_state <= IDLE; --- --- end case; --- ---end process STATS_MACHINE; --- ---STATS_CTR_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') or (stats_current_state = IDLE) then --- stats_ctr <= 0; --- elsif (stats_current_state = LOAD_VECTOR and stat_ack ='1') then --- stats_ctr <= stats_ctr + 1; --- end if; --- end if; ---end process STATS_CTR_PROC; --- -----stat_data <= arr(stats_ctr); --- ---stat_addr <= x"0c" + std_logic_vector(to_unsigned(stats_ctr, 8)); --- ---stat_rdy <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; --- ---stat_data(7 downto 0) <= arr(stats_ctr)(31 downto 24); ---stat_data(15 downto 8) <= arr(stats_ctr)(23 downto 16); ---stat_data(23 downto 16) <= arr(stats_ctr)(15 downto 8); ---stat_data(31 downto 24) <= arr(stats_ctr)(7 downto 0); - - --- **** debug ---FRAME_WAITING_CTR_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- frame_waiting_ctr <= (others => '0'); --- elsif (RC_FRAME_WAITING_IN = '1') then --- frame_waiting_ctr <= frame_waiting_ctr + x"1"; --- end if; --- end if; ---end process FRAME_WAITING_CTR_PROC; --- ---SAVE_VALUES_PROC : process(CLK) ---begin --- if rising_edge(CLK) then --- if (RESET = '1') then --- ps_busy_q <= (others => '0'); --- rc_frame_proto_q <= (others => '0'); --- elsif (redirect_current_state = IDLE and RC_FRAME_WAITING_IN = '1') then --- ps_busy_q <= ps_busy; --- rc_frame_proto_q <= RC_FRAME_PROTO_IN; --- end if; --- end if; ---end process SAVE_VALUES_PROC; - - --- **** + end process LINK_OK_CTR_PROC; + --link_ok <= '1' when (link_current_state = ACTIVE) or (link_current_state = GET_ADDRESS) else '0'; + link_ok <= '1'; + WAIT_CTR_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (link_current_state = WAIT_FOR_BOOT) then + wait_ctr <= wait_ctr + x"1"; + else + wait_ctr <= (others => '0'); + end if; + end if; + end process WAIT_CTR_PROC; + + --dhcp_start <= '1' when link_current_state = GET_ADDRESS else '0'; + + --LINK_DOWN_CTR_PROC : process(CLK) + --begin + -- if rising_edge(CLK) then + -- if (RESET = '1') then + -- link_down_ctr <= (others => '0'); + -- link_down_ctr_lock <= '0'; + -- elsif (PCS_AN_COMPLETE_IN = '1') then + -- link_down_ctr_lock <= '0'; + -- elsif ((PCS_AN_COMPLETE_IN = '0') and (link_down_ctr_lock = '0')) then + -- link_down_ctr <= link_down_ctr + x"1"; + -- link_down_ctr_lock <= '1'; + -- end if; + -- end if; + --end process LINK_DOWN_CTR_PROC; + + MC_LINK_OK_OUT <= link_ok; -- or nothing_sent; + + -- END OF LINK STATE CONTROL + --************* + + --************* + -- GENERATE MAC_ADDRESS + --g_MY_MAC <= unique_id(31 downto 8) & x"be0002"; + MC_MY_MAC_OUT <= unique_id(31 downto 8) & x"be0002"; + + --************* + + --**************** + -- TRI SPEED MAC CONTROLLER + + --TSMAC_CONTROLLER : trb_net16_gbe_mac_control + --port map( + -- CLK => CLK, + -- RESET => MC_RESET_LINK_IN, + -- + ---- signals to/from main controller + -- MC_TSMAC_READY_OUT => tsm_ready, + -- MC_RECONF_IN => tsm_reconf, + -- MC_GBE_EN_IN => '1', + -- MC_RX_DISCARD_FCS => '0', + -- MC_PROMISC_IN => '1', + -- MC_MAC_ADDR_IN => g_MY_MAC, --x"001122334455", + -- + ---- signal to/from Host interface of TriSpeed MAC + -- TSM_HADDR_OUT => tsm_haddr, + -- TSM_HDATA_OUT => tsm_hdata, + -- TSM_HCS_N_OUT => tsm_hcs_n, + -- TSM_HWRITE_N_OUT => tsm_hwrite_n, + -- TSM_HREAD_N_OUT => tsm_hread_n, + -- TSM_HREADY_N_IN => TSM_HREADY_N_IN, + -- TSM_HDATA_EN_N_IN => TSM_HDATA_EN_N_IN, + -- + -- DEBUG_OUT => open + --); + + --DEBUG_OUT <= mac_control_debug; + process(CLK) + begin + if rising_edge(CLK) then + if link_current_state = INACTIVE and PCS_AN_COMPLETE_IN = '1' then + tsm_reconf <= '1'; + else + tsm_reconf <= '0'; + end if; + end if; + end process; + MAC_RECONF_OUT <= tsm_reconf; + --tsm_reconf <= '1' when (link_current_state = INACTIVE) and (PCS_AN_COMPLETE_IN = '0') else '0'; + + TSM_HADDR_OUT <= tsm_haddr; + TSM_HCS_N_OUT <= tsm_hcs_n; + TSM_HDATA_OUT <= tsm_hdata; + TSM_HREAD_N_OUT <= tsm_hread_n; + TSM_HWRITE_N_OUT <= tsm_hwrite_n; + + -- END OF TRI SPEED MAC CONTROLLER + --*************** + + + -- ***** + -- STATISTICS + -- ***** + + -- + --CTRS_GEN : for n in 0 to 15 generate + -- + -- CTR_PROC : process(CLK) + -- begin + -- if rising_edge(CLK) then + -- if (RESET = '1') then + -- arr(n) <= (others => '0'); + -- elsif (rx_stat_en_q = '1' and rx_stat_vec_q(16 + n) = '1') then + -- arr(n) <= arr(n) + x"1"; + -- end if; + -- end if; + -- end process CTR_PROC; + -- + --end generate CTRS_GEN; + -- + --STAT_VEC_SYNC : signal_sync + --generic map ( + -- WIDTH => 32, + -- DEPTH => 2 + --) + --port map ( + -- RESET => RESET, + -- CLK0 => CLK, + -- CLK1 => CLK, + -- D_IN => TSM_RX_STAT_VEC_IN, + -- D_OUT => rx_stat_vec_q + --); + -- + -- + --STAT_VEC_EN_SYNC : pulse_sync + --port map( + -- CLK_A_IN => CLK_125, + -- RESET_A_IN => RESET, + -- PULSE_A_IN => TSM_RX_STAT_EN_IN, + -- CLK_B_IN => CLK, + -- RESET_B_IN => RESET, + -- PULSE_B_OUT => rx_stat_en_q + --); + -- + -- + --STATS_MACHINE_PROC : process(CLK) + --begin + -- if rising_edge(CLK) then + -- if (RESET = '1') then + -- stats_current_state <= IDLE; + -- else + -- stats_current_state <= stats_next_state; + -- end if; + -- end if; + --end process STATS_MACHINE_PROC; + -- + --STATS_MACHINE : process(stats_current_state, rx_stat_en_q, stats_ctr) + --begin + -- + -- case (stats_current_state) is + -- + -- when IDLE => + -- if (rx_stat_en_q = '1') then + -- stats_next_state <= LOAD_VECTOR; + -- else + -- stats_next_state <= IDLE; + -- end if; + -- + -- when LOAD_VECTOR => + -- --if (stat_ack = '1') then + -- if (stats_ctr = 15) then + -- stats_next_state <= CLEANUP; + -- else + -- stats_next_state <= LOAD_VECTOR; + -- end if; + -- + -- when CLEANUP => + -- stats_next_state <= IDLE; + -- + -- end case; + -- + --end process STATS_MACHINE; + -- + --STATS_CTR_PROC : process(CLK) + --begin + -- if rising_edge(CLK) then + -- if (RESET = '1') or (stats_current_state = IDLE) then + -- stats_ctr <= 0; + -- elsif (stats_current_state = LOAD_VECTOR and stat_ack ='1') then + -- stats_ctr <= stats_ctr + 1; + -- end if; + -- end if; + --end process STATS_CTR_PROC; + -- + ----stat_data <= arr(stats_ctr); + -- + --stat_addr <= x"0c" + std_logic_vector(to_unsigned(stats_ctr, 8)); + -- + --stat_rdy <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; + -- + --stat_data(7 downto 0) <= arr(stats_ctr)(31 downto 24); + --stat_data(15 downto 8) <= arr(stats_ctr)(23 downto 16); + --stat_data(23 downto 16) <= arr(stats_ctr)(15 downto 8); + --stat_data(31 downto 24) <= arr(stats_ctr)(7 downto 0); + + + -- **** debug + --FRAME_WAITING_CTR_PROC : process(CLK) + --begin + -- if rising_edge(CLK) then + -- if (RESET = '1') then + -- frame_waiting_ctr <= (others => '0'); + -- elsif (RC_FRAME_WAITING_IN = '1') then + -- frame_waiting_ctr <= frame_waiting_ctr + x"1"; + -- end if; + -- end if; + --end process FRAME_WAITING_CTR_PROC; + -- + --SAVE_VALUES_PROC : process(CLK) + --begin + -- if rising_edge(CLK) then + -- if (RESET = '1') then + -- ps_busy_q <= (others => '0'); + -- rc_frame_proto_q <= (others => '0'); + -- elsif (redirect_current_state = IDLE and RC_FRAME_WAITING_IN = '1') then + -- ps_busy_q <= ps_busy; + -- rc_frame_proto_q <= RC_FRAME_PROTO_IN; + -- end if; + -- end if; + --end process SAVE_VALUES_PROC; + + + -- **** + + process(CLK) + begin + if rising_edge(CLK) then + DEBUG_OUT(3 downto 0) <= redirect_state; + DEBUG_OUT(7 downto 4) <= flow_state; + DEBUG_OUT(11 downto 8) <= link_state; + DEBUG_OUT(31 downto 12) <= (others => '0'); + + DEBUG_OUT(63 downto 32) <= selector_debug(31 downto 0); + end if; + end process; end trb_net16_gbe_main_control; \ No newline at end of file diff --git a/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd b/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd index 3489079..300b96f 100644 --- a/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd +++ b/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd @@ -146,7 +146,9 @@ port ( MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); DATA_HIST_OUT : out hist_array; - SCTRL_HIST_OUT : out hist_array + SCTRL_HIST_OUT : out hist_array; + + DEBUG_OUT : out std_logic_vector(63 downto 0) ); end trb_net16_gbe_protocol_selector; @@ -204,6 +206,7 @@ attribute syn_keep of state, mult : signal is true; attribute syn_preserve of state, mult : signal is true; signal my_ip : std_logic_vector(31 downto 0); +signal select_state : std_logic_vector(3 downto 0); begin @@ -662,10 +665,12 @@ end process SELECT_MACHINE_PROC; SELECT_MACHINE : process(select_current_state, MC_BUSY_IN, resp_ready, index, zeros, busy) begin + select_state <= x"0"; case (select_current_state) is - when IDLE => + when IDLE => + select_state <= x"1"; if (MC_BUSY_IN = '0') then select_next_state <= LOOP_OVER; else @@ -673,6 +678,7 @@ begin end if; when LOOP_OVER => + select_state <= x"2"; if (resp_ready /= zeros) then if (resp_ready(index) = '1') then select_next_state <= SELECT_ONE; @@ -686,6 +692,7 @@ begin end if; when SELECT_ONE => + select_state <= x"3"; if (MC_BUSY_IN = '1') then select_next_state <= PROCESS_REQUEST; else @@ -693,6 +700,7 @@ begin end if; when PROCESS_REQUEST => + select_state <= x"4"; if (busy(index) = '0') then --if (MC_BUSY_IN = '0') then select_next_state <= CLEANUP; else @@ -700,7 +708,10 @@ begin end if; when CLEANUP => + select_state <= x"5"; select_next_state <= IDLE; + + when others => select_next_state <= IDLE; end case; @@ -759,6 +770,17 @@ begin end if; end process SELECTOR_PROC; +process(CLK) +begin + if rising_edge(CLK) then + DEBUG_OUT(3 downto 0) <= select_state; + DEBUG_OUT(11 downto 4) <= std_logic_vector(to_unsigned(index, 8)); + DEBUG_OUT(19 downto 12) <= "000" & resp_ready; -- 4:0 + DEBUG_OUT(27 downto 20) <= "000" & busy; -- 4:0 + DEBUG_OUT(63 downto 28) <= (others => '0'); + end if; +end process; + end trb_net16_gbe_protocol_selector; diff --git a/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd b/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd index f48d76a..ed92de7 100644 --- a/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd +++ b/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd @@ -56,7 +56,9 @@ port ( SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0) + MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0); + + DEBUG_OUT : out std_logic_vector(63 downto 0) ); end trb_net16_gbe_transmit_control2; @@ -76,6 +78,7 @@ signal actual_frame_bytes, full_packet_size, ip_size, packet_loaded_bytes : std_ signal go_to_divide, more_fragments : std_logic; signal first_frame : std_logic; signal mon_packets_sent_ctr : std_logic_vector(31 downto 0); +signal state : std_logic_vector(3 downto 0); begin @@ -90,9 +93,11 @@ end process TRANSMIT_MACHINE_PROC; TRANSMIT_MACHINE : process(transmit_current_state, FC_H_READY_IN, TC_DATAREADY_IN, FC_READY_IN, local_end, TC_MAX_FRAME_IN, actual_frame_bytes, go_to_divide) begin + state <= x"0"; case transmit_current_state is - when IDLE => + when IDLE => + state <= x"1"; if (TC_DATAREADY_IN = '1') then transmit_next_state <= PREPARE_HEADERS; else @@ -100,9 +105,11 @@ begin end if; when PREPARE_HEADERS => + state <= x"2"; transmit_next_state<= WAIT_FOR_H; when WAIT_FOR_H => + state <= x"3"; if (FC_H_READY_IN = '1') then transmit_next_state <= TRANSMIT; else @@ -110,6 +117,7 @@ begin end if; when TRANSMIT => + state <= x"4"; if (local_end = x"0000") then transmit_next_state <= SEND_ONE; else @@ -121,15 +129,19 @@ begin end if; when SEND_ONE => + state <= x"5"; transmit_next_state <= SEND_TWO; when SEND_TWO => + state <= x"6"; transmit_next_state <= CLOSE; when CLOSE => + state <= x"7"; transmit_next_state <= WAIT_FOR_TRANS; when WAIT_FOR_TRANS => + state <= x"8"; if (FC_READY_IN = '1') then if (go_to_divide = '1') then transmit_next_state <= DIVIDE; @@ -141,9 +153,11 @@ begin end if; when DIVIDE => + state <= x"9"; transmit_next_state <= PREPARE_HEADERS; when CLEANUP => + state <= x"a"; transmit_next_state <= IDLE; end case; @@ -314,6 +328,10 @@ end process; MONITOR_TX_PACKETS_OUT <= mon_packets_sent_ctr; +DEBUG_OUT(3 downto 0) <= state; +DEBUG_OUT(4) <= FC_READY_IN; + + end trb_net16_gbe_transmit_control2; diff --git a/gbe_trb/base/trb_net_gbe_components.vhd b/gbe_trb/base/trb_net_gbe_components.vhd index 738c320..2508d4e 100644 --- a/gbe_trb/base/trb_net_gbe_components.vhd +++ b/gbe_trb/base/trb_net_gbe_components.vhd @@ -304,137 +304,137 @@ port ( ); end component; -component trb_net16_gbe_protocol_selector is -generic( - RX_PATH_ENABLE : integer range 0 to 1 := 1; - DO_SIMULATION : integer range 0 to 1 := 0; - - INCLUDE_READOUT : std_logic := '0'; - INCLUDE_SLOWCTRL : std_logic := '0'; - INCLUDE_DHCP : std_logic := '0'; - INCLUDE_ARP : std_logic := '0'; - INCLUDE_PING : std_logic := '0'; - - READOUT_BUFFER_SIZE : integer range 1 to 4; - SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 - ); -port ( - CLK : in std_logic; -- system clock - RESET : in std_logic; - RESET_FOR_DHCP : in std_logic; - --- signals to/from main controller - PS_DATA_IN : in std_logic_vector(8 downto 0); - PS_WR_EN_IN : in std_logic; - PS_PROTO_SELECT_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - PS_BUSY_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); - PS_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - PS_RESPONSE_READY_OUT : out std_logic; - - PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); - PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); - PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); - PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); - --- singals to/from transmi controller with constructed response - TC_DATA_OUT : out std_logic_vector(8 downto 0); - TC_RD_EN_IN : in std_logic; - TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); - TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); - TC_IDENT_OUT : out std_logic_vector(15 downto 0); - TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); - TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); - TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); - TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); - TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); - TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); - MC_BUSY_IN : in std_logic; - - -- misc signals for response constructors - MY_MAC_IN : in std_logic_vector(47 downto 0); - MY_IP_OUT : out std_logic_vector(31 downto 0); - DHCP_START_IN : in std_logic; - DHCP_DONE_OUT : out std_logic; - - GSC_CLK_IN : in std_logic; - GSC_INIT_DATAREADY_OUT : out std_logic; - GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); - GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); - GSC_INIT_READ_IN : in std_logic; - GSC_REPLY_DATAREADY_IN : in std_logic; - GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); - GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); - GSC_REPLY_READ_OUT : out std_logic; - GSC_BUSY_IN : in std_logic; - - MAKE_RESET_OUT : out std_logic; - - -- signal for data readout - -- CTS interface - CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - CTS_CODE_IN : in std_logic_vector (7 downto 0); - CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - CTS_START_READOUT_IN : in std_logic; - CTS_DATA_OUT : out std_logic_vector (31 downto 0); - CTS_DATAREADY_OUT : out std_logic; - CTS_READOUT_FINISHED_OUT : out std_logic; - CTS_READ_IN : in std_logic; - CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- Data payload interface - FEE_DATA_IN : in std_logic_vector (15 downto 0); - FEE_DATAREADY_IN : in std_logic; - FEE_READ_OUT : out std_logic; - FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - FEE_BUSY_IN : in std_logic; - -- ip configurator - SLV_ADDR_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_BUSY_OUT : out std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - - CFG_GBE_ENABLE_IN : in std_logic; - CFG_IPU_ENABLE_IN : in std_logic; - CFG_MULT_ENABLE_IN : in std_logic; - CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); - CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); - CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); - CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); - CFG_READOUT_CTR_VALID_IN : in std_logic; - CFG_INSERT_TTYPE_IN : in std_logic; - CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); - CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); - CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); - - CFG_ADDITIONAL_HDR_IN : in std_logic; - CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0); - - -- input for statistics from outside - STAT_DATA_IN : in std_logic_vector(31 downto 0); - STAT_ADDR_IN : in std_logic_vector(7 downto 0); - STAT_DATA_RDY_IN : in std_logic; - STAT_DATA_ACK_OUT : out std_logic; - - MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); - MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); - - DATA_HIST_OUT : out hist_array; - SCTRL_HIST_OUT : out hist_array -); -end component; +--component trb_net16_gbe_protocol_selector is +--generic( +-- RX_PATH_ENABLE : integer range 0 to 1 := 1; +-- DO_SIMULATION : integer range 0 to 1 := 0; +-- +-- INCLUDE_READOUT : std_logic := '0'; +-- INCLUDE_SLOWCTRL : std_logic := '0'; +-- INCLUDE_DHCP : std_logic := '0'; +-- INCLUDE_ARP : std_logic := '0'; +-- INCLUDE_PING : std_logic := '0'; +-- +-- READOUT_BUFFER_SIZE : integer range 1 to 4; +-- SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 +-- ); +--port ( +-- CLK : in std_logic; -- system clock +-- RESET : in std_logic; +-- RESET_FOR_DHCP : in std_logic; +-- +---- signals to/from main controller +-- PS_DATA_IN : in std_logic_vector(8 downto 0); +-- PS_WR_EN_IN : in std_logic; +-- PS_PROTO_SELECT_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); +-- PS_BUSY_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0); +-- PS_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); +-- PS_RESPONSE_READY_OUT : out std_logic; +-- +-- PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); +-- PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); +-- PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); +-- PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); +-- PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); +-- PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0); +-- +---- singals to/from transmi controller with constructed response +-- TC_DATA_OUT : out std_logic_vector(8 downto 0); +-- TC_RD_EN_IN : in std_logic; +-- TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); +-- TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); +-- TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); +-- TC_IDENT_OUT : out std_logic_vector(15 downto 0); +-- TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0); +-- TC_DEST_IP_OUT : out std_logic_vector(31 downto 0); +-- TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0); +-- TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0); +-- TC_SRC_IP_OUT : out std_logic_vector(31 downto 0); +-- TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0); +-- MC_BUSY_IN : in std_logic; +-- +-- -- misc signals for response constructors +-- MY_MAC_IN : in std_logic_vector(47 downto 0); +-- MY_IP_OUT : out std_logic_vector(31 downto 0); +-- DHCP_START_IN : in std_logic; +-- DHCP_DONE_OUT : out std_logic; +-- +-- GSC_CLK_IN : in std_logic; +-- GSC_INIT_DATAREADY_OUT : out std_logic; +-- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); +-- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0); +-- GSC_INIT_READ_IN : in std_logic; +-- GSC_REPLY_DATAREADY_IN : in std_logic; +-- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); +-- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0); +-- GSC_REPLY_READ_OUT : out std_logic; +-- GSC_BUSY_IN : in std_logic; +-- +-- MAKE_RESET_OUT : out std_logic; +-- +-- -- signal for data readout +-- -- CTS interface +-- CTS_NUMBER_IN : in std_logic_vector (15 downto 0); +-- CTS_CODE_IN : in std_logic_vector (7 downto 0); +-- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); +-- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); +-- CTS_START_READOUT_IN : in std_logic; +-- CTS_DATA_OUT : out std_logic_vector (31 downto 0); +-- CTS_DATAREADY_OUT : out std_logic; +-- CTS_READOUT_FINISHED_OUT : out std_logic; +-- CTS_READ_IN : in std_logic; +-- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); +-- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); +-- -- Data payload interface +-- FEE_DATA_IN : in std_logic_vector (15 downto 0); +-- FEE_DATAREADY_IN : in std_logic; +-- FEE_READ_OUT : out std_logic; +-- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); +-- FEE_BUSY_IN : in std_logic; +-- -- ip configurator +-- SLV_ADDR_IN : in std_logic_vector(7 downto 0); +-- SLV_READ_IN : in std_logic; +-- SLV_WRITE_IN : in std_logic; +-- SLV_BUSY_OUT : out std_logic; +-- SLV_ACK_OUT : out std_logic; +-- SLV_DATA_IN : in std_logic_vector(31 downto 0); +-- SLV_DATA_OUT : out std_logic_vector(31 downto 0); +-- +-- CFG_GBE_ENABLE_IN : in std_logic; +-- CFG_IPU_ENABLE_IN : in std_logic; +-- CFG_MULT_ENABLE_IN : in std_logic; +-- CFG_SUBEVENT_ID_IN : in std_logic_vector(31 downto 0); +-- CFG_SUBEVENT_DEC_IN : in std_logic_vector(31 downto 0); +-- CFG_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); +-- CFG_READOUT_CTR_IN : in std_logic_vector(23 downto 0); +-- CFG_READOUT_CTR_VALID_IN : in std_logic; +-- CFG_INSERT_TTYPE_IN : in std_logic; +-- CFG_MAX_SUB_IN : in std_logic_vector(15 downto 0); +-- CFG_MAX_QUEUE_IN : in std_logic_vector(15 downto 0); +-- CFG_MAX_SUBS_IN_QUEUE_IN : in std_logic_vector(15 downto 0); +-- CFG_MAX_SINGLE_SUB_IN : in std_logic_vector(15 downto 0); +-- +-- CFG_ADDITIONAL_HDR_IN : in std_logic; +-- CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0); +-- +-- -- input for statistics from outside +-- STAT_DATA_IN : in std_logic_vector(31 downto 0); +-- STAT_ADDR_IN : in std_logic_vector(7 downto 0); +-- STAT_DATA_RDY_IN : in std_logic; +-- STAT_DATA_ACK_OUT : out std_logic; +-- +-- MONITOR_SELECT_REC_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); +-- MONITOR_SELECT_REC_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); +-- MONITOR_SELECT_SENT_BYTES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); +-- MONITOR_SELECT_SENT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); +-- MONITOR_SELECT_DROP_IN_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); +-- MONITOR_SELECT_DROP_OUT_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0); +-- MONITOR_SELECT_GEN_DBG_OUT : out std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0); +-- +-- DATA_HIST_OUT : out hist_array; +-- SCTRL_HIST_OUT : out hist_array +--); +--end component; component trb_net16_gbe_mac_control is port ( diff --git a/gbe_trb/ipcores/ecp3/fifo_2048x8x16_cnt.lpc b/gbe_trb/ipcores/ecp3/fifo_2048x8x16_cnt.lpc new file mode 100644 index 0000000..6c9940b --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_2048x8x16_cnt.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.8 +ModuleName=fifo_2048x8x16_cnt +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/08/2015 +Time=13:54:24 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=2048 +Width=8 +RDepth=1024 +RWidth=16 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=1 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_2048x8x16_cnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 11 -data_width 8 -num_words 2048 -rdata_width 16 -no_enable -pe -1 -pf -1 -fill diff --git a/gbe_trb/ipcores/ecp3/fifo_2048x8x16_cnt.vhd b/gbe_trb/ipcores/ecp3/fifo_2048x8x16_cnt.vhd new file mode 100644 index 0000000..01d5de2 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_2048x8x16_cnt.vhd @@ -0,0 +1,1483 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.5.0.102 +-- Module Version: 5.8 +--/home/soft/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n fifo_2048x8x16_cnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 8 -depth 2048 -rdata_width 16 -no_enable -pe -1 -pf -1 -fill + +-- Sat Aug 8 13:54:24 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_2048x8x16_cnt is + port ( + Data: in std_logic_vector(7 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(15 downto 0); + WCNT: out std_logic_vector(11 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_2048x8x16_cnt; + +architecture Structure of fifo_2048x8x16_cnt is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal wcount_r0: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal wptr_11: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal wptr_0: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co5: std_logic; + signal co4: std_logic; + signal wcount_11: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal co5_1: std_logic; + signal co4_1: std_logic; + signal rcount_10: std_logic; + signal wfill_sub_0: std_logic; + signal precin: std_logic; + signal scuba_vhi: std_logic; + signal wptr_1: std_logic; + signal wfill_sub_1: std_logic; + signal wfill_sub_2: std_logic; + signal co0_2: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wfill_sub_3: std_logic; + signal wfill_sub_4: std_logic; + signal co1_2: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wfill_sub_5: std_logic; + signal wfill_sub_6: std_logic; + signal co2_2: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wfill_sub_7: std_logic; + signal wfill_sub_8: std_logic; + signal co3_2: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wfill_sub_9: std_logic; + signal wfill_sub_10: std_logic; + signal co4_2: std_logic; + signal wptr_10: std_logic; + signal wfill_sub_msb: std_logic; + signal co5_2d: std_logic; + signal co5_2: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_3: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_3: std_logic; + signal wcount_r7: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_3: std_logic; + signal wcount_r9: std_logic; + signal wcount_r10: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_3: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_4: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_4: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_4: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_4: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w8: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_4: std_logic; + signal rcount_w9: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_10: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8x16_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t24: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t23: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t22: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t21: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t20: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t19: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t18: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t17: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t16: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t15: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t14: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t13: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t12: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t11: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t10: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t9: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t8: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t7: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t6: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t5: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t4: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t3: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t2: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t1: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_0); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_1); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_2); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>r_gcount_w210, + DO0=>r_g2b_xor_cluster_0); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_gcount_w26, + DO0=>r_g2b_xor_cluster_1); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w21, AD0=>r_gcount_w22, DO0=>rcount_w1); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); + + XOR2_t0: XOR2 + port map (A=>wptr_11, B=>r_gcount_w210, Z=>wfill_sub_msb); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>scuba_vlo, DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>scuba_vlo, + ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, ADB7=>rptr_3, + ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6, ADB11=>rptr_7, + ADB12=>rptr_8, ADB13=>rptr_9, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), + DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), + DOB6=>Q(6), DOB7=>Q(7), DOB8=>open, DOB9=>Q(8), DOB10=>Q(9), + DOB11=>Q(10), DOB12=>Q(11), DOB13=>Q(12), DOB14=>Q(13), + DOB15=>Q(14), DOB16=>Q(15), DOB17=>open); + + FF_128: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_127: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_126: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_125: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_124: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_123: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_122: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_121: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_120: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_119: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_118: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_117: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_116: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_115: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_114: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_113: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_112: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_111: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_110: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_109: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_108: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_107: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_106: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_105: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_104: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_103: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_102: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_101: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_100: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_99: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_98: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_97: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_96: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_95: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_94: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_93: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_92: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_91: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_90: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_89: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_88: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_87: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_86: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_85: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_84: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_83: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_82: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_81: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_80: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_79: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_78: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_77: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_76: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_75: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_74: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_73: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_72: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_71: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_70: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_69: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_68: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_67: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_66: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_65: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_64: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_63: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_62: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_61: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_60: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_59: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_58: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_57: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_56: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_55: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_54: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_53: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_52: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_51: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_50: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_49: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_48: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_47: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_46: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_45: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_44: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_43: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_42: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_41: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_40: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_39: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_38: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_37: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_36: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_35: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_34: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_33: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_32: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_31: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_30: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_29: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_28: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_27: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_26: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_25: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_24: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_23: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_22: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_21: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_20: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_19: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_18: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_17: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_16: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_15: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_14: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_13: FD1S3DX + port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); + + FF_12: FD1S3DX + port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); + + FF_11: FD1S3DX + port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); + + FF_10: FD1S3DX + port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); + + FF_9: FD1S3DX + port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); + + FF_8: FD1S3DX + port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); + + FF_7: FD1S3DX + port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); + + FF_6: FD1S3DX + port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); + + FF_5: FD1S3DX + port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); + + FF_4: FD1S3DX + port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); + + FF_3: FD1S3DX + port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); + + FF_2: FD1S3DX + port map (D=>wptr_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_1, + NC0=>ircount_10, NC1=>open); + + precin_inst271: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + wfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wptr_1, B0=>scuba_vlo, + B1=>rcount_w0, BI=>precin, BOUT=>co0_2, S0=>open, + S1=>wfill_sub_0); + + wfill_1: FSUB2B + port map (A0=>wptr_2, A1=>wptr_3, B0=>rcount_w1, B1=>rcount_w2, + BI=>co0_2, BOUT=>co1_2, S0=>wfill_sub_1, S1=>wfill_sub_2); + + wfill_2: FSUB2B + port map (A0=>wptr_4, A1=>wptr_5, B0=>rcount_w3, B1=>rcount_w4, + BI=>co1_2, BOUT=>co2_2, S0=>wfill_sub_3, S1=>wfill_sub_4); + + wfill_3: FSUB2B + port map (A0=>wptr_6, A1=>wptr_7, B0=>rcount_w5, B1=>rcount_w6, + BI=>co2_2, BOUT=>co3_2, S0=>wfill_sub_5, S1=>wfill_sub_6); + + wfill_4: FSUB2B + port map (A0=>wptr_8, A1=>wptr_9, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w8, BI=>co3_2, BOUT=>co4_2, S0=>wfill_sub_7, + S1=>wfill_sub_8); + + wfill_5: FSUB2B + port map (A0=>wptr_10, A1=>wfill_sub_msb, B0=>rcount_w9, + B1=>scuba_vlo, BI=>co4_2, BOUT=>co5_2, S0=>wfill_sub_9, + S1=>wfill_sub_10); + + wfilld: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co5_2, COUT=>open, S0=>co5_2d, S1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r1, + B1=>wcount_r2, CI=>cmp_ci, GE=>co0_3); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r3, + B1=>wcount_r4, CI=>co0_3, GE=>co1_3); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r5, + B1=>wcount_r6, CI=>co1_3, GE=>co2_3); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r7, + B1=>w_g2b_xor_cluster_0, CI=>co2_3, GE=>co3_3); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r9, + B1=>wcount_r10, CI=>co3_3, GE=>co4_3); + + empty_cmp_5: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co4_3, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>rcount_w0, CI=>cmp_ci_1, GE=>co0_4); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w1, + B1=>rcount_w2, CI=>co0_4, GE=>co1_4); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w3, + B1=>rcount_w4, CI=>co1_4, GE=>co2_4); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w5, + B1=>rcount_w6, CI=>co2_4, GE=>co3_4); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w8, CI=>co3_4, GE=>co4_4); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w9, + B1=>full_cmp_clr, CI=>co4_4, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_2048x8x16_cnt is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.lpc b/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.lpc new file mode 100644 index 0000000..57245ed --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.8 +ModuleName=fifo_2kx9x18_wcnt +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/08/2015 +Time=14:48:54 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=2048 +Width=9 +RDepth=1024 +RWidth=18 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=1 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_2kx9x18_wcnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 11 -data_width 9 -num_words 2048 -rdata_width 18 -no_enable -pe -1 -pf -1 -fill diff --git a/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd b/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd new file mode 100644 index 0000000..431edd5 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd @@ -0,0 +1,1483 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.5.0.102 +-- Module Version: 5.8 +--/home/soft/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n fifo_2kx9x18_wcnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 9 -depth 2048 -rdata_width 18 -no_enable -pe -1 -pf -1 -fill + +-- Sat Aug 8 14:48:54 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_2kx9x18_wcnt is + port ( + Data: in std_logic_vector(8 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(17 downto 0); + WCNT: out std_logic_vector(11 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_2kx9x18_wcnt; + +architecture Structure of fifo_2kx9x18_wcnt is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal wcount_r0: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal wptr_11: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal wptr_0: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co5: std_logic; + signal co4: std_logic; + signal wcount_11: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal co5_1: std_logic; + signal co4_1: std_logic; + signal rcount_10: std_logic; + signal wfill_sub_0: std_logic; + signal precin: std_logic; + signal scuba_vhi: std_logic; + signal wptr_1: std_logic; + signal wfill_sub_1: std_logic; + signal wfill_sub_2: std_logic; + signal co0_2: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wfill_sub_3: std_logic; + signal wfill_sub_4: std_logic; + signal co1_2: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wfill_sub_5: std_logic; + signal wfill_sub_6: std_logic; + signal co2_2: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wfill_sub_7: std_logic; + signal wfill_sub_8: std_logic; + signal co3_2: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wfill_sub_9: std_logic; + signal wfill_sub_10: std_logic; + signal co4_2: std_logic; + signal wptr_10: std_logic; + signal wfill_sub_msb: std_logic; + signal co5_2d: std_logic; + signal co5_2: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_3: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_3: std_logic; + signal wcount_r7: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_3: std_logic; + signal wcount_r9: std_logic; + signal wcount_r10: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_3: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_4: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_4: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_4: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_4: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w8: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_4: std_logic; + signal rcount_w9: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_10: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2kx9x18_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t24: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t23: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t22: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t21: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t20: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t19: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t18: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t17: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t16: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t15: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t14: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t13: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t12: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t11: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t10: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t9: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t8: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t7: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t6: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t5: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t4: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t3: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t2: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t1: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_0); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_1); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_2); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>r_gcount_w210, + DO0=>r_g2b_xor_cluster_0); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_gcount_w26, + DO0=>r_g2b_xor_cluster_1); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w21, AD0=>r_gcount_w22, DO0=>rcount_w1); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); + + XOR2_t0: XOR2 + port map (A=>wptr_11, B=>r_gcount_w210, Z=>wfill_sub_msb); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>scuba_vlo, + ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2, ADB7=>rptr_3, + ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6, ADB11=>rptr_7, + ADB12=>rptr_8, ADB13=>rptr_9, CEB=>rden_i, CLKB=>RdClock, + OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), + DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), + DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), DOB9=>Q(9), DOB10=>Q(10), + DOB11=>Q(11), DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14), + DOB15=>Q(15), DOB16=>Q(16), DOB17=>Q(17)); + + FF_128: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_127: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_126: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_125: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_124: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_123: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_122: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_121: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_120: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_119: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_118: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_117: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_116: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_115: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_114: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_113: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_112: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_111: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_110: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_109: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_108: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_107: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_106: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_105: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_104: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_103: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_102: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_101: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_100: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_99: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_98: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_97: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_96: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_95: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_94: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_93: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_92: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_91: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_90: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_89: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_88: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_87: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_86: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_85: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_84: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_83: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_82: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_81: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_80: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_79: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_78: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_77: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_76: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_75: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_74: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_73: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_72: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_71: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_70: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_69: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_68: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_67: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_66: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_65: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_64: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_63: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_62: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_61: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_60: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_59: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_58: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_57: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_56: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_55: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_54: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_53: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_52: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_51: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_50: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_49: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_48: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_47: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_46: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_45: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_44: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_43: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_42: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_41: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_40: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_39: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_38: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_37: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_36: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_35: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_34: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_33: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_32: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_31: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_30: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_29: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_28: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_27: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_26: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_25: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_24: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_23: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_22: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_21: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_20: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_19: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_18: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_17: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_16: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_15: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_14: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_13: FD1S3DX + port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); + + FF_12: FD1S3DX + port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); + + FF_11: FD1S3DX + port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); + + FF_10: FD1S3DX + port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); + + FF_9: FD1S3DX + port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); + + FF_8: FD1S3DX + port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); + + FF_7: FD1S3DX + port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); + + FF_6: FD1S3DX + port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); + + FF_5: FD1S3DX + port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); + + FF_4: FD1S3DX + port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); + + FF_3: FD1S3DX + port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); + + FF_2: FD1S3DX + port map (D=>wptr_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_1, + NC0=>ircount_10, NC1=>open); + + precin_inst274: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + wfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wptr_1, B0=>scuba_vlo, + B1=>rcount_w0, BI=>precin, BOUT=>co0_2, S0=>open, + S1=>wfill_sub_0); + + wfill_1: FSUB2B + port map (A0=>wptr_2, A1=>wptr_3, B0=>rcount_w1, B1=>rcount_w2, + BI=>co0_2, BOUT=>co1_2, S0=>wfill_sub_1, S1=>wfill_sub_2); + + wfill_2: FSUB2B + port map (A0=>wptr_4, A1=>wptr_5, B0=>rcount_w3, B1=>rcount_w4, + BI=>co1_2, BOUT=>co2_2, S0=>wfill_sub_3, S1=>wfill_sub_4); + + wfill_3: FSUB2B + port map (A0=>wptr_6, A1=>wptr_7, B0=>rcount_w5, B1=>rcount_w6, + BI=>co2_2, BOUT=>co3_2, S0=>wfill_sub_5, S1=>wfill_sub_6); + + wfill_4: FSUB2B + port map (A0=>wptr_8, A1=>wptr_9, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w8, BI=>co3_2, BOUT=>co4_2, S0=>wfill_sub_7, + S1=>wfill_sub_8); + + wfill_5: FSUB2B + port map (A0=>wptr_10, A1=>wfill_sub_msb, B0=>rcount_w9, + B1=>scuba_vlo, BI=>co4_2, BOUT=>co5_2, S0=>wfill_sub_9, + S1=>wfill_sub_10); + + wfilld: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co5_2, COUT=>open, S0=>co5_2d, S1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r1, + B1=>wcount_r2, CI=>cmp_ci, GE=>co0_3); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r3, + B1=>wcount_r4, CI=>co0_3, GE=>co1_3); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r5, + B1=>wcount_r6, CI=>co1_3, GE=>co2_3); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r7, + B1=>w_g2b_xor_cluster_0, CI=>co2_3, GE=>co3_3); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r9, + B1=>wcount_r10, CI=>co3_3, GE=>co4_3); + + empty_cmp_5: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co4_3, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>rcount_w0, CI=>cmp_ci_1, GE=>co0_4); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w1, + B1=>rcount_w2, CI=>co0_4, GE=>co1_4); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w3, + B1=>rcount_w4, CI=>co1_4, GE=>co2_4); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w5, + B1=>rcount_w6, CI=>co2_4, GE=>co3_4); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w8, CI=>co3_4, GE=>co4_4); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w9, + B1=>full_cmp_clr, CI=>co4_4, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_2kx9x18_wcnt is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.lpc b/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.lpc new file mode 100644 index 0000000..25f1696 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.8 +ModuleName=fifo_32kx18x9_wcnt +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/08/2015 +Time=15:18:02 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=32768 +Width=18 +RDepth=65536 +RWidth=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Dynamic - Single Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=1 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_32kx18x9_wcnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -fill diff --git a/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.vhd b/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.vhd new file mode 100644 index 0000000..8864ea2 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.vhd @@ -0,0 +1,5100 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.5.0.102 +-- Module Version: 5.8 +--/home/soft/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n fifo_32kx18x9_wcnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 9 -no_enable -pe 0 -pf 0 -fill + +-- Sat Aug 8 15:18:02 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_32kx18x9_wcnt is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + AmEmptyThresh: in std_logic_vector(15 downto 0); + AmFullThresh: in std_logic_vector(14 downto 0); + Q: out std_logic_vector(8 downto 0); + WCNT: out std_logic_vector(15 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end fifo_32kx18x9_wcnt; + +architecture Structure of fifo_32kx18x9_wcnt is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal func_and_inet: std_logic; + signal func_and_inet_1: std_logic; + signal func_and_inet_2: std_logic; + signal func_and_inet_3: std_logic; + signal func_and_inet_4: std_logic; + signal func_and_inet_5: std_logic; + signal func_and_inet_6: std_logic; + signal func_and_inet_7: std_logic; + signal func_and_inet_8: std_logic; + signal func_and_inet_9: std_logic; + signal func_and_inet_10: std_logic; + signal func_and_inet_11: std_logic; + signal func_and_inet_12: std_logic; + signal func_and_inet_13: std_logic; + signal func_and_inet_14: std_logic; + signal func_and_inet_15: std_logic; + signal func_and_inet_16: std_logic; + signal func_and_inet_17: std_logic; + signal func_and_inet_18: std_logic; + signal func_and_inet_19: std_logic; + signal func_and_inet_20: std_logic; + signal func_and_inet_21: std_logic; + signal func_and_inet_22: std_logic; + signal func_and_inet_23: std_logic; + signal func_and_inet_24: std_logic; + signal func_and_inet_25: std_logic; + signal func_and_inet_26: std_logic; + signal func_and_inet_27: std_logic; + signal func_and_inet_28: std_logic; + signal func_and_inet_29: std_logic; + signal wptr_14_inv: std_logic; + signal func_and_inet_30: std_logic; + signal rptr_15_inv: std_logic; + signal func_and_inet_31: std_logic; + signal func_and_inet_32: std_logic; + signal func_and_inet_33: std_logic; + signal func_and_inet_34: std_logic; + signal func_and_inet_35: std_logic; + signal func_and_inet_36: std_logic; + signal func_and_inet_37: std_logic; + signal func_and_inet_38: std_logic; + signal func_and_inet_39: std_logic; + signal func_and_inet_40: std_logic; + signal func_and_inet_41: std_logic; + signal func_and_inet_42: std_logic; + signal func_and_inet_43: std_logic; + signal func_and_inet_44: std_logic; + signal func_and_inet_45: std_logic; + signal wptr_13_inv: std_logic; + signal func_and_inet_46: std_logic; + signal rptr_14_inv: std_logic; + signal func_and_inet_47: std_logic; + signal func_and_inet_48: std_logic; + signal func_and_inet_49: std_logic; + signal func_and_inet_50: std_logic; + signal func_and_inet_51: std_logic; + signal func_and_inet_52: std_logic; + signal func_and_inet_53: std_logic; + signal wptr_12_inv: std_logic; + signal func_and_inet_54: std_logic; + signal rptr_13_inv: std_logic; + signal func_and_inet_55: std_logic; + signal func_and_inet_56: std_logic; + signal func_and_inet_57: std_logic; + signal wptr_11_inv: std_logic; + signal func_and_inet_58: std_logic; + signal rptr_12_inv: std_logic; + signal func_and_inet_59: std_logic; + signal wptr_10_inv: std_logic; + signal func_and_inet_60: std_logic; + signal rptr_11_inv: std_logic; + signal func_and_inet_61: std_logic; + signal func_and_inet_62: std_logic; + signal func_and_inet_63: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_3: std_logic; + signal func_xor_inet_2: std_logic; + signal func_xor_inet_1: std_logic; + signal func_xor_inet: std_logic; + signal rcount_w0: std_logic; + signal func_xor_inet_4: std_logic; + signal func_xor_inet_5: std_logic; + signal rcnt_reg_15_inv: std_logic; + signal dec1_r10: std_logic; + signal dec0_p00: std_logic; + signal dec3_r11: std_logic; + signal dec2_p01: std_logic; + signal dec5_r12: std_logic; + signal dec4_p02: std_logic; + signal dec7_r13: std_logic; + signal dec6_p03: std_logic; + signal dec9_r14: std_logic; + signal dec8_p04: std_logic; + signal dec11_r15: std_logic; + signal dec10_p05: std_logic; + signal dec13_r16: std_logic; + signal dec12_p06: std_logic; + signal dec15_r17: std_logic; + signal dec14_p07: std_logic; + signal dec17_r18: std_logic; + signal dec16_p08: std_logic; + signal dec19_r19: std_logic; + signal dec18_p09: std_logic; + signal dec21_r110: std_logic; + signal dec20_p010: std_logic; + signal dec23_r111: std_logic; + signal dec22_p011: std_logic; + signal dec25_r112: std_logic; + signal dec24_p012: std_logic; + signal dec27_r113: std_logic; + signal dec26_p013: std_logic; + signal dec29_r114: std_logic; + signal dec28_p014: std_logic; + signal dec31_r115: std_logic; + signal dec30_p015: std_logic; + signal dec33_r116: std_logic; + signal dec32_p016: std_logic; + signal dec35_r117: std_logic; + signal dec34_p017: std_logic; + signal dec37_r118: std_logic; + signal dec36_p018: std_logic; + signal dec39_r119: std_logic; + signal dec38_p019: std_logic; + signal dec41_r120: std_logic; + signal dec40_p020: std_logic; + signal dec43_r121: std_logic; + signal dec42_p021: std_logic; + signal dec45_r122: std_logic; + signal dec44_p022: std_logic; + signal dec47_r123: std_logic; + signal dec46_p023: std_logic; + signal dec49_r124: std_logic; + signal dec48_p024: std_logic; + signal dec51_r125: std_logic; + signal dec50_p025: std_logic; + signal dec53_r126: std_logic; + signal dec52_p026: std_logic; + signal dec55_r127: std_logic; + signal dec54_p027: std_logic; + signal dec57_r128: std_logic; + signal dec56_p028: std_logic; + signal dec59_r129: std_logic; + signal dec58_p029: std_logic; + signal dec61_r130: std_logic; + signal dec60_p030: std_logic; + signal dec63_r131: std_logic; + signal dec62_p031: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal wptr_15: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal r_gdata_15: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_16: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rptr_13: std_logic; + signal rptr_14: std_logic; + signal rptr_15: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal r_gcount_16: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal r_gcount_w216: std_logic; + signal r_gcount_w16: std_logic; + signal rcnt_reg_16: std_logic; + signal empty_i: std_logic; + signal full_i: std_logic; + signal rRst: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co7: std_logic; + signal co6: std_logic; + signal wcount_15: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co6_1: std_logic; + signal ircount_16: std_logic; + signal co8: std_logic; + signal co7_1: std_logic; + signal rcount_16: std_logic; + signal mdout1_31_0: std_logic; + signal mdout1_30_0: std_logic; + signal mdout1_29_0: std_logic; + signal mdout1_28_0: std_logic; + signal mdout1_27_0: std_logic; + signal mdout1_26_0: std_logic; + signal mdout1_25_0: std_logic; + signal mdout1_24_0: std_logic; + signal mdout1_23_0: std_logic; + signal mdout1_22_0: std_logic; + signal mdout1_21_0: std_logic; + signal mdout1_20_0: std_logic; + signal mdout1_19_0: std_logic; + signal mdout1_18_0: std_logic; + signal mdout1_17_0: std_logic; + signal mdout1_16_0: std_logic; + signal mdout1_15_0: std_logic; + signal mdout1_14_0: std_logic; + signal mdout1_13_0: std_logic; + signal mdout1_12_0: std_logic; + signal mdout1_11_0: std_logic; + signal mdout1_10_0: std_logic; + signal mdout1_9_0: std_logic; + signal mdout1_8_0: std_logic; + signal mdout1_7_0: std_logic; + signal mdout1_6_0: std_logic; + signal mdout1_5_0: std_logic; + signal mdout1_4_0: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_31_1: std_logic; + signal mdout1_30_1: std_logic; + signal mdout1_29_1: std_logic; + signal mdout1_28_1: std_logic; + signal mdout1_27_1: std_logic; + signal mdout1_26_1: std_logic; + signal mdout1_25_1: std_logic; + signal mdout1_24_1: std_logic; + signal mdout1_23_1: std_logic; + signal mdout1_22_1: std_logic; + signal mdout1_21_1: std_logic; + signal mdout1_20_1: std_logic; + signal mdout1_19_1: std_logic; + signal mdout1_18_1: std_logic; + signal mdout1_17_1: std_logic; + signal mdout1_16_1: std_logic; + signal mdout1_15_1: std_logic; + signal mdout1_14_1: std_logic; + signal mdout1_13_1: std_logic; + signal mdout1_12_1: std_logic; + signal mdout1_11_1: std_logic; + signal mdout1_10_1: std_logic; + signal mdout1_9_1: std_logic; + signal mdout1_8_1: std_logic; + signal mdout1_7_1: std_logic; + signal mdout1_6_1: std_logic; + signal mdout1_5_1: std_logic; + signal mdout1_4_1: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_31_2: std_logic; + signal mdout1_30_2: std_logic; + signal mdout1_29_2: std_logic; + signal mdout1_28_2: std_logic; + signal mdout1_27_2: std_logic; + signal mdout1_26_2: std_logic; + signal mdout1_25_2: std_logic; + signal mdout1_24_2: std_logic; + signal mdout1_23_2: std_logic; + signal mdout1_22_2: std_logic; + signal mdout1_21_2: std_logic; + signal mdout1_20_2: std_logic; + signal mdout1_19_2: std_logic; + signal mdout1_18_2: std_logic; + signal mdout1_17_2: std_logic; + signal mdout1_16_2: std_logic; + signal mdout1_15_2: std_logic; + signal mdout1_14_2: std_logic; + signal mdout1_13_2: std_logic; + signal mdout1_12_2: std_logic; + signal mdout1_11_2: std_logic; + signal mdout1_10_2: std_logic; + signal mdout1_9_2: std_logic; + signal mdout1_8_2: std_logic; + signal mdout1_7_2: std_logic; + signal mdout1_6_2: std_logic; + signal mdout1_5_2: std_logic; + signal mdout1_4_2: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_31_3: std_logic; + signal mdout1_30_3: std_logic; + signal mdout1_29_3: std_logic; + signal mdout1_28_3: std_logic; + signal mdout1_27_3: std_logic; + signal mdout1_26_3: std_logic; + signal mdout1_25_3: std_logic; + signal mdout1_24_3: std_logic; + signal mdout1_23_3: std_logic; + signal mdout1_22_3: std_logic; + signal mdout1_21_3: std_logic; + signal mdout1_20_3: std_logic; + signal mdout1_19_3: std_logic; + signal mdout1_18_3: std_logic; + signal mdout1_17_3: std_logic; + signal mdout1_16_3: std_logic; + signal mdout1_15_3: std_logic; + signal mdout1_14_3: std_logic; + signal mdout1_13_3: std_logic; + signal mdout1_12_3: std_logic; + signal mdout1_11_3: std_logic; + signal mdout1_10_3: std_logic; + signal mdout1_9_3: std_logic; + signal mdout1_8_3: std_logic; + signal mdout1_7_3: std_logic; + signal mdout1_6_3: std_logic; + signal mdout1_5_3: std_logic; + signal mdout1_4_3: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_31_4: std_logic; + signal mdout1_30_4: std_logic; + signal mdout1_29_4: std_logic; + signal mdout1_28_4: std_logic; + signal mdout1_27_4: std_logic; + signal mdout1_26_4: std_logic; + signal mdout1_25_4: std_logic; + signal mdout1_24_4: std_logic; + signal mdout1_23_4: std_logic; + signal mdout1_22_4: std_logic; + signal mdout1_21_4: std_logic; + signal mdout1_20_4: std_logic; + signal mdout1_19_4: std_logic; + signal mdout1_18_4: std_logic; + signal mdout1_17_4: std_logic; + signal mdout1_16_4: std_logic; + signal mdout1_15_4: std_logic; + signal mdout1_14_4: std_logic; + signal mdout1_13_4: std_logic; + signal mdout1_12_4: std_logic; + signal mdout1_11_4: std_logic; + signal mdout1_10_4: std_logic; + signal mdout1_9_4: std_logic; + signal mdout1_8_4: std_logic; + signal mdout1_7_4: std_logic; + signal mdout1_6_4: std_logic; + signal mdout1_5_4: std_logic; + signal mdout1_4_4: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_31_5: std_logic; + signal mdout1_30_5: std_logic; + signal mdout1_29_5: std_logic; + signal mdout1_28_5: std_logic; + signal mdout1_27_5: std_logic; + signal mdout1_26_5: std_logic; + signal mdout1_25_5: std_logic; + signal mdout1_24_5: std_logic; + signal mdout1_23_5: std_logic; + signal mdout1_22_5: std_logic; + signal mdout1_21_5: std_logic; + signal mdout1_20_5: std_logic; + signal mdout1_19_5: std_logic; + signal mdout1_18_5: std_logic; + signal mdout1_17_5: std_logic; + signal mdout1_16_5: std_logic; + signal mdout1_15_5: std_logic; + signal mdout1_14_5: std_logic; + signal mdout1_13_5: std_logic; + signal mdout1_12_5: std_logic; + signal mdout1_11_5: std_logic; + signal mdout1_10_5: std_logic; + signal mdout1_9_5: std_logic; + signal mdout1_8_5: std_logic; + signal mdout1_7_5: std_logic; + signal mdout1_6_5: std_logic; + signal mdout1_5_5: std_logic; + signal mdout1_4_5: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_31_6: std_logic; + signal mdout1_30_6: std_logic; + signal mdout1_29_6: std_logic; + signal mdout1_28_6: std_logic; + signal mdout1_27_6: std_logic; + signal mdout1_26_6: std_logic; + signal mdout1_25_6: std_logic; + signal mdout1_24_6: std_logic; + signal mdout1_23_6: std_logic; + signal mdout1_22_6: std_logic; + signal mdout1_21_6: std_logic; + signal mdout1_20_6: std_logic; + signal mdout1_19_6: std_logic; + signal mdout1_18_6: std_logic; + signal mdout1_17_6: std_logic; + signal mdout1_16_6: std_logic; + signal mdout1_15_6: std_logic; + signal mdout1_14_6: std_logic; + signal mdout1_13_6: std_logic; + signal mdout1_12_6: std_logic; + signal mdout1_11_6: std_logic; + signal mdout1_10_6: std_logic; + signal mdout1_9_6: std_logic; + signal mdout1_8_6: std_logic; + signal mdout1_7_6: std_logic; + signal mdout1_6_6: std_logic; + signal mdout1_5_6: std_logic; + signal mdout1_4_6: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_31_7: std_logic; + signal mdout1_30_7: std_logic; + signal mdout1_29_7: std_logic; + signal mdout1_28_7: std_logic; + signal mdout1_27_7: std_logic; + signal mdout1_26_7: std_logic; + signal mdout1_25_7: std_logic; + signal mdout1_24_7: std_logic; + signal mdout1_23_7: std_logic; + signal mdout1_22_7: std_logic; + signal mdout1_21_7: std_logic; + signal mdout1_20_7: std_logic; + signal mdout1_19_7: std_logic; + signal mdout1_18_7: std_logic; + signal mdout1_17_7: std_logic; + signal mdout1_16_7: std_logic; + signal mdout1_15_7: std_logic; + signal mdout1_14_7: std_logic; + signal mdout1_13_7: std_logic; + signal mdout1_12_7: std_logic; + signal mdout1_11_7: std_logic; + signal mdout1_10_7: std_logic; + signal mdout1_9_7: std_logic; + signal mdout1_8_7: std_logic; + signal mdout1_7_7: std_logic; + signal mdout1_6_7: std_logic; + signal mdout1_5_7: std_logic; + signal mdout1_4_7: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_15_ff: std_logic; + signal rptr_14_ff: std_logic; + signal rptr_13_ff: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_31_8: std_logic; + signal mdout1_30_8: std_logic; + signal mdout1_29_8: std_logic; + signal mdout1_28_8: std_logic; + signal mdout1_27_8: std_logic; + signal mdout1_26_8: std_logic; + signal mdout1_25_8: std_logic; + signal mdout1_24_8: std_logic; + signal mdout1_23_8: std_logic; + signal mdout1_22_8: std_logic; + signal mdout1_21_8: std_logic; + signal mdout1_20_8: std_logic; + signal mdout1_19_8: std_logic; + signal mdout1_18_8: std_logic; + signal mdout1_17_8: std_logic; + signal mdout1_16_8: std_logic; + signal mdout1_15_8: std_logic; + signal mdout1_14_8: std_logic; + signal mdout1_13_8: std_logic; + signal mdout1_12_8: std_logic; + signal mdout1_11_8: std_logic; + signal mdout1_10_8: std_logic; + signal mdout1_9_8: std_logic; + signal mdout1_8_8: std_logic; + signal mdout1_7_8: std_logic; + signal mdout1_6_8: std_logic; + signal mdout1_5_8: std_logic; + signal mdout1_4_8: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal wcnt_sub_0: std_logic; + signal precin: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; + signal co0_2: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; + signal co1_2: std_logic; + signal wcnt_sub_5: std_logic; + signal wcnt_sub_6: std_logic; + signal co2_2: std_logic; + signal wcnt_sub_7: std_logic; + signal wcnt_sub_8: std_logic; + signal co3_2: std_logic; + signal wcnt_sub_9: std_logic; + signal wcnt_sub_10: std_logic; + signal co4_2: std_logic; + signal wcnt_sub_11: std_logic; + signal wcnt_sub_12: std_logic; + signal co5_2: std_logic; + signal wcnt_sub_13: std_logic; + signal wcnt_sub_14: std_logic; + signal co6_2: std_logic; + signal wcnt_sub_15: std_logic; + signal co7_2: std_logic; + signal wcnt_sub_msb: std_logic; + signal rcnt_sub_0: std_logic; + signal precin_1: std_logic; + signal rcnt_sub_1: std_logic; + signal rcnt_sub_2: std_logic; + signal co0_3: std_logic; + signal rcnt_sub_3: std_logic; + signal rcnt_sub_4: std_logic; + signal co1_3: std_logic; + signal rcnt_sub_5: std_logic; + signal rcnt_sub_6: std_logic; + signal co2_3: std_logic; + signal rcnt_sub_7: std_logic; + signal rcnt_sub_8: std_logic; + signal co3_3: std_logic; + signal rcnt_sub_9: std_logic; + signal rcnt_sub_10: std_logic; + signal co4_3: std_logic; + signal rcnt_sub_11: std_logic; + signal rcnt_sub_12: std_logic; + signal co5_3: std_logic; + signal rcnt_sub_13: std_logic; + signal rcnt_sub_14: std_logic; + signal co6_3: std_logic; + signal rcnt_sub_15: std_logic; + signal rcnt_sub_16: std_logic; + signal co7_3: std_logic; + signal rcnt_sub_msb: std_logic; + signal co8_1d: std_logic; + signal co8_1: std_logic; + signal wfill_sub_0: std_logic; + signal precin_2: std_logic; + signal scuba_vhi: std_logic; + signal wptr_0: std_logic; + signal wfill_sub_1: std_logic; + signal wfill_sub_2: std_logic; + signal co0_4: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wfill_sub_3: std_logic; + signal wfill_sub_4: std_logic; + signal co1_4: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wfill_sub_5: std_logic; + signal wfill_sub_6: std_logic; + signal co2_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wfill_sub_7: std_logic; + signal wfill_sub_8: std_logic; + signal co3_4: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wfill_sub_9: std_logic; + signal wfill_sub_10: std_logic; + signal co4_4: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wfill_sub_11: std_logic; + signal wfill_sub_12: std_logic; + signal co5_4: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wfill_sub_13: std_logic; + signal wfill_sub_14: std_logic; + signal co6_4: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal wfill_sub_15: std_logic; + signal co7_4: std_logic; + signal wfill_sub_msb: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_5: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_5: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_5: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_5: std_logic; + signal wcount_r7: std_logic; + signal wcount_r8: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_5: std_logic; + signal wcount_r9: std_logic; + signal wcount_r10: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_5: std_logic; + signal wcount_r11: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_5: std_logic; + signal wcount_r13: std_logic; + signal wcount_r14: std_logic; + signal rcount_14: std_logic; + signal rcount_15: std_logic; + signal co7_5: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_6: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_6: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_6: std_logic; + signal rcount_w7: std_logic; + signal rcount_w8: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_6: std_logic; + signal rcount_w9: std_logic; + signal rcount_w10: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_6: std_logic; + signal rcount_w11: std_logic; + signal rcount_w12: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_6: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w14: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_6: std_logic; + signal rcount_w15: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_14: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal rden_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcnt_reg_0: std_logic; + signal rcnt_reg_1: std_logic; + signal co0_7: std_logic; + signal rcnt_reg_2: std_logic; + signal rcnt_reg_3: std_logic; + signal co1_7: std_logic; + signal rcnt_reg_4: std_logic; + signal rcnt_reg_5: std_logic; + signal co2_7: std_logic; + signal rcnt_reg_6: std_logic; + signal rcnt_reg_7: std_logic; + signal co3_7: std_logic; + signal rcnt_reg_8: std_logic; + signal rcnt_reg_9: std_logic; + signal co4_7: std_logic; + signal rcnt_reg_10: std_logic; + signal rcnt_reg_11: std_logic; + signal co5_7: std_logic; + signal rcnt_reg_12: std_logic; + signal rcnt_reg_13: std_logic; + signal co6_7: std_logic; + signal rcnt_reg_14: std_logic; + signal rcnt_reg_15: std_logic; + signal co7_6: std_logic; + signal ae_clrsig: std_logic; + signal ae_setsig: std_logic; + signal ae_d: std_logic; + signal ae_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_3: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; + signal co0_8: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; + signal co1_8: std_logic; + signal wcnt_reg_4: std_logic; + signal wcnt_reg_5: std_logic; + signal co2_8: std_logic; + signal wcnt_reg_6: std_logic; + signal wcnt_reg_7: std_logic; + signal co3_8: std_logic; + signal wcnt_reg_8: std_logic; + signal wcnt_reg_9: std_logic; + signal co4_8: std_logic; + signal wcnt_reg_10: std_logic; + signal wcnt_reg_11: std_logic; + signal co5_8: std_logic; + signal wcnt_reg_12: std_logic; + signal wcnt_reg_13: std_logic; + signal co6_8: std_logic; + signal wcnt_reg_14: std_logic; + signal wcnt_reg_15: std_logic; + signal af_d: std_logic; + signal af_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX321 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; D4: in std_logic; D5: in std_logic; + D6: in std_logic; D7: in std_logic; D8: in std_logic; + D9: in std_logic; D10: in std_logic; D11: in std_logic; + D12: in std_logic; D13: in std_logic; D14: in std_logic; + D15: in std_logic; D16: in std_logic; D17: in std_logic; + D18: in std_logic; D19: in std_logic; D20: in std_logic; + D21: in std_logic; D22: in std_logic; D23: in std_logic; + D24: in std_logic; D25: in std_logic; D26: in std_logic; + D27: in std_logic; D28: in std_logic; D29: in std_logic; + D30: in std_logic; D31: in std_logic; SD1: in std_logic; + SD2: in std_logic; SD3: in std_logic; SD4: in std_logic; + SD5: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; + attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; + attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; + attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; + attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; + attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is ""; + attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is ""; + attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is ""; + attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is ""; + attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is ""; + attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is ""; + attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is ""; + attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is ""; + attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is ""; + attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is ""; + attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is ""; + attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is ""; + attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is ""; + attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is ""; + attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is ""; + attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is ""; + attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is ""; + attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is ""; + attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is ""; + attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is ""; + attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is ""; + attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is ""; + attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is ""; + attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is ""; + attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; + attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_32kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; + attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC"; + attribute GSR of FF_222 : label is "ENABLED"; + attribute GSR of FF_221 : label is "ENABLED"; + attribute GSR of FF_220 : label is "ENABLED"; + attribute GSR of FF_219 : label is "ENABLED"; + attribute GSR of FF_218 : label is "ENABLED"; + attribute GSR of FF_217 : label is "ENABLED"; + attribute GSR of FF_216 : label is "ENABLED"; + attribute GSR of FF_215 : label is "ENABLED"; + attribute GSR of FF_214 : label is "ENABLED"; + attribute GSR of FF_213 : label is "ENABLED"; + attribute GSR of FF_212 : label is "ENABLED"; + attribute GSR of FF_211 : label is "ENABLED"; + attribute GSR of FF_210 : label is "ENABLED"; + attribute GSR of FF_209 : label is "ENABLED"; + attribute GSR of FF_208 : label is "ENABLED"; + attribute GSR of FF_207 : label is "ENABLED"; + attribute GSR of FF_206 : label is "ENABLED"; + attribute GSR of FF_205 : label is "ENABLED"; + attribute GSR of FF_204 : label is "ENABLED"; + attribute GSR of FF_203 : label is "ENABLED"; + attribute GSR of FF_202 : label is "ENABLED"; + attribute GSR of FF_201 : label is "ENABLED"; + attribute GSR of FF_200 : label is "ENABLED"; + attribute GSR of FF_199 : label is "ENABLED"; + attribute GSR of FF_198 : label is "ENABLED"; + attribute GSR of FF_197 : label is "ENABLED"; + attribute GSR of FF_196 : label is "ENABLED"; + attribute GSR of FF_195 : label is "ENABLED"; + attribute GSR of FF_194 : label is "ENABLED"; + attribute GSR of FF_193 : label is "ENABLED"; + attribute GSR of FF_192 : label is "ENABLED"; + attribute GSR of FF_191 : label is "ENABLED"; + attribute GSR of FF_190 : label is "ENABLED"; + attribute GSR of FF_189 : label is "ENABLED"; + attribute GSR of FF_188 : label is "ENABLED"; + attribute GSR of FF_187 : label is "ENABLED"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t38: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_12: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t37: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_11: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t36: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t35: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t34: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t33: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t32: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t31: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t30: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t29: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t28: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t27: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t26: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t25: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t24: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t23: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t22: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t21: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t20: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t19: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t18: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t17: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t16: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t15: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t14: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t13: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t12: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t11: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t10: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t9: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t8: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t7: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t6: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + XOR2_t5: XOR2 + port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); + + INV_10: INV + port map (A=>wptr_10, Z=>wptr_10_inv); + + INV_9: INV + port map (A=>wptr_11, Z=>wptr_11_inv); + + INV_8: INV + port map (A=>wptr_12, Z=>wptr_12_inv); + + INV_7: INV + port map (A=>wptr_13, Z=>wptr_13_inv); + + INV_6: INV + port map (A=>wptr_14, Z=>wptr_14_inv); + + LUT4_180: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet); + + LUT4_179: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_p00); + + INV_5: INV + port map (A=>rptr_11, Z=>rptr_11_inv); + + INV_4: INV + port map (A=>rptr_12, Z=>rptr_12_inv); + + INV_3: INV + port map (A=>rptr_13, Z=>rptr_13_inv); + + INV_2: INV + port map (A=>rptr_14, Z=>rptr_14_inv); + + INV_1: INV + port map (A=>rptr_15, Z=>rptr_15_inv); + + LUT4_178: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_1); + + LUT4_177: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec1_r10); + + LUT4_176: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_2); + + LUT4_175: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec2_p01); + + LUT4_174: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_3); + + LUT4_173: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec3_r11); + + LUT4_172: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_4); + + LUT4_171: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec4_p02); + + LUT4_170: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_5); + + LUT4_169: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec5_r12); + + LUT4_168: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_6); + + LUT4_167: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec6_p03); + + LUT4_166: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_7); + + LUT4_165: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec7_r13); + + LUT4_164: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_8); + + LUT4_163: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec8_p04); + + LUT4_162: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_9); + + LUT4_161: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec9_r14); + + LUT4_160: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_10); + + LUT4_159: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); + + LUT4_158: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_11); + + LUT4_157: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); + + LUT4_156: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_12); + + LUT4_155: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); + + LUT4_154: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_13); + + LUT4_153: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); + + LUT4_152: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_14); + + LUT4_151: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); + + LUT4_150: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_15); + + LUT4_149: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); + + LUT4_148: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_16); + + LUT4_147: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); + + LUT4_146: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_17); + + LUT4_145: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); + + LUT4_144: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_18); + + LUT4_143: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); + + LUT4_142: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_19); + + LUT4_141: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); + + LUT4_140: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_20); + + LUT4_139: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); + + LUT4_138: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_21); + + LUT4_137: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); + + LUT4_136: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_22); + + LUT4_135: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); + + LUT4_134: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_23); + + LUT4_133: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); + + LUT4_132: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_24); + + LUT4_131: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); + + LUT4_130: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_25); + + LUT4_129: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); + + LUT4_128: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_26); + + LUT4_127: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); + + LUT4_126: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_27); + + LUT4_125: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); + + LUT4_124: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_28); + + LUT4_123: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); + + LUT4_122: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_29); + + LUT4_121: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); + + LUT4_120: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, + DO0=>func_and_inet_30); + + LUT4_119: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); + + LUT4_118: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_31); + + LUT4_117: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); + + LUT4_116: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_32); + + LUT4_115: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec32_p016); + + LUT4_114: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_33); + + LUT4_113: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec33_r116); + + LUT4_112: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_34); + + LUT4_111: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec34_p017); + + LUT4_110: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_35); + + LUT4_109: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec35_r117); + + LUT4_108: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_36); + + LUT4_107: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec36_p018); + + LUT4_106: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_37); + + LUT4_105: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec37_r118); + + LUT4_104: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_38); + + LUT4_103: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec38_p019); + + LUT4_102: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_39); + + LUT4_101: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec39_r119); + + LUT4_100: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_40); + + LUT4_99: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec40_p020); + + LUT4_98: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_41); + + LUT4_97: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec41_r120); + + LUT4_96: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_42); + + LUT4_95: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec42_p021); + + LUT4_94: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_43); + + LUT4_93: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec43_r121); + + LUT4_92: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_44); + + LUT4_91: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec44_p022); + + LUT4_90: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_45); + + LUT4_89: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec45_r122); + + LUT4_88: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_46); + + LUT4_87: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec46_p023); + + LUT4_86: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_47); + + LUT4_85: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec47_r123); + + LUT4_84: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_48); + + LUT4_83: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec48_p024); + + LUT4_82: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_49); + + LUT4_81: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec49_r124); + + LUT4_80: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_50); + + LUT4_79: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec50_p025); + + LUT4_78: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_51); + + LUT4_77: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec51_r125); + + LUT4_76: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_52); + + LUT4_75: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec52_p026); + + LUT4_74: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_53); + + LUT4_73: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec53_r126); + + LUT4_72: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_54); + + LUT4_71: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec54_p027); + + LUT4_70: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_55); + + LUT4_69: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec55_r127); + + LUT4_68: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_56); + + LUT4_67: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec56_p028); + + LUT4_66: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_57); + + LUT4_65: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec57_r128); + + LUT4_64: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_58); + + LUT4_63: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec58_p029); + + LUT4_62: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_59); + + LUT4_61: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec59_r129); + + LUT4_60: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_60); + + LUT4_59: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec60_p030); + + LUT4_58: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_61); + + LUT4_57: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec61_r130); + + LUT4_56: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, + DO0=>func_and_inet_62); + + LUT4_55: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec62_p031); + + LUT4_54: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_63); + + LUT4_53: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec63_r131); + + LUT4_52: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, + DO0=>w_g2b_xor_cluster_0); + + LUT4_51: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_1); + + LUT4_50: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_2); + + LUT4_49: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_3); + + LUT4_48: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_47: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); + + LUT4_46: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_45: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); + + LUT4_44: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); + + LUT4_43: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_42: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_41: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); + + LUT4_40: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r2); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r1); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r0); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>r_gcount_w216, + DO0=>r_g2b_xor_cluster_0); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_1); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_2); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_3); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w15); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, + AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, + DO0=>rcount_w10); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w3); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w2); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_4); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, + AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, + DO0=>func_xor_inet_5); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); + + XOR2_t4: XOR2 + port map (A=>wcount_15, B=>r_gcount_w216, Z=>wcnt_sub_msb); + + XOR2_t3: XOR2 + port map (A=>w_gcount_r215, B=>rcount_16, Z=>rcnt_sub_msb); + + XOR2_t2: XOR2 + port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + INV_0: INV + port map (A=>rcnt_reg_15, Z=>rcnt_reg_15_inv); + + AND2_t1: AND2 + port map (A=>rcnt_reg_16, B=>rcnt_reg_15_inv, Z=>ae_clrsig); + + AND2_t0: AND2 + port map (A=>rcnt_reg_16, B=>rcnt_reg_15, Z=>ae_setsig); + + pdp_ram_0_0_31: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec1_r10, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_30: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec3_r11, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_29: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec5_r12, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, + DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, + DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, + DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_28: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec7_r13, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, + DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, + DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, + DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_4_0_27: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec9_r14, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, + DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, + DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, + DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_5_0_26: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec11_r15, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, + DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, + DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, + DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_6_0_25: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec13_r16, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, + DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, + DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, + DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_7_0_24: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec15_r17, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, + DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, + DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, + DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_8_0_23: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec17_r18, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, + DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, + DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, + DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_9_0_22: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec19_r19, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, + DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, + DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, + DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_10_0_21: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec21_r110, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_10_0, DOB1=>mdout1_10_1, + DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, DOB4=>mdout1_10_4, + DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, DOB7=>mdout1_10_7, + DOB8=>mdout1_10_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_11_0_20: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec23_r111, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_11_0, DOB1=>mdout1_11_1, + DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, DOB4=>mdout1_11_4, + DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, DOB7=>mdout1_11_7, + DOB8=>mdout1_11_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_12_0_19: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec25_r112, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_12_0, DOB1=>mdout1_12_1, + DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, DOB4=>mdout1_12_4, + DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, DOB7=>mdout1_12_7, + DOB8=>mdout1_12_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_13_0_18: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec27_r113, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_13_0, DOB1=>mdout1_13_1, + DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, DOB4=>mdout1_13_4, + DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, DOB7=>mdout1_13_7, + DOB8=>mdout1_13_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_14_0_17: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec29_r114, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_14_0, DOB1=>mdout1_14_1, + DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, DOB4=>mdout1_14_4, + DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, DOB7=>mdout1_14_7, + DOB8=>mdout1_14_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_15_0_16: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec31_r115, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_15_0, DOB1=>mdout1_15_1, + DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, DOB4=>mdout1_15_4, + DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, DOB7=>mdout1_15_7, + DOB8=>mdout1_15_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_16_0_15: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec33_r116, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_16_0, DOB1=>mdout1_16_1, + DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, DOB4=>mdout1_16_4, + DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, DOB7=>mdout1_16_7, + DOB8=>mdout1_16_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_17_0_14: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec35_r117, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_17_0, DOB1=>mdout1_17_1, + DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, DOB4=>mdout1_17_4, + DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, DOB7=>mdout1_17_7, + DOB8=>mdout1_17_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_18_0_13: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec37_r118, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_18_0, DOB1=>mdout1_18_1, + DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, DOB4=>mdout1_18_4, + DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, DOB7=>mdout1_18_7, + DOB8=>mdout1_18_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_19_0_12: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec39_r119, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_19_0, DOB1=>mdout1_19_1, + DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, DOB4=>mdout1_19_4, + DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, DOB7=>mdout1_19_7, + DOB8=>mdout1_19_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_20_0_11: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec41_r120, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_20_0, DOB1=>mdout1_20_1, + DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, DOB4=>mdout1_20_4, + DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, DOB7=>mdout1_20_7, + DOB8=>mdout1_20_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_21_0_10: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec43_r121, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_21_0, DOB1=>mdout1_21_1, + DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, DOB4=>mdout1_21_4, + DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, DOB7=>mdout1_21_7, + DOB8=>mdout1_21_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_22_0_9: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec45_r122, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_22_0, DOB1=>mdout1_22_1, + DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, DOB4=>mdout1_22_4, + DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, DOB7=>mdout1_22_7, + DOB8=>mdout1_22_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_23_0_8: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec47_r123, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_23_0, DOB1=>mdout1_23_1, + DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, DOB4=>mdout1_23_4, + DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, DOB7=>mdout1_23_7, + DOB8=>mdout1_23_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_24_0_7: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec49_r124, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_24_0, DOB1=>mdout1_24_1, + DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, DOB4=>mdout1_24_4, + DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, DOB7=>mdout1_24_7, + DOB8=>mdout1_24_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_25_0_6: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec51_r125, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_25_0, DOB1=>mdout1_25_1, + DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, DOB4=>mdout1_25_4, + DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, DOB7=>mdout1_25_7, + DOB8=>mdout1_25_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_26_0_5: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec53_r126, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_26_0, DOB1=>mdout1_26_1, + DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, DOB4=>mdout1_26_4, + DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, DOB7=>mdout1_26_7, + DOB8=>mdout1_26_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_27_0_4: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec55_r127, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_27_0, DOB1=>mdout1_27_1, + DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, DOB4=>mdout1_27_4, + DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, DOB7=>mdout1_27_7, + DOB8=>mdout1_27_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_28_0_3: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec57_r128, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_28_0, DOB1=>mdout1_28_1, + DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, DOB4=>mdout1_28_4, + DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, DOB7=>mdout1_28_7, + DOB8=>mdout1_28_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_29_0_2: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec59_r129, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_29_0, DOB1=>mdout1_29_1, + DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, DOB4=>mdout1_29_4, + DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, DOB7=>mdout1_29_7, + DOB8=>mdout1_29_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_30_0_1: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec61_r130, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_30_0, DOB1=>mdout1_30_1, + DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, DOB4=>mdout1_30_4, + DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, DOB7=>mdout1_30_7, + DOB8=>mdout1_30_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_31_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec63_r131, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_31_0, DOB1=>mdout1_31_1, + DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, DOB4=>mdout1_31_4, + DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, DOB7=>mdout1_31_7, + DOB8=>mdout1_31_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_222: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_221: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_220: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_219: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_218: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_217: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_216: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_215: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_214: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_213: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_212: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_211: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_210: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_209: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_208: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_207: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_206: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_205: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_204: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_203: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_202: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_201: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_200: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_199: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_198: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_197: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_196: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_195: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_194: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_193: FD1P3DX + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_192: FD1P3DX + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_191: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_190: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_189: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_188: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_187: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_186: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_185: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_184: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_183: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_182: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_181: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_180: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_179: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_178: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_177: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_176: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_175: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_174: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_173: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_172: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_171: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_170: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_169: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_168: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_167: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_166: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_165: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_164: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_163: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_162: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_161: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_160: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_159: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_158: FD1P3DX + port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_16); + + FF_157: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_156: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_155: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_154: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_153: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_152: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_151: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_150: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_149: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_148: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_147: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_146: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_145: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_144: FD1P3DX + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_143: FD1P3DX + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_142: FD1P3DX + port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_141: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_16); + + FF_140: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_139: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_138: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_137: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_136: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_135: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_134: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_133: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_132: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_131: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_130: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_129: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_128: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_127: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_126: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_125: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_124: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_16); + + FF_123: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_122: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_121: FD1P3DX + port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_13_ff); + + FF_120: FD1P3DX + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_119: FD1P3DX + port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_15_ff); + + FF_118: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_117: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_116: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_115: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_114: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_113: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_112: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_111: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_110: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_109: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_108: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_107: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_106: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_105: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_104: FD1S3DX + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_103: FD1S3DX + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_102: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_101: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_100: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_99: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_98: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_97: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_96: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_95: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_94: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_93: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_92: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_91: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_90: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_89: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_88: FD1S3DX + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_87: FD1S3DX + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_86: FD1S3DX + port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); + + FF_85: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_84: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_83: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_82: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_81: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_80: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_79: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_78: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_77: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_76: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_75: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_74: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_73: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_72: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_71: FD1S3DX + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_70: FD1S3DX + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_69: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_68: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_67: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_66: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_65: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_64: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_63: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_62: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_61: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_60: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_59: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_58: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_57: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_56: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_55: FD1S3DX + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_54: FD1S3DX + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_53: FD1S3DX + port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w216); + + FF_52: FD1S3DX + port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); + + FF_51: FD1S3DX + port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); + + FF_50: FD1S3DX + port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); + + FF_49: FD1S3DX + port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); + + FF_48: FD1S3DX + port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); + + FF_47: FD1S3DX + port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); + + FF_46: FD1S3DX + port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); + + FF_45: FD1S3DX + port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); + + FF_44: FD1S3DX + port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8); + + FF_43: FD1S3DX + port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9); + + FF_42: FD1S3DX + port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10); + + FF_41: FD1S3DX + port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11); + + FF_40: FD1S3DX + port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12); + + FF_39: FD1S3DX + port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13); + + FF_38: FD1S3DX + port map (D=>wcnt_sub_14, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_14); + + FF_37: FD1S3DX + port map (D=>wcnt_sub_15, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_15); + + FF_36: FD1S3DX + port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); + + FF_35: FD1S3DX + port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); + + FF_34: FD1S3DX + port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); + + FF_33: FD1S3DX + port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); + + FF_32: FD1S3DX + port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); + + FF_31: FD1S3DX + port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); + + FF_30: FD1S3DX + port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); + + FF_29: FD1S3DX + port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); + + FF_28: FD1S3DX + port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8); + + FF_27: FD1S3DX + port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9); + + FF_26: FD1S3DX + port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10); + + FF_25: FD1S3DX + port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11); + + FF_24: FD1S3DX + port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12); + + FF_23: FD1S3DX + port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13); + + FF_22: FD1S3DX + port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14); + + FF_21: FD1S3DX + port map (D=>rcnt_sub_15, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_15); + + FF_20: FD1S3DX + port map (D=>rcnt_sub_16, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_16); + + FF_19: FD1S3DX + port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); + + FF_18: FD1S3DX + port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); + + FF_17: FD1S3DX + port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); + + FF_16: FD1S3DX + port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); + + FF_15: FD1S3DX + port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); + + FF_14: FD1S3DX + port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); + + FF_13: FD1S3DX + port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); + + FF_12: FD1S3DX + port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); + + FF_11: FD1S3DX + port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); + + FF_10: FD1S3DX + port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); + + FF_9: FD1S3DX + port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); + + FF_8: FD1S3DX + port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); + + FF_7: FD1S3DX + port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); + + FF_6: FD1S3DX + port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); + + FF_5: FD1S3DX + port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); + + FF_4: FD1S3DX + port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); + + FF_3: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_2: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_1: FD1S3BX + port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, + NC0=>iwcount_14, NC1=>iwcount_15); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, + NC0=>ircount_14, NC1=>ircount_15); + + r_gctr_8: CU2 + port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8, + NC0=>ircount_16, NC1=>open); + + mux_8: MUX321 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, + D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, + D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, + D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, + D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, + D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, + D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, + D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, + D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, + D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(0)); + + mux_7: MUX321 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, + D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, + D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, + D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, + D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, + D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, + D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, + D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, + D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, + D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(1)); + + mux_6: MUX321 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, + D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, + D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, + D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, + D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, + D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, + D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, + D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, + D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, + D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(2)); + + mux_5: MUX321 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, + D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, + D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, + D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, + D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, + D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, + D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, + D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, + D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, + D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(3)); + + mux_4: MUX321 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, + D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, + D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, + D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, + D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, + D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, + D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, + D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, + D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, + D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(4)); + + mux_3: MUX321 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, + D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, + D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, + D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, + D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, + D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, + D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, + D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, + D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, + D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(5)); + + mux_2: MUX321 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, + D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, + D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, + D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, + D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, + D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, + D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, + D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, + D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, + D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(6)); + + mux_1: MUX321 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, + D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, + D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, + D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, + D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, + D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, + D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, + D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, + D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, + D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(7)); + + mux_0: MUX321 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, + D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, + D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, + D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, + D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, + D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, + D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, + D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, + D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, + D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(8)); + + precin_inst843: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, + S1=>open); + + wcnt_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo, + B1=>rcount_w1, BI=>precin, BOUT=>co0_2, S0=>open, + S1=>wcnt_sub_0); + + wcnt_1: FSUB2B + port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2, + B1=>rcount_w3, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1, + S1=>wcnt_sub_2); + + wcnt_2: FSUB2B + port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4, + B1=>rcount_w5, BI=>co1_2, BOUT=>co2_2, S0=>wcnt_sub_3, + S1=>wcnt_sub_4); + + wcnt_3: FSUB2B + port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6, + B1=>rcount_w7, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5, + S1=>wcnt_sub_6); + + wcnt_4: FSUB2B + port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8, + B1=>rcount_w9, BI=>co3_2, BOUT=>co4_2, S0=>wcnt_sub_7, + S1=>wcnt_sub_8); + + wcnt_5: FSUB2B + port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10, + B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wcnt_sub_9, + S1=>wcnt_sub_10); + + wcnt_6: FSUB2B + port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2, + S0=>wcnt_sub_11, S1=>wcnt_sub_12); + + wcnt_7: FSUB2B + port map (A0=>wcount_13, A1=>wcount_14, B0=>rcount_w14, + B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wcnt_sub_13, + S1=>wcnt_sub_14); + + wcnt_8: FSUB2B + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wcnt_sub_15, + S1=>open); + + precin_inst886: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin_1, S0=>open, + S1=>open); + + rcnt_0: FSUB2B + port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>rcount_0, BI=>precin_1, BOUT=>co0_3, S0=>open, + S1=>rcnt_sub_0); + + rcnt_1: FSUB2B + port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1, + B1=>rcount_2, BI=>co0_3, BOUT=>co1_3, S0=>rcnt_sub_1, + S1=>rcnt_sub_2); + + rcnt_2: FSUB2B + port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3, + B1=>rcount_4, BI=>co1_3, BOUT=>co2_3, S0=>rcnt_sub_3, + S1=>rcnt_sub_4); + + rcnt_3: FSUB2B + port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5, + B1=>rcount_6, BI=>co2_3, BOUT=>co3_3, S0=>rcnt_sub_5, + S1=>rcnt_sub_6); + + rcnt_4: FSUB2B + port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7, + B1=>rcount_8, BI=>co3_3, BOUT=>co4_3, S0=>rcnt_sub_7, + S1=>rcnt_sub_8); + + rcnt_5: FSUB2B + port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9, + B1=>rcount_10, BI=>co4_3, BOUT=>co5_3, S0=>rcnt_sub_9, + S1=>rcnt_sub_10); + + rcnt_6: FSUB2B + port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rcount_11, + B1=>rcount_12, BI=>co5_3, BOUT=>co6_3, S0=>rcnt_sub_11, + S1=>rcnt_sub_12); + + rcnt_7: FSUB2B + port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r13, B0=>rcount_13, + B1=>rcount_14, BI=>co6_3, BOUT=>co7_3, S0=>rcnt_sub_13, + S1=>rcnt_sub_14); + + rcnt_8: FSUB2B + port map (A0=>wcount_r14, A1=>rcnt_sub_msb, B0=>rcount_15, + B1=>scuba_vlo, BI=>co7_3, BOUT=>co8_1, S0=>rcnt_sub_15, + S1=>rcnt_sub_16); + + rcntd: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co8_1, COUT=>open, S0=>co8_1d, S1=>open); + + precin_inst931: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin_2, S0=>open, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + wfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, + B1=>rcount_w1, BI=>precin_2, BOUT=>co0_4, S0=>open, + S1=>wfill_sub_0); + + wfill_1: FSUB2B + port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3, + BI=>co0_4, BOUT=>co1_4, S0=>wfill_sub_1, S1=>wfill_sub_2); + + wfill_2: FSUB2B + port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5, + BI=>co1_4, BOUT=>co2_4, S0=>wfill_sub_3, S1=>wfill_sub_4); + + wfill_3: FSUB2B + port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7, + BI=>co2_4, BOUT=>co3_4, S0=>wfill_sub_5, S1=>wfill_sub_6); + + wfill_4: FSUB2B + port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9, + BI=>co3_4, BOUT=>co4_4, S0=>wfill_sub_7, S1=>wfill_sub_8); + + wfill_5: FSUB2B + port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10, + B1=>rcount_w11, BI=>co4_4, BOUT=>co5_4, S0=>wfill_sub_9, + S1=>wfill_sub_10); + + wfill_6: FSUB2B + port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, BI=>co5_4, BOUT=>co6_4, + S0=>wfill_sub_11, S1=>wfill_sub_12); + + wfill_7: FSUB2B + port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14, + B1=>rcount_w15, BI=>co6_4, BOUT=>co7_4, S0=>wfill_sub_13, + S1=>wfill_sub_14); + + wfill_8: FSUB2B + port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co7_4, BOUT=>open, S0=>wfill_sub_15, + S1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>wcount_r0, CI=>cmp_ci, GE=>co0_5); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, + B1=>wcount_r2, CI=>co0_5, GE=>co1_5); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, + B1=>wcount_r4, CI=>co1_5, GE=>co2_5); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, + B1=>wcount_r6, CI=>co2_5, GE=>co3_5); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, + B1=>wcount_r8, CI=>co3_5, GE=>co4_5); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, + B1=>wcount_r10, CI=>co4_5, GE=>co5_5); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, + B1=>w_g2b_xor_cluster_0, CI=>co5_5, GE=>co6_5); + + empty_cmp_7: AGEB2 + port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13, + B1=>wcount_r14, CI=>co6_5, GE=>co7_5); + + empty_cmp_8: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co7_5, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, + B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_6); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, + B1=>rcount_w4, CI=>co0_6, GE=>co1_6); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, + B1=>rcount_w6, CI=>co1_6, GE=>co2_6); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, + B1=>rcount_w8, CI=>co2_6, GE=>co3_6); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, + B1=>rcount_w10, CI=>co3_6, GE=>co4_6); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11, + B1=>rcount_w12, CI=>co4_6, GE=>co5_6); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w14, CI=>co5_6, GE=>co6_6); + + full_cmp_7: AGEB2 + port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15, + B1=>full_cmp_clr, CI=>co6_6, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + ae_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + ae_cmp_0: AGEB2 + port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), + B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_7); + + ae_cmp_1: AGEB2 + port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), + B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_7, GE=>co1_7); + + ae_cmp_2: AGEB2 + port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), + B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_7, GE=>co2_7); + + ae_cmp_3: AGEB2 + port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7), + B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_7, GE=>co3_7); + + ae_cmp_4: AGEB2 + port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9), + B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_7, GE=>co4_7); + + ae_cmp_5: AGEB2 + port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11), + B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_7, GE=>co5_7); + + ae_cmp_6: AGEB2 + port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13), + B0=>rcnt_reg_12, B1=>rcnt_reg_13, CI=>co5_7, GE=>co6_7); + + ae_cmp_7: AGEB2 + port map (A0=>AmEmptyThresh(14), A1=>AmEmptyThresh(15), + B0=>rcnt_reg_14, B1=>rcnt_reg_15, CI=>co6_7, GE=>co7_6); + + ae_cmp_8: AGEB2 + port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig, + B1=>scuba_vlo, CI=>co7_6, GE=>ae_d_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); + + af_d_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); + + af_d_cmp_0: AGEB2 + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_8); + + af_d_cmp_1: AGEB2 + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), CI=>co0_8, GE=>co1_8); + + af_d_cmp_2: AGEB2 + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), CI=>co1_8, GE=>co2_8); + + af_d_cmp_3: AGEB2 + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), CI=>co2_8, GE=>co3_8); + + af_d_cmp_4: AGEB2 + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>AmFullThresh(9), CI=>co3_8, GE=>co4_8); + + af_d_cmp_5: AGEB2 + port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), + B1=>AmFullThresh(11), CI=>co4_8, GE=>co5_8); + + af_d_cmp_6: AGEB2 + port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), + B1=>AmFullThresh(13), CI=>co5_8, GE=>co6_8); + + af_d_cmp_7: AGEB2 + port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14), + B1=>scuba_vlo, CI=>co6_8, GE=>af_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a3: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_32kx18x9_wcnt is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX321 use entity ecp3.MUX321(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.lpc b/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.lpc new file mode 100644 index 0000000..d9fb54b --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.8 +ModuleName=fifo_4kx18x9_wcnt +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/08/2015 +Time=13:56:51 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=2048 +Width=18 +RDepth=4096 +RWidth=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=1 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_4kx18x9_wcnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 11 -data_width 18 -num_words 2048 -rdata_width 9 -no_enable -pe -1 -pf -1 -fill diff --git a/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd b/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd new file mode 100644 index 0000000..6b658a6 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd @@ -0,0 +1,1688 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.5.0.102 +-- Module Version: 5.8 +--/home/soft/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n fifo_4kx18x9_wcnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 18 -depth 2048 -rdata_width 9 -no_enable -pe -1 -pf -1 -fill + +-- Sat Aug 8 13:56:51 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_4kx18x9_wcnt is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + WCNT: out std_logic_vector(11 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_4kx18x9_wcnt; + +architecture Structure of fifo_4kx18x9_wcnt is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal rcount_w0: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal wptr_11: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_12: std_logic; + signal rptr_11: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co5: std_logic; + signal co4: std_logic; + signal wcount_11: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal co6: std_logic; + signal co5_1: std_logic; + signal rcount_12: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal wfill_sub_0: std_logic; + signal precin: std_logic; + signal scuba_vhi: std_logic; + signal wptr_0: std_logic; + signal wfill_sub_1: std_logic; + signal wfill_sub_2: std_logic; + signal co0_2: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wfill_sub_3: std_logic; + signal wfill_sub_4: std_logic; + signal co1_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wfill_sub_5: std_logic; + signal wfill_sub_6: std_logic; + signal co2_2: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wfill_sub_7: std_logic; + signal wfill_sub_8: std_logic; + signal co3_2: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wfill_sub_9: std_logic; + signal wfill_sub_10: std_logic; + signal co4_2: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wfill_sub_11: std_logic; + signal co5_2: std_logic; + signal wfill_sub_msb: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_3: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_3: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_3: std_logic; + signal wcount_r7: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_3: std_logic; + signal wcount_r9: std_logic; + signal wcount_r10: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_3: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_4: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_4: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_4: std_logic; + signal rcount_w7: std_logic; + signal rcount_w8: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_4: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w10: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_4: std_logic; + signal rcount_w11: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_10: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX21 + port (D0: in std_logic; D1: in std_logic; SD: in std_logic; + Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_4kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_0 : label is "fifo_4kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_0 : label is ""; + attribute RESETMODE of pdp_ram_1_0_0 : label is "SYNC"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t26: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t25: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t24: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t23: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t22: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t21: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t20: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t19: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t18: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t17: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t16: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t15: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t14: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t13: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t12: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t11: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t10: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t9: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t8: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t7: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t6: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t5: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t4: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t3: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t2: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t1: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_0); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_1); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_2); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_0); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_1); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_2); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w11); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>scuba_vlo, DO0=>rcount_w10); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>rcount_w10, DO0=>rcount_w7); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w20, DO0=>rcount_w0); + + XOR2_t0: XOR2 + port map (A=>wptr_11, B=>r_gcount_w212, Z=>wfill_sub_msb); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_12, AD2=>rcount_12, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w212, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_1: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>wptr_10, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, + DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, + DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, + DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_1_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>wptr_10, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>rptr_11, + CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, + DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, + DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, + DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, + DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, + DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, + DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, + DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); + + FF_139: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_138: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_137: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_136: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_135: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_134: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_133: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_132: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_131: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_130: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_129: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_128: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_127: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_126: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_125: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_124: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_123: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_122: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_121: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_120: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_119: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_118: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_117: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_116: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_115: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_114: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_113: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_112: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_111: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_110: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_109: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_108: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_107: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_106: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_105: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_104: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_103: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_102: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_101: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_100: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_99: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_98: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_97: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_96: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_95: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_94: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_93: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_92: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_91: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_90: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_89: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_88: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_87: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_86: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_85: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_84: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_83: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_82: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_81: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_80: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_79: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_78: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_77: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_76: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_75: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_74: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_73: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_72: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_71: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_70: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_69: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_68: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_67: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_66: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_65: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_64: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_63: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_62: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_61: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_60: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_59: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_58: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_57: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_56: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_55: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_54: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_53: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_52: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_51: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_50: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_49: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_48: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_47: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_46: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_45: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_44: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_43: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_42: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_41: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_40: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_39: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_38: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_37: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_36: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_35: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_34: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_33: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_32: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_31: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_30: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_29: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_28: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_27: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_26: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_25: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_24: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_23: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_22: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_21: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_20: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_19: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_18: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_17: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_16: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_15: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_14: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_13: FD1S3DX + port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); + + FF_12: FD1S3DX + port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); + + FF_11: FD1S3DX + port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); + + FF_10: FD1S3DX + port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); + + FF_9: FD1S3DX + port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); + + FF_8: FD1S3DX + port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); + + FF_7: FD1S3DX + port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); + + FF_6: FD1S3DX + port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); + + FF_5: FD1S3DX + port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); + + FF_4: FD1S3DX + port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); + + FF_3: FD1S3DX + port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); + + FF_2: FD1S3DX + port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>scuba_vlo, CO=>co6, + NC0=>ircount_12, NC1=>open); + + mux_8: MUX21 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff, + Z=>Q(0)); + + mux_7: MUX21 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff, + Z=>Q(1)); + + mux_6: MUX21 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff, + Z=>Q(2)); + + mux_5: MUX21 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff, + Z=>Q(3)); + + mux_4: MUX21 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff, + Z=>Q(4)); + + mux_3: MUX21 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff, + Z=>Q(5)); + + mux_2: MUX21 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff, + Z=>Q(6)); + + mux_1: MUX21 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff, + Z=>Q(7)); + + mux_0: MUX21 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff, + Z=>Q(8)); + + precin_inst312: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + wfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, + B1=>rcount_w1, BI=>precin, BOUT=>co0_2, S0=>open, + S1=>wfill_sub_0); + + wfill_1: FSUB2B + port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3, + BI=>co0_2, BOUT=>co1_2, S0=>wfill_sub_1, S1=>wfill_sub_2); + + wfill_2: FSUB2B + port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5, + BI=>co1_2, BOUT=>co2_2, S0=>wfill_sub_3, S1=>wfill_sub_4); + + wfill_3: FSUB2B + port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7, + BI=>co2_2, BOUT=>co3_2, S0=>wfill_sub_5, S1=>wfill_sub_6); + + wfill_4: FSUB2B + port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, + B1=>r_g2b_xor_cluster_0, BI=>co3_2, BOUT=>co4_2, + S0=>wfill_sub_7, S1=>wfill_sub_8); + + wfill_5: FSUB2B + port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10, + B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wfill_sub_9, + S1=>wfill_sub_10); + + wfill_6: FSUB2B + port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co5_2, BOUT=>open, S0=>wfill_sub_11, + S1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>wcount_r0, CI=>cmp_ci, GE=>co0_3); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, + B1=>wcount_r2, CI=>co0_3, GE=>co1_3); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, + B1=>wcount_r4, CI=>co1_3, GE=>co2_3); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, + B1=>wcount_r6, CI=>co2_3, GE=>co3_3); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, + B1=>w_g2b_xor_cluster_0, CI=>co3_3, GE=>co4_3); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, + B1=>wcount_r10, CI=>co4_3, GE=>co5_3); + + empty_cmp_6: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co5_3, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, + B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_4); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, + B1=>rcount_w4, CI=>co0_4, GE=>co1_4); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, + B1=>rcount_w6, CI=>co1_4, GE=>co2_4); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, + B1=>rcount_w8, CI=>co2_4, GE=>co3_4); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w10, CI=>co3_4, GE=>co4_4); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w11, + B1=>full_cmp_clr, CI=>co4_4, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_4kx18x9_wcnt is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX21 use entity ecp3.MUX21(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.lpc b/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.lpc new file mode 100644 index 0000000..d1ea4f6 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.8 +ModuleName=fifo_64kx18x9_wcnt +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/08/2015 +Time=13:57:08 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=32768 +Width=18 +RDepth=65536 +RWidth=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=1 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_64kx18x9_wcnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe -1 -pf -1 -fill diff --git a/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.vhd b/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.vhd new file mode 100644 index 0000000..796c528 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.vhd @@ -0,0 +1,4641 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.5.0.102 +-- Module Version: 5.8 +--/home/soft/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n fifo_64kx18x9_wcnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 32768 -width 18 -depth 32768 -rdata_width 9 -no_enable -pe -1 -pf -1 -fill + +-- Sat Aug 8 13:57:09 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_64kx18x9_wcnt is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + WCNT: out std_logic_vector(15 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_64kx18x9_wcnt; + +architecture Structure of fifo_64kx18x9_wcnt is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal func_and_inet: std_logic; + signal func_and_inet_1: std_logic; + signal func_and_inet_2: std_logic; + signal func_and_inet_3: std_logic; + signal func_and_inet_4: std_logic; + signal func_and_inet_5: std_logic; + signal func_and_inet_6: std_logic; + signal func_and_inet_7: std_logic; + signal func_and_inet_8: std_logic; + signal func_and_inet_9: std_logic; + signal func_and_inet_10: std_logic; + signal func_and_inet_11: std_logic; + signal func_and_inet_12: std_logic; + signal func_and_inet_13: std_logic; + signal func_and_inet_14: std_logic; + signal func_and_inet_15: std_logic; + signal func_and_inet_16: std_logic; + signal func_and_inet_17: std_logic; + signal func_and_inet_18: std_logic; + signal func_and_inet_19: std_logic; + signal func_and_inet_20: std_logic; + signal func_and_inet_21: std_logic; + signal func_and_inet_22: std_logic; + signal func_and_inet_23: std_logic; + signal func_and_inet_24: std_logic; + signal func_and_inet_25: std_logic; + signal func_and_inet_26: std_logic; + signal func_and_inet_27: std_logic; + signal func_and_inet_28: std_logic; + signal func_and_inet_29: std_logic; + signal wptr_14_inv: std_logic; + signal func_and_inet_30: std_logic; + signal rptr_15_inv: std_logic; + signal func_and_inet_31: std_logic; + signal func_and_inet_32: std_logic; + signal func_and_inet_33: std_logic; + signal func_and_inet_34: std_logic; + signal func_and_inet_35: std_logic; + signal func_and_inet_36: std_logic; + signal func_and_inet_37: std_logic; + signal func_and_inet_38: std_logic; + signal func_and_inet_39: std_logic; + signal func_and_inet_40: std_logic; + signal func_and_inet_41: std_logic; + signal func_and_inet_42: std_logic; + signal func_and_inet_43: std_logic; + signal func_and_inet_44: std_logic; + signal func_and_inet_45: std_logic; + signal wptr_13_inv: std_logic; + signal func_and_inet_46: std_logic; + signal rptr_14_inv: std_logic; + signal func_and_inet_47: std_logic; + signal func_and_inet_48: std_logic; + signal func_and_inet_49: std_logic; + signal func_and_inet_50: std_logic; + signal func_and_inet_51: std_logic; + signal func_and_inet_52: std_logic; + signal func_and_inet_53: std_logic; + signal wptr_12_inv: std_logic; + signal func_and_inet_54: std_logic; + signal rptr_13_inv: std_logic; + signal func_and_inet_55: std_logic; + signal func_and_inet_56: std_logic; + signal func_and_inet_57: std_logic; + signal wptr_11_inv: std_logic; + signal func_and_inet_58: std_logic; + signal rptr_12_inv: std_logic; + signal func_and_inet_59: std_logic; + signal wptr_10_inv: std_logic; + signal func_and_inet_60: std_logic; + signal rptr_11_inv: std_logic; + signal func_and_inet_61: std_logic; + signal func_and_inet_62: std_logic; + signal func_and_inet_63: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_3: std_logic; + signal func_xor_inet_2: std_logic; + signal func_xor_inet_1: std_logic; + signal func_xor_inet: std_logic; + signal rcount_w0: std_logic; + signal func_xor_inet_4: std_logic; + signal func_xor_inet_5: std_logic; + signal dec1_r10: std_logic; + signal dec0_p00: std_logic; + signal dec3_r11: std_logic; + signal dec2_p01: std_logic; + signal dec5_r12: std_logic; + signal dec4_p02: std_logic; + signal dec7_r13: std_logic; + signal dec6_p03: std_logic; + signal dec9_r14: std_logic; + signal dec8_p04: std_logic; + signal dec11_r15: std_logic; + signal dec10_p05: std_logic; + signal dec13_r16: std_logic; + signal dec12_p06: std_logic; + signal dec15_r17: std_logic; + signal dec14_p07: std_logic; + signal dec17_r18: std_logic; + signal dec16_p08: std_logic; + signal dec19_r19: std_logic; + signal dec18_p09: std_logic; + signal dec21_r110: std_logic; + signal dec20_p010: std_logic; + signal dec23_r111: std_logic; + signal dec22_p011: std_logic; + signal dec25_r112: std_logic; + signal dec24_p012: std_logic; + signal dec27_r113: std_logic; + signal dec26_p013: std_logic; + signal dec29_r114: std_logic; + signal dec28_p014: std_logic; + signal dec31_r115: std_logic; + signal dec30_p015: std_logic; + signal dec33_r116: std_logic; + signal dec32_p016: std_logic; + signal dec35_r117: std_logic; + signal dec34_p017: std_logic; + signal dec37_r118: std_logic; + signal dec36_p018: std_logic; + signal dec39_r119: std_logic; + signal dec38_p019: std_logic; + signal dec41_r120: std_logic; + signal dec40_p020: std_logic; + signal dec43_r121: std_logic; + signal dec42_p021: std_logic; + signal dec45_r122: std_logic; + signal dec44_p022: std_logic; + signal dec47_r123: std_logic; + signal dec46_p023: std_logic; + signal dec49_r124: std_logic; + signal dec48_p024: std_logic; + signal dec51_r125: std_logic; + signal dec50_p025: std_logic; + signal dec53_r126: std_logic; + signal dec52_p026: std_logic; + signal dec55_r127: std_logic; + signal dec54_p027: std_logic; + signal dec57_r128: std_logic; + signal dec56_p028: std_logic; + signal dec59_r129: std_logic; + signal dec58_p029: std_logic; + signal dec61_r130: std_logic; + signal dec60_p030: std_logic; + signal dec63_r131: std_logic; + signal dec62_p031: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal wptr_15: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal r_gdata_15: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_16: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rptr_13: std_logic; + signal rptr_14: std_logic; + signal rptr_15: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal r_gcount_16: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal r_gcount_w216: std_logic; + signal r_gcount_w16: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co7: std_logic; + signal co6: std_logic; + signal wcount_15: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co6_1: std_logic; + signal ircount_16: std_logic; + signal co8: std_logic; + signal co7_1: std_logic; + signal rcount_16: std_logic; + signal mdout1_31_0: std_logic; + signal mdout1_30_0: std_logic; + signal mdout1_29_0: std_logic; + signal mdout1_28_0: std_logic; + signal mdout1_27_0: std_logic; + signal mdout1_26_0: std_logic; + signal mdout1_25_0: std_logic; + signal mdout1_24_0: std_logic; + signal mdout1_23_0: std_logic; + signal mdout1_22_0: std_logic; + signal mdout1_21_0: std_logic; + signal mdout1_20_0: std_logic; + signal mdout1_19_0: std_logic; + signal mdout1_18_0: std_logic; + signal mdout1_17_0: std_logic; + signal mdout1_16_0: std_logic; + signal mdout1_15_0: std_logic; + signal mdout1_14_0: std_logic; + signal mdout1_13_0: std_logic; + signal mdout1_12_0: std_logic; + signal mdout1_11_0: std_logic; + signal mdout1_10_0: std_logic; + signal mdout1_9_0: std_logic; + signal mdout1_8_0: std_logic; + signal mdout1_7_0: std_logic; + signal mdout1_6_0: std_logic; + signal mdout1_5_0: std_logic; + signal mdout1_4_0: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_31_1: std_logic; + signal mdout1_30_1: std_logic; + signal mdout1_29_1: std_logic; + signal mdout1_28_1: std_logic; + signal mdout1_27_1: std_logic; + signal mdout1_26_1: std_logic; + signal mdout1_25_1: std_logic; + signal mdout1_24_1: std_logic; + signal mdout1_23_1: std_logic; + signal mdout1_22_1: std_logic; + signal mdout1_21_1: std_logic; + signal mdout1_20_1: std_logic; + signal mdout1_19_1: std_logic; + signal mdout1_18_1: std_logic; + signal mdout1_17_1: std_logic; + signal mdout1_16_1: std_logic; + signal mdout1_15_1: std_logic; + signal mdout1_14_1: std_logic; + signal mdout1_13_1: std_logic; + signal mdout1_12_1: std_logic; + signal mdout1_11_1: std_logic; + signal mdout1_10_1: std_logic; + signal mdout1_9_1: std_logic; + signal mdout1_8_1: std_logic; + signal mdout1_7_1: std_logic; + signal mdout1_6_1: std_logic; + signal mdout1_5_1: std_logic; + signal mdout1_4_1: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_31_2: std_logic; + signal mdout1_30_2: std_logic; + signal mdout1_29_2: std_logic; + signal mdout1_28_2: std_logic; + signal mdout1_27_2: std_logic; + signal mdout1_26_2: std_logic; + signal mdout1_25_2: std_logic; + signal mdout1_24_2: std_logic; + signal mdout1_23_2: std_logic; + signal mdout1_22_2: std_logic; + signal mdout1_21_2: std_logic; + signal mdout1_20_2: std_logic; + signal mdout1_19_2: std_logic; + signal mdout1_18_2: std_logic; + signal mdout1_17_2: std_logic; + signal mdout1_16_2: std_logic; + signal mdout1_15_2: std_logic; + signal mdout1_14_2: std_logic; + signal mdout1_13_2: std_logic; + signal mdout1_12_2: std_logic; + signal mdout1_11_2: std_logic; + signal mdout1_10_2: std_logic; + signal mdout1_9_2: std_logic; + signal mdout1_8_2: std_logic; + signal mdout1_7_2: std_logic; + signal mdout1_6_2: std_logic; + signal mdout1_5_2: std_logic; + signal mdout1_4_2: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_31_3: std_logic; + signal mdout1_30_3: std_logic; + signal mdout1_29_3: std_logic; + signal mdout1_28_3: std_logic; + signal mdout1_27_3: std_logic; + signal mdout1_26_3: std_logic; + signal mdout1_25_3: std_logic; + signal mdout1_24_3: std_logic; + signal mdout1_23_3: std_logic; + signal mdout1_22_3: std_logic; + signal mdout1_21_3: std_logic; + signal mdout1_20_3: std_logic; + signal mdout1_19_3: std_logic; + signal mdout1_18_3: std_logic; + signal mdout1_17_3: std_logic; + signal mdout1_16_3: std_logic; + signal mdout1_15_3: std_logic; + signal mdout1_14_3: std_logic; + signal mdout1_13_3: std_logic; + signal mdout1_12_3: std_logic; + signal mdout1_11_3: std_logic; + signal mdout1_10_3: std_logic; + signal mdout1_9_3: std_logic; + signal mdout1_8_3: std_logic; + signal mdout1_7_3: std_logic; + signal mdout1_6_3: std_logic; + signal mdout1_5_3: std_logic; + signal mdout1_4_3: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_31_4: std_logic; + signal mdout1_30_4: std_logic; + signal mdout1_29_4: std_logic; + signal mdout1_28_4: std_logic; + signal mdout1_27_4: std_logic; + signal mdout1_26_4: std_logic; + signal mdout1_25_4: std_logic; + signal mdout1_24_4: std_logic; + signal mdout1_23_4: std_logic; + signal mdout1_22_4: std_logic; + signal mdout1_21_4: std_logic; + signal mdout1_20_4: std_logic; + signal mdout1_19_4: std_logic; + signal mdout1_18_4: std_logic; + signal mdout1_17_4: std_logic; + signal mdout1_16_4: std_logic; + signal mdout1_15_4: std_logic; + signal mdout1_14_4: std_logic; + signal mdout1_13_4: std_logic; + signal mdout1_12_4: std_logic; + signal mdout1_11_4: std_logic; + signal mdout1_10_4: std_logic; + signal mdout1_9_4: std_logic; + signal mdout1_8_4: std_logic; + signal mdout1_7_4: std_logic; + signal mdout1_6_4: std_logic; + signal mdout1_5_4: std_logic; + signal mdout1_4_4: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_31_5: std_logic; + signal mdout1_30_5: std_logic; + signal mdout1_29_5: std_logic; + signal mdout1_28_5: std_logic; + signal mdout1_27_5: std_logic; + signal mdout1_26_5: std_logic; + signal mdout1_25_5: std_logic; + signal mdout1_24_5: std_logic; + signal mdout1_23_5: std_logic; + signal mdout1_22_5: std_logic; + signal mdout1_21_5: std_logic; + signal mdout1_20_5: std_logic; + signal mdout1_19_5: std_logic; + signal mdout1_18_5: std_logic; + signal mdout1_17_5: std_logic; + signal mdout1_16_5: std_logic; + signal mdout1_15_5: std_logic; + signal mdout1_14_5: std_logic; + signal mdout1_13_5: std_logic; + signal mdout1_12_5: std_logic; + signal mdout1_11_5: std_logic; + signal mdout1_10_5: std_logic; + signal mdout1_9_5: std_logic; + signal mdout1_8_5: std_logic; + signal mdout1_7_5: std_logic; + signal mdout1_6_5: std_logic; + signal mdout1_5_5: std_logic; + signal mdout1_4_5: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_31_6: std_logic; + signal mdout1_30_6: std_logic; + signal mdout1_29_6: std_logic; + signal mdout1_28_6: std_logic; + signal mdout1_27_6: std_logic; + signal mdout1_26_6: std_logic; + signal mdout1_25_6: std_logic; + signal mdout1_24_6: std_logic; + signal mdout1_23_6: std_logic; + signal mdout1_22_6: std_logic; + signal mdout1_21_6: std_logic; + signal mdout1_20_6: std_logic; + signal mdout1_19_6: std_logic; + signal mdout1_18_6: std_logic; + signal mdout1_17_6: std_logic; + signal mdout1_16_6: std_logic; + signal mdout1_15_6: std_logic; + signal mdout1_14_6: std_logic; + signal mdout1_13_6: std_logic; + signal mdout1_12_6: std_logic; + signal mdout1_11_6: std_logic; + signal mdout1_10_6: std_logic; + signal mdout1_9_6: std_logic; + signal mdout1_8_6: std_logic; + signal mdout1_7_6: std_logic; + signal mdout1_6_6: std_logic; + signal mdout1_5_6: std_logic; + signal mdout1_4_6: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_31_7: std_logic; + signal mdout1_30_7: std_logic; + signal mdout1_29_7: std_logic; + signal mdout1_28_7: std_logic; + signal mdout1_27_7: std_logic; + signal mdout1_26_7: std_logic; + signal mdout1_25_7: std_logic; + signal mdout1_24_7: std_logic; + signal mdout1_23_7: std_logic; + signal mdout1_22_7: std_logic; + signal mdout1_21_7: std_logic; + signal mdout1_20_7: std_logic; + signal mdout1_19_7: std_logic; + signal mdout1_18_7: std_logic; + signal mdout1_17_7: std_logic; + signal mdout1_16_7: std_logic; + signal mdout1_15_7: std_logic; + signal mdout1_14_7: std_logic; + signal mdout1_13_7: std_logic; + signal mdout1_12_7: std_logic; + signal mdout1_11_7: std_logic; + signal mdout1_10_7: std_logic; + signal mdout1_9_7: std_logic; + signal mdout1_8_7: std_logic; + signal mdout1_7_7: std_logic; + signal mdout1_6_7: std_logic; + signal mdout1_5_7: std_logic; + signal mdout1_4_7: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_15_ff: std_logic; + signal rptr_14_ff: std_logic; + signal rptr_13_ff: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_31_8: std_logic; + signal mdout1_30_8: std_logic; + signal mdout1_29_8: std_logic; + signal mdout1_28_8: std_logic; + signal mdout1_27_8: std_logic; + signal mdout1_26_8: std_logic; + signal mdout1_25_8: std_logic; + signal mdout1_24_8: std_logic; + signal mdout1_23_8: std_logic; + signal mdout1_22_8: std_logic; + signal mdout1_21_8: std_logic; + signal mdout1_20_8: std_logic; + signal mdout1_19_8: std_logic; + signal mdout1_18_8: std_logic; + signal mdout1_17_8: std_logic; + signal mdout1_16_8: std_logic; + signal mdout1_15_8: std_logic; + signal mdout1_14_8: std_logic; + signal mdout1_13_8: std_logic; + signal mdout1_12_8: std_logic; + signal mdout1_11_8: std_logic; + signal mdout1_10_8: std_logic; + signal mdout1_9_8: std_logic; + signal mdout1_8_8: std_logic; + signal mdout1_7_8: std_logic; + signal mdout1_6_8: std_logic; + signal mdout1_5_8: std_logic; + signal mdout1_4_8: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal wfill_sub_0: std_logic; + signal precin: std_logic; + signal scuba_vhi: std_logic; + signal wptr_0: std_logic; + signal wfill_sub_1: std_logic; + signal wfill_sub_2: std_logic; + signal co0_2: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wfill_sub_3: std_logic; + signal wfill_sub_4: std_logic; + signal co1_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wfill_sub_5: std_logic; + signal wfill_sub_6: std_logic; + signal co2_2: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wfill_sub_7: std_logic; + signal wfill_sub_8: std_logic; + signal co3_2: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wfill_sub_9: std_logic; + signal wfill_sub_10: std_logic; + signal co4_2: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wfill_sub_11: std_logic; + signal wfill_sub_12: std_logic; + signal co5_2: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wfill_sub_13: std_logic; + signal wfill_sub_14: std_logic; + signal co6_2: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal wfill_sub_15: std_logic; + signal co7_2: std_logic; + signal wfill_sub_msb: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_3: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_3: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_3: std_logic; + signal wcount_r7: std_logic; + signal wcount_r8: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_3: std_logic; + signal wcount_r9: std_logic; + signal wcount_r10: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_3: std_logic; + signal wcount_r11: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_3: std_logic; + signal wcount_r13: std_logic; + signal wcount_r14: std_logic; + signal rcount_14: std_logic; + signal rcount_15: std_logic; + signal co7_3: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_4: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_4: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_4: std_logic; + signal rcount_w7: std_logic; + signal rcount_w8: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_4: std_logic; + signal rcount_w9: std_logic; + signal rcount_w10: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_4: std_logic; + signal rcount_w11: std_logic; + signal rcount_w12: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_4: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w14: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_4: std_logic; + signal rcount_w15: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_14: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX321 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; D4: in std_logic; D5: in std_logic; + D6: in std_logic; D7: in std_logic; D8: in std_logic; + D9: in std_logic; D10: in std_logic; D11: in std_logic; + D12: in std_logic; D13: in std_logic; D14: in std_logic; + D15: in std_logic; D16: in std_logic; D17: in std_logic; + D18: in std_logic; D19: in std_logic; D20: in std_logic; + D21: in std_logic; D22: in std_logic; D23: in std_logic; + D24: in std_logic; D25: in std_logic; D26: in std_logic; + D27: in std_logic; D28: in std_logic; D29: in std_logic; + D30: in std_logic; D31: in std_logic; SD1: in std_logic; + SD2: in std_logic; SD3: in std_logic; SD4: in std_logic; + SD5: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; + attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; + attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; + attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; + attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; + attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is ""; + attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is ""; + attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is ""; + attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is ""; + attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is ""; + attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is ""; + attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is ""; + attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is ""; + attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is ""; + attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is ""; + attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is ""; + attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is ""; + attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is ""; + attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is ""; + attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is ""; + attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is ""; + attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is ""; + attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is ""; + attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is ""; + attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is ""; + attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is ""; + attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is ""; + attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is ""; + attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is ""; + attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; + attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; + attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC"; + attribute GSR of FF_187 : label is "ENABLED"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t34: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_11: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t33: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_10: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t32: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t31: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t30: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t29: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t28: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t27: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t26: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t25: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t24: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t23: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t22: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t21: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t20: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t19: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t18: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t17: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t16: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t15: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t14: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t13: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t12: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t11: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t10: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t9: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t8: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t7: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t6: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t5: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t4: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t3: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t2: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + XOR2_t1: XOR2 + port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); + + INV_9: INV + port map (A=>wptr_10, Z=>wptr_10_inv); + + INV_8: INV + port map (A=>wptr_11, Z=>wptr_11_inv); + + INV_7: INV + port map (A=>wptr_12, Z=>wptr_12_inv); + + INV_6: INV + port map (A=>wptr_13, Z=>wptr_13_inv); + + INV_5: INV + port map (A=>wptr_14, Z=>wptr_14_inv); + + LUT4_180: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet); + + LUT4_179: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_p00); + + INV_4: INV + port map (A=>rptr_11, Z=>rptr_11_inv); + + INV_3: INV + port map (A=>rptr_12, Z=>rptr_12_inv); + + INV_2: INV + port map (A=>rptr_13, Z=>rptr_13_inv); + + INV_1: INV + port map (A=>rptr_14, Z=>rptr_14_inv); + + INV_0: INV + port map (A=>rptr_15, Z=>rptr_15_inv); + + LUT4_178: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_1); + + LUT4_177: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec1_r10); + + LUT4_176: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_2); + + LUT4_175: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec2_p01); + + LUT4_174: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_3); + + LUT4_173: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec3_r11); + + LUT4_172: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_4); + + LUT4_171: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec4_p02); + + LUT4_170: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_5); + + LUT4_169: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec5_r12); + + LUT4_168: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_6); + + LUT4_167: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec6_p03); + + LUT4_166: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_7); + + LUT4_165: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec7_r13); + + LUT4_164: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_8); + + LUT4_163: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec8_p04); + + LUT4_162: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_9); + + LUT4_161: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec9_r14); + + LUT4_160: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_10); + + LUT4_159: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); + + LUT4_158: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_11); + + LUT4_157: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); + + LUT4_156: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_12); + + LUT4_155: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); + + LUT4_154: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_13); + + LUT4_153: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); + + LUT4_152: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_14); + + LUT4_151: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); + + LUT4_150: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_15); + + LUT4_149: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); + + LUT4_148: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_16); + + LUT4_147: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); + + LUT4_146: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_17); + + LUT4_145: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); + + LUT4_144: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_18); + + LUT4_143: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); + + LUT4_142: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_19); + + LUT4_141: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); + + LUT4_140: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_20); + + LUT4_139: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); + + LUT4_138: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_21); + + LUT4_137: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); + + LUT4_136: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_22); + + LUT4_135: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); + + LUT4_134: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_23); + + LUT4_133: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); + + LUT4_132: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_24); + + LUT4_131: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); + + LUT4_130: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_25); + + LUT4_129: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); + + LUT4_128: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_26); + + LUT4_127: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); + + LUT4_126: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_27); + + LUT4_125: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); + + LUT4_124: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_28); + + LUT4_123: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); + + LUT4_122: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_29); + + LUT4_121: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); + + LUT4_120: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, + DO0=>func_and_inet_30); + + LUT4_119: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); + + LUT4_118: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_31); + + LUT4_117: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); + + LUT4_116: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_32); + + LUT4_115: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec32_p016); + + LUT4_114: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_33); + + LUT4_113: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec33_r116); + + LUT4_112: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_34); + + LUT4_111: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec34_p017); + + LUT4_110: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_35); + + LUT4_109: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec35_r117); + + LUT4_108: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_36); + + LUT4_107: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec36_p018); + + LUT4_106: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_37); + + LUT4_105: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec37_r118); + + LUT4_104: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_38); + + LUT4_103: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec38_p019); + + LUT4_102: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_39); + + LUT4_101: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec39_r119); + + LUT4_100: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_40); + + LUT4_99: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec40_p020); + + LUT4_98: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_41); + + LUT4_97: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec41_r120); + + LUT4_96: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_42); + + LUT4_95: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec42_p021); + + LUT4_94: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_43); + + LUT4_93: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec43_r121); + + LUT4_92: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_44); + + LUT4_91: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec44_p022); + + LUT4_90: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_45); + + LUT4_89: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec45_r122); + + LUT4_88: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_46); + + LUT4_87: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec46_p023); + + LUT4_86: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_47); + + LUT4_85: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec47_r123); + + LUT4_84: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_48); + + LUT4_83: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec48_p024); + + LUT4_82: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_49); + + LUT4_81: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec49_r124); + + LUT4_80: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_50); + + LUT4_79: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec50_p025); + + LUT4_78: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_51); + + LUT4_77: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec51_r125); + + LUT4_76: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_52); + + LUT4_75: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec52_p026); + + LUT4_74: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_53); + + LUT4_73: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec53_r126); + + LUT4_72: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_54); + + LUT4_71: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec54_p027); + + LUT4_70: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_55); + + LUT4_69: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec55_r127); + + LUT4_68: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_56); + + LUT4_67: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec56_p028); + + LUT4_66: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_57); + + LUT4_65: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec57_r128); + + LUT4_64: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_58); + + LUT4_63: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec58_p029); + + LUT4_62: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_59); + + LUT4_61: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec59_r129); + + LUT4_60: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_60); + + LUT4_59: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec60_p030); + + LUT4_58: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_61); + + LUT4_57: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec61_r130); + + LUT4_56: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, + DO0=>func_and_inet_62); + + LUT4_55: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec62_p031); + + LUT4_54: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_63); + + LUT4_53: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec63_r131); + + LUT4_52: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, + DO0=>w_g2b_xor_cluster_0); + + LUT4_51: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_1); + + LUT4_50: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_2); + + LUT4_49: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_3); + + LUT4_48: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_47: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); + + LUT4_46: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_45: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); + + LUT4_44: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); + + LUT4_43: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_42: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_41: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); + + LUT4_40: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r2); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r1); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r0); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>r_gcount_w216, + DO0=>r_g2b_xor_cluster_0); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_1); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_2); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_3); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w15); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, + AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, + DO0=>rcount_w10); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w3); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w2); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_4); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, + AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, + DO0=>func_xor_inet_5); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); + + XOR2_t0: XOR2 + port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_31: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec1_r10, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_30: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec2_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec3_r11, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_29: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec4_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec5_r12, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, + DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, + DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, + DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_28: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec6_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec7_r13, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, + DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, + DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, + DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_4_0_27: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec8_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec9_r14, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, + DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, + DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, + DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_5_0_26: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec10_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec11_r15, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, + DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, + DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, + DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_6_0_25: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec12_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec13_r16, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, + DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, + DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, + DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_7_0_24: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec14_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec15_r17, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, + DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, + DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, + DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_8_0_23: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec16_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec17_r18, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, + DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, + DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, + DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_9_0_22: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec18_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec19_r19, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, + DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, + DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, + DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_10_0_21: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec20_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec21_r110, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_10_0, DOB1=>mdout1_10_1, + DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, DOB4=>mdout1_10_4, + DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, DOB7=>mdout1_10_7, + DOB8=>mdout1_10_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_11_0_20: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec22_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec23_r111, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_11_0, DOB1=>mdout1_11_1, + DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, DOB4=>mdout1_11_4, + DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, DOB7=>mdout1_11_7, + DOB8=>mdout1_11_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_12_0_19: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec24_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec25_r112, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_12_0, DOB1=>mdout1_12_1, + DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, DOB4=>mdout1_12_4, + DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, DOB7=>mdout1_12_7, + DOB8=>mdout1_12_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_13_0_18: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec26_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec27_r113, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_13_0, DOB1=>mdout1_13_1, + DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, DOB4=>mdout1_13_4, + DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, DOB7=>mdout1_13_7, + DOB8=>mdout1_13_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_14_0_17: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec28_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec29_r114, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_14_0, DOB1=>mdout1_14_1, + DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, DOB4=>mdout1_14_4, + DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, DOB7=>mdout1_14_7, + DOB8=>mdout1_14_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_15_0_16: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec30_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec31_r115, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_15_0, DOB1=>mdout1_15_1, + DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, DOB4=>mdout1_15_4, + DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, DOB7=>mdout1_15_7, + DOB8=>mdout1_15_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_16_0_15: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec32_p016, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec33_r116, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_16_0, DOB1=>mdout1_16_1, + DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, DOB4=>mdout1_16_4, + DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, DOB7=>mdout1_16_7, + DOB8=>mdout1_16_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_17_0_14: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec34_p017, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec35_r117, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_17_0, DOB1=>mdout1_17_1, + DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, DOB4=>mdout1_17_4, + DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, DOB7=>mdout1_17_7, + DOB8=>mdout1_17_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_18_0_13: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec36_p018, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec37_r118, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_18_0, DOB1=>mdout1_18_1, + DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, DOB4=>mdout1_18_4, + DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, DOB7=>mdout1_18_7, + DOB8=>mdout1_18_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_19_0_12: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec38_p019, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec39_r119, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_19_0, DOB1=>mdout1_19_1, + DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, DOB4=>mdout1_19_4, + DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, DOB7=>mdout1_19_7, + DOB8=>mdout1_19_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_20_0_11: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec40_p020, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec41_r120, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_20_0, DOB1=>mdout1_20_1, + DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, DOB4=>mdout1_20_4, + DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, DOB7=>mdout1_20_7, + DOB8=>mdout1_20_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_21_0_10: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec42_p021, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec43_r121, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_21_0, DOB1=>mdout1_21_1, + DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, DOB4=>mdout1_21_4, + DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, DOB7=>mdout1_21_7, + DOB8=>mdout1_21_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_22_0_9: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec44_p022, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec45_r122, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_22_0, DOB1=>mdout1_22_1, + DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, DOB4=>mdout1_22_4, + DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, DOB7=>mdout1_22_7, + DOB8=>mdout1_22_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_23_0_8: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec46_p023, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec47_r123, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_23_0, DOB1=>mdout1_23_1, + DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, DOB4=>mdout1_23_4, + DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, DOB7=>mdout1_23_7, + DOB8=>mdout1_23_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_24_0_7: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec48_p024, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec49_r124, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_24_0, DOB1=>mdout1_24_1, + DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, DOB4=>mdout1_24_4, + DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, DOB7=>mdout1_24_7, + DOB8=>mdout1_24_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_25_0_6: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec50_p025, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec51_r125, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_25_0, DOB1=>mdout1_25_1, + DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, DOB4=>mdout1_25_4, + DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, DOB7=>mdout1_25_7, + DOB8=>mdout1_25_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_26_0_5: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec52_p026, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec53_r126, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_26_0, DOB1=>mdout1_26_1, + DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, DOB4=>mdout1_26_4, + DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, DOB7=>mdout1_26_7, + DOB8=>mdout1_26_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_27_0_4: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec54_p027, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec55_r127, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_27_0, DOB1=>mdout1_27_1, + DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, DOB4=>mdout1_27_4, + DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, DOB7=>mdout1_27_7, + DOB8=>mdout1_27_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_28_0_3: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec56_p028, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec57_r128, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_28_0, DOB1=>mdout1_28_1, + DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, DOB4=>mdout1_28_4, + DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, DOB7=>mdout1_28_7, + DOB8=>mdout1_28_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_29_0_2: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec58_p029, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec59_r129, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_29_0, DOB1=>mdout1_29_1, + DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, DOB4=>mdout1_29_4, + DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, DOB7=>mdout1_29_7, + DOB8=>mdout1_29_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_30_0_1: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec60_p030, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec61_r130, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_30_0, DOB1=>mdout1_30_1, + DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, DOB4=>mdout1_30_4, + DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, DOB7=>mdout1_30_7, + DOB8=>mdout1_30_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_31_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9, + CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, + CSA0=>dec62_p031, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, + ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, + ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, + CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, + CSB0=>dec63_r131, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>mdout1_31_0, DOB1=>mdout1_31_1, + DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, DOB4=>mdout1_31_4, + DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, DOB7=>mdout1_31_7, + DOB8=>mdout1_31_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_187: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_186: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_185: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_184: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_183: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_182: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_181: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_180: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_179: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_178: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_177: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_176: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_175: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_174: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_173: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_172: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_171: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_170: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_169: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_168: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_167: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_166: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_165: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_164: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_163: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_162: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_161: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_160: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_159: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_158: FD1P3DX + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_157: FD1P3DX + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_156: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_155: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_154: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_153: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_152: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_151: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_150: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_149: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_148: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_147: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_146: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_145: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_144: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_143: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_142: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_141: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_140: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_139: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_138: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_137: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_136: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_135: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_134: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_133: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_132: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_131: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_130: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_129: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_128: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_127: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_126: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_125: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_124: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_123: FD1P3DX + port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_16); + + FF_122: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_121: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_120: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_119: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_118: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_117: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_116: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_115: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_114: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_113: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_112: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_111: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_110: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_109: FD1P3DX + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_108: FD1P3DX + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_107: FD1P3DX + port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_106: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_16); + + FF_105: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_104: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_103: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_102: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_101: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_100: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_99: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_98: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_97: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_96: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_95: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_94: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_93: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_92: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_91: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_90: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_89: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_16); + + FF_88: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_87: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_86: FD1P3DX + port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_13_ff); + + FF_85: FD1P3DX + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_84: FD1P3DX + port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_15_ff); + + FF_83: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_82: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_81: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_80: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_79: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_78: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_77: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_76: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_75: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_74: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_73: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_72: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_71: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_70: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_69: FD1S3DX + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_68: FD1S3DX + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_67: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_66: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_65: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_64: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_63: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_62: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_61: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_60: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_59: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_58: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_57: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_56: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_55: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_54: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_53: FD1S3DX + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_52: FD1S3DX + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_51: FD1S3DX + port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); + + FF_50: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_49: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_48: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_47: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_46: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_45: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_44: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_43: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_42: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_41: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_40: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_39: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_38: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_37: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_36: FD1S3DX + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_35: FD1S3DX + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_34: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_33: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_32: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_31: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_30: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_29: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_28: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_27: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_26: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_25: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_24: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_23: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_22: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_21: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_20: FD1S3DX + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_19: FD1S3DX + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_18: FD1S3DX + port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w216); + + FF_17: FD1S3DX + port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); + + FF_16: FD1S3DX + port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); + + FF_15: FD1S3DX + port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); + + FF_14: FD1S3DX + port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); + + FF_13: FD1S3DX + port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); + + FF_12: FD1S3DX + port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); + + FF_11: FD1S3DX + port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); + + FF_10: FD1S3DX + port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); + + FF_9: FD1S3DX + port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); + + FF_8: FD1S3DX + port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); + + FF_7: FD1S3DX + port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); + + FF_6: FD1S3DX + port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); + + FF_5: FD1S3DX + port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); + + FF_4: FD1S3DX + port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); + + FF_3: FD1S3DX + port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); + + FF_2: FD1S3DX + port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, + NC0=>iwcount_14, NC1=>iwcount_15); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, + NC0=>ircount_14, NC1=>ircount_15); + + r_gctr_8: CU2 + port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8, + NC0=>ircount_16, NC1=>open); + + mux_8: MUX321 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, + D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, + D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, + D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, + D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, + D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, + D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, + D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, + D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, + D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(0)); + + mux_7: MUX321 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, + D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, + D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, + D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, + D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, + D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, + D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, + D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, + D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, + D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(1)); + + mux_6: MUX321 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, + D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, + D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, + D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, + D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, + D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, + D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, + D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, + D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, + D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(2)); + + mux_5: MUX321 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, + D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, + D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, + D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, + D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, + D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, + D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, + D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, + D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, + D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(3)); + + mux_4: MUX321 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, + D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, + D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, + D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, + D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, + D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, + D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, + D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, + D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, + D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(4)); + + mux_3: MUX321 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, + D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, + D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, + D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, + D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, + D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, + D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, + D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, + D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, + D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(5)); + + mux_2: MUX321 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, + D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, + D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, + D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, + D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, + D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, + D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, + D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, + D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, + D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(6)); + + mux_1: MUX321 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, + D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, + D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, + D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, + D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, + D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, + D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, + D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, + D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, + D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(7)); + + mux_0: MUX321 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, + D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, + D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, + D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, + D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, + D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, + D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, + D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, + D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, + D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(8)); + + precin_inst812: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + wfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, + B1=>rcount_w1, BI=>precin, BOUT=>co0_2, S0=>open, + S1=>wfill_sub_0); + + wfill_1: FSUB2B + port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3, + BI=>co0_2, BOUT=>co1_2, S0=>wfill_sub_1, S1=>wfill_sub_2); + + wfill_2: FSUB2B + port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5, + BI=>co1_2, BOUT=>co2_2, S0=>wfill_sub_3, S1=>wfill_sub_4); + + wfill_3: FSUB2B + port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7, + BI=>co2_2, BOUT=>co3_2, S0=>wfill_sub_5, S1=>wfill_sub_6); + + wfill_4: FSUB2B + port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9, + BI=>co3_2, BOUT=>co4_2, S0=>wfill_sub_7, S1=>wfill_sub_8); + + wfill_5: FSUB2B + port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10, + B1=>rcount_w11, BI=>co4_2, BOUT=>co5_2, S0=>wfill_sub_9, + S1=>wfill_sub_10); + + wfill_6: FSUB2B + port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, BI=>co5_2, BOUT=>co6_2, + S0=>wfill_sub_11, S1=>wfill_sub_12); + + wfill_7: FSUB2B + port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14, + B1=>rcount_w15, BI=>co6_2, BOUT=>co7_2, S0=>wfill_sub_13, + S1=>wfill_sub_14); + + wfill_8: FSUB2B + port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co7_2, BOUT=>open, S0=>wfill_sub_15, + S1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>wcount_r0, CI=>cmp_ci, GE=>co0_3); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, + B1=>wcount_r2, CI=>co0_3, GE=>co1_3); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, + B1=>wcount_r4, CI=>co1_3, GE=>co2_3); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, + B1=>wcount_r6, CI=>co2_3, GE=>co3_3); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, + B1=>wcount_r8, CI=>co3_3, GE=>co4_3); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, + B1=>wcount_r10, CI=>co4_3, GE=>co5_3); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, + B1=>w_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3); + + empty_cmp_7: AGEB2 + port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13, + B1=>wcount_r14, CI=>co6_3, GE=>co7_3); + + empty_cmp_8: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co7_3, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, + B1=>rcount_w2, CI=>cmp_ci_1, GE=>co0_4); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, + B1=>rcount_w4, CI=>co0_4, GE=>co1_4); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, + B1=>rcount_w6, CI=>co1_4, GE=>co2_4); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, + B1=>rcount_w8, CI=>co2_4, GE=>co3_4); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, + B1=>rcount_w10, CI=>co3_4, GE=>co4_4); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11, + B1=>rcount_w12, CI=>co4_4, GE=>co5_4); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w14, CI=>co5_4, GE=>co6_4); + + full_cmp_7: AGEB2 + port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15, + B1=>full_cmp_clr, CI=>co6_4, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_64kx18x9_wcnt is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX321 use entity ecp3.MUX321(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.lpc b/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.lpc new file mode 100644 index 0000000..3b9c0bd --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.8 +ModuleName=fifo_64kx9_af_cnt +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/06/2015 +Time=14:43:28 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=65536 +Width=9 +RDepth=65536 +RWidth=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Dual Threshold +PfAssert=65500 +PfDeassert=65490 +RDataCount=0 +WDataCount=1 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_64kx9_af_cnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 16 -data_width 9 -num_words 65536 -rdata_width 9 -no_enable -pe -1 -pf 65500 -pf2 65490 -fill diff --git a/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.vhd b/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.vhd new file mode 100644 index 0000000..a940449 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.vhd @@ -0,0 +1,5231 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.5.0.102 +-- Module Version: 5.8 +--/home/soft/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n fifo_64kx9_af_cnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 65536 -width 9 -depth 65536 -rdata_width 9 -no_enable -pe -1 -pf 65500 -pf2 65490 -fill + +-- Thu Aug 6 14:43:29 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_64kx9_af_cnt is + port ( + Data: in std_logic_vector(8 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + WCNT: out std_logic_vector(16 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_64kx9_af_cnt; + +architecture Structure of fifo_64kx9_af_cnt is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal func_and_inet: std_logic; + signal func_and_inet_1: std_logic; + signal func_and_inet_2: std_logic; + signal func_and_inet_3: std_logic; + signal func_and_inet_4: std_logic; + signal func_and_inet_5: std_logic; + signal func_and_inet_6: std_logic; + signal func_and_inet_7: std_logic; + signal func_and_inet_8: std_logic; + signal func_and_inet_9: std_logic; + signal func_and_inet_10: std_logic; + signal func_and_inet_11: std_logic; + signal func_and_inet_12: std_logic; + signal func_and_inet_13: std_logic; + signal func_and_inet_14: std_logic; + signal func_and_inet_15: std_logic; + signal func_and_inet_16: std_logic; + signal func_and_inet_17: std_logic; + signal func_and_inet_18: std_logic; + signal func_and_inet_19: std_logic; + signal func_and_inet_20: std_logic; + signal func_and_inet_21: std_logic; + signal func_and_inet_22: std_logic; + signal func_and_inet_23: std_logic; + signal func_and_inet_24: std_logic; + signal func_and_inet_25: std_logic; + signal func_and_inet_26: std_logic; + signal func_and_inet_27: std_logic; + signal func_and_inet_28: std_logic; + signal func_and_inet_29: std_logic; + signal wptr_15_inv: std_logic; + signal func_and_inet_30: std_logic; + signal rptr_15_inv: std_logic; + signal func_and_inet_31: std_logic; + signal func_and_inet_32: std_logic; + signal func_and_inet_33: std_logic; + signal func_and_inet_34: std_logic; + signal func_and_inet_35: std_logic; + signal func_and_inet_36: std_logic; + signal func_and_inet_37: std_logic; + signal func_and_inet_38: std_logic; + signal func_and_inet_39: std_logic; + signal func_and_inet_40: std_logic; + signal func_and_inet_41: std_logic; + signal func_and_inet_42: std_logic; + signal func_and_inet_43: std_logic; + signal func_and_inet_44: std_logic; + signal func_and_inet_45: std_logic; + signal wptr_14_inv: std_logic; + signal func_and_inet_46: std_logic; + signal rptr_14_inv: std_logic; + signal func_and_inet_47: std_logic; + signal func_and_inet_48: std_logic; + signal func_and_inet_49: std_logic; + signal func_and_inet_50: std_logic; + signal func_and_inet_51: std_logic; + signal func_and_inet_52: std_logic; + signal func_and_inet_53: std_logic; + signal wptr_13_inv: std_logic; + signal func_and_inet_54: std_logic; + signal rptr_13_inv: std_logic; + signal func_and_inet_55: std_logic; + signal func_and_inet_56: std_logic; + signal func_and_inet_57: std_logic; + signal wptr_12_inv: std_logic; + signal func_and_inet_58: std_logic; + signal rptr_12_inv: std_logic; + signal func_and_inet_59: std_logic; + signal wptr_11_inv: std_logic; + signal func_and_inet_60: std_logic; + signal rptr_11_inv: std_logic; + signal func_and_inet_61: std_logic; + signal func_and_inet_62: std_logic; + signal func_and_inet_63: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_3: std_logic; + signal func_xor_inet_2: std_logic; + signal func_xor_inet_1: std_logic; + signal func_xor_inet: std_logic; + signal func_xor_inet_4: std_logic; + signal func_xor_inet_5: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_9: std_logic; + signal func_xor_inet_8: std_logic; + signal func_xor_inet_7: std_logic; + signal func_xor_inet_6: std_logic; + signal func_xor_inet_10: std_logic; + signal func_xor_inet_11: std_logic; + signal dec1_r10: std_logic; + signal dec0_p00: std_logic; + signal dec3_r11: std_logic; + signal dec2_p01: std_logic; + signal dec5_r12: std_logic; + signal dec4_p02: std_logic; + signal dec7_r13: std_logic; + signal dec6_p03: std_logic; + signal dec9_r14: std_logic; + signal dec8_p04: std_logic; + signal dec11_r15: std_logic; + signal dec10_p05: std_logic; + signal dec13_r16: std_logic; + signal dec12_p06: std_logic; + signal dec15_r17: std_logic; + signal dec14_p07: std_logic; + signal dec17_r18: std_logic; + signal dec16_p08: std_logic; + signal dec19_r19: std_logic; + signal dec18_p09: std_logic; + signal dec21_r110: std_logic; + signal dec20_p010: std_logic; + signal dec23_r111: std_logic; + signal dec22_p011: std_logic; + signal dec25_r112: std_logic; + signal dec24_p012: std_logic; + signal dec27_r113: std_logic; + signal dec26_p013: std_logic; + signal dec29_r114: std_logic; + signal dec28_p014: std_logic; + signal dec31_r115: std_logic; + signal dec30_p015: std_logic; + signal dec33_r116: std_logic; + signal dec32_p016: std_logic; + signal dec35_r117: std_logic; + signal dec34_p017: std_logic; + signal dec37_r118: std_logic; + signal dec36_p018: std_logic; + signal dec39_r119: std_logic; + signal dec38_p019: std_logic; + signal dec41_r120: std_logic; + signal dec40_p020: std_logic; + signal dec43_r121: std_logic; + signal dec42_p021: std_logic; + signal dec45_r122: std_logic; + signal dec44_p022: std_logic; + signal dec47_r123: std_logic; + signal dec46_p023: std_logic; + signal dec49_r124: std_logic; + signal dec48_p024: std_logic; + signal dec51_r125: std_logic; + signal dec50_p025: std_logic; + signal dec53_r126: std_logic; + signal dec52_p026: std_logic; + signal dec55_r127: std_logic; + signal dec54_p027: std_logic; + signal dec57_r128: std_logic; + signal dec56_p028: std_logic; + signal dec59_r129: std_logic; + signal dec58_p029: std_logic; + signal dec61_r130: std_logic; + signal dec60_p030: std_logic; + signal dec63_r131: std_logic; + signal dec62_p031: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal w_gdata_15: std_logic; + signal wptr_16: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal r_gdata_15: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_16: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rptr_13: std_logic; + signal rptr_14: std_logic; + signal rptr_15: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal w_gcount_16: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal r_gcount_16: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal w_gcount_r216: std_logic; + signal w_gcount_r16: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal r_gcount_w216: std_logic; + signal r_gcount_w16: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal af: std_logic; + signal af_d: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co6: std_logic; + signal iwcount_16: std_logic; + signal co8: std_logic; + signal co7: std_logic; + signal wcount_16: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co6_1: std_logic; + signal ircount_16: std_logic; + signal co8_1: std_logic; + signal co7_1: std_logic; + signal rcount_16: std_logic; + signal mdout1_31_0: std_logic; + signal mdout1_30_0: std_logic; + signal mdout1_29_0: std_logic; + signal mdout1_28_0: std_logic; + signal mdout1_27_0: std_logic; + signal mdout1_26_0: std_logic; + signal mdout1_25_0: std_logic; + signal mdout1_24_0: std_logic; + signal mdout1_23_0: std_logic; + signal mdout1_22_0: std_logic; + signal mdout1_21_0: std_logic; + signal mdout1_20_0: std_logic; + signal mdout1_19_0: std_logic; + signal mdout1_18_0: std_logic; + signal mdout1_17_0: std_logic; + signal mdout1_16_0: std_logic; + signal mdout1_15_0: std_logic; + signal mdout1_14_0: std_logic; + signal mdout1_13_0: std_logic; + signal mdout1_12_0: std_logic; + signal mdout1_11_0: std_logic; + signal mdout1_10_0: std_logic; + signal mdout1_9_0: std_logic; + signal mdout1_8_0: std_logic; + signal mdout1_7_0: std_logic; + signal mdout1_6_0: std_logic; + signal mdout1_5_0: std_logic; + signal mdout1_4_0: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_31_1: std_logic; + signal mdout1_30_1: std_logic; + signal mdout1_29_1: std_logic; + signal mdout1_28_1: std_logic; + signal mdout1_27_1: std_logic; + signal mdout1_26_1: std_logic; + signal mdout1_25_1: std_logic; + signal mdout1_24_1: std_logic; + signal mdout1_23_1: std_logic; + signal mdout1_22_1: std_logic; + signal mdout1_21_1: std_logic; + signal mdout1_20_1: std_logic; + signal mdout1_19_1: std_logic; + signal mdout1_18_1: std_logic; + signal mdout1_17_1: std_logic; + signal mdout1_16_1: std_logic; + signal mdout1_15_1: std_logic; + signal mdout1_14_1: std_logic; + signal mdout1_13_1: std_logic; + signal mdout1_12_1: std_logic; + signal mdout1_11_1: std_logic; + signal mdout1_10_1: std_logic; + signal mdout1_9_1: std_logic; + signal mdout1_8_1: std_logic; + signal mdout1_7_1: std_logic; + signal mdout1_6_1: std_logic; + signal mdout1_5_1: std_logic; + signal mdout1_4_1: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_31_2: std_logic; + signal mdout1_30_2: std_logic; + signal mdout1_29_2: std_logic; + signal mdout1_28_2: std_logic; + signal mdout1_27_2: std_logic; + signal mdout1_26_2: std_logic; + signal mdout1_25_2: std_logic; + signal mdout1_24_2: std_logic; + signal mdout1_23_2: std_logic; + signal mdout1_22_2: std_logic; + signal mdout1_21_2: std_logic; + signal mdout1_20_2: std_logic; + signal mdout1_19_2: std_logic; + signal mdout1_18_2: std_logic; + signal mdout1_17_2: std_logic; + signal mdout1_16_2: std_logic; + signal mdout1_15_2: std_logic; + signal mdout1_14_2: std_logic; + signal mdout1_13_2: std_logic; + signal mdout1_12_2: std_logic; + signal mdout1_11_2: std_logic; + signal mdout1_10_2: std_logic; + signal mdout1_9_2: std_logic; + signal mdout1_8_2: std_logic; + signal mdout1_7_2: std_logic; + signal mdout1_6_2: std_logic; + signal mdout1_5_2: std_logic; + signal mdout1_4_2: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_31_3: std_logic; + signal mdout1_30_3: std_logic; + signal mdout1_29_3: std_logic; + signal mdout1_28_3: std_logic; + signal mdout1_27_3: std_logic; + signal mdout1_26_3: std_logic; + signal mdout1_25_3: std_logic; + signal mdout1_24_3: std_logic; + signal mdout1_23_3: std_logic; + signal mdout1_22_3: std_logic; + signal mdout1_21_3: std_logic; + signal mdout1_20_3: std_logic; + signal mdout1_19_3: std_logic; + signal mdout1_18_3: std_logic; + signal mdout1_17_3: std_logic; + signal mdout1_16_3: std_logic; + signal mdout1_15_3: std_logic; + signal mdout1_14_3: std_logic; + signal mdout1_13_3: std_logic; + signal mdout1_12_3: std_logic; + signal mdout1_11_3: std_logic; + signal mdout1_10_3: std_logic; + signal mdout1_9_3: std_logic; + signal mdout1_8_3: std_logic; + signal mdout1_7_3: std_logic; + signal mdout1_6_3: std_logic; + signal mdout1_5_3: std_logic; + signal mdout1_4_3: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_31_4: std_logic; + signal mdout1_30_4: std_logic; + signal mdout1_29_4: std_logic; + signal mdout1_28_4: std_logic; + signal mdout1_27_4: std_logic; + signal mdout1_26_4: std_logic; + signal mdout1_25_4: std_logic; + signal mdout1_24_4: std_logic; + signal mdout1_23_4: std_logic; + signal mdout1_22_4: std_logic; + signal mdout1_21_4: std_logic; + signal mdout1_20_4: std_logic; + signal mdout1_19_4: std_logic; + signal mdout1_18_4: std_logic; + signal mdout1_17_4: std_logic; + signal mdout1_16_4: std_logic; + signal mdout1_15_4: std_logic; + signal mdout1_14_4: std_logic; + signal mdout1_13_4: std_logic; + signal mdout1_12_4: std_logic; + signal mdout1_11_4: std_logic; + signal mdout1_10_4: std_logic; + signal mdout1_9_4: std_logic; + signal mdout1_8_4: std_logic; + signal mdout1_7_4: std_logic; + signal mdout1_6_4: std_logic; + signal mdout1_5_4: std_logic; + signal mdout1_4_4: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_31_5: std_logic; + signal mdout1_30_5: std_logic; + signal mdout1_29_5: std_logic; + signal mdout1_28_5: std_logic; + signal mdout1_27_5: std_logic; + signal mdout1_26_5: std_logic; + signal mdout1_25_5: std_logic; + signal mdout1_24_5: std_logic; + signal mdout1_23_5: std_logic; + signal mdout1_22_5: std_logic; + signal mdout1_21_5: std_logic; + signal mdout1_20_5: std_logic; + signal mdout1_19_5: std_logic; + signal mdout1_18_5: std_logic; + signal mdout1_17_5: std_logic; + signal mdout1_16_5: std_logic; + signal mdout1_15_5: std_logic; + signal mdout1_14_5: std_logic; + signal mdout1_13_5: std_logic; + signal mdout1_12_5: std_logic; + signal mdout1_11_5: std_logic; + signal mdout1_10_5: std_logic; + signal mdout1_9_5: std_logic; + signal mdout1_8_5: std_logic; + signal mdout1_7_5: std_logic; + signal mdout1_6_5: std_logic; + signal mdout1_5_5: std_logic; + signal mdout1_4_5: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_31_6: std_logic; + signal mdout1_30_6: std_logic; + signal mdout1_29_6: std_logic; + signal mdout1_28_6: std_logic; + signal mdout1_27_6: std_logic; + signal mdout1_26_6: std_logic; + signal mdout1_25_6: std_logic; + signal mdout1_24_6: std_logic; + signal mdout1_23_6: std_logic; + signal mdout1_22_6: std_logic; + signal mdout1_21_6: std_logic; + signal mdout1_20_6: std_logic; + signal mdout1_19_6: std_logic; + signal mdout1_18_6: std_logic; + signal mdout1_17_6: std_logic; + signal mdout1_16_6: std_logic; + signal mdout1_15_6: std_logic; + signal mdout1_14_6: std_logic; + signal mdout1_13_6: std_logic; + signal mdout1_12_6: std_logic; + signal mdout1_11_6: std_logic; + signal mdout1_10_6: std_logic; + signal mdout1_9_6: std_logic; + signal mdout1_8_6: std_logic; + signal mdout1_7_6: std_logic; + signal mdout1_6_6: std_logic; + signal mdout1_5_6: std_logic; + signal mdout1_4_6: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_31_7: std_logic; + signal mdout1_30_7: std_logic; + signal mdout1_29_7: std_logic; + signal mdout1_28_7: std_logic; + signal mdout1_27_7: std_logic; + signal mdout1_26_7: std_logic; + signal mdout1_25_7: std_logic; + signal mdout1_24_7: std_logic; + signal mdout1_23_7: std_logic; + signal mdout1_22_7: std_logic; + signal mdout1_21_7: std_logic; + signal mdout1_20_7: std_logic; + signal mdout1_19_7: std_logic; + signal mdout1_18_7: std_logic; + signal mdout1_17_7: std_logic; + signal mdout1_16_7: std_logic; + signal mdout1_15_7: std_logic; + signal mdout1_14_7: std_logic; + signal mdout1_13_7: std_logic; + signal mdout1_12_7: std_logic; + signal mdout1_11_7: std_logic; + signal mdout1_10_7: std_logic; + signal mdout1_9_7: std_logic; + signal mdout1_8_7: std_logic; + signal mdout1_7_7: std_logic; + signal mdout1_6_7: std_logic; + signal mdout1_5_7: std_logic; + signal mdout1_4_7: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_15_ff: std_logic; + signal rptr_14_ff: std_logic; + signal rptr_13_ff: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_31_8: std_logic; + signal mdout1_30_8: std_logic; + signal mdout1_29_8: std_logic; + signal mdout1_28_8: std_logic; + signal mdout1_27_8: std_logic; + signal mdout1_26_8: std_logic; + signal mdout1_25_8: std_logic; + signal mdout1_24_8: std_logic; + signal mdout1_23_8: std_logic; + signal mdout1_22_8: std_logic; + signal mdout1_21_8: std_logic; + signal mdout1_20_8: std_logic; + signal mdout1_19_8: std_logic; + signal mdout1_18_8: std_logic; + signal mdout1_17_8: std_logic; + signal mdout1_16_8: std_logic; + signal mdout1_15_8: std_logic; + signal mdout1_14_8: std_logic; + signal mdout1_13_8: std_logic; + signal mdout1_12_8: std_logic; + signal mdout1_11_8: std_logic; + signal mdout1_10_8: std_logic; + signal mdout1_9_8: std_logic; + signal mdout1_8_8: std_logic; + signal mdout1_7_8: std_logic; + signal mdout1_6_8: std_logic; + signal mdout1_5_8: std_logic; + signal mdout1_4_8: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal wfill_sub_0: std_logic; + signal precin: std_logic; + signal wptr_0: std_logic; + signal wfill_sub_1: std_logic; + signal wfill_sub_2: std_logic; + signal co0_2: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wfill_sub_3: std_logic; + signal wfill_sub_4: std_logic; + signal co1_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wfill_sub_5: std_logic; + signal wfill_sub_6: std_logic; + signal co2_2: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wfill_sub_7: std_logic; + signal wfill_sub_8: std_logic; + signal co3_2: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wfill_sub_9: std_logic; + signal wfill_sub_10: std_logic; + signal co4_2: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wfill_sub_11: std_logic; + signal wfill_sub_12: std_logic; + signal co5_2: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wfill_sub_13: std_logic; + signal wfill_sub_14: std_logic; + signal co6_2: std_logic; + signal wptr_13: std_logic; + signal wptr_14: std_logic; + signal wfill_sub_15: std_logic; + signal wfill_sub_16: std_logic; + signal co7_2: std_logic; + signal wptr_15: std_logic; + signal wfill_sub_msb: std_logic; + signal co8_2d: std_logic; + signal co8_2: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_3: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_3: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_3: std_logic; + signal wcount_r8: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_3: std_logic; + signal wcount_r10: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_3: std_logic; + signal wcount_r12: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_3: std_logic; + signal wcount_r14: std_logic; + signal wcount_r15: std_logic; + signal rcount_14: std_logic; + signal rcount_15: std_logic; + signal co7_3: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_4: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_4: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_4: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_4: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_4: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_4: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_4: std_logic; + signal wcount_14: std_logic; + signal wcount_15: std_logic; + signal co7_4: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal iaf_setcount_0: std_logic; + signal iaf_setcount_1: std_logic; + signal af_set_ctr_ci: std_logic; + signal iaf_setcount_2: std_logic; + signal iaf_setcount_3: std_logic; + signal co0_5: std_logic; + signal iaf_setcount_4: std_logic; + signal iaf_setcount_5: std_logic; + signal co1_5: std_logic; + signal iaf_setcount_6: std_logic; + signal iaf_setcount_7: std_logic; + signal co2_5: std_logic; + signal iaf_setcount_8: std_logic; + signal iaf_setcount_9: std_logic; + signal co3_5: std_logic; + signal iaf_setcount_10: std_logic; + signal iaf_setcount_11: std_logic; + signal co4_5: std_logic; + signal iaf_setcount_12: std_logic; + signal iaf_setcount_13: std_logic; + signal co5_5: std_logic; + signal iaf_setcount_14: std_logic; + signal iaf_setcount_15: std_logic; + signal co6_5: std_logic; + signal iaf_setcount_16: std_logic; + signal co8_3: std_logic; + signal co7_5: std_logic; + signal af_setcount_16: std_logic; + signal cmp_ci_2: std_logic; + signal af_setcount_0: std_logic; + signal af_setcount_1: std_logic; + signal co0_6: std_logic; + signal af_setcount_2: std_logic; + signal af_setcount_3: std_logic; + signal co1_6: std_logic; + signal af_setcount_4: std_logic; + signal af_setcount_5: std_logic; + signal co2_6: std_logic; + signal af_setcount_6: std_logic; + signal af_setcount_7: std_logic; + signal co3_6: std_logic; + signal af_setcount_8: std_logic; + signal af_setcount_9: std_logic; + signal co4_6: std_logic; + signal af_setcount_10: std_logic; + signal af_setcount_11: std_logic; + signal co5_6: std_logic; + signal af_setcount_12: std_logic; + signal af_setcount_13: std_logic; + signal co6_6: std_logic; + signal af_setcount_14: std_logic; + signal af_setcount_15: std_logic; + signal co7_6: std_logic; + signal af_set_cmp_clr: std_logic; + signal af_set_cmp_set: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; + signal scuba_vhi: std_logic; + signal iaf_clrcount_0: std_logic; + signal iaf_clrcount_1: std_logic; + signal af_clr_ctr_ci: std_logic; + signal iaf_clrcount_2: std_logic; + signal iaf_clrcount_3: std_logic; + signal co0_7: std_logic; + signal iaf_clrcount_4: std_logic; + signal iaf_clrcount_5: std_logic; + signal co1_7: std_logic; + signal iaf_clrcount_6: std_logic; + signal iaf_clrcount_7: std_logic; + signal co2_7: std_logic; + signal iaf_clrcount_8: std_logic; + signal iaf_clrcount_9: std_logic; + signal co3_7: std_logic; + signal iaf_clrcount_10: std_logic; + signal iaf_clrcount_11: std_logic; + signal co4_7: std_logic; + signal iaf_clrcount_12: std_logic; + signal iaf_clrcount_13: std_logic; + signal co5_7: std_logic; + signal iaf_clrcount_14: std_logic; + signal iaf_clrcount_15: std_logic; + signal co6_7: std_logic; + signal iaf_clrcount_16: std_logic; + signal co8_4: std_logic; + signal co7_7: std_logic; + signal af_clrcount_16: std_logic; + signal wren_i: std_logic; + signal cmp_ci_3: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal af_clrcount_0: std_logic; + signal af_clrcount_1: std_logic; + signal co0_8: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal af_clrcount_2: std_logic; + signal af_clrcount_3: std_logic; + signal co1_8: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal af_clrcount_4: std_logic; + signal af_clrcount_5: std_logic; + signal co2_8: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal af_clrcount_6: std_logic; + signal af_clrcount_7: std_logic; + signal co3_8: std_logic; + signal rcount_w8: std_logic; + signal rcount_w9: std_logic; + signal af_clrcount_8: std_logic; + signal af_clrcount_9: std_logic; + signal co4_8: std_logic; + signal rcount_w10: std_logic; + signal rcount_w11: std_logic; + signal af_clrcount_10: std_logic; + signal af_clrcount_11: std_logic; + signal co5_8: std_logic; + signal rcount_w12: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal af_clrcount_12: std_logic; + signal af_clrcount_13: std_logic; + signal co6_8: std_logic; + signal rcount_w14: std_logic; + signal rcount_w15: std_logic; + signal af_clrcount_14: std_logic; + signal af_clrcount_15: std_logic; + signal co7_8: std_logic; + signal af_clr_cmp_clr: std_logic; + signal af_clr_cmp_set: std_logic; + signal af_clr: std_logic; + signal af_clr_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX321 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; D4: in std_logic; D5: in std_logic; + D6: in std_logic; D7: in std_logic; D8: in std_logic; + D9: in std_logic; D10: in std_logic; D11: in std_logic; + D12: in std_logic; D13: in std_logic; D14: in std_logic; + D15: in std_logic; D16: in std_logic; D17: in std_logic; + D18: in std_logic; D19: in std_logic; D20: in std_logic; + D21: in std_logic; D22: in std_logic; D23: in std_logic; + D24: in std_logic; D25: in std_logic; D26: in std_logic; + D27: in std_logic; D28: in std_logic; D29: in std_logic; + D30: in std_logic; D31: in std_logic; SD1: in std_logic; + SD2: in std_logic; SD3: in std_logic; SD4: in std_logic; + SD5: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute RESETMODE of pdp_ram_0_0_31 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; + attribute RESETMODE of pdp_ram_1_0_30 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; + attribute RESETMODE of pdp_ram_2_0_29 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; + attribute RESETMODE of pdp_ram_3_0_28 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; + attribute RESETMODE of pdp_ram_4_0_27 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; + attribute RESETMODE of pdp_ram_5_0_26 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is ""; + attribute RESETMODE of pdp_ram_6_0_25 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is ""; + attribute RESETMODE of pdp_ram_7_0_24 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is ""; + attribute RESETMODE of pdp_ram_8_0_23 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is ""; + attribute RESETMODE of pdp_ram_9_0_22 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is ""; + attribute RESETMODE of pdp_ram_10_0_21 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is ""; + attribute RESETMODE of pdp_ram_11_0_20 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is ""; + attribute RESETMODE of pdp_ram_12_0_19 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is ""; + attribute RESETMODE of pdp_ram_13_0_18 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is ""; + attribute RESETMODE of pdp_ram_14_0_17 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is ""; + attribute RESETMODE of pdp_ram_15_0_16 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is ""; + attribute RESETMODE of pdp_ram_16_0_15 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is ""; + attribute RESETMODE of pdp_ram_17_0_14 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is ""; + attribute RESETMODE of pdp_ram_18_0_13 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is ""; + attribute RESETMODE of pdp_ram_19_0_12 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is ""; + attribute RESETMODE of pdp_ram_20_0_11 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is ""; + attribute RESETMODE of pdp_ram_21_0_10 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is ""; + attribute RESETMODE of pdp_ram_22_0_9 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is ""; + attribute RESETMODE of pdp_ram_23_0_8 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is ""; + attribute RESETMODE of pdp_ram_24_0_7 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is ""; + attribute RESETMODE of pdp_ram_25_0_6 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is ""; + attribute RESETMODE of pdp_ram_26_0_5 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is ""; + attribute RESETMODE of pdp_ram_27_0_4 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is ""; + attribute RESETMODE of pdp_ram_28_0_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is ""; + attribute RESETMODE of pdp_ram_29_0_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; + attribute RESETMODE of pdp_ram_30_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_64kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; + attribute RESETMODE of pdp_ram_31_0_0 : label is "SYNC"; + attribute GSR of FF_228 : label is "ENABLED"; + attribute GSR of FF_227 : label is "ENABLED"; + attribute GSR of FF_226 : label is "ENABLED"; + attribute GSR of FF_225 : label is "ENABLED"; + attribute GSR of FF_224 : label is "ENABLED"; + attribute GSR of FF_223 : label is "ENABLED"; + attribute GSR of FF_222 : label is "ENABLED"; + attribute GSR of FF_221 : label is "ENABLED"; + attribute GSR of FF_220 : label is "ENABLED"; + attribute GSR of FF_219 : label is "ENABLED"; + attribute GSR of FF_218 : label is "ENABLED"; + attribute GSR of FF_217 : label is "ENABLED"; + attribute GSR of FF_216 : label is "ENABLED"; + attribute GSR of FF_215 : label is "ENABLED"; + attribute GSR of FF_214 : label is "ENABLED"; + attribute GSR of FF_213 : label is "ENABLED"; + attribute GSR of FF_212 : label is "ENABLED"; + attribute GSR of FF_211 : label is "ENABLED"; + attribute GSR of FF_210 : label is "ENABLED"; + attribute GSR of FF_209 : label is "ENABLED"; + attribute GSR of FF_208 : label is "ENABLED"; + attribute GSR of FF_207 : label is "ENABLED"; + attribute GSR of FF_206 : label is "ENABLED"; + attribute GSR of FF_205 : label is "ENABLED"; + attribute GSR of FF_204 : label is "ENABLED"; + attribute GSR of FF_203 : label is "ENABLED"; + attribute GSR of FF_202 : label is "ENABLED"; + attribute GSR of FF_201 : label is "ENABLED"; + attribute GSR of FF_200 : label is "ENABLED"; + attribute GSR of FF_199 : label is "ENABLED"; + attribute GSR of FF_198 : label is "ENABLED"; + attribute GSR of FF_197 : label is "ENABLED"; + attribute GSR of FF_196 : label is "ENABLED"; + attribute GSR of FF_195 : label is "ENABLED"; + attribute GSR of FF_194 : label is "ENABLED"; + attribute GSR of FF_193 : label is "ENABLED"; + attribute GSR of FF_192 : label is "ENABLED"; + attribute GSR of FF_191 : label is "ENABLED"; + attribute GSR of FF_190 : label is "ENABLED"; + attribute GSR of FF_189 : label is "ENABLED"; + attribute GSR of FF_188 : label is "ENABLED"; + attribute GSR of FF_187 : label is "ENABLED"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t35: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_11: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t34: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_10: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t33: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t32: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t31: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t30: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t29: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t28: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t27: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t26: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t25: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t24: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t23: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t22: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t21: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t20: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t19: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t18: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t17: XOR2 + port map (A=>wcount_15, B=>wcount_16, Z=>w_gdata_15); + + XOR2_t16: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t15: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t14: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t13: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t12: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t11: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t10: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t9: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t8: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t7: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t6: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t5: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t4: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t3: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t2: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + XOR2_t1: XOR2 + port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); + + INV_9: INV + port map (A=>wptr_11, Z=>wptr_11_inv); + + INV_8: INV + port map (A=>wptr_12, Z=>wptr_12_inv); + + INV_7: INV + port map (A=>wptr_13, Z=>wptr_13_inv); + + INV_6: INV + port map (A=>wptr_14, Z=>wptr_14_inv); + + INV_5: INV + port map (A=>wptr_15, Z=>wptr_15_inv); + + LUT4_192: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet); + + LUT4_191: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_p00); + + INV_4: INV + port map (A=>rptr_11, Z=>rptr_11_inv); + + INV_3: INV + port map (A=>rptr_12, Z=>rptr_12_inv); + + INV_2: INV + port map (A=>rptr_13, Z=>rptr_13_inv); + + INV_1: INV + port map (A=>rptr_14, Z=>rptr_14_inv); + + INV_0: INV + port map (A=>rptr_15, Z=>rptr_15_inv); + + LUT4_190: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_1); + + LUT4_189: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec1_r10); + + LUT4_188: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_2); + + LUT4_187: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_2, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec2_p01); + + LUT4_186: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_3); + + LUT4_185: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec3_r11); + + LUT4_184: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_4); + + LUT4_183: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_4, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec4_p02); + + LUT4_182: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_5); + + LUT4_181: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec5_r12); + + LUT4_180: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_6); + + LUT4_179: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_6, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec6_p03); + + LUT4_178: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_7); + + LUT4_177: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec7_r13); + + LUT4_176: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_8); + + LUT4_175: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_8, AD2=>wptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec8_p04); + + LUT4_174: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_9); + + LUT4_173: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec9_r14); + + LUT4_172: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_10); + + LUT4_171: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_10, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); + + LUT4_170: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_11); + + LUT4_169: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); + + LUT4_168: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_12); + + LUT4_167: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_12, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); + + LUT4_166: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_13); + + LUT4_165: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); + + LUT4_164: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_14); + + LUT4_163: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_14, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); + + LUT4_162: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_15); + + LUT4_161: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); + + LUT4_160: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_16); + + LUT4_159: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_16, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); + + LUT4_158: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_17); + + LUT4_157: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); + + LUT4_156: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_18); + + LUT4_155: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_18, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); + + LUT4_154: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_19); + + LUT4_153: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); + + LUT4_152: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_20); + + LUT4_151: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_20, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); + + LUT4_150: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_21); + + LUT4_149: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); + + LUT4_148: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_22); + + LUT4_147: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_22, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); + + LUT4_146: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_23); + + LUT4_145: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); + + LUT4_144: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_24); + + LUT4_143: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_24, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); + + LUT4_142: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_25); + + LUT4_141: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); + + LUT4_140: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_26); + + LUT4_139: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_26, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); + + LUT4_138: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_27); + + LUT4_137: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); + + LUT4_136: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_28); + + LUT4_135: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_28, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); + + LUT4_134: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_29); + + LUT4_133: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); + + LUT4_132: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, + DO0=>func_and_inet_30); + + LUT4_131: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_30, AD2=>wptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); + + LUT4_130: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_31); + + LUT4_129: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); + + LUT4_128: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_32); + + LUT4_127: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_32, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec32_p016); + + LUT4_126: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_33); + + LUT4_125: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec33_r116); + + LUT4_124: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_34); + + LUT4_123: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_34, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec34_p017); + + LUT4_122: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_35); + + LUT4_121: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec35_r117); + + LUT4_120: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_36); + + LUT4_119: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_36, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec36_p018); + + LUT4_118: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_37); + + LUT4_117: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec37_r118); + + LUT4_116: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14_inv, DO0=>func_and_inet_38); + + LUT4_115: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_38, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec38_p019); + + LUT4_114: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_39); + + LUT4_113: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec39_r119); + + LUT4_112: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_40); + + LUT4_111: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_40, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec40_p020); + + LUT4_110: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_41); + + LUT4_109: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec41_r120); + + LUT4_108: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_42); + + LUT4_107: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_42, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec42_p021); + + LUT4_106: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_43); + + LUT4_105: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec43_r121); + + LUT4_104: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_44); + + LUT4_103: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_44, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec44_p022); + + LUT4_102: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_45); + + LUT4_101: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec45_r122); + + LUT4_100: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14_inv, DO0=>func_and_inet_46); + + LUT4_99: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_46, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec46_p023); + + LUT4_98: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_47); + + LUT4_97: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec47_r123); + + LUT4_96: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_48); + + LUT4_95: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_48, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec48_p024); + + LUT4_94: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_49); + + LUT4_93: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec49_r124); + + LUT4_92: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_50); + + LUT4_91: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_50, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec50_p025); + + LUT4_90: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_51); + + LUT4_89: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec51_r125); + + LUT4_88: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_52); + + LUT4_87: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_52, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec52_p026); + + LUT4_86: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_53); + + LUT4_85: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec53_r126); + + LUT4_84: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv, + AD0=>wptr_14, DO0=>func_and_inet_54); + + LUT4_83: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_54, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec54_p027); + + LUT4_82: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_55); + + LUT4_81: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec55_r127); + + LUT4_80: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_56); + + LUT4_79: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_56, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec56_p028); + + LUT4_78: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_57); + + LUT4_77: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec57_r128); + + LUT4_76: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_58); + + LUT4_75: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_58, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec58_p029); + + LUT4_74: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_59); + + LUT4_73: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec59_r129); + + LUT4_72: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13, + AD0=>wptr_14, DO0=>func_and_inet_60); + + LUT4_71: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_60, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec60_p030); + + LUT4_70: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_61); + + LUT4_69: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec61_r130); + + LUT4_68: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14, + DO0=>func_and_inet_62); + + LUT4_67: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_62, AD2=>wptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec62_p031); + + LUT4_66: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_63); + + LUT4_65: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec63_r131); + + LUT4_64: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>w_gcount_r216, + DO0=>w_g2b_xor_cluster_0); + + LUT4_63: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_gcount_r212, + DO0=>w_g2b_xor_cluster_1); + + LUT4_62: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, + DO0=>w_g2b_xor_cluster_2); + + LUT4_61: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_3); + + LUT4_60: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r215, AD2=>w_gcount_r216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r15); + + LUT4_59: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, + AD1=>w_gcount_r216, AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_58: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>wcount_r15, DO0=>wcount_r12); + + LUT4_57: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_56: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>w_g2b_xor_cluster_0, + DO0=>wcount_r10); + + LUT4_55: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_54: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_53: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>w_gcount_r28, DO0=>wcount_r7); + + LUT4_52: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_51: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r6); + + LUT4_50: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_49: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r24, DO0=>wcount_r4); + + LUT4_48: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_47: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r3); + + LUT4_46: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_45: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r2); + + LUT4_44: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r1); + + LUT4_43: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>func_xor_inet); + + LUT4_42: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>func_xor_inet_1); + + LUT4_41: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, DO0=>func_xor_inet_2); + + LUT4_40: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, DO0=>func_xor_inet_3); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_4); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, + AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, + DO0=>func_xor_inet_5); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>r_gcount_w216, + DO0=>r_g2b_xor_cluster_0); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_1); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_2); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_3); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w15); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, + AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, + DO0=>rcount_w10); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w3); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w2); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet_6); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_7); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_8); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_9); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_10); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_6, AD2=>func_xor_inet_7, + AD1=>func_xor_inet_8, AD0=>func_xor_inet_9, + DO0=>func_xor_inet_11); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_11, AD2=>func_xor_inet_10, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); + + XOR2_t0: XOR2 + port map (A=>wptr_16, B=>r_gcount_w216, Z=>wfill_sub_msb); + + LUT4_8: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_7: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r216, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_6: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_5: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_16, AD2=>wcount_16, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + LUT4_4: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_setcount_16, AD2=>wcount_16, + AD1=>r_gcount_w216, AD0=>wptr_16, DO0=>af_set_cmp_set); + + LUT4_3: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_setcount_16, AD2=>wcount_16, + AD1=>r_gcount_w216, AD0=>wptr_16, DO0=>af_set_cmp_clr); + + LUT4_2: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_clrcount_16, AD2=>wcount_16, + AD1=>r_gcount_w216, AD0=>wptr_16, DO0=>af_clr_cmp_set); + + LUT4_1: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_clrcount_16, AD2=>wcount_16, + AD1=>r_gcount_w216, AD0=>wptr_16, DO0=>af_clr_cmp_clr); + + LUT4_0: ROM16X1A + generic map (initval=> X"4450") + port map (AD3=>af, AD2=>af_set, AD1=>af_clr, AD0=>scuba_vlo, + DO0=>af_d); + + pdp_ram_0_0_31: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec0_p00, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec1_r10, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_30: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec2_p01, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec3_r11, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_29: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec4_p02, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec5_r12, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, + DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, + DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, + DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_28: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec6_p03, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec7_r13, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, + DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, + DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, + DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_4_0_27: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec8_p04, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec9_r14, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0, DOB1=>mdout1_4_1, + DOB2=>mdout1_4_2, DOB3=>mdout1_4_3, DOB4=>mdout1_4_4, + DOB5=>mdout1_4_5, DOB6=>mdout1_4_6, DOB7=>mdout1_4_7, + DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_5_0_26: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec10_p05, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec11_r15, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0, DOB1=>mdout1_5_1, + DOB2=>mdout1_5_2, DOB3=>mdout1_5_3, DOB4=>mdout1_5_4, + DOB5=>mdout1_5_5, DOB6=>mdout1_5_6, DOB7=>mdout1_5_7, + DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_6_0_25: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec12_p06, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec13_r16, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0, DOB1=>mdout1_6_1, + DOB2=>mdout1_6_2, DOB3=>mdout1_6_3, DOB4=>mdout1_6_4, + DOB5=>mdout1_6_5, DOB6=>mdout1_6_6, DOB7=>mdout1_6_7, + DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_7_0_24: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec14_p07, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec15_r17, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0, DOB1=>mdout1_7_1, + DOB2=>mdout1_7_2, DOB3=>mdout1_7_3, DOB4=>mdout1_7_4, + DOB5=>mdout1_7_5, DOB6=>mdout1_7_6, DOB7=>mdout1_7_7, + DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_8_0_23: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec16_p08, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec17_r18, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0, DOB1=>mdout1_8_1, + DOB2=>mdout1_8_2, DOB3=>mdout1_8_3, DOB4=>mdout1_8_4, + DOB5=>mdout1_8_5, DOB6=>mdout1_8_6, DOB7=>mdout1_8_7, + DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_9_0_22: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec18_p09, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec19_r19, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0, DOB1=>mdout1_9_1, + DOB2=>mdout1_9_2, DOB3=>mdout1_9_3, DOB4=>mdout1_9_4, + DOB5=>mdout1_9_5, DOB6=>mdout1_9_6, DOB7=>mdout1_9_7, + DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_10_0_21: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec20_p010, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec21_r110, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_10_0, + DOB1=>mdout1_10_1, DOB2=>mdout1_10_2, DOB3=>mdout1_10_3, + DOB4=>mdout1_10_4, DOB5=>mdout1_10_5, DOB6=>mdout1_10_6, + DOB7=>mdout1_10_7, DOB8=>mdout1_10_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_11_0_20: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec22_p011, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec23_r111, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_11_0, + DOB1=>mdout1_11_1, DOB2=>mdout1_11_2, DOB3=>mdout1_11_3, + DOB4=>mdout1_11_4, DOB5=>mdout1_11_5, DOB6=>mdout1_11_6, + DOB7=>mdout1_11_7, DOB8=>mdout1_11_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_12_0_19: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec24_p012, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec25_r112, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_12_0, + DOB1=>mdout1_12_1, DOB2=>mdout1_12_2, DOB3=>mdout1_12_3, + DOB4=>mdout1_12_4, DOB5=>mdout1_12_5, DOB6=>mdout1_12_6, + DOB7=>mdout1_12_7, DOB8=>mdout1_12_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_13_0_18: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec26_p013, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec27_r113, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_13_0, + DOB1=>mdout1_13_1, DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, + DOB4=>mdout1_13_4, DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, + DOB7=>mdout1_13_7, DOB8=>mdout1_13_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_14_0_17: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec28_p014, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec29_r114, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_14_0, + DOB1=>mdout1_14_1, DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, + DOB4=>mdout1_14_4, DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, + DOB7=>mdout1_14_7, DOB8=>mdout1_14_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_15_0_16: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec30_p015, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec31_r115, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_15_0, + DOB1=>mdout1_15_1, DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, + DOB4=>mdout1_15_4, DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, + DOB7=>mdout1_15_7, DOB8=>mdout1_15_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_16_0_15: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec32_p016, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec33_r116, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_16_0, + DOB1=>mdout1_16_1, DOB2=>mdout1_16_2, DOB3=>mdout1_16_3, + DOB4=>mdout1_16_4, DOB5=>mdout1_16_5, DOB6=>mdout1_16_6, + DOB7=>mdout1_16_7, DOB8=>mdout1_16_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_17_0_14: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec34_p017, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec35_r117, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_17_0, + DOB1=>mdout1_17_1, DOB2=>mdout1_17_2, DOB3=>mdout1_17_3, + DOB4=>mdout1_17_4, DOB5=>mdout1_17_5, DOB6=>mdout1_17_6, + DOB7=>mdout1_17_7, DOB8=>mdout1_17_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_18_0_13: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec36_p018, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec37_r118, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_18_0, + DOB1=>mdout1_18_1, DOB2=>mdout1_18_2, DOB3=>mdout1_18_3, + DOB4=>mdout1_18_4, DOB5=>mdout1_18_5, DOB6=>mdout1_18_6, + DOB7=>mdout1_18_7, DOB8=>mdout1_18_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_19_0_12: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec38_p019, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec39_r119, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_19_0, + DOB1=>mdout1_19_1, DOB2=>mdout1_19_2, DOB3=>mdout1_19_3, + DOB4=>mdout1_19_4, DOB5=>mdout1_19_5, DOB6=>mdout1_19_6, + DOB7=>mdout1_19_7, DOB8=>mdout1_19_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_20_0_11: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec40_p020, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec41_r120, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_20_0, + DOB1=>mdout1_20_1, DOB2=>mdout1_20_2, DOB3=>mdout1_20_3, + DOB4=>mdout1_20_4, DOB5=>mdout1_20_5, DOB6=>mdout1_20_6, + DOB7=>mdout1_20_7, DOB8=>mdout1_20_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_21_0_10: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec42_p021, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec43_r121, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_21_0, + DOB1=>mdout1_21_1, DOB2=>mdout1_21_2, DOB3=>mdout1_21_3, + DOB4=>mdout1_21_4, DOB5=>mdout1_21_5, DOB6=>mdout1_21_6, + DOB7=>mdout1_21_7, DOB8=>mdout1_21_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_22_0_9: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec44_p022, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec45_r122, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_22_0, + DOB1=>mdout1_22_1, DOB2=>mdout1_22_2, DOB3=>mdout1_22_3, + DOB4=>mdout1_22_4, DOB5=>mdout1_22_5, DOB6=>mdout1_22_6, + DOB7=>mdout1_22_7, DOB8=>mdout1_22_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_23_0_8: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec46_p023, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec47_r123, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_23_0, + DOB1=>mdout1_23_1, DOB2=>mdout1_23_2, DOB3=>mdout1_23_3, + DOB4=>mdout1_23_4, DOB5=>mdout1_23_5, DOB6=>mdout1_23_6, + DOB7=>mdout1_23_7, DOB8=>mdout1_23_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_24_0_7: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec48_p024, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec49_r124, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_24_0, + DOB1=>mdout1_24_1, DOB2=>mdout1_24_2, DOB3=>mdout1_24_3, + DOB4=>mdout1_24_4, DOB5=>mdout1_24_5, DOB6=>mdout1_24_6, + DOB7=>mdout1_24_7, DOB8=>mdout1_24_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_25_0_6: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec50_p025, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec51_r125, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_25_0, + DOB1=>mdout1_25_1, DOB2=>mdout1_25_2, DOB3=>mdout1_25_3, + DOB4=>mdout1_25_4, DOB5=>mdout1_25_5, DOB6=>mdout1_25_6, + DOB7=>mdout1_25_7, DOB8=>mdout1_25_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_26_0_5: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec52_p026, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec53_r126, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_26_0, + DOB1=>mdout1_26_1, DOB2=>mdout1_26_2, DOB3=>mdout1_26_3, + DOB4=>mdout1_26_4, DOB5=>mdout1_26_5, DOB6=>mdout1_26_6, + DOB7=>mdout1_26_7, DOB8=>mdout1_26_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_27_0_4: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec54_p027, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec55_r127, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_27_0, + DOB1=>mdout1_27_1, DOB2=>mdout1_27_2, DOB3=>mdout1_27_3, + DOB4=>mdout1_27_4, DOB5=>mdout1_27_5, DOB6=>mdout1_27_6, + DOB7=>mdout1_27_7, DOB8=>mdout1_27_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_28_0_3: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec56_p028, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec57_r128, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_28_0, + DOB1=>mdout1_28_1, DOB2=>mdout1_28_2, DOB3=>mdout1_28_3, + DOB4=>mdout1_28_4, DOB5=>mdout1_28_5, DOB6=>mdout1_28_6, + DOB7=>mdout1_28_7, DOB8=>mdout1_28_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_29_0_2: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec58_p029, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec59_r129, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_29_0, + DOB1=>mdout1_29_1, DOB2=>mdout1_29_2, DOB3=>mdout1_29_3, + DOB4=>mdout1_29_4, DOB5=>mdout1_29_5, DOB6=>mdout1_29_6, + DOB7=>mdout1_29_7, DOB8=>mdout1_29_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_30_0_1: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec60_p030, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec61_r130, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_30_0, + DOB1=>mdout1_30_1, DOB2=>mdout1_30_2, DOB3=>mdout1_30_3, + DOB4=>mdout1_30_4, DOB5=>mdout1_30_5, DOB6=>mdout1_30_6, + DOB7=>mdout1_30_7, DOB8=>mdout1_30_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + pdp_ram_31_0_0: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>dec62_p031, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>dec63_r131, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_31_0, + DOB1=>mdout1_31_1, DOB2=>mdout1_31_2, DOB3=>mdout1_31_3, + DOB4=>mdout1_31_4, DOB5=>mdout1_31_5, DOB6=>mdout1_31_6, + DOB7=>mdout1_31_7, DOB8=>mdout1_31_8, DOB9=>open, + DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open, + DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); + + FF_228: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_227: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_226: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_225: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_224: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_223: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_222: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_221: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_220: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_219: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_218: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_217: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_216: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_215: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_214: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_213: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_212: FD1P3DX + port map (D=>iwcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_16); + + FF_211: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_210: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_209: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_208: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_207: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_206: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_205: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_204: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_203: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_202: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_201: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_200: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_199: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_198: FD1P3DX + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_197: FD1P3DX + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_196: FD1P3DX + port map (D=>w_gdata_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_195: FD1P3DX + port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_16); + + FF_194: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_193: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_192: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_191: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_190: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_189: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_188: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_187: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_186: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_185: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_184: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_183: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_182: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_181: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_180: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_179: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_178: FD1P3DX + port map (D=>wcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_16); + + FF_177: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_176: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_175: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_174: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_173: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_172: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_171: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_170: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_169: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_168: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_167: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_166: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_165: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_164: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_163: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_162: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_161: FD1P3DX + port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_16); + + FF_160: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_159: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_158: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_157: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_156: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_155: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_154: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_153: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_152: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_151: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_150: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_149: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_148: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_147: FD1P3DX + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_146: FD1P3DX + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_145: FD1P3DX + port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_144: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_16); + + FF_143: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_142: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_141: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_140: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_139: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_138: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_137: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_136: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_135: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_134: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_133: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_132: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_131: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_130: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_129: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_128: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_127: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_16); + + FF_126: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_125: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_124: FD1P3DX + port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_13_ff); + + FF_123: FD1P3DX + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_122: FD1P3DX + port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_15_ff); + + FF_121: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_120: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_119: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_118: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_117: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_116: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_115: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_114: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_113: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_112: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_111: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_110: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_109: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_108: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_107: FD1S3DX + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_106: FD1S3DX + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_105: FD1S3DX + port map (D=>w_gcount_16, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r16); + + FF_104: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_103: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_102: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_101: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_100: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_99: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_98: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_97: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_96: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_95: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_94: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_93: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_92: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_91: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_90: FD1S3DX + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_89: FD1S3DX + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_88: FD1S3DX + port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); + + FF_87: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_86: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_85: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_84: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_83: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_82: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_81: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_80: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_79: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_78: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_77: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_76: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_75: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_74: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_73: FD1S3DX + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_72: FD1S3DX + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_71: FD1S3DX + port map (D=>w_gcount_r16, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r216); + + FF_70: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_69: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_68: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_67: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_66: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_65: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_64: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_63: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_62: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_61: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_60: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_59: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_58: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_57: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_56: FD1S3DX + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_55: FD1S3DX + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_54: FD1S3DX + port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w216); + + FF_53: FD1S3DX + port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); + + FF_52: FD1S3DX + port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); + + FF_51: FD1S3DX + port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); + + FF_50: FD1S3DX + port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); + + FF_49: FD1S3DX + port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); + + FF_48: FD1S3DX + port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); + + FF_47: FD1S3DX + port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); + + FF_46: FD1S3DX + port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); + + FF_45: FD1S3DX + port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); + + FF_44: FD1S3DX + port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); + + FF_43: FD1S3DX + port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); + + FF_42: FD1S3DX + port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); + + FF_41: FD1S3DX + port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); + + FF_40: FD1S3DX + port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); + + FF_39: FD1S3DX + port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); + + FF_38: FD1S3DX + port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); + + FF_37: FD1S3DX + port map (D=>wfill_sub_16, CK=>WrClock, CD=>Reset, Q=>WCNT(16)); + + FF_36: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_35: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_34: FD1P3BX + port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_0); + + FF_33: FD1P3DX + port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_1); + + FF_32: FD1P3BX + port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_2); + + FF_31: FD1P3DX + port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_3); + + FF_30: FD1P3DX + port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_4); + + FF_29: FD1P3BX + port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_5); + + FF_28: FD1P3DX + port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_6); + + FF_27: FD1P3DX + port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_7); + + FF_26: FD1P3DX + port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_8); + + FF_25: FD1P3DX + port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_9); + + FF_24: FD1P3DX + port map (D=>iaf_setcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_10); + + FF_23: FD1P3DX + port map (D=>iaf_setcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_11); + + FF_22: FD1P3DX + port map (D=>iaf_setcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_12); + + FF_21: FD1P3DX + port map (D=>iaf_setcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_13); + + FF_20: FD1P3DX + port map (D=>iaf_setcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_14); + + FF_19: FD1P3DX + port map (D=>iaf_setcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_15); + + FF_18: FD1P3DX + port map (D=>iaf_setcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_16); + + FF_17: FD1P3BX + port map (D=>iaf_clrcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_0); + + FF_16: FD1P3BX + port map (D=>iaf_clrcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_1); + + FF_15: FD1P3BX + port map (D=>iaf_clrcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_2); + + FF_14: FD1P3BX + port map (D=>iaf_clrcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_3); + + FF_13: FD1P3DX + port map (D=>iaf_clrcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_4); + + FF_12: FD1P3BX + port map (D=>iaf_clrcount_5, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_5); + + FF_11: FD1P3DX + port map (D=>iaf_clrcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_6); + + FF_10: FD1P3DX + port map (D=>iaf_clrcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_7); + + FF_9: FD1P3DX + port map (D=>iaf_clrcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_8); + + FF_8: FD1P3DX + port map (D=>iaf_clrcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_9); + + FF_7: FD1P3DX + port map (D=>iaf_clrcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_10); + + FF_6: FD1P3DX + port map (D=>iaf_clrcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_11); + + FF_5: FD1P3DX + port map (D=>iaf_clrcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_12); + + FF_4: FD1P3DX + port map (D=>iaf_clrcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_13); + + FF_3: FD1P3DX + port map (D=>iaf_clrcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_14); + + FF_2: FD1P3DX + port map (D=>iaf_clrcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_15); + + FF_1: FD1P3DX + port map (D=>iaf_clrcount_16, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_16); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>af); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + w_gctr_7: CU2 + port map (CI=>co6, PC0=>wcount_14, PC1=>wcount_15, CO=>co7, + NC0=>iwcount_14, NC1=>iwcount_15); + + w_gctr_8: CU2 + port map (CI=>co7, PC0=>wcount_16, PC1=>scuba_vlo, CO=>co8, + NC0=>iwcount_16, NC1=>open); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + r_gctr_7: CU2 + port map (CI=>co6_1, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_1, + NC0=>ircount_14, NC1=>ircount_15); + + r_gctr_8: CU2 + port map (CI=>co7_1, PC0=>rcount_16, PC1=>scuba_vlo, CO=>co8_1, + NC0=>ircount_16, NC1=>open); + + mux_8: MUX321 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, + D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, + D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, + D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, + D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, + D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, + D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, + D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, + D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, + D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(0)); + + mux_7: MUX321 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, + D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, + D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, + D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, + D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, + D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, + D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, + D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, + D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, + D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(1)); + + mux_6: MUX321 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, + D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, + D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, + D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, + D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, + D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, + D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, + D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, + D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, + D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(2)); + + mux_5: MUX321 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, + D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, + D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, + D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, + D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, + D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, + D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, + D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, + D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, + D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(3)); + + mux_4: MUX321 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, + D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, + D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, + D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, + D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, + D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, + D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, + D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, + D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, + D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(4)); + + mux_3: MUX321 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, + D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, + D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, + D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, + D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, + D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, + D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, + D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, + D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, + D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(5)); + + mux_2: MUX321 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, + D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, + D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, + D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, + D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, + D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, + D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, + D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, + D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, + D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(6)); + + mux_1: MUX321 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, + D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, + D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, + D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, + D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, + D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, + D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, + D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, + D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, + D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(7)); + + mux_0: MUX321 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, + D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, + D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, + D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, + D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, + D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, + D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, + D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, + D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, + D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(8)); + + precin_inst820: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, + S1=>open); + + wfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, + B1=>rcount_w0, BI=>precin, BOUT=>co0_2, S0=>open, + S1=>wfill_sub_0); + + wfill_1: FSUB2B + port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w1, B1=>rcount_w2, + BI=>co0_2, BOUT=>co1_2, S0=>wfill_sub_1, S1=>wfill_sub_2); + + wfill_2: FSUB2B + port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w3, B1=>rcount_w4, + BI=>co1_2, BOUT=>co2_2, S0=>wfill_sub_3, S1=>wfill_sub_4); + + wfill_3: FSUB2B + port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w5, B1=>rcount_w6, + BI=>co2_2, BOUT=>co3_2, S0=>wfill_sub_5, S1=>wfill_sub_6); + + wfill_4: FSUB2B + port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w7, B1=>rcount_w8, + BI=>co3_2, BOUT=>co4_2, S0=>wfill_sub_7, S1=>wfill_sub_8); + + wfill_5: FSUB2B + port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w9, B1=>rcount_w10, + BI=>co4_2, BOUT=>co5_2, S0=>wfill_sub_9, S1=>wfill_sub_10); + + wfill_6: FSUB2B + port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w11, + B1=>rcount_w12, BI=>co5_2, BOUT=>co6_2, S0=>wfill_sub_11, + S1=>wfill_sub_12); + + wfill_7: FSUB2B + port map (A0=>wptr_13, A1=>wptr_14, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w14, BI=>co6_2, BOUT=>co7_2, S0=>wfill_sub_13, + S1=>wfill_sub_14); + + wfill_8: FSUB2B + port map (A0=>wptr_15, A1=>wfill_sub_msb, B0=>rcount_w15, + B1=>scuba_vlo, BI=>co7_2, BOUT=>co8_2, S0=>wfill_sub_15, + S1=>wfill_sub_16); + + wfilld: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co8_2, COUT=>open, S0=>co8_2d, S1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_3); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_3, GE=>co1_3); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_3, GE=>co2_3); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_3, GE=>co3_3); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>wcount_r9, CI=>co3_3, GE=>co4_3); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r10, + B1=>wcount_r11, CI=>co4_3, GE=>co5_3); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r12, + B1=>w_g2b_xor_cluster_0, CI=>co5_3, GE=>co6_3); + + empty_cmp_7: AGEB2 + port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r14, + B1=>wcount_r15, CI=>co6_3, GE=>co7_3); + + empty_cmp_8: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co7_3, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_4); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_4, GE=>co1_4); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_4, GE=>co2_4); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_4, GE=>co3_4); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_4, GE=>co4_4); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_4, GE=>co5_4); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, CI=>co5_4, GE=>co6_4); + + full_cmp_7: AGEB2 + port map (A0=>wcount_14, A1=>wcount_15, B0=>rcount_w14, + B1=>rcount_w15, CI=>co6_4, GE=>co7_4); + + full_cmp_8: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co7_4, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + af_set_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, + S1=>open); + + af_set_ctr_0: CU2 + port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, + PC1=>af_setcount_1, CO=>co0_5, NC0=>iaf_setcount_0, + NC1=>iaf_setcount_1); + + af_set_ctr_1: CU2 + port map (CI=>co0_5, PC0=>af_setcount_2, PC1=>af_setcount_3, + CO=>co1_5, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); + + af_set_ctr_2: CU2 + port map (CI=>co1_5, PC0=>af_setcount_4, PC1=>af_setcount_5, + CO=>co2_5, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5); + + af_set_ctr_3: CU2 + port map (CI=>co2_5, PC0=>af_setcount_6, PC1=>af_setcount_7, + CO=>co3_5, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7); + + af_set_ctr_4: CU2 + port map (CI=>co3_5, PC0=>af_setcount_8, PC1=>af_setcount_9, + CO=>co4_5, NC0=>iaf_setcount_8, NC1=>iaf_setcount_9); + + af_set_ctr_5: CU2 + port map (CI=>co4_5, PC0=>af_setcount_10, PC1=>af_setcount_11, + CO=>co5_5, NC0=>iaf_setcount_10, NC1=>iaf_setcount_11); + + af_set_ctr_6: CU2 + port map (CI=>co5_5, PC0=>af_setcount_12, PC1=>af_setcount_13, + CO=>co6_5, NC0=>iaf_setcount_12, NC1=>iaf_setcount_13); + + af_set_ctr_7: CU2 + port map (CI=>co6_5, PC0=>af_setcount_14, PC1=>af_setcount_15, + CO=>co7_5, NC0=>iaf_setcount_14, NC1=>iaf_setcount_15); + + af_set_ctr_8: CU2 + port map (CI=>co7_5, PC0=>af_setcount_16, PC1=>scuba_vlo, + CO=>co8_3, NC0=>iaf_setcount_16, NC1=>open); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_6); + + af_set_cmp_1: AGEB2 + port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_6, GE=>co1_6); + + af_set_cmp_2: AGEB2 + port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_6, GE=>co2_6); + + af_set_cmp_3: AGEB2 + port map (A0=>af_setcount_6, A1=>af_setcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_6, GE=>co3_6); + + af_set_cmp_4: AGEB2 + port map (A0=>af_setcount_8, A1=>af_setcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_6, GE=>co4_6); + + af_set_cmp_5: AGEB2 + port map (A0=>af_setcount_10, A1=>af_setcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_6, GE=>co5_6); + + af_set_cmp_6: AGEB2 + port map (A0=>af_setcount_12, A1=>af_setcount_13, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, CI=>co5_6, GE=>co6_6); + + af_set_cmp_7: AGEB2 + port map (A0=>af_setcount_14, A1=>af_setcount_15, B0=>rcount_w14, + B1=>rcount_w15, CI=>co6_6, GE=>co7_6); + + af_set_cmp_8: AGEB2 + port map (A0=>af_set_cmp_set, A1=>scuba_vlo, B0=>af_set_cmp_clr, + B1=>scuba_vlo, CI=>co7_6, GE=>af_set_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_clr_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_clr_ctr_ci, S0=>open, + S1=>open); + + af_clr_ctr_0: CU2 + port map (CI=>af_clr_ctr_ci, PC0=>af_clrcount_0, + PC1=>af_clrcount_1, CO=>co0_7, NC0=>iaf_clrcount_0, + NC1=>iaf_clrcount_1); + + af_clr_ctr_1: CU2 + port map (CI=>co0_7, PC0=>af_clrcount_2, PC1=>af_clrcount_3, + CO=>co1_7, NC0=>iaf_clrcount_2, NC1=>iaf_clrcount_3); + + af_clr_ctr_2: CU2 + port map (CI=>co1_7, PC0=>af_clrcount_4, PC1=>af_clrcount_5, + CO=>co2_7, NC0=>iaf_clrcount_4, NC1=>iaf_clrcount_5); + + af_clr_ctr_3: CU2 + port map (CI=>co2_7, PC0=>af_clrcount_6, PC1=>af_clrcount_7, + CO=>co3_7, NC0=>iaf_clrcount_6, NC1=>iaf_clrcount_7); + + af_clr_ctr_4: CU2 + port map (CI=>co3_7, PC0=>af_clrcount_8, PC1=>af_clrcount_9, + CO=>co4_7, NC0=>iaf_clrcount_8, NC1=>iaf_clrcount_9); + + af_clr_ctr_5: CU2 + port map (CI=>co4_7, PC0=>af_clrcount_10, PC1=>af_clrcount_11, + CO=>co5_7, NC0=>iaf_clrcount_10, NC1=>iaf_clrcount_11); + + af_clr_ctr_6: CU2 + port map (CI=>co5_7, PC0=>af_clrcount_12, PC1=>af_clrcount_13, + CO=>co6_7, NC0=>iaf_clrcount_12, NC1=>iaf_clrcount_13); + + af_clr_ctr_7: CU2 + port map (CI=>co6_7, PC0=>af_clrcount_14, PC1=>af_clrcount_15, + CO=>co7_7, NC0=>iaf_clrcount_14, NC1=>iaf_clrcount_15); + + af_clr_ctr_8: CU2 + port map (CI=>co7_7, PC0=>af_clrcount_16, PC1=>scuba_vlo, + CO=>co8_4, NC0=>iaf_clrcount_16, NC1=>open); + + af_clr_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); + + af_clr_cmp_0: AGEB2 + port map (A0=>af_clrcount_0, A1=>af_clrcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_3, GE=>co0_8); + + af_clr_cmp_1: AGEB2 + port map (A0=>af_clrcount_2, A1=>af_clrcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_8, GE=>co1_8); + + af_clr_cmp_2: AGEB2 + port map (A0=>af_clrcount_4, A1=>af_clrcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_8, GE=>co2_8); + + af_clr_cmp_3: AGEB2 + port map (A0=>af_clrcount_6, A1=>af_clrcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_8, GE=>co3_8); + + af_clr_cmp_4: AGEB2 + port map (A0=>af_clrcount_8, A1=>af_clrcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_8, GE=>co4_8); + + af_clr_cmp_5: AGEB2 + port map (A0=>af_clrcount_10, A1=>af_clrcount_11, B0=>rcount_w10, + B1=>rcount_w11, CI=>co4_8, GE=>co5_8); + + af_clr_cmp_6: AGEB2 + port map (A0=>af_clrcount_12, A1=>af_clrcount_13, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, CI=>co5_8, GE=>co6_8); + + af_clr_cmp_7: AGEB2 + port map (A0=>af_clrcount_14, A1=>af_clrcount_15, B0=>rcount_w14, + B1=>rcount_w15, CI=>co6_8, GE=>co7_8); + + af_clr_cmp_8: AGEB2 + port map (A0=>af_clr_cmp_set, A1=>scuba_vlo, B0=>af_clr_cmp_clr, + B1=>scuba_vlo, CI=>co7_8, GE=>af_clr_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a3: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_clr_c, COUT=>open, S0=>af_clr, + S1=>open); + + Empty <= empty_i; + Full <= full_i; + AlmostFull <= af; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_64kx9_af_cnt is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX321 use entity ecp3.MUX321(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.lpc b/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.lpc new file mode 100644 index 0000000..699e5fa --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.8 +ModuleName=fifo_8kx9_af_cnt +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=09/08/2015 +Time=15:54:57 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=8192 +Width=9 +RDepth=8192 +RWidth=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=8100 +PeDeassert=8090 +FullFlg=1 +PfMode=Static - Dual Threshold +PfAssert=8100 +PfDeassert=8090 +RDataCount=0 +WDataCount=1 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_8kx9_af_cnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 13 -data_width 9 -num_words 8192 -rdata_width 9 -no_enable -pe -1 -pf 8100 -pf2 8090 -fill diff --git a/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd b/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd new file mode 100644 index 0000000..f8d626f --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd @@ -0,0 +1,2371 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.5.0.102 +-- Module Version: 5.8 +--/home/soft/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n fifo_8kx9_af_cnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 8192 -width 9 -depth 8192 -rdata_width 9 -no_enable -pe -1 -pf 8100 -pf2 8090 -fill + +-- Tue Sep 8 15:54:57 2015 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_8kx9_af_cnt is + port ( + Data: in std_logic_vector(8 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + WCNT: out std_logic_vector(13 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_8kx9_af_cnt; + +architecture Structure of fifo_8kx9_af_cnt is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal wptr_13: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_13: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal af: std_logic; + signal af_d: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co6: std_logic; + signal co5: std_logic; + signal wcount_13: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co6_1: std_logic; + signal co5_1: std_logic; + signal rcount_13: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal wfill_sub_0: std_logic; + signal precin: std_logic; + signal wptr_0: std_logic; + signal wfill_sub_1: std_logic; + signal wfill_sub_2: std_logic; + signal co0_2: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wfill_sub_3: std_logic; + signal wfill_sub_4: std_logic; + signal co1_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wfill_sub_5: std_logic; + signal wfill_sub_6: std_logic; + signal co2_2: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wfill_sub_7: std_logic; + signal wfill_sub_8: std_logic; + signal co3_2: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wfill_sub_9: std_logic; + signal wfill_sub_10: std_logic; + signal co4_2: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wfill_sub_11: std_logic; + signal wfill_sub_12: std_logic; + signal co5_2: std_logic; + signal wptr_11: std_logic; + signal wptr_12: std_logic; + signal wfill_sub_13: std_logic; + signal co6_2: std_logic; + signal wfill_sub_msb: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_3: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_3: std_logic; + signal wcount_r6: std_logic; + signal wcount_r7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_3: std_logic; + signal wcount_r8: std_logic; + signal wcount_r9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_3: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal wcount_r11: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_3: std_logic; + signal wcount_r12: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_12: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_4: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_4: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_4: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_4: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_4: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_4: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_12: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal iaf_setcount_0: std_logic; + signal iaf_setcount_1: std_logic; + signal af_set_ctr_ci: std_logic; + signal iaf_setcount_2: std_logic; + signal iaf_setcount_3: std_logic; + signal co0_5: std_logic; + signal iaf_setcount_4: std_logic; + signal iaf_setcount_5: std_logic; + signal co1_5: std_logic; + signal iaf_setcount_6: std_logic; + signal iaf_setcount_7: std_logic; + signal co2_5: std_logic; + signal iaf_setcount_8: std_logic; + signal iaf_setcount_9: std_logic; + signal co3_5: std_logic; + signal iaf_setcount_10: std_logic; + signal iaf_setcount_11: std_logic; + signal co4_5: std_logic; + signal iaf_setcount_12: std_logic; + signal iaf_setcount_13: std_logic; + signal co6_3: std_logic; + signal co5_5: std_logic; + signal af_setcount_13: std_logic; + signal cmp_ci_2: std_logic; + signal af_setcount_0: std_logic; + signal af_setcount_1: std_logic; + signal co0_6: std_logic; + signal af_setcount_2: std_logic; + signal af_setcount_3: std_logic; + signal co1_6: std_logic; + signal af_setcount_4: std_logic; + signal af_setcount_5: std_logic; + signal co2_6: std_logic; + signal af_setcount_6: std_logic; + signal af_setcount_7: std_logic; + signal co3_6: std_logic; + signal af_setcount_8: std_logic; + signal af_setcount_9: std_logic; + signal co4_6: std_logic; + signal af_setcount_10: std_logic; + signal af_setcount_11: std_logic; + signal co5_6: std_logic; + signal af_set_cmp_clr: std_logic; + signal af_setcount_12: std_logic; + signal af_set_cmp_set: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; + signal scuba_vhi: std_logic; + signal iaf_clrcount_0: std_logic; + signal iaf_clrcount_1: std_logic; + signal af_clr_ctr_ci: std_logic; + signal iaf_clrcount_2: std_logic; + signal iaf_clrcount_3: std_logic; + signal co0_7: std_logic; + signal iaf_clrcount_4: std_logic; + signal iaf_clrcount_5: std_logic; + signal co1_7: std_logic; + signal iaf_clrcount_6: std_logic; + signal iaf_clrcount_7: std_logic; + signal co2_7: std_logic; + signal iaf_clrcount_8: std_logic; + signal iaf_clrcount_9: std_logic; + signal co3_7: std_logic; + signal iaf_clrcount_10: std_logic; + signal iaf_clrcount_11: std_logic; + signal co4_7: std_logic; + signal iaf_clrcount_12: std_logic; + signal iaf_clrcount_13: std_logic; + signal co6_4: std_logic; + signal co5_7: std_logic; + signal af_clrcount_13: std_logic; + signal wren_i: std_logic; + signal cmp_ci_3: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal af_clrcount_0: std_logic; + signal af_clrcount_1: std_logic; + signal co0_8: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal af_clrcount_2: std_logic; + signal af_clrcount_3: std_logic; + signal co1_8: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal af_clrcount_4: std_logic; + signal af_clrcount_5: std_logic; + signal co2_8: std_logic; + signal rcount_w6: std_logic; + signal rcount_w7: std_logic; + signal af_clrcount_6: std_logic; + signal af_clrcount_7: std_logic; + signal co3_8: std_logic; + signal rcount_w8: std_logic; + signal rcount_w9: std_logic; + signal af_clrcount_8: std_logic; + signal af_clrcount_9: std_logic; + signal co4_8: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w11: std_logic; + signal af_clrcount_10: std_logic; + signal af_clrcount_11: std_logic; + signal co5_8: std_logic; + signal rcount_w12: std_logic; + signal af_clr_cmp_clr: std_logic; + signal af_clrcount_12: std_logic; + signal af_clr_cmp_set: std_logic; + signal af_clr: std_logic; + signal af_clr_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX41 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; SD1: in std_logic; SD2: in std_logic; + Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_3 : label is "fifo_8kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_3 : label is ""; + attribute RESETMODE of pdp_ram_0_0_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_1_0_2 : label is "fifo_8kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_2 : label is ""; + attribute RESETMODE of pdp_ram_1_0_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_2_0_1 : label is "fifo_8kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_1 : label is ""; + attribute RESETMODE of pdp_ram_2_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_3_0_0 : label is "fifo_8kx9_af_cnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_0 : label is ""; + attribute RESETMODE of pdp_ram_3_0_0 : label is "SYNC"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t29: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t28: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t27: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t26: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t25: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t24: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t23: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t22: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t21: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t20: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t19: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t18: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t17: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t16: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t15: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t14: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t13: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t12: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t11: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t10: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t9: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t8: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t7: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t6: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t5: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t4: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t3: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t2: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t1: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + LUT4_42: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>w_gcount_r213, + DO0=>w_g2b_xor_cluster_0); + + LUT4_41: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_gcount_r29, + DO0=>w_g2b_xor_cluster_1); + + LUT4_40: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>w_gcount_r25, + DO0=>w_g2b_xor_cluster_2); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r12); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>scuba_vlo, DO0=>wcount_r11); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>wcount_r12, DO0=>wcount_r9); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r7); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r6); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r24, AD0=>w_gcount_r25, DO0=>wcount_r4); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r21, DO0=>wcount_r1); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r0); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_gcount_w213, + DO0=>r_g2b_xor_cluster_0); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>r_gcount_w29, + DO0=>r_g2b_xor_cluster_1); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>r_gcount_w25, + DO0=>r_g2b_xor_cluster_2); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w12); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>scuba_vlo, DO0=>rcount_w11); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>rcount_w12, DO0=>rcount_w9); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>rcount_w11, DO0=>rcount_w8); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w7); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w25, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w24, AD0=>r_gcount_w25, DO0=>rcount_w4); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w21, DO0=>rcount_w1); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w0); + + XOR2_t0: XOR2 + port map (A=>wptr_13, B=>r_gcount_w213, Z=>wfill_sub_msb); + + LUT4_8: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_13, AD2=>rcount_13, AD1=>w_gcount_r213, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_7: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_13, AD2=>rcount_13, AD1=>w_gcount_r213, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_6: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_13, AD2=>wcount_13, AD1=>r_gcount_w213, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_5: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_13, AD2=>wcount_13, AD1=>r_gcount_w213, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + LUT4_4: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_setcount_13, AD2=>wcount_13, + AD1=>r_gcount_w213, AD0=>wptr_13, DO0=>af_set_cmp_set); + + LUT4_3: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_setcount_13, AD2=>wcount_13, + AD1=>r_gcount_w213, AD0=>wptr_13, DO0=>af_set_cmp_clr); + + LUT4_2: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_clrcount_13, AD2=>wcount_13, + AD1=>r_gcount_w213, AD0=>wptr_13, DO0=>af_clr_cmp_set); + + LUT4_1: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_clrcount_13, AD2=>wcount_13, + AD1=>r_gcount_w213, AD0=>wptr_13, DO0=>af_clr_cmp_clr); + + LUT4_0: ROM16X1A + generic map (initval=> X"4450") + port map (AD3=>af, AD2=>af_set, AD1=>af_clr, AD0=>scuba_vlo, + DO0=>af_d); + + pdp_ram_0_0_3: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1, + DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4, + DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7, + DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_1_0_2: DP16KC + generic map (CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1, + DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4, + DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7, + DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_2_0_1: DP16KC + generic map (CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1, + DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4, + DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7, + DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_3_0_0: DP16KC + generic map (CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>RdClock, OCEB=>rden_i, + WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1, + DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4, + DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7, + DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_186: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_185: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_184: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_183: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_182: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_181: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_180: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_179: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_178: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_177: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_176: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_175: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_174: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_173: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_172: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_171: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_170: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_169: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_168: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_167: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_166: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_165: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_164: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_163: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_162: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_161: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_160: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_159: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_158: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_157: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_156: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_155: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_154: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_153: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_152: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_151: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_150: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_149: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_148: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_147: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_146: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_145: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_144: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_143: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_142: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_141: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_140: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_139: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_138: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_137: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_136: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_135: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_134: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_133: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_132: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_131: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_130: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_129: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_128: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_127: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_126: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_125: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_124: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_123: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_122: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_121: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_120: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_119: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_118: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_117: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_116: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_115: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_114: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_113: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_112: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_111: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_110: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_109: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_108: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_107: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_106: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_105: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_104: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_103: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_102: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_101: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_100: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_99: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_98: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_97: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_96: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_95: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_94: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_93: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_92: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_91: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_90: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_89: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_88: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_87: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_86: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_85: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_84: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_83: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_82: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_81: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_80: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_79: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_78: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_77: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_76: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_75: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_74: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_73: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_72: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_71: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_70: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_69: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_68: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_67: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_66: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_65: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_64: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_63: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_62: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_61: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_60: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_59: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_58: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_57: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_56: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_55: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_54: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_53: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_52: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_51: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_50: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_49: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_48: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_47: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_46: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_45: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_44: FD1S3DX + port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); + + FF_43: FD1S3DX + port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); + + FF_42: FD1S3DX + port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); + + FF_41: FD1S3DX + port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); + + FF_40: FD1S3DX + port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); + + FF_39: FD1S3DX + port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); + + FF_38: FD1S3DX + port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); + + FF_37: FD1S3DX + port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); + + FF_36: FD1S3DX + port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); + + FF_35: FD1S3DX + port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); + + FF_34: FD1S3DX + port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); + + FF_33: FD1S3DX + port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); + + FF_32: FD1S3DX + port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); + + FF_31: FD1S3DX + port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); + + FF_30: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_29: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_28: FD1P3BX + port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_0); + + FF_27: FD1P3DX + port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_1); + + FF_26: FD1P3BX + port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_2); + + FF_25: FD1P3BX + port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_3); + + FF_24: FD1P3BX + port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_4); + + FF_23: FD1P3DX + port map (D=>iaf_setcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_5); + + FF_22: FD1P3BX + port map (D=>iaf_setcount_6, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_6); + + FF_21: FD1P3DX + port map (D=>iaf_setcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_7); + + FF_20: FD1P3DX + port map (D=>iaf_setcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_8); + + FF_19: FD1P3DX + port map (D=>iaf_setcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_9); + + FF_18: FD1P3DX + port map (D=>iaf_setcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_10); + + FF_17: FD1P3DX + port map (D=>iaf_setcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_11); + + FF_16: FD1P3DX + port map (D=>iaf_setcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_12); + + FF_15: FD1P3DX + port map (D=>iaf_setcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_13); + + FF_14: FD1P3BX + port map (D=>iaf_clrcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_0); + + FF_13: FD1P3BX + port map (D=>iaf_clrcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_1); + + FF_12: FD1P3BX + port map (D=>iaf_clrcount_2, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_2); + + FF_11: FD1P3DX + port map (D=>iaf_clrcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_3); + + FF_10: FD1P3DX + port map (D=>iaf_clrcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_4); + + FF_9: FD1P3BX + port map (D=>iaf_clrcount_5, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_5); + + FF_8: FD1P3BX + port map (D=>iaf_clrcount_6, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_clrcount_6); + + FF_7: FD1P3DX + port map (D=>iaf_clrcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_7); + + FF_6: FD1P3DX + port map (D=>iaf_clrcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_8); + + FF_5: FD1P3DX + port map (D=>iaf_clrcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_9); + + FF_4: FD1P3DX + port map (D=>iaf_clrcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_10); + + FF_3: FD1P3DX + port map (D=>iaf_clrcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_11); + + FF_2: FD1P3DX + port map (D=>iaf_clrcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_12); + + FF_1: FD1P3DX + port map (D=>iaf_clrcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_clrcount_13); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>af); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_gctr_4: CU2 + port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_gctr_5: CU2 + port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5, + NC0=>iwcount_10, NC1=>iwcount_11); + + w_gctr_6: CU2 + port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6, + NC0=>iwcount_12, NC1=>iwcount_13); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1, + NC0=>ircount_6, NC1=>ircount_7); + + r_gctr_4: CU2 + port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1, + NC0=>ircount_8, NC1=>ircount_9); + + r_gctr_5: CU2 + port map (CI=>co4_1, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_1, + NC0=>ircount_10, NC1=>ircount_11); + + r_gctr_6: CU2 + port map (CI=>co5_1, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_1, + NC0=>ircount_12, NC1=>ircount_13); + + mux_8: MUX41 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(0)); + + mux_7: MUX41 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(1)); + + mux_6: MUX41 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(2)); + + mux_5: MUX41 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(3)); + + mux_4: MUX41 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(4)); + + mux_3: MUX41 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(5)); + + mux_2: MUX41 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(6)); + + mux_1: MUX41 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(7)); + + mux_0: MUX41 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(8)); + + precin_inst353: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, + S1=>open); + + wfill_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, + B1=>rcount_w0, BI=>precin, BOUT=>co0_2, S0=>open, + S1=>wfill_sub_0); + + wfill_1: FSUB2B + port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w1, B1=>rcount_w2, + BI=>co0_2, BOUT=>co1_2, S0=>wfill_sub_1, S1=>wfill_sub_2); + + wfill_2: FSUB2B + port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w3, B1=>rcount_w4, + BI=>co1_2, BOUT=>co2_2, S0=>wfill_sub_3, S1=>wfill_sub_4); + + wfill_3: FSUB2B + port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w5, B1=>rcount_w6, + BI=>co2_2, BOUT=>co3_2, S0=>wfill_sub_5, S1=>wfill_sub_6); + + wfill_4: FSUB2B + port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w7, B1=>rcount_w8, + BI=>co3_2, BOUT=>co4_2, S0=>wfill_sub_7, S1=>wfill_sub_8); + + wfill_5: FSUB2B + port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w9, + B1=>r_g2b_xor_cluster_0, BI=>co4_2, BOUT=>co5_2, + S0=>wfill_sub_9, S1=>wfill_sub_10); + + wfill_6: FSUB2B + port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w11, + B1=>rcount_w12, BI=>co5_2, BOUT=>co6_2, S0=>wfill_sub_11, + S1=>wfill_sub_12); + + wfill_7: FSUB2B + port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co6_2, BOUT=>open, S0=>wfill_sub_13, + S1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_3); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_3, GE=>co1_3); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_3, GE=>co2_3); + + empty_cmp_3: AGEB2 + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r6, + B1=>wcount_r7, CI=>co2_3, GE=>co3_3); + + empty_cmp_4: AGEB2 + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r8, + B1=>wcount_r9, CI=>co3_3, GE=>co4_3); + + empty_cmp_5: AGEB2 + port map (A0=>rcount_10, A1=>rcount_11, B0=>w_g2b_xor_cluster_0, + B1=>wcount_r11, CI=>co4_3, GE=>co5_3); + + empty_cmp_6: AGEB2 + port map (A0=>rcount_12, A1=>empty_cmp_set, B0=>wcount_r12, + B1=>empty_cmp_clr, CI=>co5_3, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_4); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_4, GE=>co1_4); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_4, GE=>co2_4); + + full_cmp_3: AGEB2 + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_4, GE=>co3_4); + + full_cmp_4: AGEB2 + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_4, GE=>co4_4); + + full_cmp_5: AGEB2 + port map (A0=>wcount_10, A1=>wcount_11, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w11, CI=>co4_4, GE=>co5_4); + + full_cmp_6: AGEB2 + port map (A0=>wcount_12, A1=>full_cmp_set, B0=>rcount_w12, + B1=>full_cmp_clr, CI=>co5_4, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + af_set_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, + S1=>open); + + af_set_ctr_0: CU2 + port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, + PC1=>af_setcount_1, CO=>co0_5, NC0=>iaf_setcount_0, + NC1=>iaf_setcount_1); + + af_set_ctr_1: CU2 + port map (CI=>co0_5, PC0=>af_setcount_2, PC1=>af_setcount_3, + CO=>co1_5, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); + + af_set_ctr_2: CU2 + port map (CI=>co1_5, PC0=>af_setcount_4, PC1=>af_setcount_5, + CO=>co2_5, NC0=>iaf_setcount_4, NC1=>iaf_setcount_5); + + af_set_ctr_3: CU2 + port map (CI=>co2_5, PC0=>af_setcount_6, PC1=>af_setcount_7, + CO=>co3_5, NC0=>iaf_setcount_6, NC1=>iaf_setcount_7); + + af_set_ctr_4: CU2 + port map (CI=>co3_5, PC0=>af_setcount_8, PC1=>af_setcount_9, + CO=>co4_5, NC0=>iaf_setcount_8, NC1=>iaf_setcount_9); + + af_set_ctr_5: CU2 + port map (CI=>co4_5, PC0=>af_setcount_10, PC1=>af_setcount_11, + CO=>co5_5, NC0=>iaf_setcount_10, NC1=>iaf_setcount_11); + + af_set_ctr_6: CU2 + port map (CI=>co5_5, PC0=>af_setcount_12, PC1=>af_setcount_13, + CO=>co6_3, NC0=>iaf_setcount_12, NC1=>iaf_setcount_13); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_2, GE=>co0_6); + + af_set_cmp_1: AGEB2 + port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_6, GE=>co1_6); + + af_set_cmp_2: AGEB2 + port map (A0=>af_setcount_4, A1=>af_setcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_6, GE=>co2_6); + + af_set_cmp_3: AGEB2 + port map (A0=>af_setcount_6, A1=>af_setcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_6, GE=>co3_6); + + af_set_cmp_4: AGEB2 + port map (A0=>af_setcount_8, A1=>af_setcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_6, GE=>co4_6); + + af_set_cmp_5: AGEB2 + port map (A0=>af_setcount_10, A1=>af_setcount_11, + B0=>r_g2b_xor_cluster_0, B1=>rcount_w11, CI=>co4_6, + GE=>co5_6); + + af_set_cmp_6: AGEB2 + port map (A0=>af_setcount_12, A1=>af_set_cmp_set, B0=>rcount_w12, + B1=>af_set_cmp_clr, CI=>co5_6, GE=>af_set_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_clr_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_clr_ctr_ci, S0=>open, + S1=>open); + + af_clr_ctr_0: CU2 + port map (CI=>af_clr_ctr_ci, PC0=>af_clrcount_0, + PC1=>af_clrcount_1, CO=>co0_7, NC0=>iaf_clrcount_0, + NC1=>iaf_clrcount_1); + + af_clr_ctr_1: CU2 + port map (CI=>co0_7, PC0=>af_clrcount_2, PC1=>af_clrcount_3, + CO=>co1_7, NC0=>iaf_clrcount_2, NC1=>iaf_clrcount_3); + + af_clr_ctr_2: CU2 + port map (CI=>co1_7, PC0=>af_clrcount_4, PC1=>af_clrcount_5, + CO=>co2_7, NC0=>iaf_clrcount_4, NC1=>iaf_clrcount_5); + + af_clr_ctr_3: CU2 + port map (CI=>co2_7, PC0=>af_clrcount_6, PC1=>af_clrcount_7, + CO=>co3_7, NC0=>iaf_clrcount_6, NC1=>iaf_clrcount_7); + + af_clr_ctr_4: CU2 + port map (CI=>co3_7, PC0=>af_clrcount_8, PC1=>af_clrcount_9, + CO=>co4_7, NC0=>iaf_clrcount_8, NC1=>iaf_clrcount_9); + + af_clr_ctr_5: CU2 + port map (CI=>co4_7, PC0=>af_clrcount_10, PC1=>af_clrcount_11, + CO=>co5_7, NC0=>iaf_clrcount_10, NC1=>iaf_clrcount_11); + + af_clr_ctr_6: CU2 + port map (CI=>co5_7, PC0=>af_clrcount_12, PC1=>af_clrcount_13, + CO=>co6_4, NC0=>iaf_clrcount_12, NC1=>iaf_clrcount_13); + + af_clr_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); + + af_clr_cmp_0: AGEB2 + port map (A0=>af_clrcount_0, A1=>af_clrcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_3, GE=>co0_8); + + af_clr_cmp_1: AGEB2 + port map (A0=>af_clrcount_2, A1=>af_clrcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_8, GE=>co1_8); + + af_clr_cmp_2: AGEB2 + port map (A0=>af_clrcount_4, A1=>af_clrcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_8, GE=>co2_8); + + af_clr_cmp_3: AGEB2 + port map (A0=>af_clrcount_6, A1=>af_clrcount_7, B0=>rcount_w6, + B1=>rcount_w7, CI=>co2_8, GE=>co3_8); + + af_clr_cmp_4: AGEB2 + port map (A0=>af_clrcount_8, A1=>af_clrcount_9, B0=>rcount_w8, + B1=>rcount_w9, CI=>co3_8, GE=>co4_8); + + af_clr_cmp_5: AGEB2 + port map (A0=>af_clrcount_10, A1=>af_clrcount_11, + B0=>r_g2b_xor_cluster_0, B1=>rcount_w11, CI=>co4_8, + GE=>co5_8); + + af_clr_cmp_6: AGEB2 + port map (A0=>af_clrcount_12, A1=>af_clr_cmp_set, B0=>rcount_w12, + B1=>af_clr_cmp_clr, CI=>co5_8, GE=>af_clr_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a3: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_clr_c, COUT=>open, S0=>af_clr, + S1=>open); + + Empty <= empty_i; + Full <= full_i; + AlmostFull <= af; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_8kx9_af_cnt is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX41 use entity ecp3.MUX41(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd index eeadc34..6e587e4 100644 --- a/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd +++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd @@ -200,6 +200,7 @@ wait_value <= x"2000_0000" when DO_SIMULATION = 0 else x"0000_0010"; MAIN_MACHINE : process(main_current_state, DHCP_START_IN, construct_current_state, wait_ctr, receive_current_state, PS_DATA_IN, wait_value) begin + state2 <= x"0"; case (main_current_state) is @@ -212,6 +213,7 @@ begin end if; when DELAY => + state2 <= x"2"; if (wait_ctr = wait_value) then main_next_state <= SENDING_DISCOVER; else @@ -219,7 +221,7 @@ begin end if; when SENDING_DISCOVER => - state2 <= x"2"; + state2 <= x"3"; if (construct_current_state = CLEANUP) then main_next_state <= WAITING_FOR_OFFER; else @@ -227,7 +229,7 @@ begin end if; when WAITING_FOR_OFFER => - state2 <= x"3"; + state2 <= x"4"; if (receive_current_state = SAVE_VALUES) and (PS_DATA_IN(8) = '1') then main_next_state <= SENDING_REQUEST; elsif (wait_ctr = x"2000_0000") then @@ -237,7 +239,7 @@ begin end if; when SENDING_REQUEST => - state2 <= x"4"; + state2 <= x"5"; if (construct_current_state = CLEANUP) then main_next_state <= WAITING_FOR_ACK; else @@ -245,7 +247,7 @@ begin end if; when WAITING_FOR_ACK => - state2 <= x"5"; + state2 <= x"6"; if (receive_current_state = SAVE_VALUES) and (PS_DATA_IN(8) = '1') then main_next_state <= ESTABLISHED; elsif (wait_ctr = x"2000_0000") then @@ -255,12 +257,14 @@ begin end if; when ESTABLISHED => - state2 <= x"6"; + state2 <= x"7"; -- if (wait_ctr = x"2000_0000") then -- main_next_state <= SENDING_DISCOVER; -- else main_next_state <= ESTABLISHED; -- end if; + + when others => main_next_state <= BOOTING; end case; @@ -297,6 +301,8 @@ end process RECEIVE_MACHINE_PROC; RECEIVE_MACHINE : process(receive_current_state, main_current_state, bootp_hdr, saved_dhcp_type, saved_transaction_id, PS_DATA_IN, PS_DEST_MAC_ADDRESS_IN, MY_MAC_IN, PS_ACTIVATE_IN, PS_WR_EN_IN, save_ctr) begin + state3 <= x"0"; + case receive_current_state is when IDLE => @@ -343,6 +349,8 @@ begin when CLEANUP => state3 <= x"4"; receive_next_state <= IDLE; + + when others => receive_next_state <= IDLE; end case; @@ -486,6 +494,8 @@ end process CONSTRUCT_MACHINE_PROC; CONSTRUCT_MACHINE : process(construct_current_state, main_current_state, load_ctr, PS_SELECTED_IN) begin + state <= x"0"; + case construct_current_state is when IDLE => @@ -514,7 +524,7 @@ begin end if; when CLIENT_IP => - state <= x"5"; + state <= x"4"; if (load_ctr = 15) then construct_next_state <= YOUR_IP; else @@ -522,7 +532,7 @@ begin end if; when YOUR_IP => - state <= x"b"; + state <= x"5"; if (load_ctr = 19) then construct_next_state <= ZEROS1; else @@ -530,7 +540,7 @@ begin end if; when ZEROS1 => - state <= x"c"; + state <= x"6"; if (load_ctr = 27) then construct_next_state <= MY_MAC; else @@ -538,7 +548,7 @@ begin end if; when MY_MAC => - state <= x"6"; + state <= x"7"; if (load_ctr = 33) then construct_next_state <= ZEROS2; else @@ -546,7 +556,7 @@ begin end if; when ZEROS2 => - state <= x"7"; + state <= x"8"; if (load_ctr = 235) then construct_next_state <= VENDOR_VALS; else @@ -554,7 +564,7 @@ begin end if; when VENDOR_VALS => - state <= x"8"; + state <= x"9"; if (load_ctr = 257) then -- for discover it's enough of values if (main_current_state = SENDING_DISCOVER) then @@ -568,7 +578,7 @@ begin end if; when VENDOR_VALS2 => - state <= x"d"; + state <= x"a"; if (load_ctr = 263) then construct_next_state <= TERMINATION; else @@ -576,12 +586,14 @@ begin end if; when TERMINATION => - state <= x"e"; + state <= x"b"; construct_next_state <= CLEANUP; when CLEANUP => - state <= x"9"; + state <= x"c"; construct_next_state <= IDLE; + + when others => construct_next_state <= IDLE; end case; end process CONSTRUCT_MACHINE; @@ -814,9 +826,15 @@ end process SENT_FRAMES_PROC; -- **** debug ---DEBUG_OUT(3 downto 0) <= state; ---DEBUG_OUT(7 downto 4) <= state2; ---DEBUG_OUT(11 downto 8) <= state3; +process(CLK) +begin + if rising_edge(CLK) then + DEBUG_OUT(3 downto 0) <= state; + DEBUG_OUT(7 downto 4) <= state2; + DEBUG_OUT(11 downto 8) <= state3; + end if; +end process; + --DEBUG_OUT(15 downto 12) <= (others => '0'); --DEBUG_OUT(31 downto 16) <= discarded_ctr; -- diff --git a/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd b/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd index 5f6f95a..667d141 100644 --- a/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd +++ b/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd @@ -156,11 +156,13 @@ attribute syn_preserve of rx_fifo_wr, rx_fifo_rd, gsc_init_dataready, tx_fifo_wr signal hist_inst : hist_array; signal reset_all_hist : std_logic_vector(31 downto 0); +signal rx_cnt, tx_cnt : std_logic_vector(15 downto 0); + begin MAKE_RESET_OUT <= make_reset; -receive_fifo : fifo_2048x8x16 +receive_fifo : entity work.fifo_2kx9x18_wcnt PORT map( Reset => RESET, RPReset => RESET, @@ -171,7 +173,8 @@ receive_fifo : fifo_2048x8x16 RdEn => rx_fifo_rd, Q => rx_fifo_q, Full => rx_full, - Empty => rx_empty + Empty => rx_empty, + WCNT => rx_cnt(11 downto 0) ); --TODO: change to synchronous @@ -326,7 +329,7 @@ begin end process PACKET_NUM_PROC; tf_4k_gen : if SLOWCTRL_BUFFER_SIZE = 1 generate - transmit_fifo : fifo_4kx18x9 + transmit_fifo : entity work.fifo_4kx18x9_wcnt PORT map( Reset => tx_fifo_reset, RPReset => tx_fifo_reset, @@ -337,12 +340,13 @@ tf_4k_gen : if SLOWCTRL_BUFFER_SIZE = 1 generate RdEn => tx_fifo_rd, Q => tx_fifo_q, Full => tx_full, - Empty => tx_empty + Empty => tx_empty, + WCNT => tx_cnt(11 downto 0) ); end generate tf_4k_gen; tf_65k_gen : if SLOWCTRL_BUFFER_SIZE = 2 generate - transmit_fifo : fifo_65536x18x9 + transmit_fifo : entity work.fifo_64kx18x9_wcnt PORT map( Reset => tx_fifo_reset, RPReset => tx_fifo_reset, @@ -353,7 +357,8 @@ tf_65k_gen : if SLOWCTRL_BUFFER_SIZE = 2 generate RdEn => tx_fifo_rd, Q => tx_fifo_q, Full => tx_full, - Empty => tx_empty + Empty => tx_empty, + WCNT => tx_cnt ); end generate tf_65k_gen; @@ -519,10 +524,12 @@ end process DISSECT_MACHINE_PROC; DISSECT_MACHINE : process(dissect_current_state, reset_detected, too_much_data, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, PS_SELECTED_IN, GSC_INIT_READ_IN, GSC_REPLY_DATAREADY_IN, tx_loaded_ctr, tx_data_ctr, rx_fifo_q, GSC_BUSY_IN) begin + state <= x"0"; + case dissect_current_state is when IDLE => - state <= x"0"; + state <= x"1"; if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then dissect_next_state <= READ_FRAME; else @@ -530,7 +537,7 @@ begin end if; when READ_FRAME => - state <= x"1"; + state <= x"2"; if (PS_DATA_IN(8) = '1') then dissect_next_state <= WAIT_FOR_HUB; else @@ -538,7 +545,7 @@ begin end if; when WAIT_FOR_HUB => - state <= x"2"; + state <= x"3"; if (GSC_INIT_READ_IN = '1') then dissect_next_state <= LOAD_TO_HUB; else @@ -546,7 +553,7 @@ begin end if; when LOAD_TO_HUB => - state <= x"3"; + state <= x"4"; if (rx_fifo_q(17) = '1') then if (reset_detected = '1') then dissect_next_state <= CLEANUP; @@ -558,7 +565,7 @@ begin end if; when WAIT_FOR_RESPONSE => - state <= x"4"; + state <= x"5"; if (GSC_REPLY_DATAREADY_IN = '1') then dissect_next_state <= SAVE_RESPONSE; else @@ -566,7 +573,7 @@ begin end if; when SAVE_RESPONSE => - state <= x"5"; + state <= x"6"; if (GSC_REPLY_DATAREADY_IN = '0' and GSC_BUSY_IN = '0') then if (too_much_data = '0') then dissect_next_state <= WAIT_FOR_LOAD; @@ -578,7 +585,7 @@ begin end if; when WAIT_FOR_LOAD => - state <= x"6"; + state <= x"7"; if (PS_SELECTED_IN = '1') then dissect_next_state <= LOAD_FRAME; else @@ -586,7 +593,7 @@ begin end if; when LOAD_FRAME => - state <= x"7"; + state <= x"8"; if (tx_loaded_ctr = tx_data_ctr) then dissect_next_state <= CLEANUP; else @@ -594,8 +601,10 @@ begin end if; when CLEANUP => - state <= x"8"; + state <= x"9"; dissect_next_state <= IDLE; + + when others => dissect_next_state <= IDLE; end case; end process DISSECT_MACHINE; @@ -671,11 +680,12 @@ begin DEBUG_OUT(2) <= tx_full; DEBUG_OUT(3) <= tx_empty; DEBUG_OUT(7 downto 4) <= state; + DEBUG_OUT(23 downto 8) <= rx_cnt; + DEBUG_OUT(39 downto 24) <= tx_cnt; + DEBUG_OUT(63 downto 40) <= (others => '0'); end if; end process; -DEBUG_OUT(63 downto 8) <= (others => '0'); - process(CLK) begin if rising_edge(CLK) then diff --git a/gbe_trb/testbenches/aa_full_wrapper_tb.vhd b/gbe_trb/testbenches/aa_full_wrapper_tb.vhd index e710131..a610f00 100644 --- a/gbe_trb/testbenches/aa_full_wrapper_tb.vhd +++ b/gbe_trb/testbenches/aa_full_wrapper_tb.vhd @@ -28,13 +28,13 @@ begin USE_INTERNAL_TRBNET_DUMMY => 0, USE_EXTERNAL_TRBNET_DUMMY => 1, RX_PATH_ENABLE => 1, - FIXED_SIZE_MODE => 1, - INCREMENTAL_MODE => 0, - FIXED_SIZE => 13750, + FIXED_SIZE_MODE => 0, + INCREMENTAL_MODE => 1, + FIXED_SIZE => 100, --13750, FIXED_DELAY_MODE => 1, - UP_DOWN_MODE => 0, - UP_DOWN_LIMIT => 100, - FIXED_DELAY => 200, + UP_DOWN_MODE => 1, + UP_DOWN_LIMIT => 1000, + FIXED_DELAY => 10, NUMBER_OF_GBE_LINKS => 4, LINKS_ACTIVE => "1111", LINK_HAS_PING => "1111", @@ -122,13 +122,14 @@ begin gsr_n <= '1'; wait for 20 us; + trigger <= '1'; - for i in 0 to 10000 loop - trigger <= '1'; - wait for 100 ns; - trigger <= '0'; - wait for 10 us; - end loop; +-- for i in 0 to 10000 loop +-- trigger <= '1'; +-- wait for 100 ns; +-- trigger <= '0'; +-- wait for 10 us; +-- end loop; wait; end process; diff --git a/gbe_trb/transcript b/gbe_trb/transcript new file mode 100644 index 0000000..b135899 Binary files /dev/null and b/gbe_trb/transcript differ diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index 25af82d..c6be94a 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -53,7 +53,7 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is -- Placer Directives attribute HGROUP : string; -- for whole architecture - attribute HGROUP of trb_net16_ibuf_arch : architecture is "IBUF_group"; + --attribute HGROUP of trb_net16_ibuf_arch : architecture is "IBUF_group"; signal fifo_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal fifo_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); diff --git a/trb_net16_ibuf2.vhd b/trb_net16_ibuf2.vhd index 1be3599..b66c7f4 100644 --- a/trb_net16_ibuf2.vhd +++ b/trb_net16_ibuf2.vhd @@ -51,7 +51,7 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is -- Placer Directives attribute HGROUP : string; -- for whole architecture - attribute HGROUP of trb_net16_ibuf_arch : architecture is "IBUF_group"; + --attribute HGROUP of trb_net16_ibuf_arch : architecture is "IBUF_group"; signal fifo_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal fifo_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 19950e2..63ba7b1 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -43,7 +43,7 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is -- Placer Directives attribute HGROUP : string; -- for whole architecture - attribute HGROUP of trb_net16_obuf_arch : architecture is "OBUF_group"; + --attribute HGROUP of trb_net16_obuf_arch : architecture is "OBUF_group"; attribute syn_hier : string; attribute syn_hier of trb_net16_obuf_arch : architecture is "flatten, firm"; attribute syn_sharing : string; diff --git a/trb_net16_obuf_nodata.vhd b/trb_net16_obuf_nodata.vhd index 10f6c5d..0734f65 100644 --- a/trb_net16_obuf_nodata.vhd +++ b/trb_net16_obuf_nodata.vhd @@ -45,7 +45,7 @@ architecture trb_net16_obuf_nodata_arch of trb_net16_obuf_nodata is -- Placer Directives attribute HGROUP : string; -- for whole architecture - attribute HGROUP of trb_net16_obuf_nodata_arch : architecture is "OBUF_group"; + --attribute HGROUP of trb_net16_obuf_nodata_arch : architecture is "OBUF_group"; begin SEND_BUFFER_SIZE_IN <= CTRL_BUFFER(3 downto 0);