From: hadeshyp <hadeshyp>
Date: Mon, 25 May 2009 16:34:17 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~450
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=affd75f305105f91e3b092d9c1afa83e39c18890;p=trbnet.git

*** empty log message ***
---

diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd
index b790fdc..d1e8edd 100644
--- a/trb_net16_regIO.vhd
+++ b/trb_net16_regIO.vhd
@@ -224,10 +224,14 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is
 begin
 
   pattern_gen_inst : trb_net_pattern_gen
+    generic map(
+      WIDTH => 5
+      )
     port map(
-      INPUT_IN   => address(5 downto 0),
-      RESULT_OUT => reg_enable_pattern
+      INPUT_IN   => address(4 downto 0),
+      RESULT_OUT => reg_enable_pattern(31 downto 0)
       );
+  reg_enable_pattern(63 downto 32) <= (others => '0');
 
   addresses : trb_net16_addresses
     generic map(
@@ -390,7 +394,7 @@ begin
         when ONE_WRITE =>  --wait for register address
           if API_TYP_IN = TYPE_DAT and API_PACKET_NUM_IN = c_F0 and API_DATAREADY_IN = '1' then
             next_address <= API_DATA_IN;
-            if or_all(API_DATA_IN(c_REGIO_ADDRESS_WIDTH-1 downto 8)) = '1' then  --data port address
+            if or_all(API_DATA_IN(15 downto 8)) = '1' then  --data port address
               if USE_DAT_PORT = c_YES then
                 next_state <= REG_WRITE;
               else
@@ -423,9 +427,11 @@ begin
                 next_Reg_low <= API_DATA_IN;
                 if or_all(address(15 downto 8)) = '0' then
                   if address(7 downto 6) = "11" then
-                    next_REGISTERS_OUT_write_enable <= reg_enable_pattern(2**NUM_CTRL_REGS-1 downto 0);
+                    next_REGISTERS_OUT_write_enable <= reg_enable_pattern(2**NUM_CTRL_REGS-1 downto 0) or
+                                                       reg_enable_pattern(2**NUM_CTRL_REGS+31 downto 32);
                   else
-                    next_COMMON_REGISTERS_OUT_write_enable <= reg_enable_pattern(std_COMCTRLREG-1 downto 0);
+                    next_COMMON_REGISTERS_OUT_write_enable <= reg_enable_pattern(std_COMCTRLREG-1 downto 0) or
+                                                              reg_enable_pattern(std_COMCTRLREG+31 downto 32);
                   end if;
                   next_state   <= REG_READ;
                 else