From: Jan Michel Date: Wed, 2 Apr 2014 15:41:34 +0000 (+0200) Subject: added SED instance to the repository X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b004495d6ad55d97a215e06a0fe5c3b369e3bc30;p=trb3.git added SED instance to the repository --- diff --git a/base/code/sedcheck.vhd b/base/code/sedcheck.vhd index 6aed783..ce11075 100644 --- a/base/code/sedcheck.vhd +++ b/base/code/sedcheck.vhd @@ -40,7 +40,7 @@ architecture sed_arch of sedcheck is ); end component; - type state_t is (IDLE, INIT_1, INIT_2, INIT_3, START_1, START_2, WAITACTIVE, WAITDONE, RESULT); + type state_t is (IDLE, INIT_1, INIT_2, INIT_3, START_1, START_2, WAITACTIVE, WAITDONE); signal state : state_t; signal state_bits : std_logic_vector(3 downto 0); @@ -58,9 +58,6 @@ architecture sed_arch of sedcheck is signal sed_done_q : std_logic; signal sed_error_q : std_logic; signal sed_inprogress_q : std_logic; - signal sed_done_reg : std_logic; - signal sed_error_reg : std_logic; - signal sed_inprogress_reg : std_logic; signal control_i : std_logic_vector(31 downto 0) := (others => '0'); signal status_i : std_logic_vector(31 downto 0); @@ -72,17 +69,13 @@ architecture sed_arch of sedcheck is begin sed_clock_last <= sed_clock_q when rising_edge(CLK); -sed_edge <= not sed_clock_q and sed_clock_last; +sed_edge <= sed_clock_q and not sed_clock_last when rising_edge(CLK); sed_clock_q <= sed_clock when rising_edge(CLK); +sed_done_q <= sed_done when rising_edge(CLK); +sed_inprogress_q <= sed_inprogress when rising_edge(CLK); +sed_error_q <= sed_error when rising_edge(CLK); -sed_done_q <= sed_done_reg when rising_edge(CLK); -sed_inprogress_q <= sed_inprogress_reg when rising_edge(CLK); -sed_error_q <= sed_error_reg when rising_edge(CLK); - -sed_error_reg <= sed_error when falling_edge(sed_clock); -sed_done_reg <= sed_done when falling_edge(sed_clock); -sed_inprogress_reg <= sed_inprogress when falling_edge(sed_clock); --------------------------------------------------------------------------- -- Status / Control Register for internal data bus @@ -118,8 +111,8 @@ proc_ctrl : process begin sed_enable <= '0'; sed_start <= '0'; if control_i(0) = '1' then - state <= INIT_1; - timer <= "000001"; + state <= INIT_1; + timer <= "000001"; end if; when INIT_1 => sed_enable <= '1'; @@ -148,7 +141,7 @@ proc_ctrl : process begin when START_2 => sed_enable <= '1'; sed_start <= '1'; - if sed_edge = '1' then + if sed_edge = '1' and sed_inprogress_q = '1' then state <= WAITACTIVE; end if; when WAITACTIVE => @@ -158,18 +151,15 @@ proc_ctrl : process begin state <= WAITDONE; end if; when WAITDONE => + sed_enable <= '1'; + sed_start <= '0'; if sed_edge = '1' and sed_inprogress_q = '0' and sed_done_q = '1' then - state <= RESULT; - timer <= "000001"; - end if; - when RESULT => --- if timer = 0 then - state <= IDLE; + state <= INIT_1; run_counter <= run_counter + 1; if sed_error_q = '1' then error_counter <= error_counter + 1; end if; --- end if; + end if; end case; if control_i(0) = '0' then @@ -190,7 +180,7 @@ state_bits <= x"8" when state = IDLE else x"5" when state = START_2 else x"6" when state = WAITACTIVE else x"7" when state = WAITDONE else - x"9" when state = RESULT else +-- x"9" when state = RESULT else x"F"; status_i(3 downto 0) <= state_bits; diff --git a/hadesstart/compile_periph_frankfurt.pl b/hadesstart/compile_periph_frankfurt.pl index 1421666..dc92350 100755 --- a/hadesstart/compile_periph_frankfurt.pl +++ b/hadesstart/compile_periph_frankfurt.pl @@ -9,6 +9,8 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph_hadesstart"; #Name of top-level entity +#my $lattice_path = '/d/jspc29/lattice/diamond/2.1_x64'; +#my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; my $lattice_path = '/d/jspc29/lattice/diamond/3.0_x64'; my $synplify_path = '/d/jspc29/lattice/synplify/I-2013.09-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; @@ -36,7 +38,7 @@ my $SPEEDGRADE="8"; #create full lpf file system("cp ../base/trb3_periph_ada.lpf workdir/$TOPNAME.lpf"); system("cat currentRelease/trbnet_constraints.lpf >> workdir/$TOPNAME.lpf"); -system("cat currentRelease/tdc_constraints.lpf >> workdir/$TOPNAME.lpf"); +system("cat currentRelease/tdc_constraints_4.lpf >> workdir/$TOPNAME.lpf"); #set -e @@ -111,7 +113,7 @@ system("rm $TOPNAME.ncd"); #$c=qq|mpartrce -p "../$TOPNAME.p2t" -log "$TOPNAME.log" -o "$TOPNAME.rpt" -pr "$TOPNAME.prf" -tf "$TOPNAME.pt" "|.$TOPNAME.qq|_map.ncd" "$TOPNAME.ncd"|; # $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; -$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 3 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|; +$c=qq|$lattice_path/ispfpga/bin/lin/par -w -l 5 -i 6 -t 4 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF $tpmap.ncd $TOPNAME.ncd $TOPNAME.prf|; execute($c); # IOR IO Timing Report # $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; diff --git a/hadesstart/trb3_periph_hadesstart.vhd b/hadesstart/trb3_periph_hadesstart.vhd index 16a4fe5..0ffed00 100644 --- a/hadesstart/trb3_periph_hadesstart.vhd +++ b/hadesstart/trb3_periph_hadesstart.vhd @@ -99,6 +99,7 @@ architecture trb3_periph_hadesstart_arch of trb3_periph_hadesstart is signal clear_i : std_logic; signal reset_i : std_logic; signal GSR_N : std_logic; + signal i_rst_p : std_logic; attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; @@ -279,6 +280,7 @@ begin --------------------------------------------------------------------------- GSR_N <= pll_lock; + i_rst_p <= not pll_lock; THE_RESET_HANDLER : trb_net_reset_handler generic map( @@ -784,6 +786,14 @@ THE_SED : entity work.sedcheck ADDR_IN => sed_addr ); +-- THE_SED : entity work.sedcheck +-- port map( +-- CLK => clk_100_i, +-- ERROR_OUT => sed_error, +-- i_rst_p => i_rst_p, +-- STATUS_OUT => TEST_LINE(11 downto 0) +-- ); + --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- @@ -796,8 +806,8 @@ THE_SED : entity work.sedcheck -- Test Connector - Logic Analyser --------------------------------------------------------------------------- - TEST_LINE <= logic_analyser_i; - +-- TEST_LINE <= logic_analyser_i; + TEST_LINE(15 downto 12) <= (others => '0'); ------------------------------------------------------------------------------- -- TDC