From: hadeshyp <hadeshyp>
Date: Fri, 12 Dec 2008 17:14:12 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~504
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b043abff2008f8052391e89d98da13c8cc7ce96c;p=trbnet.git

*** empty log message ***
---

diff --git a/testbench/trb_net16_dummy_apl.vhd b/testbench/trb_net16_dummy_apl.vhd
index 8d7dfec..f65e580 100644
--- a/testbench/trb_net16_dummy_apl.vhd
+++ b/testbench/trb_net16_dummy_apl.vhd
@@ -65,12 +65,12 @@ begin
 --   address <= x"0008";
 --   reghigh <= x"DEAD";
 --   reglow  <= x"AFFE";
-  reg_F0 <= x"1010"; --x"0001";
+  reg_F0 <= x"8023"; --x"0001";
 
   reg_F1 <= x"8000";
   reg_F2 <= x"0000";--xor_all(APL_DATA_IN) & "000000000000011";
   reg_F3 <= x"0000";
-  APL_DTYPE_OUT <= x"B";
+  APL_DTYPE_OUT <= x"9";
   APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS;
 
   process(current_state)
diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd
index 8aee02c..186af9f 100644
--- a/trb_net16_regIO.vhd
+++ b/trb_net16_regIO.vhd
@@ -147,7 +147,8 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is
   end component;
 
   type fsm_state_t is (IDLE, HEADER_RECV, REG_READ, REG_WRITE, ONE_READ, ONE_WRITE, SEND_REPLY_SHORT_TRANSFER, MEM_START_WRITE,
-                       MEM_READ, MEM_WRITE, DAT_START_READ, DAT_READ, SEND_REPLY_DATA_finish, ADDRESS_ACK, ADDRESS_RECV,MEM_START_READ);
+                       MEM_READ, MEM_WRITE, DAT_START_READ, DAT_READ, SEND_REPLY_DATA_finish, ADDRESS_ACK, ADDRESS_RECV,
+                       MEM_START_READ, DAT_START_READ_AFTER_WRITE);
   signal current_state, next_state             : fsm_state_t;
 --  signal HDR_F1, HDR_F2, HDR_F3, HDR_F0        : std_logic_vector(c_DATA_WIDTH-1 downto 0);
 --  signal next_HDR_F1, next_HDR_F2, next_HDR_F3, next_HDR_F0 : std_logic_vector(c_DATA_WIDTH-1 downto 0);
@@ -341,7 +342,7 @@ begin
             if or_all(API_DATA_IN(c_REGIO_ADDRESS_WIDTH-1 downto 8)) = '1' then  --data port address
               if USE_DAT_PORT = c_YES then
                 next_DAT_READ_ENABLE_OUT <= '1';
-                next_state <= DAT_READ;
+                next_state <= DAT_START_READ;
               else
                 next_state <= SEND_REPLY_SHORT_TRANSFER;
                 next_dont_understand <= '1';
@@ -394,7 +395,7 @@ begin
                   next_state   <= REG_READ;
                 else
                   next_DAT_WRITE_ENABLE_OUT <= '1';
-                  next_state   <= DAT_START_READ;
+                  next_state   <= DAT_START_READ_AFTER_WRITE;
                 end if;
               when others => null;
             end case;
@@ -525,6 +526,10 @@ begin
             end if;
           end if;
 
+        when DAT_START_READ_AFTER_WRITE =>
+          next_state <= DAT_START_READ;
+          next_DAT_READ_ENABLE_OUT <= '1';
+
         when DAT_START_READ =>
           if DAT_DATAREADY_IN = '1' then
             next_state <= DAT_READ;
@@ -533,6 +538,7 @@ begin
           end if;
 
         when DAT_READ =>
+          next_API_SEND_OUT <= '1';
           next_API_DATAREADY_OUT <= '1';
           case next_packet_counter is
             when c_F0 => next_API_DATA_OUT <= address;