From: palka Date: Thu, 7 Feb 2008 13:17:26 +0000 (+0000) Subject: changes to synch state machine X-Git-Tag: oldGBE~606 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b04cc1d12d5ebbe33454789f04c71efbb6593bdf;p=trbnet.git changes to synch state machine --- diff --git a/optical_link/flexi_PCS_channel_synch.vhd b/optical_link/flexi_PCS_channel_synch.vhd index 586a5dc..8f0dc4b 100644 --- a/optical_link/flexi_PCS_channel_synch.vhd +++ b/optical_link/flexi_PCS_channel_synch.vhd @@ -59,7 +59,7 @@ architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is CLK : in std_logic; CLR : in std_logic); end component; - type SYNCH_MACHINE is (IDLE, SYNCH_START, RESYNC1, RESYNC2, RESYNC3, NORMAL_OPERATION); + type SYNCH_MACHINE is (IDLE, SYNCH_START, RESYNC1, RESYNC2, RESYNC3, WAIT_1, WAIT_2, NORMAL_OPERATION_1, NORMAL_OPERATION_2); signal SYNCH_CURRENT, SYNCH_NEXT : SYNCH_MACHINE; signal fsm_debug_register : std_logic_vector(2 downto 0); signal resync_counter_up :std_logic; @@ -70,6 +70,9 @@ architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is signal cv_counter : std_logic_vector(15 downto 0); signal rx_rst_i : std_logic; signal rxd_synch_i : std_logic_vector(15 downto 0); + signal rxd_synch_synch_i : std_logic_vector(15 downto 0); + signal rx_k_synch_i : std_logic_vector(1 downto 0); + signal rx_k_synch_synch_i : std_logic_vector(1 downto 0); signal fifo_data_in : std_logic_vector(17 downto 0); signal fifo_data_out : std_logic_vector(17 downto 0); signal fifo_wr_en : std_logic; @@ -80,6 +83,8 @@ architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is signal fifo_empty : std_logic; signal fifo_almost_empty : std_logic; signal packet_number : std_logic_vector(1 downto 0); + signal start_counter : std_logic_vector(31 downto 0); + signal start_counter_2 : std_logic_vector(31 downto 0); begin PACKET_NUM: process (CLK, RESET) begin @@ -102,22 +107,27 @@ begin FLEXI_PCS_STATUS(15 downto 8) <= cv_counter(15 downto 12) & cv_counter(3 downto 0); end if; end process SYNCH_PROCESS; - VALID_DATA_SEND_TO_OPTICAL: process (CLK, RESET, DATA_VALID_IN) - begin - if rising_edge(CLK) then - if RESET = '1' then - TX_FORCE_DISP(1) <= '1'; - TXD_SYNCH <= (others => '0'); - elsif DATA_VALID_IN = '1' then - TX_FORCE_DISP(1) <= '0'; - TXD_SYNCH <= TXD; - else - TX_FORCE_DISP(1) <= '1'; - TXD_SYNCH <= x"bc50"; - end if; - end if; - end process VALID_DATA_SEND_TO_OPTICAL; - fifo_data_in <= RX_K & RXD; + VALID_DATA_SEND_TO_OPTICAL: process (CLK, RESET, DATA_VALID_IN) + begin + if rising_edge(CLK) then + if RESET = '1' then + TX_FORCE_DISP(1) <= '0'; + TXD_SYNCH <= (others => '0'); + elsif DATA_VALID_IN = '1' and (SYNCH_CURRENT = NORMAL_OPERATION_1 or SYNCH_CURRENT = NORMAL_OPERATION_2) then + TX_FORCE_DISP(1) <= '0'; + TXD_SYNCH <= TXD; + elsif start_counter(15) = '1' and (SYNCH_CURRENT = WAIT_1 or SYNCH_CURRENT = WAIT_2) then + TX_FORCE_DISP(1) <= '1'; + TXD_SYNCH <= x"bc50"; + elsif start_counter(15) = '0' and (SYNCH_CURRENT = WAIT_1 or SYNCH_CURRENT = WAIT_2) then + TX_FORCE_DISP(1) <= '0'; + TXD_SYNCH <= x"0000"; + else + TX_FORCE_DISP(1) <= '1'; + TXD_SYNCH <= x"bc50"; + end if; + end if; + end process VALID_DATA_SEND_TO_OPTICAL; CHANNEL_FIFO: flexi_PCS_fifo_EBR port map ( Data => fifo_data_in, @@ -142,11 +152,31 @@ begin if rising_edge(RX_CLK) then if RESET = '1' then rxd_synch_i <= (others => '0'); + rxd_synch_synch_i <= rxd_synch_i; + rx_k_synch_i <= "00"; + rx_k_synch_synch_i <= rx_k_synch_i; else-- RX_K(0) = '1' then rxd_synch_i <= RXD; + rxd_synch_synch_i <= rxd_synch_i; + rx_k_synch_i <= RX_K; + rx_k_synch_synch_i <= rx_k_synch_i; end if; end if; end process VALID_DATA_SEND_TO_API; + SHIFT_OR_NOT_DATA_IN: process (RX_CLK, RESET) + begin + if rising_edge(RX_CLK) then + if RESET = '1' then + fifo_data_in <= (others => '0'); + elsif SYNCH_CURRENT = NORMAL_OPERATION_1 then + fifo_data_in <= rx_k_synch_i & rxd_synch_i; + elsif SYNCH_CURRENT = NORMAL_OPERATION_2 then + fifo_data_in <= rx_k_synch_synch_i(0) & rx_k_synch_i(1) & rxd_synch_synch_i(7 downto 0) & rxd_synch_i(15 downto 8); + else + fifo_data_in <= (others => '0'); + end if; + end if; + end process SHIFT_OR_NOT_DATA_IN; SYNCH_CLOCK : process (CLK, RESET) begin if rising_edge (CLK) then @@ -164,73 +194,121 @@ begin case (SYNCH_CURRENT) is when IDLE => fifo_rst <= '0'; - fifo_wr_en <= '1'; - fifo_rd_en <= '1'; + fifo_wr_en <= '0'; + fifo_rd_en <= '0'; fsm_debug_register(2 downto 0) <= "001"; rx_rst_i <= '0'; resync_counter_up <= '0'; resync_counter_clr <= '1'; - if rxd_synch_i = x"bc50" then - SYNCH_NEXT <= NORMAL_OPERATION; - else + if rxd_synch_i = x"bc50" then + SYNCH_NEXT <= NORMAL_OPERATION_1;--WAIT_1; + elsif rxd_synch_i = x"50bc" then + SYNCH_NEXT <= NORMAL_OPERATION_2; --WAIT_2; + else SYNCH_NEXT <= RESYNC1; end if; - when RESYNC1 => - fifo_rst <= '1'; + when RESYNC1 => + fifo_rst <= '0'; + fifo_wr_en <= '0'; + fifo_rd_en <= '0'; + fsm_debug_register(2 downto 0) <= "010"; + rx_rst_i <= '1'; + resync_counter_up <= '1'; + resync_counter_clr <= '0'; + if resync_counter = 200 then + SYNCH_NEXT <= RESYNC2; + else + SYNCH_NEXT <= RESYNC1; + end if; + when RESYNC2 => + fifo_rst <= '0'; + fifo_wr_en <= '0'; + fifo_rd_en <= '0'; + fsm_debug_register(2 downto 0) <= "011"; + rx_rst_i <= '0'; + resync_counter_up <= '1'; + resync_counter_clr <= '0'; + if resync_counter = 50001 then --at least 400us + SYNCH_NEXT <= RESYNC3; + else + SYNCH_NEXT <= RESYNC2; + end if; + + when RESYNC3 => + fifo_rst <= '0'; + fifo_wr_en <= '0'; + fifo_rd_en <= '0'; + fsm_debug_register(2 downto 0) <= "011"; + rx_rst_i <= '0'; + resync_counter_up <= '0'; + resync_counter_clr <= '1'; + if rxd_synch_i = x"bc50" then + SYNCH_NEXT <= NORMAL_OPERATION_1; + elsif rxd_synch_i = x"50bc" then + SYNCH_NEXT <= NORMAL_OPERATION_2; + else + SYNCH_NEXT <= IDLE; + end if; + when WAIT_1 => + fifo_rst <= '0'; fifo_wr_en <= '0'; fifo_rd_en <= '0'; + rx_rst_i <= '0'; fsm_debug_register(2 downto 0) <= "010"; - rx_rst_i <= '1'; - resync_counter_up <= '1'; + resync_counter_up <= '0'; resync_counter_clr <= '0'; - if resync_counter = 20003 then - SYNCH_NEXT <= RESYNC2; + if rxd_synch_i = x"0000" and start_counter(24) = '1' then + SYNCH_NEXT <= NORMAL_OPERATION_1; else - SYNCH_NEXT <= RESYNC1; + SYNCH_NEXT <= WAIT_1; end if; - when RESYNC2 => + when WAIT_2 => fifo_rst <= '0'; - fifo_wr_en <= '1'; + fifo_wr_en <= '0'; fifo_rd_en <= '0'; - fsm_debug_register(2 downto 0) <= "011"; rx_rst_i <= '0'; - resync_counter_up <= '1'; - resync_counter_clr <= '0'; - if resync_counter = 20200 then - SYNCH_NEXT <= RESYNC3; - else - SYNCH_NEXT <= RESYNC2; - end if; - when RESYNC3 => - fifo_rst <= '0'; - fifo_wr_en <= '1'; - fifo_rd_en <= '1'; fsm_debug_register(2 downto 0) <= "011"; - rx_rst_i <= '0'; - resync_counter_up <= '1'; + resync_counter_up <= '0'; resync_counter_clr <= '0'; - if resync_counter = 60000 then - SYNCH_NEXT <= IDLE; + if rxd_synch_i = x"0000" and start_counter(24) = '1' then + SYNCH_NEXT <= NORMAL_OPERATION_2; else - SYNCH_NEXT <= RESYNC3; + SYNCH_NEXT <= WAIT_1; end if; - when NORMAL_OPERATION => - fifo_rst <= '0'; - fifo_wr_en <= '1'; - fifo_rd_en <= '1'; - fsm_debug_register(2 downto 0) <= "100"; - rx_rst_i <= '0'; - resync_counter_up <= '0'; - resync_counter_clr <= '0'; - if cv_i(0) = '1' or cv_i(1) = '1' then - SYNCH_NEXT <= IDLE; + + when NORMAL_OPERATION_1 => + fifo_rst <= '0'; + fifo_wr_en <= RX_K(0); + fifo_rd_en <= DATA_VALID_IN; + fsm_debug_register(2 downto 0) <= "100"; + rx_rst_i <= '0'; + resync_counter_up <= '0'; + resync_counter_clr <= '0'; + if cv_i(0) = '1' or cv_i(1) = '1' then + SYNCH_NEXT <= IDLE; else - SYNCH_NEXT <= NORMAL_OPERATION; - end if; + SYNCH_NEXT <= NORMAL_OPERATION_1; + end if; + when NORMAL_OPERATION_2 => + fifo_rst <= '0'; + fifo_wr_en <= RX_K(0); + fifo_rd_en <= DATA_VALID_IN; + fsm_debug_register(2 downto 0) <= "101"; + rx_rst_i <= '0'; + resync_counter_up <= '0'; + resync_counter_clr <= '0'; + if cv_i(0) = '1' or cv_i(1) = '1' then + SYNCH_NEXT <= IDLE; + else + SYNCH_NEXT <= NORMAL_OPERATION_2; + end if; + when others => fifo_rst <= '0'; fifo_wr_en <= '0'; fifo_rd_en <= '0'; + resync_counter_up <= '0'; + resync_counter_clr <= '0'; fsm_debug_register(2 downto 0) <= "000"; rx_rst_i <= '0'; resync_counter_up <= '0'; @@ -238,6 +316,18 @@ begin SYNCH_NEXT <= IDLE; end case; end process SYNCH_FSM; + START_PROCEDURE_COUNTER: process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + start_counter <= (others => '0'); + elsif SYNCH_CURRENT = WAIT_1 or SYNCH_CURRENT = WAIT_2 then + start_counter <= start_counter +1; + else + start_counter <= start_counter; + end if; + end if; + end process START_PROCEDURE_COUNTER; RESYNC_COUNTER_INST : simpleupcounter_16bit port map ( QOUT => resync_counter, @@ -252,3 +342,13 @@ begin CLK => CLK, CLR => '0'); end flexi_PCS_channel_synch; +--reciving idle for 1ms and start e11o until recive e11o and idle +--write to fifo when rx_k is 1 ? +-- wait for reset +-- wait for pll locked +-- send idles +-- wait 650ms (counter(27) = 1) +-- enable rx +-- wait 650ms (counter(27) = 1) +-- enable tx +-- ready