From: admin <admin@44570794-fe78-5344-a7c8-9252e64eda2e>
Date: Fri, 6 Sep 2013 11:53:48 +0000 (+0000)
Subject: git-svn-id: file:///d/jspc55.1/Elektronik/repo@23 44570794-fe78-5344-a7c8-9252e64eda2e
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b102ce7b119bb92fa3689e5bb4e7d76054d2fd3f;p=mvdelectronics.git

git-svn-id: file:///d/jspc55.1/Elektronik/repo@23 44570794-fe78-5344-a7c8-9252e64eda2e
---

diff --git a/CB2013/CB13_ADC.SchDoc b/CB2013/CB13_ADC.SchDoc
index 5f97b2d..35535e0 100644
Binary files a/CB2013/CB13_ADC.SchDoc and b/CB2013/CB13_ADC.SchDoc differ
diff --git a/CB2013/CB2013.PcbDoc b/CB2013/CB2013.PcbDoc
index 7b8bf7f..8d211d7 100644
Binary files a/CB2013/CB2013.PcbDoc and b/CB2013/CB2013.PcbDoc differ
diff --git a/CB2013/CB2013.PrjPCB b/CB2013/CB2013.PrjPCB
index 0a971c5..86f74cd 100644
--- a/CB2013/CB2013.PrjPCB
+++ b/CB2013/CB2013.PrjPCB
@@ -29,7 +29,7 @@ PowerPortNamesTakePriority=0
 PushECOToAnnotationFile=1
 DItemRevisionGUID=
 ReportSuppressedErrorsInMessages=0
-OutputPath=
+OutputPath=Project Outputs for CB2013
 
 [Document1]
 DocumentPath=CB13_ADC.SchDoc
@@ -446,14 +446,14 @@ AutoOpenFile=0
 AutoOpenOutJob=-1
 
 [Generic_SmartPDFSettings]
-ProjectMode=-1
+ProjectMode=0
 ZoomPrecision=50
 AddNetsInformation=-1
-AddNetPins=-1
-AddNetNetLabels=-1
-AddNetPorts=-1
-ShowComponentParameters=-1
-ExportBOM=-1
+AddNetPins=0
+AddNetNetLabels=0
+AddNetPorts=0
+ShowComponentParameters=0
+ExportBOM=0
 TemplateFilename=BOM Default Template 95.xlt
 TemplateStoreRelative=-1
 PCB_PrintColor=0
@@ -476,7 +476,7 @@ SCH_HasExpandLogicalToPhysicalSheets=-1
 SaveSettingsToOutJob=-1
 
 [Generic_EDE]
-OutputDir=
+OutputDir=Project Outputs for CB2013
 
 [OutputGroup1]
 Name=Netlist Outputs
diff --git a/CB2013/CB2013.SCHLIB b/CB2013/CB2013.SCHLIB
index 1a1d0f1..90d7de9 100644
Binary files a/CB2013/CB2013.SCHLIB and b/CB2013/CB2013.SCHLIB differ
diff --git a/CB2013/FEB2013.PrjPCB b/CB2013/FEB2013.PrjPCB
index 1f9360e..0b7b587 100644
--- a/CB2013/FEB2013.PrjPCB
+++ b/CB2013/FEB2013.PrjPCB
@@ -29,7 +29,7 @@ PowerPortNamesTakePriority=0
 PushECOToAnnotationFile=1
 DItemRevisionGUID=
 ReportSuppressedErrorsInMessages=0
-OutputPath=
+OutputPath=Project Outputs for FEB2013
 
 [Document1]
 DocumentPath=CB2013.SCHLIB
@@ -95,6 +95,22 @@ ClassGenNCAutoScope=None
 DItemRevisionGUID=
 GenerateClassCluster=0
 
+[Document5]
+DocumentPath=FEB2013.OutJob
+AnnotationEnabled=1
+AnnotateStartValue=1
+AnnotationIndexControlEnabled=0
+AnnotateSuffix=
+AnnotateScope=All
+AnnotateOrder=-1
+DoLibraryUpdate=1
+DoDatabaseUpdate=1
+ClassGenCCAutoEnabled=1
+ClassGenCCAutoRoomEnabled=1
+ClassGenNCAutoScope=None
+DItemRevisionGUID=
+GenerateClassCluster=0
+
 [Configuration1]
 Name=Default Configuration
 ParameterCount=0
@@ -105,6 +121,43 @@ Variant=[No Variations]
 GenerateBOM=1
 OutputJobsCount=0
 
+[Generic_SmartPDF]
+AutoOpenFile=0
+AutoOpenOutJob=0
+
+[Generic_SmartPDFSettings]
+ProjectMode=-1
+ZoomPrecision=50
+AddNetsInformation=-1
+AddNetPins=-1
+AddNetNetLabels=-1
+AddNetPorts=-1
+ShowComponentParameters=-1
+ExportBOM=0
+TemplateFilename=
+TemplateStoreRelative=-1
+PCB_PrintColor=0
+SCH_PrintColor=0
+SCH_ShowNoErc=-1
+SCH_ShowParameter=-1
+SCH_ShowProbes=-1
+SCH_ShowBlankets=-1
+SCH_NoERCSymbolsToShow="Thin Cross","Thick Cross","Small Cross",Checkbox,Triangle
+SCH_ShowNote=-1
+SCH_ShowNoteCollapsed=-1
+SCH_ExpandLogicalToPhysical=-1
+SCH_VariantName=[No Variations]
+SCH_ExpandComponentDesignators=-1
+SCH_ExpandNetlabels=0
+SCH_ExpandPorts=0
+SCH_ExpandSheetNumber=0
+SCH_ExpandDocumentNumber=0
+SCH_HasExpandLogicalToPhysicalSheets=-1
+SaveSettingsToOutJob=-1
+
+[Generic_EDE]
+OutputDir=Project Outputs for FEB2013
+
 [OutputGroup1]
 Name=Netlist Outputs
 Description=
diff --git a/CB2013/FrontEndBoard2013_ChipBlock.SchDoc b/CB2013/FrontEndBoard2013_ChipBlock.SchDoc
index 92f385a..a1245be 100644
Binary files a/CB2013/FrontEndBoard2013_ChipBlock.SchDoc and b/CB2013/FrontEndBoard2013_ChipBlock.SchDoc differ