From: Cahit Date: Tue, 8 Apr 2014 08:16:19 +0000 (+0200) Subject: multicycle constraint for clock domain crossings X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b1aafaa064d9301e174874569b39559a9b27f276;p=trb3.git multicycle constraint for clock domain crossings --- diff --git a/base/trb3_periph_32PinAddOn.lpf b/base/trb3_periph_32PinAddOn.lpf index 1fb3d5a..9a94475 100644 --- a/base/trb3_periph_32PinAddOn.lpf +++ b/base/trb3_periph_32PinAddOn.lpf @@ -14,6 +14,9 @@ FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; +MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ; +MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ; + ################################################################# # Clock I/O ################################################################# diff --git a/base/trb3_periph_ADA.lpf b/base/trb3_periph_ADA.lpf index 56c8eac..caeaf6c 100644 --- a/base/trb3_periph_ADA.lpf +++ b/base/trb3_periph_ADA.lpf @@ -14,6 +14,9 @@ FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; +MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ; +MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ; + ################################################################# # Clock I/O ################################################################# diff --git a/base/trb3_periph_ada.lpf b/base/trb3_periph_ada.lpf index efeac68..7d2e6ca 100644 --- a/base/trb3_periph_ada.lpf +++ b/base/trb3_periph_ada.lpf @@ -94,6 +94,9 @@ BLOCK RD_DURING_WR_PATHS ; FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; +MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ; +MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ; + ################################################################# # Clock I/O ################################################################# diff --git a/base/trb3_periph_gpin.lpf b/base/trb3_periph_gpin.lpf index 50999ca..96e89d1 100644 --- a/base/trb3_periph_gpin.lpf +++ b/base/trb3_periph_gpin.lpf @@ -12,6 +12,9 @@ FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; +MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ; +MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ; + ################################################################# # Clock I/O ################################################################# diff --git a/base/trb3_periph_padiwa.lpf b/base/trb3_periph_padiwa.lpf index 41b07c9..d6144d4 100644 --- a/base/trb3_periph_padiwa.lpf +++ b/base/trb3_periph_padiwa.lpf @@ -12,6 +12,9 @@ FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; +MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ; +MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ; + ################################################################# # Clock I/O #################################################################