From: hadeshyp Date: Mon, 26 Feb 2007 16:16:22 +0000 (+0000) Subject: Simulations file for the TRB_NET_OLD_TO_NEW MODULE. X-Git-Tag: oldGBE~756 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b2e4cc9a788f81bc20731daf61032b048a23e3bf;p=trbnet.git Simulations file for the TRB_NET_OLD_TO_NEW MODULE. --- diff --git a/testbench/p_trb_net_old_to_new_testbench.vhd b/testbench/p_trb_net_old_to_new_testbench.vhd new file mode 100644 index 0000000..d684400 --- /dev/null +++ b/testbench/p_trb_net_old_to_new_testbench.vhd @@ -0,0 +1,530 @@ +------------------------------------------------------------------------------- +-- Title : trb_net_old_to_new_testbench +-- Project : HADES trigger new net +------------------------------------------------------------------------------- +-- File : trb_net_old_to_new_testbench.vhd +-- Author : Tiago Perez (tiago.perez@uni-giessen.de) +-- Created : 2007/02/26 T. Perez +-- Last modified : +------------------------------------------------------------------------------- +-- Description : Testbench for the "trb_net_old_to_new" and the "OLD" trigger +-- bus in general. PACKAGE +-- +------------------------------------------------------------------------------- +-- Modification history : +-- 2007/02/26 : created +-- I change ARITH for UNSIGNED. Some funtions are nicer defined +-- there, adn this is anyhow only for sim. +------------------------------------------------------------------------------- +library IEEE; +use IEEE.Std_Logic_1164.all; +use std.textio.all; +--use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; +use IEEE.numeric_std.all; + +------------------------------------------------------------------------ +-- Package Declaration +------------------------------------------------------------------------ + +package p_trb_net_old_to_new_testbench is + +-- Constant for the clock period we will use + constant PERIOD : time := 100 ns; -- 10 MHz + constant PERIOD_TRB : time := 10 ns; -- 100 MHz + +-- This function converts std_logic to character so the standard +-- write routine for character can be used + + function STDU2CHAR (LOGIC : std_logic) return character; + +------------------------------------------------------------------------ +-- The following procedures perform the actions required of the commands +-- DO_RESET, DO_BE_RU (DO begin run), DO_SE_TR (DO send Trigger), DO_EN_RU (DO +-- end run +------------------------------------------------------------------------ + + procedure DO_RESET(signal RESET : out std_logic); + + procedure DO_VME_RE(signal T_VME_ADDRESS : out std_logic_vector(7 downto 1); + signal T_VME_DATA : out std_logic_vector(7 downto 0); + signal T_VME_DLY1 : out std_logic; + signal T_VME_WRT : out std_logic; + signal T_VME_BSEL1 : out std_logic; + SETTING : in string(1 to 3)); + + procedure DO_BE_RU(signal T_TRIGBUS_TSTR : out std_logic; + signal T_TRIGBUS_DSTR : out std_logic; + signal T_TRIGBUS_DIN : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY : in std_logic); + + procedure DO_SE_TR_LVL1(SETTING : in string(1 to 3); + signal T_TRIGBUS_TSTR : out std_logic; + signal T_TRIGBUS_DSTR : out std_logic; + signal T_TRIGBUS_DIN : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY : in std_logic); + + procedure DO_SE_TR_LVL2(SETTING : in string(1 to 3); + signal T_TRIGBUS_TSTR : out std_logic; + signal T_TRIGBUS_DSTR : out std_logic; + signal T_TRIGBUS_DIN : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY : in std_logic); + + procedure DO_EN_RU(signal T_TRIGBUS_TSTR : out std_logic; + signal T_TRIGBUS_DSTR : out std_logic; + signal T_TRIGBUS_DIN : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY : in std_logic); + + procedure DO_SE_CY(signal T_TRIGBUS_TSTR : out std_logic; + signal T_TRIGBUS_DSTR : out std_logic; + signal T_TRIGBUS_DIN : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY : in std_logic); + procedure DO_SE_CY_ALL(signal T_TRIGBUS_TSTR_1 : out std_logic; + signal T_TRIGBUS_DSTR_1 : out std_logic; + signal T_TRIGBUS_DIN_1 : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY_1 : in std_logic; + signal T_TRIGBUS_TSTR_2 : out std_logic; + signal T_TRIGBUS_DSTR_2 : out std_logic; + signal T_TRIGBUS_DIN_2 : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY_2 : in std_logic + ); + + procedure DO_WAIT; + +end p_trb_net_old_to_new_testbench; + + +------------------------------------------------------------------------ +-- Package Body Declaration +------------------------------------------------------------------------ +package body p_trb_net_old_to_new_testbench is +------------------------------------------------------------------------ + +------------------------------------------------------------------------ +-- STDU2CHAR type conversion function +------------------------------------------------------------------------ + function STDU2CHAR (LOGIC : std_logic) return character is + variable CHAR : character; + begin + case LOGIC is + when '1' => CHAR := '1'; + when '0' => CHAR := '0'; + when others => CHAR := '-'; + end case; + return CHAR; + end STDU2CHAR; + + function CHAR2INT (CHAR : character) return integer is + variable INT : integer; + begin + case CHAR is + when '0' => INT := 0; + when '1' => INT := 1; + when '2' => INT := 2; + when '3' => INT := 3; + when '4' => INT := 4; + when '5' => INT := 5; + when '6' => INT := 6; + when '7' => INT := 7; + when '8' => INT := 8; + when '9' => INT := 9; + when others => + end case; + return INT; + end CHAR2INT; + + function INT2CHAR (INT : integer) return character is + variable temp : character; + begin + case INT is + --when 0 => temp := character('0'); + when 0 => temp := '0'; + when 1 => temp := '1'; + when 2 => temp := '2'; + when 3 => temp := '3'; + when 4 => temp := '4'; + when 5 => temp := '5'; + when 6 => temp := '6'; + when 7 => temp := '7'; + when 8 => temp := '8'; + when 9 => temp := '9'; + when others => temp := '-'; + end case; + return temp; + end INT2CHAR; + +------------------------------------------------------------------------ +-- DO_RESET command +------------------------------------------------------------------------ + procedure DO_RESET(signal RESET : out std_logic) is + begin + RESET <= '0'; + wait for 2*PERIOD; + RESET <= '1'; + wait for 1 us; + RESET <= '0'; + end DO_RESET; + +------------------------------------------------------------------------ +-- DO_VME_RE command +------------------------------------------------------------------------ + procedure DO_VME_RE(signal T_VME_ADDRESS : out std_logic_vector(7 downto 1); + signal T_VME_DATA : out std_logic_vector(7 downto 0); + signal T_VME_DLY1 : out std_logic; + signal T_VME_WRT : out std_logic; + signal T_VME_BSEL1 : out std_logic; + SETTING : in string(1 to 3)) is + + variable TTAG : integer; + variable STTAG_TEMP : unsigned(7 downto 0); + variable STTAG : unsigned(6 downto 0); + begin + T_VME_DATA <= "ZZZZZZZZ"; + TTAG := CHAR2INT(SETTING(1))*100; + TTAG := TTAG + CHAR2INT(SETTING(2))*10; + TTAG := TTAG + CHAR2INT(SETTING(3)); + STTAG_TEMP := to_unsigned(TTAG, 8); + STTAG(6 downto 0) := STTAG_TEMP(7 downto 1); + + T_VME_ADDRESS <= std_logic_vector(STTAG); + T_VME_DLY1 <= '1'; + T_VME_BSEL1 <= '0'; + T_VME_WRT <= '1'; + wait for 2*PERIOD; + wait for 2*PERIOD; + T_VME_ADDRESS <= "0000000"; + T_VME_DLY1 <= '0'; + T_VME_BSEL1 <= '1'; + T_VME_WRT <= '1'; + wait for 2*PERIOD; + end DO_VME_RE; + +------------------------------------------------------------------------ +-- DO Begin RUN command +------------------------------------------------------------------------ + procedure DO_BE_RU(signal T_TRIGBUS_TSTR : out std_logic; + signal T_TRIGBUS_DSTR : out std_logic; + signal T_TRIGBUS_DIN : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY : in std_logic) + is + begin + assert false report "DO_BE_RU called" severity note; + --wait until T_TRIGBUS_BUSY='0'; + wait for 0.4*PERIOD; + T_TRIGBUS_TSTR <= '1'; + T_TRIGBUS_DSTR <= '0'; + T_TRIGBUS_DIN <= "1101"; -- check if this is now the correct code + wait for 0.6*PERIOD; -- the ctu does seem to send this and not + wait for PERIOD; -- "0010" + T_TRIGBUS_TSTR <= '0'; + wait for 0.8*PERIOD; + T_TRIGBUS_DIN <= "1111"; + wait for 0.2*PERIOD; + for k in 0 to 2 loop + T_TRIGBUS_DIN <= "0000"; +-- wait for PERIOD; + T_TRIGBUS_DSTR <= '1'; + wait for period; + T_TRIGBUS_DSTR <= '0'; + wait for period; + end loop; -- k + + end DO_BE_RU; + +------------------------------------------------------------------------ +-- DO Send Trigger command +------------------------------------------------------------------------ + procedure DO_SE_TR_LVL1(SETTING : in string(1 to 3); + signal T_TRIGBUS_TSTR : out std_logic; + signal T_TRIGBUS_DSTR : out std_logic; + signal T_TRIGBUS_DIN : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY : in std_logic) + is + variable TTAG : integer; + variable STTAG : unsigned(7 downto 0); + variable debug_string : string(1 to 3) := "000"; + variable OUTBLA : string(1 to 20); + + begin + assert false report "DO_SE_TR_LVL1 called" severity note; + assert false report "SETTING" severity note; + assert false report SETTING severity note; + -- debug ------------------------------------------------------------------ + --assert false report "waiting for T_TRIGBUS_BUSY = '0'" severity NOTE; + assert false report "Set T_TRIGBUS_DIN 0000-1111-0000" severity note; + T_TRIGBUS_DIN <= "0000"; + wait for PERIOD; + T_TRIGBUS_DIN <= "1111"; + wait for PERIOD; + T_TRIGBUS_DIN <= "0000"; + --------------------------------------------------------------------------- + --assert not T_TRIGBUS_BUSY='0' report "bla" severity NOTE; + + --report time'image(NOW); + --report std_logic'image(T_TRIGBUS_BUSY); + if T_TRIGBUS_BUSY = '1' then + wait until T_TRIGBUS_BUSY = '0'; + end if; + + assert false report "T_TRIGBUS_BUSY = 0" severity note; + TTAG := CHAR2INT(SETTING(1))*100; + debug_string(1) := INT2CHAR(integer(TTAG / 100)); + TTAG := TTAG + CHAR2INT(SETTING(2))*10; + debug_string(2) := INT2CHAR(integer((TTAG mod 100)/10)); + TTAG := TTAG + CHAR2INT(SETTING(3)); + debug_string(3) := INT2CHAR(TTAG mod 10); + STTAG := to_unsigned(TTAG, 8); + assert false report "debug String = " severity note; + assert false report debug_string severity note; + --assert false report "TTAG = " severity note; + --report integer'image(TTAG); + wait for 0.4*PERIOD; + T_TRIGBUS_TSTR <= '1'; + T_TRIGBUS_DSTR <= '0'; + T_TRIGBUS_DIN <= "0001"; -- triger code + wait for 0.6*PERIOD; + wait for PERIOD; + T_TRIGBUS_TSTR <= '0'; + wait for 0.8*PERIOD; + T_TRIGBUS_DIN <= "1111"; -- <- Why that? + wait for 0.2*PERIOD; + T_TRIGBUS_DIN <= std_logic_vector(STTAG(3 downto 0)); +-- wait for PERIOD; -- the ctu should wait but DOES NOT!!! + T_TRIGBUS_DSTR <= '1'; + wait for period; + T_TRIGBUS_DSTR <= '0'; + wait for period; + T_TRIGBUS_DIN <= std_logic_vector(STTAG(7 downto 4)); +-- wait for PERIOD; + T_TRIGBUS_DSTR <= '1'; + wait for period; + T_TRIGBUS_DSTR <= '0'; + wait for period; + T_TRIGBUS_DIN <= "0000"; +-- wait for PERIOD; + T_TRIGBUS_DSTR <= '1'; + wait for period; + T_TRIGBUS_DSTR <= '0'; + wait for period; + + end DO_SE_TR_LVL1; + +------------------------------------------------------------------------------- +-- SEND LVL2 TRIGER +------------------------------------------------------------------------------- + procedure DO_SE_TR_LVL2(SETTING : in string(1 to 3); + signal T_TRIGBUS_TSTR : out std_logic; + signal T_TRIGBUS_DSTR : out std_logic; + signal T_TRIGBUS_DIN : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY : in std_logic) + is + variable TTAG : integer; + variable STTAG : unsigned(7 downto 0); + variable debug_string : string(1 to 3) := "000"; + begin + assert false report "DO_SE_TR_LVL2 called" severity note; + assert false report "SETTING" severity note; + assert false report SETTING severity note; + + --------------------------------------------------------------------------- + -- CHECK BUSY COND + --------------------------------------------------------------------------- + --wait for 150 ns; + if T_TRIGBUS_BUSY = '1' then + wait until T_TRIGBUS_BUSY = '0'; + end if; + + TTAG := CHAR2INT(SETTING(1))*100; + debug_string(1) := INT2CHAR(integer(TTAG / 100)); + TTAG := TTAG + CHAR2INT(SETTING(2))*10; + debug_string(2) := INT2CHAR(integer((TTAG mod 100)/10)); + TTAG := TTAG + CHAR2INT(SETTING(3)); + debug_string(3) := INT2CHAR(TTAG mod 10); + STTAG := to_unsigned(TTAG, 8); + assert false report debug_string severity note; + wait for 0.4*PERIOD; + T_TRIGBUS_TSTR <= '1'; + T_TRIGBUS_DSTR <= '0'; + T_TRIGBUS_DIN <= "0001"; + wait for 0.6*PERIOD; + wait for PERIOD; + T_TRIGBUS_TSTR <= '0'; + wait for 0.8*PERIOD; + T_TRIGBUS_DIN <= "1111"; + wait for 0.2*PERIOD; + T_TRIGBUS_DIN <= std_logic_vector(STTAG(3 downto 0)); +-- wait for PERIOD; -- the ctu should wait but DOES NOT!!! + T_TRIGBUS_DSTR <= '1'; + wait for period; + T_TRIGBUS_DSTR <= '0'; + wait for period; + T_TRIGBUS_DIN <= std_logic_vector(STTAG(7 downto 4)); +-- wait for PERIOD; + T_TRIGBUS_DSTR <= '1'; + wait for period; + T_TRIGBUS_DSTR <= '0'; + wait for period; + T_TRIGBUS_DIN <= "0000"; +-- wait for PERIOD; + T_TRIGBUS_DSTR <= '1'; + wait for period; + T_TRIGBUS_DSTR <= '0'; + wait for period; + + end DO_SE_TR_LVL2; + + + procedure DO_SE_TR2_LVL1(TTAG : in natural; + signal T_TRIGBUS_TSTR : out std_logic; + signal T_TRIGBUS_DSTR : out std_logic; + signal T_TRIGBUS_DIN : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY : in std_logic ) + is + variable STTAG : unsigned(7 downto 0); + begin + wait until T_TRIGBUS_BUSY = '0'; + STTAG := to_unsigned(TTAG, 8); + wait for 0.4*PERIOD; + T_TRIGBUS_TSTR <= '1'; + T_TRIGBUS_DSTR <= '0'; + T_TRIGBUS_DIN <= "0001"; + wait for 0.6*PERIOD; + wait for PERIOD; + T_TRIGBUS_TSTR <= '0'; + wait for 0.8*PERIOD; + T_TRIGBUS_DIN <= "1111"; + wait for 0.2*PERIOD; + T_TRIGBUS_DIN <= std_logic_vector(STTAG(3 downto 0)); +-- wait for PERIOD; + T_TRIGBUS_DSTR <= '1'; + wait for period; + T_TRIGBUS_DSTR <= '0'; + wait for period; + T_TRIGBUS_DIN <= std_logic_vector(STTAG(7 downto 4)); +-- wait for PERIOD; + T_TRIGBUS_DSTR <= '1'; + wait for period; + T_TRIGBUS_DSTR <= '0'; + wait for period; + T_TRIGBUS_DIN <= "0000"; + -- wait for PERIOD; + T_TRIGBUS_DSTR <= '1'; + wait for period; + T_TRIGBUS_DSTR <= '0'; + wait for period; + end DO_SE_TR2_LVL1; + + + procedure DO_SE_TR2_LVL2(TTAG : in natural; + signal T_TRIGBUS_TSTR : out std_logic; + signal T_TRIGBUS_DSTR : out std_logic; + signal T_TRIGBUS_DIN : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY : in std_logic ) + is + variable STTAG : unsigned(7 downto 0); + begin + wait until T_TRIGBUS_BUSY = '0'; + STTAG := to_unsigned(TTAG, 8); + wait for 0.4*PERIOD; + T_TRIGBUS_TSTR <= '1'; + T_TRIGBUS_DSTR <= '0'; + T_TRIGBUS_DIN <= "0001"; + wait for 0.6*PERIOD; + wait for PERIOD; + T_TRIGBUS_TSTR <= '0'; + wait for 0.8*PERIOD; + T_TRIGBUS_DIN <= "1111"; + wait for 0.2*PERIOD; + T_TRIGBUS_DIN <= std_logic_vector(STTAG(3 downto 0)); +-- wait for PERIOD; + T_TRIGBUS_DSTR <= '1'; + wait for period; + T_TRIGBUS_DSTR <= '0'; + wait for period; + T_TRIGBUS_DIN <= std_logic_vector(STTAG(7 downto 4)); +-- wait for PERIOD; + T_TRIGBUS_DSTR <= '1'; + wait for period; + T_TRIGBUS_DSTR <= '0'; + wait for period; + T_TRIGBUS_DIN <= "0000"; + -- wait for PERIOD; + T_TRIGBUS_DSTR <= '1'; + wait for period; + T_TRIGBUS_DSTR <= '0'; + wait for period; + end DO_SE_TR2_LVL2; + + + +------------------------------------------------------------------------ +-- DO End Run command +------------------------------------------------------------------------ + procedure DO_EN_RU(signal T_TRIGBUS_TSTR : out std_logic; + signal T_TRIGBUS_DSTR : out std_logic; + signal T_TRIGBUS_DIN : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY : in std_logic) + is + begin + wait until T_TRIGBUS_BUSY = '0'; + wait for 0.4*PERIOD; + T_TRIGBUS_TSTR <= '1'; + T_TRIGBUS_DSTR <= '0'; + T_TRIGBUS_DIN <= "0011"; + wait for 0.6*PERIOD; + wait for PERIOD; + T_TRIGBUS_TSTR <= '0'; + wait for 0.8*PERIOD; + T_TRIGBUS_DIN <= "1111"; + wait for 0.2*PERIOD; + for k in 0 to 2 loop + T_TRIGBUS_DIN <= "0000"; +-- wait for PERIOD; + T_TRIGBUS_DSTR <= '1'; + wait for period; + T_TRIGBUS_DSTR <= '0'; + wait for period; + end loop; -- k + + end DO_EN_RU; + + procedure DO_SE_CY(signal T_TRIGBUS_TSTR : out std_logic; + signal T_TRIGBUS_DSTR : out std_logic; + signal T_TRIGBUS_DIN : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY : in std_logic + ) + is + begin + + for k in 0 to 255 loop + DO_SE_TR2_LVL1(k, T_TRIGBUS_TSTR, T_TRIGBUS_DSTR, T_TRIGBUS_DIN, T_TRIGBUS_BUSY); + end loop; -- k + + end DO_SE_CY; + + procedure DO_SE_CY_ALL(signal T_TRIGBUS_TSTR_1 : out std_logic; + signal T_TRIGBUS_DSTR_1 : out std_logic; + signal T_TRIGBUS_DIN_1 : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY_1 : in std_logic; + signal T_TRIGBUS_TSTR_2 : out std_logic; + signal T_TRIGBUS_DSTR_2 : out std_logic; + signal T_TRIGBUS_DIN_2 : out std_logic_vector(3 downto 0); + signal T_TRIGBUS_BUSY_2 : in std_logic + ) + is + begin + + for k in 0 to 255 loop + DO_SE_TR2_LVL1(k, T_TRIGBUS_TSTR_1, T_TRIGBUS_DSTR_1, T_TRIGBUS_DIN_1, T_TRIGBUS_BUSY_1); + DO_SE_TR2_LVL2(k, T_TRIGBUS_TSTR_2, T_TRIGBUS_DSTR_2, T_TRIGBUS_DIN_2, T_TRIGBUS_BUSY_2); + end loop; -- k + + end DO_SE_CY_ALL; + + procedure DO_WAIT + is + begin + wait for 75*PERIOD; + end DO_WAIT; + +end p_trb_net_old_to_new_testbench; diff --git a/testbench/trb_net_old_to_new_testbench.tcl b/testbench/trb_net_old_to_new_testbench.tcl new file mode 100644 index 0000000..d4252eb --- /dev/null +++ b/testbench/trb_net_old_to_new_testbench.tcl @@ -0,0 +1,38 @@ + +# NC-Sim Command File +# TOOL: ncsim 05.70-s005 +# +# +# You can restore this configuration with: +# +# ncsim -update -tcl -gui -cdslib /home/tiago/work/hades/trbnet/ssim/cds.lib -logfile ncsim.log -errormax 15 -status worklib.trb_net_old_to_new_testbench:test -input /home/tiago/work/hades/trbnet/ssim/TRB1.tcl +# + +set tcl_prompt1 {puts -nonewline "ncsim> "} +set tcl_prompt2 {puts -nonewline "> "} +set vlog_format %h +set vhdl_format %v +set real_precision 6 +set display_unit auto +set time_unit module +set assert_report_level note +set assert_stop_level error +set autoscope yes +set assert_1164_warnings yes +set pack_assert_off {} +set severity_pack_assert_off {note warning} +set assert_output_stop_level failed +set tcl_debug_level 0 +set relax_path_name 0 +set vhdl_vcdmap XX01ZX01X +set intovf_severity_level ERROR +set probe_screen_format 0 +set rangecnst_severity_level ERROR +set textio_severity_level ERROR +alias . run +alias quit exit +database -open -shm -into waves.shm waves -default +probe -create -database waves :uut_1:LVL1:CLK_EN :uut_1:LVL1:CLK :uut_1:LVL1:RESET :uut_1:LVL1:OLD_T :uut_1:LVL1:OLD_TS :uut_1:LVL1:OLD_TD :uut_1:LVL1:OLD_TB :uut_1:LVL1:OLD_TE :uut_1:LVL1:APL_DATA_IN :uut_1:LVL1:APL_DATA_OUT :uut_1:LVL1:APL_DATAREADY_IN :uut_1:LVL1:APL_DTYPE_OUT :uut_1:LVL1:APL_ERROR_PATTERN_OUT :uut_1:LVL1:APL_FIFO_FULL_IN :uut_1:LVL1:APL_READ_OUT :uut_1:LVL1:APL_RUN_IN :uut_1:LVL1:APL_SEND_OUT :uut_1:LVL1:APL_SEQNR_IN :uut_1:LVL1:APL_SHORT_TRANSFER_OUT :uut_1:LVL1:APL_TARGET_ADDRESS_OUT :uut_1:LVL1:APL_TYP_IN :uut_1:LVL1:APL_WRITE_OUT :uut_1:LVL1:do_send_cnt :uut_1:LVL1:DVAL_i :uut_1:LVL1:next_state :uut_1:LVL1:present_state :uut_1:LVL1:TRIGCODE_i :uut_1:LVL1:TRIGGER_LEVEL :uut_1:LVL1:TRIGTAG_i :uut_1:LVL1:TRIGTAG_ii :uut_1:LVL1:TRIGTAG_MISMATCH_reg +probe -create -database waves :uut_1:LVL2:CLK :uut_1:LVL2:RESET :uut_1:LVL2:OLD_T :uut_1:LVL2:OLD_TS :uut_1:LVL2:OLD_TD :uut_1:LVL2:OLD_TB :uut_1:LVL2:OLD_TE :uut_1:LVL2:DVAL_i :uut_1:LVL2:present_state :uut_1:LVL2:next_state :uut_1:LVL2:APL_SEND_OUT :uut_1:LVL2:APL_READ_OUT :uut_1:LVL2:APL_RUN_IN :uut_1:LVL2:APL_DTYPE_OUT :uut_1:LVL2:APL_DATA_OUT + +simvision -input /home/tiago/work/hades/trbnet/ssim/TRB1.tcl.sv diff --git a/testbench/trb_net_old_to_new_testbench.tcl.sv b/testbench/trb_net_old_to_new_testbench.tcl.sv new file mode 100644 index 0000000..bf8c297 --- /dev/null +++ b/testbench/trb_net_old_to_new_testbench.tcl.sv @@ -0,0 +1,162 @@ +# SimVision Command Script (Mon Feb 26 17:08:36 CET 2007) +# +# Version 05.70.s005 +# +# You can restore this configuration with: +# +# ncsim -update -tcl -gui -cdslib /home/tiago/work/hades/trbnet/ssim/cds.lib -logfile ncsim.log -errormax 15 -status worklib.trb_net_old_to_new_testbench:test -input /home/tiago/work/hades/trbnet/ssim/TRB1.tcl +# + + +# +# preferences +# +preferences set toolbar-CursorControl-WatchList { + usual + position -row 0 +} +preferences set toolbar-Standard-WatchList { + usual + position -row 1 +} +preferences set toolbar-Edit-WatchList { + usual + shown 0 +} +preferences set toolbar-Windows-SrcBrowser { + usual + hide icheck +} +preferences set toolbar-Windows-WaveWindow { + usual + hide icheck + position -pos 3 +} +preferences set toolbar-Windows-WatchList { + usual + hide icheck + position -pos 2 -anchor w +} +preferences set toolbar-TimeSearch-WatchList { + usual + shown 0 +} + +# +# Simulator +# + +database require simulator -hints { + simulator "ncsim -update -tcl -gui -cdslib /home/tiago/work/hades/trbnet/ssim/cds.lib -logfile ncsim.log -errormax 15 -status worklib.trb_net_old_to_new_testbench:test -input TRB1.tcl" +} + +# +# conditions +# +set expression {bus(:uut_1:LVL2:APL_DATA_OUT[7], :uut_1:LVL2:APL_DATA_OUT[6], :uut_1:LVL2:APL_DATA_OUT[5], :uut_1:LVL2:APL_DATA_OUT[4], :uut_1:LVL2:APL_DATA_OUT[3], :uut_1:LVL2:APL_DATA_OUT[2], :uut_1:LVL2:APL_DATA_OUT[1], :uut_1:LVL2:APL_DATA_OUT[0])} +if {[catch {condition new -name DATA_OUT -expr $expression}] != ""} { + condition set -using DATA_OUT -expr $expression +} + +# +# cursors +# +set time 43545000000fs +if {[catch {cursor new -name TimeA -time $time}] != ""} { + cursor set -using TimeA -time $time +} +set time 120000000000fs +if {[catch {cursor new -name TimeB -time $time}] != ""} { + cursor set -using TimeB -time $time +} +cursor set -using TimeB -marching 1 + +# +# mmaps +# +mmap new -reuse -name {Boolean as Logic} -contents { +{%c=FALSE -edgepriority 1 -shape low} +{%c=TRUE -edgepriority 1 -shape high} +} +mmap new -reuse -name {Example Map} -contents { +{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus} +{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT} +{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT} +{%x=* -label %x -linecolor gray -shape bus} +} + +# +# timeranges +# +timerange new -name LVL1 -start 8890ns -end 10250ns + +# +# Design Browser windows +# +if {[catch {window new WatchList -name "Design Browser 1" -geometry 1082x707+1478+267}] != ""} { + window geometry "Design Browser 1" 1082x707+1478+267 +} +window target "Design Browser 1" on +browser using {Design Browser 1} +browser set \ + -scope :uut_1:LVL2 \ + -showassertions 0 \ + -showfibers 0 \ + -showinouts 0 \ + -showinputs 0 \ + -showinternals 0 +browser yview see :uut_1:LVL2 +browser timecontrol set -lock 0 + +# +# Waveform windows +# +if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1280x963+0+0}] != ""} { + window geometry "Waveform 1" 1280x963+0+0 +} +window target "Waveform 1" on +waveform using {Waveform 1} +waveform sidebar visibility partial +waveform set \ + -primarycursor TimeA \ + -signalnames name \ + -signalwidth 175 \ + -units ns \ + -valuewidth 75 +cursor set -using TimeA -time 43,545,000,000fs +waveform baseline set -time 10,250,000,000fs + +set id [waveform add -signals [list :uut_1:LVL1:CLK_EN \ + :uut_1:LVL1:CLK \ + :uut_1:LVL1:RESET \ + :uut_1:LVL1:OLD_T \ + :uut_1:LVL1:OLD_TS \ + :uut_1:LVL1:OLD_TD \ + :uut_1:LVL1:OLD_TB \ + :uut_1:LVL1:OLD_TE \ + :uut_1:LVL1:present_state \ + :uut_1:LVL1:next_state \ + :uut_1:LVL1:APL_SEND_OUT \ + :uut_1:LVL1:APL_READ_OUT \ + :uut_1:LVL1:APL_RUN_IN \ + :uut_1:LVL1:APL_SEQNR_IN \ + :uut_1:LVL1:APL_DTYPE_OUT \ + DATA_OUT \ + :uut_1:LVL2:CLK \ + :uut_1:LVL2:CLK \ + :uut_1:LVL2:RESET \ + :uut_1:LVL2:OLD_T \ + :uut_1:LVL2:OLD_TS \ + :uut_1:LVL2:OLD_TD \ + :uut_1:LVL2:OLD_TB \ + :uut_1:LVL2:OLD_TE \ + :uut_1:LVL2:DVAL_i \ + :uut_1:LVL2:present_state \ + :uut_1:LVL2:next_state \ + :uut_1:LVL2:APL_SEND_OUT \ + :uut_1:LVL2:APL_READ_OUT \ + :uut_1:LVL2:APL_RUN_IN \ + :uut_1:LVL2:APL_DTYPE_OUT \ + DATA_OUT ]] + +waveform xview limits 0 120000ns diff --git a/testbench/trb_net_old_to_new_testbench.vhd b/testbench/trb_net_old_to_new_testbench.vhd new file mode 100644 index 0000000..8155fc7 --- /dev/null +++ b/testbench/trb_net_old_to_new_testbench.vhd @@ -0,0 +1,284 @@ +------------------------------------------------------------------------------- +-- Title : trb_net_old_to_new_testbench +-- Project : HADES trigger new net +------------------------------------------------------------------------------- +-- File : trb_net_old_to_new_testbench.vhd +-- Author : Tiago Perez (tiago.perez@uni-giessen.de) +-- Created : 2007/02/26 T. Perez +-- Last modified : +------------------------------------------------------------------------------- +-- Description : Testbench for the "trb_net_old_to_new" and the "OLD" trigger +-- bus in general +-- +------------------------------------------------------------------------------- +-- Modification history : +-- 2007/01/12 : created +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; +use std.textio.all; + +use work.p_trb_net_old_to_new_testbench.all; -- package holds procedures defining commads + +entity trb_net_old_to_new_testbench is +end trb_net_old_to_new_testbench; + +architecture TEST of trb_net_old_to_new_testbench is +------------------------------------------------------------------------------- +-- signals declaration +------------------------------------------------------------------------------- + signal SIM_END : boolean := false; + signal CLK : std_logic := '0'; + signal RESET : std_logic; + signal APL_DATA_OUT_LVL1 : std_logic_vector (47 downto 0); + signal APL_WRITE_OUT_LVL1 : std_logic; + signal APL_FIFO_FULL_IN_LVL1 : std_logic; + signal APL_SHORT_TRANSFER_OUT_LVL1 : std_logic; + signal APL_DTYPE_OUT_LVL1 : std_logic_vector (3 downto 0); + signal APL_ERROR_PATTERN_OUT_LVL1 : std_logic_vector (31 downto 0); + signal APL_SEND_OUT_LVL1 : std_logic; + signal APL_TARGET_ADDRESS_OUT_LVL1 : std_logic_vector (15 downto 0); + signal APL_DATA_IN_LVL1 : std_logic_vector (47 downto 0); + signal APL_TYP_IN_LVL1 : std_logic_vector (2 downto 0); + signal APL_DATAREADY_IN_LVL1 : std_logic; + signal APL_READ_OUT_LVL1 : std_logic; + signal APL_RUN_IN_LVL1 : std_logic := '0'; + signal APL_SEQNR_IN_LVL1 : std_logic_vector (7 downto 0) := (others => '0'); + signal OLD_T_LVL1 : std_logic; + signal OLD_TS_LVL1 : std_logic; + signal OLD_TD_LVL1 : std_logic_vector (3 downto 0); + signal OLD_TB_LVL1 : std_logic; + signal OLD_TE_LVL1 : std_logic; + -- + signal APL_DATA_OUT_LVL2 : std_logic_vector (47 downto 0); + signal APL_WRITE_OUT_LVL2 : std_logic; + signal APL_SHORT_TRANSFER_OUT_LVL2 : std_logic; + signal APL_DTYPE_OUT_LVL2 : std_logic_vector (3 downto 0); + signal APL_ERROR_PATTERN_OUT_LVL2 : std_logic_vector (31 downto 0); + signal APL_SEND_OUT_LVL2 : std_logic; + signal APL_TARGET_ADDRESS_OUT_LVL2 : std_logic_vector (15 downto 0); + signal APL_DATA_IN_LVL2 : std_logic_vector (47 downto 0); + signal APL_DATAREADY_IN_LVL2 : std_logic; + signal APL_READ_OUT_LVL2 : std_logic; + signal APL_RUN_IN_LVL2 : std_logic; + signal APL_SEQNR_IN_LVL2 : std_logic_vector (7 downto 0); + signal OLD_T_LVL2 : std_logic; + signal OLD_TS_LVL2 : std_logic; + signal OLD_TD_LVL2 : std_logic_vector (3 downto 0); + signal OLD_TB_LVL2 : std_logic; + signal OLD_TE_LVL2 : std_logic; + ----------------------------------------------------------------------------- + -- componet to test + ----------------------------------------------------------------------------- + component dudu + port ( + CLK : in std_logic; + RESET : in std_logic; + APL_DATA_OUT : out std_logic_vector (47 downto 0); + APL_WRITE_OUT : out std_logic; + APL_FIFO_FULL_IN : in std_logic; + APL_SHORT_TRANSFER_OUT : out std_logic; + APL_DTYPE_OUT : out std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + APL_SEND_OUT : out std_logic; + APL_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0); + APL_DATA_IN : in std_logic_vector (47 downto 0); + APL_TYP_IN : in std_logic_vector (2 downto 0); + APL_DATAREADY_IN : in std_logic; + APL_READ_OUT : out std_logic; + APL_RUN_IN : in std_logic; + APL_SEQNR_IN : in std_logic_vector (7 downto 0); + OLD_T : in std_logic; + OLD_TS : in std_logic; + OLD_TD : in std_logic_vector (3 downto 0); + OLD_TB : out std_logic; + OLD_TE : out std_logic; + APL_DATA_OUT_LVL2 : out std_logic_vector (47 downto 0); + APL_WRITE_OUT_LVL2 : out std_logic; + APL_SHORT_TRANSFER_OUT_LVL2 : out std_logic; + APL_DTYPE_OUT_LVL2 : out std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_OUT_LVL2 : out std_logic_vector (31 downto 0); + APL_SEND_OUT_LVL2 : out std_logic; + APL_TARGET_ADDRESS_OUT_LVL2 : out std_logic_vector (15 downto 0); + APL_DATA_IN_LVL2 : in std_logic_vector (47 downto 0); + APL_DATAREADY_IN_LVL2 : in std_logic; + APL_READ_OUT_LVL2 : out std_logic; + APL_RUN_IN_LVL2 : in std_logic; + APL_SEQNR_IN_LVL2 : in std_logic_vector (7 downto 0); + OLD_T_LVL2 : in std_logic; + OLD_TS_LVL2 : in std_logic; + OLD_TD_LVL2 : in std_logic_vector (3 downto 0); + OLD_TB_LVL2 : out std_logic; + OLD_TE_LVL2 : out std_logic); + end component; + + component trb_reply + port ( + SEND_OUT : in std_logic; + READ_OUT : in std_logic; + RUN_IN : out std_logic; + SEQNR_IN : out std_logic_vector(7 downto 0)); + end component; + +begin + -- Generate CLK + -- CLK <= not CLK after PERIOD/8 when SIM_END = false else '0'; + CLK <= not CLK after 5 ns; -- 100 MHz +-- clock: process +-- begin -- process clock +-- end process clock; + + -- Instantiate the block under test + uut_1 : dudu + port map ( + CLK => CLK, + RESET => RESET, + APL_DATA_OUT => APL_DATA_OUT_LVL1, + APL_WRITE_OUT => APL_WRITE_OUT_LVL1, + APL_FIFO_FULL_IN => APL_FIFO_FULL_IN_LVL1, + APL_SHORT_TRANSFER_OUT => APL_SHORT_TRANSFER_OUT_LVL1, + APL_DTYPE_OUT => APL_DTYPE_OUT_LVL1, + APL_ERROR_PATTERN_OUT => APL_ERROR_PATTERN_OUT_LVL1, + APL_SEND_OUT => APL_SEND_OUT_LVL1, + APL_TARGET_ADDRESS_OUT => APL_TARGET_ADDRESS_OUT_LVL1, + APL_DATA_IN => APL_DATA_IN_LVL1, + APL_TYP_IN => APL_TYP_IN_LVL1, + APL_DATAREADY_IN => APL_DATAREADY_IN_LVL1, + APL_READ_OUT => APL_READ_OUT_LVL1, + APL_RUN_IN => APL_RUN_IN_LVL1, + APL_SEQNR_IN => APL_SEQNR_IN_LVL1, + OLD_T => OLD_T_LVL1, + OLD_TS => OLD_TS_LVL1, + OLD_TD => OLD_TD_LVL1, + OLD_TB => OLD_TB_LVL1, + OLD_TE => OLD_TE_LVL1, + APL_DATA_OUT_LVL2 => APL_DATA_OUT_LVL2, + APL_WRITE_OUT_LVL2 => APL_WRITE_OUT_LVL2, + APL_SHORT_TRANSFER_OUT_LVL2 => APL_SHORT_TRANSFER_OUT_LVL2, + APL_DTYPE_OUT_LVL2 => APL_DTYPE_OUT_LVL2, + APL_ERROR_PATTERN_OUT_LVL2 => APL_ERROR_PATTERN_OUT_LVL2, + APL_SEND_OUT_LVL2 => APL_SEND_OUT_LVL2, + APL_TARGET_ADDRESS_OUT_LVL2 => APL_TARGET_ADDRESS_OUT_LVL2, + APL_DATA_IN_LVL2 => APL_DATA_IN_LVL2, + APL_DATAREADY_IN_LVL2 => APL_DATAREADY_IN_LVL2, + APL_READ_OUT_LVL2 => APL_READ_OUT_LVL2, + APL_RUN_IN_LVL2 => APL_RUN_IN_LVL2, + APL_SEQNR_IN_LVL2 => APL_SEQNR_IN_LVL2, + OLD_T_LVL2 => OLD_T_LVL2, + OLD_TS_LVL2 => OLD_TS_LVL2, + OLD_TD_LVL2 => OLD_TD_LVL2, + OLD_TB_LVL2 => OLD_TB_LVL2, + OLD_TE_LVL2 => OLD_TE_LVL2); + trb_LVL1 : trb_reply + port map ( + SEND_OUT => APL_SEND_OUT_LVL1, + READ_OUT => APL_READ_OUT_LVL1, + RUN_IN => APL_RUN_IN_LVL1, + SEQNR_IN => APL_SEQNR_IN_LVL1); + trb_LVL2 : trb_reply + port map ( + SEND_OUT => APL_SEND_OUT_LVL2, + READ_OUT => APL_READ_OUT_LVL2, + RUN_IN => APL_RUN_IN_LVL2, + SEQNR_IN => APL_SEQNR_IN_LVL2); +------------------------------------------------------------------------ +-- COMMAND INPUT process +-- This process reads command strings from the test file "command.txt" +-- and generates input stimulus to the block under test, depending upon +-- which command is read in. The commands are: +-- +-- RESET -- reset the board +-- BE_RU -- send a begin_run trigger +-- SE_TR D DDD -- send normal trigger on LVL D with tag DDD +-- SEXCY -- send a complete 256 trigger cycle to +-- LVL X where X is 1,2 or A for all +-- EN_RU -- end the run +-- VME_R DD -- simulate a VME Read Cycle on address +-- -- DD +-- WAIT_ -- waits 300*PERIOD +-- (D = integer ascii character in range 0-9) +------------------------------------------------------------------------ + COMMAND_INPUT : process + --file COMFILE : text is in "command.txt"; '87 + file COMFILE : text open read_mode is "command.txt"; + variable L : line; + variable CMD : string(1 to 5); + variable SETTING : string(1 to 3); + variable LVL : character; + variable CYCLES, SEPARATOR : character; + begin + --------------------------------------------------------------------------- + -- SET INITIAL VALUES + --------------------------------------------------------------------------- + -- set all to '0' + --------------------------------------------------------------------------- + -- TrigBus + -- lvl1 + OLD_TS_LVL1 <= '0'; + -- lvl2 + OLD_T_LVL2 <= '0'; + OLD_TS_LVL2 <= '0'; + OLD_TD_LVL2 <= (others => '0'); + + --------------------------------------------------------------------------- + -- READ COMMAND FILE + --------------------------------------------------------------------------- + -- if there are still lines to read in the text file ... + while not ENDFILE(COMFILE) loop + + -- read in next line from text file, then read the first text string + -- from the line and call this CMD. + readline(COMFILE, L); + read (L, CMD); + + -- Depending on what the command is, read in any extra information + -- from the line read from the file and then "do" the command + case CMD is + when "RST__" => assert false report "Reset" severity note; + DO_RESET(RESET); + + when "BE_RU" => assert false report "Begin Trigger to be send..." severity note; + DO_BE_RU(OLD_T_LVL1, OLD_TS_LVL1, OLD_TD_LVL1, OLD_TB_LVL1); + when "SE_TR" => read (L, SEPARATOR); + read (L, LVL); + if LVL = '1' then + read (L, SEPARATOR); + read (L, SETTING); + assert false report "Normal Trigger LVL 1 to be send..." severity note; + DO_SE_TR_LVL1(SETTING, OLD_T_LVL1, OLD_TS_LVL1, OLD_TD_LVL1, OLD_TB_LVL1); + end if; + if LVL = '2' then + read (L, SEPARATOR); + read (L, SETTING); + assert false report "Normal Trigger LVL 2 to be send..." severity note; + DO_SE_TR_LVL2(SETTING, OLD_T_LVL2, OLD_TS_LVL2, OLD_TD_LVL2, OLD_TB_LVL2); + end if; +-- when "SE1CY" => DO_SE_CY(T_TRIGBUS_TSTR_LVL1_i, T_TRIGBUS_DSTR_LVL1_i, T_TRIGBUS_DIN_LVL1_i, T_TRIGBUS_BUSY_LVL1_i); +-- when "SE2CY" => DO_SE_CY(T_TRIGBUS_TSTR_LVL2_i, T_TRIGBUS_DSTR_LVL2_i, T_TRIGBUS_DIN_LVL2_i, T_TRIGBUS_BUSY_LVL2_i); +-- when "SEACY" => DO_SE_CY_ALL(T_TRIGBUS_TSTR_LVL1_i, T_TRIGBUS_DSTR_LVL1_i, T_TRIGBUS_DIN_LVL1_i, T_TRIGBUS_BUSY_LVL1_i, +-- T_TRIGBUS_TSTR_LVL2_i, T_TRIGBUS_DSTR_LVL2_i, T_TRIGBUS_DIN_LVL2_i, T_TRIGBUS_BUSY_LVL2_i); + when "EN_RU" => DO_EN_RU(OLD_T_LVL1, OLD_TS_LVL1, OLD_TD_LVL1, OLD_TB_LVL1); + when "WAIT_" => assert false report "Wait" severity note; + DO_WAIT; + when others => assert false report "Unrecognised Instruction" + severity failure; + end case; + + end loop; + + -- No new lines to read from file, so report simulation complete and + -- stop clock generator with SIM_END signal + assert false report "Simulation complete" severity note; + SIM_END <= true; + + wait; + + end process COMMAND_INPUT; + +end TEST; + + + + diff --git a/testbench/trb_net_old_to_new_trb_reply.vhd b/testbench/trb_net_old_to_new_trb_reply.vhd new file mode 100644 index 0000000..10cec6b --- /dev/null +++ b/testbench/trb_net_old_to_new_trb_reply.vhd @@ -0,0 +1,53 @@ +------------------------------------------------------------------------------- +-- Title : trb_reply +-- Project : HADES trigger new net +------------------------------------------------------------------------------- +-- File : trb_reply.vhd +-- Author : Tiago Perez (tiago.perez@uni-giessen.de) +-- Created : 2007/02/26 T. Perez +-- Last modified : +------------------------------------------------------------------------------- +-- Description : Black box. Reply the TRB comm protocol +------------------------------------------------------------------------------- +-- Modification history : +-- 2007/01/12 : created +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + + +entity trb_reply is + port ( + SEND_OUT : in std_logic; + READ_OUT : in std_logic; + RUN_IN : out std_logic; + SEQNR_IN : out std_logic_vector(7 downto 0) + ); +end trb_reply; + +architecture behavioral of trb_reply is + + signal SEQNR : std_logic_vector(7 downto 0) := (others => '0'); +begin -- behavioral +-- purpose: simulate TRB +-- type : combinational +-- inputs : +-- outputs: + TRB_SIM: process + begin -- process TRB_SIM + wait until SEND_OUT = '1'; -- rise + wait until SEND_OUT = '0'; -- fall + wait for 1 ns; + RUN_IN <= '1'; + wait until READ_OUT ='1'; + wait until READ_OUT ='0'; + wait for 3 ns; + RUN_IN <= '0'; + SEQNR <= SEQNR + 1; + end process TRB_SIM; + SEQNR_IN <= SEQNR; + + +end behavioral;