From: hadeshyp Date: Tue, 4 Mar 2008 19:02:04 +0000 (+0000) Subject: *** empty log message *** X-Git-Tag: oldGBE~587 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b352ac1c8083114f4469f25adfb9a12441b47b00;p=trbnet.git *** empty log message *** --- diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd index 0f6c4cf..fc79df1 100644 --- a/trb_net16_med_tlk.vhd +++ b/trb_net16_med_tlk.vhd @@ -185,8 +185,8 @@ begin STAT(7) <= fifo_empty_m; STAT(8) <= fifo_full_a; STAT(9) <= fifo_full_m; - STAT(10)<= last_fifo_rd_en_m; - STAT(11)<= last_fifo_rd_en_a; +-- STAT(10)<= last_fifo_rd_en_m; +-- STAT(11)<= last_fifo_rd_en_a; STAT(12)<= fifo_almost_empty_m; STAT(13)<= fifo_almost_empty_a; STAT(14) <= reg_RX_DV; @@ -234,17 +234,6 @@ begin end if; end process; - process(CLK) - begin - if rising_edge(CLK) then - if internal_reset = '1' then - last_fifo_rd_en_a <= '0'; - else - last_fifo_rd_en_a <= fifo_rd_en_a and not fifo_empty_a; - end if; - end if; - end process; - --common network packet number reset reset_packet_num <= '0'; @@ -309,7 +298,7 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); fifo_wr_en_m <= '0'; fifo_din_m <= (others => '0'); else - fifo_wr_en_m <= (MED_DATAREADY_IN and buf_MED_READ_OUT) or fifo_almost_empty_m; + fifo_wr_en_m <= (MED_DATAREADY_IN and buf_MED_READ_OUT);-- or fifo_almost_empty_m; fifo_din_m <= fifo_almost_empty_m & (MED_DATAREADY_IN and buf_MED_READ_OUT) & MED_DATA_IN; end if; end if; @@ -321,14 +310,11 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); begin if rising_edge(TLK_CLK_neg) then if internal_reset = '1' then + reg_TX_EN <= '0'; reg_TXD <= (others => '0'); - --reg_TX_EN <= '0'; - --fifo_rd_en_m <= '0'; - last_fifo_rd_en_m <= '0'; else reg_TXD <= fifo_dout_m(15 downto 0); reg_TX_EN <= fifo_valid_read_m and fifo_dout_m(16) and not fifo_underflow_m; --last_fifo_rd_en_m; - last_fifo_rd_en_m <= fifo_rd_en_m and not fifo_empty_m; end if; end if; end process; diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 605c68e..0070508 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -14,7 +14,7 @@ package trb_net_std is constant c_DATA_WIDTH : integer := 16; constant c_NUM_WIDTH : integer := 2; - constant c_MUX_WIDTH : integer := 3; --!!! + constant c_MUX_WIDTH : integer := 1; --!!! --assigning channel names diff --git a/xilinx/virtex2/simulation/xilinx_fifo_18x1k.vhd b/xilinx/virtex2/simulation/xilinx_fifo_18x1k.vhd index 5885ba4..7a10a72 100644 --- a/xilinx/virtex2/simulation/xilinx_fifo_18x1k.vhd +++ b/xilinx/virtex2/simulation/xilinx_fifo_18x1k.vhd @@ -23,7 +23,7 @@ -- appliances, devices, or systems. Use in such applications are -- -- expressly prohibited. -- -- -- --- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -- You must compile the wrapper file xilinx_fifo_18x1k.vhd when simulating @@ -31,22 +31,21 @@ -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". --- The synthesis directives "translate_off/translate_on" specified --- below are supported by Xilinx, Mentor Graphics and Synplicity +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; --- synthesis translate_off +-- synopsys translate_off Library XilinxCoreLib; --- synthesis translate_on +-- synopsys translate_on ENTITY xilinx_fifo_18x1k IS port ( + clk: IN std_logic; din: IN std_logic_VECTOR(17 downto 0); - rd_clk: IN std_logic; rd_en: IN std_logic; rst: IN std_logic; - wr_clk: IN std_logic; wr_en: IN std_logic; dout: OUT std_logic_VECTOR(17 downto 0); empty: OUT std_logic; @@ -54,14 +53,13 @@ ENTITY xilinx_fifo_18x1k IS END xilinx_fifo_18x1k; ARCHITECTURE xilinx_fifo_18x1k_a OF xilinx_fifo_18x1k IS --- synthesis translate_off +-- synopsys translate_off component wrapped_xilinx_fifo_18x1k port ( + clk: IN std_logic; din: IN std_logic_VECTOR(17 downto 0); - rd_clk: IN std_logic; rd_en: IN std_logic; rst: IN std_logic; - wr_clk: IN std_logic; wr_en: IN std_logic; dout: OUT std_logic_VECTOR(17 downto 0); empty: OUT std_logic; @@ -69,22 +67,15 @@ component wrapped_xilinx_fifo_18x1k end component; -- Configuration specification - for all : wrapped_xilinx_fifo_18x1k use entity XilinxCoreLib.fifo_generator_v4_2(behavioral) + for all : wrapped_xilinx_fifo_18x1k use entity XilinxCoreLib.fifo_generator_v2_1(behavioral) generic map( - c_has_int_clk => 0, - c_rd_freq => 1, c_wr_response_latency => 1, - c_has_srst => 0, c_has_rd_data_count => 0, c_din_width => 18, c_has_wr_data_count => 0, - c_full_flags_rst_val => 1, - c_implementation_type => 2, - c_family => "virtex4", - c_use_embedded_reg => 0, + c_implementation_type => 0, + c_family => "virtex2", c_has_wr_rst => 0, - c_wr_freq => 1, - c_use_dout_rst => 0, c_underflow_low => 0, c_has_meminit_file => 0, c_has_overflow => 0, @@ -97,53 +88,49 @@ end component; c_has_rd_rst => 0, c_has_almost_full => 0, c_has_rst => 1, - c_data_count_width => 10, + c_data_count_width => 2, c_has_wr_ack => 0, - c_use_ecc => 0, c_wr_ack_low => 0, - c_common_clock => 0, + c_common_clock => 1, c_rd_pntr_width => 10, - c_use_fwft_data_count => 0, c_has_almost_empty => 0, - c_rd_data_count_width => 10, + c_rd_data_count_width => 2, c_enable_rlocs => 0, c_wr_pntr_width => 10, c_overflow_low => 0, c_prog_empty_type => 0, c_optimization_mode => 0, - c_wr_data_count_width => 10, + c_wr_data_count_width => 2, c_preload_regs => 0, c_dout_rst_val => "0", c_has_data_count => 0, - c_prog_full_thresh_negate_val => 1020, + c_prog_full_thresh_negate_val => 768, c_wr_depth => 1024, - c_prog_empty_thresh_negate_val => 3, - c_prog_empty_thresh_assert_val => 2, + c_prog_empty_thresh_negate_val => 256, + c_prog_empty_thresh_assert_val => 256, c_has_valid => 0, c_init_wr_pntr_val => 0, - c_prog_full_thresh_assert_val => 1021, - c_use_fifo16_flags => 0, + c_prog_full_thresh_assert_val => 768, c_has_backup => 0, c_valid_low => 0, - c_prim_fifo_type => "1kx18", + c_prim_fifo_type => 1024, c_count_type => 0, c_prog_full_type => 0, c_memory_type => 1); --- synthesis translate_on +-- synopsys translate_on BEGIN --- synthesis translate_off +-- synopsys translate_off U0 : wrapped_xilinx_fifo_18x1k port map ( + clk => clk, din => din, - rd_clk => rd_clk, rd_en => rd_en, rst => rst, - wr_clk => wr_clk, wr_en => wr_en, dout => dout, empty => empty, full => full); --- synthesis translate_on +-- synopsys translate_on END xilinx_fifo_18x1k_a; diff --git a/xilinx/virtex2/trb_net16_fifo_arch.vhd b/xilinx/virtex2/trb_net16_fifo_arch.vhd index 3fa402c..58f0d3b 100644 --- a/xilinx/virtex2/trb_net16_fifo_arch.vhd +++ b/xilinx/virtex2/trb_net16_fifo_arch.vhd @@ -5,26 +5,26 @@ USE ieee.std_logic_signed.ALL; USE IEEE.numeric_std.ALL; use work.trb_net_std.all; --- entity trb_net16_fifo is --- generic ( --- USE_VENDOR_CORES : integer range 0 to 1 := c_NO; --- DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets --- ); --- port ( --- CLK : in std_logic; --- RESET : in std_logic; --- CLK_EN : in std_logic; --- DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data --- PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data --- WRITE_ENABLE_IN : in std_logic; --- DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data --- PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data --- READ_ENABLE_IN : in std_logic; --- FULL_OUT : out std_logic; -- Full Flag --- EMPTY_OUT : out std_logic; --- DEPTH_OUT : out std_logic_vector(7 downto 0) --- ); --- end entity; +entity trb_net16_fifo is + generic ( + USE_VENDOR_CORES : integer range 0 to 1 := c_NO; + DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data + PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; -- Full Flag + EMPTY_OUT : out std_logic; + DEPTH_OUT : out std_logic_vector(7 downto 0) + ); +end entity; architecture arch_trb_net16_fifo of trb_net16_fifo is component xilinx_fifo_18x1k diff --git a/xilinx/virtex2/xilinx_fifo_18x1k.xco b/xilinx/virtex2/xilinx_fifo_18x1k.xco index 6e71e3f..104ed7f 100644 --- a/xilinx/virtex2/xilinx_fifo_18x1k.xco +++ b/xilinx/virtex2/xilinx_fifo_18x1k.xco @@ -1,81 +1,64 @@ -############################################################## -# -# Xilinx Core Generator version J.40 -# Date: Mon Feb 25 12:14:22 2008 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# # BEGIN Project Options -SET addpads = False +SET flowvendor = Foundation_iSE +SET vhdlsim = True +SET verilogsim = True +SET workingdirectory = . +SET speedgrade = -5 +SET simulationfiles = Behavioral SET asysymbol = True +SET addpads = False +SET device = xc2v250 +SET implementationfiletype = Edif SET busformat = BusFormatAngleBracketNotRipped +SET foundationsym = False +SET package = fg456 SET createndf = False SET designentry = VHDL -SET device = xc2v2000 SET devicefamily = virtex2 -SET flowvendor = Foundation_iSE SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = fg676 SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -6 -SET verilogsim = True -SET vhdlsim = True # END Project Options # BEGIN Select -SELECT Fifo_Generator family Xilinx,_Inc. 4.2 +SELECT Fifo_Generator family Xilinx,_Inc. 2.1 # END Select # BEGIN Parameters CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET component_name=xilinx_fifo_18x1k -CSET data_count=false -CSET data_count_width=10 -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=19 -CSET empty_threshold_negate_value=20 -CSET enable_ecc=false -CSET enable_int_clk=false -CSET fifo_implementation=Common_Clock_Builtin_FIFO -CSET full_flags_reset_value=0 -CSET full_threshold_assert_value=1035 -CSET full_threshold_negate_value=1034 -CSET input_data_width=18 -CSET input_depth=1024 +CSET write_data_count=false +CSET full_threshold_negate_value=768 +CSET empty_threshold_negate_value=256 CSET output_data_width=18 -CSET output_depth=1024 -CSET overflow_flag=false -CSET overflow_sense=Active_High -CSET performance_options=Standard_FIFO +CSET input_depth=1024 +CSET valid_flag=false +CSET empty_threshold_negate_presets=3/4_Empty +CSET write_acknowledge_flag=false CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET read_clock_frequency=1 -CSET read_data_count=false -CSET read_data_count_width=10 -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset +CSET full_threshold_negate_presets=3/4_Full +CSET fifo_implementation=Common_Clock_Block_RAM CSET underflow_flag=false -CSET underflow_sense=Active_High -CSET use_dout_reset=false -CSET use_embedded_registers=false CSET use_extra_logic=false -CSET valid_flag=false +CSET register_outputs=false CSET valid_sense=Active_High -CSET write_acknowledge_flag=false +CSET write_data_count_width=2 +CSET data_count_width=2 +CSET output_depth=1024 +CSET dout_reset_value=0 +CSET underflow_sense=Active_High +CSET component_name=xilinx_fifo_18x1k +CSET overflow_sense=Active_High +CSET overflow_flag=false +CSET read_data_count=false +CSET data_count=false +CSET primitive_depth=1024 +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_data_count_width=2 +CSET read_latency=1 +CSET empty_threshold_assert_presets=3/4_Empty +CSET full_threshold_assert_value=768 +CSET almost_full_flag=false +CSET full_threshold_assert_presets=3/4_Full CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=false -CSET write_data_count_width=10 +CSET empty_threshold_assert_value=256 +CSET input_data_width=18 # END Parameters GENERATE -# CRC: 605fb23