From: Adrian Weber Date: Mon, 15 Nov 2021 10:33:29 +0000 (+0100) Subject: ECP5 files for GbE support X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b3dfeb245c477494ab6fa56b56d3fc07845b9632;p=trbnet.git ECP5 files for GbE support --- diff --git a/gbe_trb/base/gbe_med_interface_ExtClk.vhd b/gbe_trb/base/gbe_med_interface_ExtClk.vhd new file mode 100644 index 0000000..3b17e43 --- /dev/null +++ b/gbe_trb/base/gbe_med_interface_ExtClk.vhd @@ -0,0 +1,891 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +use work.trb_net_gbe_components.all; +use work.config.all; + +entity gbe_med_interface is + generic ( + DO_SIMULATION : integer range 0 to 1; + NUMBER_OF_GBE_LINKS : integer range 1 to 4; + LINKS_ACTIVE : std_logic_vector(3 downto 0) + ); + port ( + RESET : in std_logic; + GSR_N : in std_logic; + CLK_SYS_IN : in std_logic; + CLK_125_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + CLK_125_IN : in std_logic; + CLK_125_RX_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + -- MAC status and config + MAC_READY_CONF_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RECONF_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_AN_READY_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + -- MAC data interface + MAC_FIFOAVAIL_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_FIFOEOF_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_FIFOEMPTY_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_FIFOFULL_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + MAC_TX_DATA_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + MAC_TX_READ_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_DISCRFRM_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_STAT_EN_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_STATS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 31 - 1 downto 0); + MAC_TX_DONE_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + MAC_RX_FIFO_ERR_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_STATS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 32 - 1 downto 0); + MAC_RX_DATA_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + MAC_RX_WRITE_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_STAT_EN_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_EOF_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_ERROR_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + --SFP Connection + SD_RXD_P_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_RXD_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_TXD_P_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_TXD_N_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_PRSNT_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_LOS_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + --CONTROL INTERFACE + BUS_SCI_RX : in CTRLBUS_RX; + BUS_SCI_TX : out CTRLBUS_TX; + + DEBUG_OUT : out std_logic_vector(255 downto 0) + ); +end entity gbe_med_interface; + +architecture RTL of gbe_med_interface is + + component sgmii_gbe_pcs35_core +port( rst_n : in std_logic; + signal_detect : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + operational_rate : in std_logic_vector(1 downto 0); + debug_link_timer_short : in std_logic; + + force_isolate : in std_logic; + force_loopback : in std_logic; + force_unidir : in std_logic; + + rx_compensation_err : out std_logic; + + ctc_drop_flag : out std_logic; + ctc_add_flag : out std_logic; + an_link_ok : out std_logic; + + tx_clk_125 : in std_logic; + tx_clock_enable_source : out std_logic; + tx_clock_enable_sink : in std_logic; + tx_d : in std_logic_vector(7 downto 0); + tx_en : in std_logic; + tx_er : in std_logic; + rx_clk_125 : in std_logic; + rx_clock_enable_source : out std_logic; + rx_clock_enable_sink : in std_logic; + rx_d : out std_logic_vector(7 downto 0); + rx_dv : out std_logic; + rx_er : out std_logic; + col : out std_logic; + crs : out std_logic; + tx_data : out std_logic_vector(7 downto 0); + tx_kcntl : out std_logic; + tx_disparity_cntl : out std_logic; + + xmit_autoneg : out std_logic; + + serdes_recovered_clk : in std_logic; + rx_data : in std_logic_vector(7 downto 0); + rx_even : in std_logic; + rx_kcntl : in std_logic; + rx_disp_err : in std_logic; + rx_cv_err : in std_logic; + rx_err_decode_mode : in std_logic; + mr_an_complete : out std_logic; + mr_page_rx : out std_logic; + mr_lp_adv_ability : out std_logic_vector(15 downto 0); + mr_main_reset : in std_logic; + mr_an_enable : in std_logic; + mr_restart_an : in std_logic; + mr_adv_ability : in std_logic_vector(15 downto 0) + ); +end component; + +component reset_controller_pcs port ( + rst_n : in std_logic; + clk : in std_logic; + tx_plol : in std_logic; + rx_cdr_lol : in std_logic; + quad_rst_out : out std_logic; + tx_pcs_rst_out : out std_logic; + rx_pcs_rst_out : out std_logic + ); +end component; +component reset_controller_cdr port ( + rst_n : in std_logic; + clk : in std_logic; + cdr_lol : in std_logic; + cdr_rst_out : out std_logic + ); +end component; + +component rate_resolution port ( + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + an_enable : in std_logic; + advertised_rate : in std_logic_vector(1 downto 0); + link_partner_rate : in std_logic_vector(1 downto 0); + non_an_rate : in std_logic_vector(1 downto 0); + operational_rate : out std_logic_vector(1 downto 0) + ); +end component; + +component register_interface_hb port ( + rst_n : in std_logic; + hclk : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + hcs_n : in std_logic; + hwrite_n : in std_logic; + haddr : in std_logic_vector(3 downto 0); + hdatain : in std_logic_vector(7 downto 0); + hdataout : out std_logic_vector(7 downto 0); + hready_n : out std_logic; + mr_an_complete : in std_logic; + mr_page_rx : in std_logic; + mr_lp_adv_ability : in std_logic_vector(15 downto 0); + mr_main_reset : out std_logic; + mr_an_enable : out std_logic; + mr_restart_an : out std_logic; + mr_adv_ability : out std_logic_vector(15 downto 0) + ); +end component; + +component tsmac35 --tsmac36 --tsmac35 +port( + --------------- clock and reset port declarations ------------------ + hclk : in std_logic; + txmac_clk : in std_logic; + rxmac_clk : in std_logic; + reset_n : in std_logic; + txmac_clk_en : in std_logic; + rxmac_clk_en : in std_logic; + ------------------- Input signals to the GMII ---------------- + rxd : in std_logic_vector(7 downto 0); + rx_dv : in std_logic; + rx_er : in std_logic; + col : in std_logic; + crs : in std_logic; + -------------------- Input signals to the CPU I/F ------------------- + haddr : in std_logic_vector(7 downto 0); + hdatain : in std_logic_vector(7 downto 0); + hcs_n : in std_logic; + hwrite_n : in std_logic; + hread_n : in std_logic; + ---------------- Input signals to the Tx MAC FIFO I/F --------------- + tx_fifodata : in std_logic_vector(7 downto 0); + tx_fifoavail : in std_logic; + tx_fifoeof : in std_logic; + tx_fifoempty : in std_logic; + tx_sndpaustim : in std_logic_vector(15 downto 0); + tx_sndpausreq : in std_logic; + tx_fifoctrl : in std_logic; + ---------------- Input signals to the Rx MAC FIFO I/F --------------- + rx_fifo_full : in std_logic; + ignore_pkt : in std_logic; + -------------------- Output signals from the GMII ----------------------- + txd : out std_logic_vector(7 downto 0); + tx_en : out std_logic; + tx_er : out std_logic; + -------------------- Output signals from the CPU I/F ------------------- + hdataout : out std_logic_vector(7 downto 0); + hdataout_en_n : out std_logic; + hready_n : out std_logic; + cpu_if_gbit_en : out std_logic; + ---------------- Output signals from the Tx MAC FIFO I/F --------------- + tx_macread : out std_logic; + tx_discfrm : out std_logic; + tx_staten : out std_logic; + tx_done : out std_logic; + tx_statvec : out std_logic_vector(30 downto 0); + ---------------- Output signals from the Rx MAC FIFO I/F --------------- + rx_fifo_error : out std_logic; + rx_stat_vector : out std_logic_vector(31 downto 0); + rx_dbout : out std_logic_vector(7 downto 0); + rx_write : out std_logic; + rx_stat_en : out std_logic; + rx_eof : out std_logic; + rx_error : out std_logic +); +end component; + + signal sd_rx_clk : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_tx_kcntl_q, sd_tx_kcntl : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_tx_data_q, sd_tx_data : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal xmit : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_tx_correct_disp_q, sd_tx_correct_disp : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_rx_data, sd_rx_data_q : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal sd_rx_kcntl, sd_rx_kcntl_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_rx_disp_error, sd_rx_disp_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_rx_cv_error, sd_rx_cv_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tx_power, rx_power : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal los, signal_detected : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal rx_cdr_lol: std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tx_pll_lol, quad_rst : std_logic; + signal tx_pcs_rst, rx_pcs_rst, rx_serdes_rst : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + --signal rst_n : std_logic; + signal rx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal operational_rate : std_logic_vector(NUMBER_OF_GBE_LINKS * 2 - 1 downto 0); + signal an_complete : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_page_rx : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_lp_adv_ability : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0); + signal mr_main_reset : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_restart_an : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_adv_ability : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0); + signal mr_an_enable : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_rxd, pcs_rxd_q, pcs_rxd_qq : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal pcs_rx_en, pcs_rx_en_q, pcs_rx_en_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_rx_er, pcs_rx_er_q, pcs_rx_er_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_col, pcs_crs : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_txd, pcs_txd_q, pcs_txd_qq : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal pcs_tx_en, pcs_tx_en_q, pcs_tx_en_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_tx_er, pcs_tx_er_q, pcs_tx_er_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hdataout_en_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hready_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hread_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hwrite_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hcs_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hdata : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal tsm_haddr : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal rx_compensation_err, an_link_ok : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + signal synced_rst, ff : std_logic; + + signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal rsl_rx_rdy,rsl_tx_rdy : std_logic; + + signal sci_data_in_i : std_logic_vector(7 downto 0); + signal sci_addr_i : std_logic_vector(5 downto 0); + signal sci_data_out_i : std_logic_vector(7 downto 0); + signal reset_n, sci_read_i, sci_write_i : std_logic; + signal sci_ch_i : std_logic_vector(4 downto 0); + signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; + signal wa_position_sel : std_logic_vector(3 downto 0); + + signal stat_fsm_reset_i, stat_tx_control_i, stat_rx_control_i : std_logic_vector(31 downto 0); + signal cnt_125_dbg : unsigned(30 downto 0) := (others => '0'); + +begin + + rx_power <= "1111"; + tx_power <= "1111"; + + --rst_n <= not RESET; + + reset_sync : process(GSR_N, CLK_SYS_IN) + begin + if (GSR_N = '0') then + ff <= '0'; + synced_rst <= '0'; + elsif rising_edge(CLK_SYS_IN) then + ff <= '1'; + synced_rst <= ff; + end if; + end process reset_sync; + + SD_TXDIS_OUT <= "0000"; + + CLK_125_OUT <= CLK_125_IN & CLK_125_IN & CLK_125_IN & CLK_125_IN; + CLK_125_RX_OUT <= sd_rx_clk; + + impl_gen : if DO_SIMULATION = 0 generate + + serdes_ch4_gen : if FPGA_TYPE /= 5 generate + gbe_serdes : entity work.serdes_gbe_4ch + port map( + ------------------ + -- CH0 -- + hdinp_ch0 => SD_RXD_P_IN(0), + hdinn_ch0 => SD_RXD_N_IN(0), + hdoutp_ch0 => SD_TXD_P_OUT(0), + hdoutn_ch0 => SD_TXD_N_OUT(0), + rxiclk_ch0 => sd_rx_clk(0), + txiclk_ch0 => CLK_125_IN, + rx_full_clk_ch0 => sd_rx_clk(0), + rx_half_clk_ch0 => open, + tx_full_clk_ch0 => open, + tx_half_clk_ch0 => open, + fpga_rxrefclk_ch0 => CLK_125_IN, + txdata_ch0 => sd_tx_data_q(7 downto 0), + tx_k_ch0 => sd_tx_kcntl_q(0), + xmit_ch0 => xmit(0), + tx_disp_correct_ch0 => sd_tx_correct_disp_q(0), + rxdata_ch0 => sd_rx_data(7 downto 0), + rx_k_ch0 => sd_rx_kcntl(0), + rx_disp_err_ch0 => sd_rx_disp_error(0), + rx_cv_err_ch0 => sd_rx_cv_error(0), + rx_serdes_rst_ch0_c => rx_serdes_rst(0), + sb_felb_ch0_c => '0', + sb_felb_rst_ch0_c => '0', + tx_pwrup_ch0_c => tx_power(0), + rx_pwrup_ch0_c => rx_power(0), + rx_los_low_ch0_s => los(0), + lsm_status_ch0_s => signal_detected(0), + rx_cdr_lol_ch0_s => rx_cdr_lol(0), + tx_pcs_rst_ch0_c => tx_pcs_rst(0), + rx_pcs_rst_ch0_c => rx_pcs_rst(0), + -- CH1 -- + hdinp_ch1 => SD_RXD_P_IN(1), + hdinn_ch1 => SD_RXD_N_IN(1), + hdoutp_ch1 => SD_TXD_P_OUT(1), + hdoutn_ch1 => SD_TXD_N_OUT(1), + rxiclk_ch1 => sd_rx_clk(1), + txiclk_ch1 => CLK_125_IN, + rx_full_clk_ch1 => sd_rx_clk(1), + rx_half_clk_ch1 => open, + tx_full_clk_ch1 => open, + tx_half_clk_ch1 => open, + fpga_rxrefclk_ch1 => CLK_125_IN, + txdata_ch1 => sd_tx_data_q(15 downto 8), + tx_k_ch1 => sd_tx_kcntl_q(1), + xmit_ch1 => xmit(1), + tx_disp_correct_ch1 => sd_tx_correct_disp_q(1), + rxdata_ch1 => sd_rx_data(15 downto 8), + rx_k_ch1 => sd_rx_kcntl(1), + rx_disp_err_ch1 => sd_rx_disp_error(1), + rx_cv_err_ch1 => sd_rx_cv_error(1), + rx_serdes_rst_ch1_c => rx_serdes_rst(1), + sb_felb_ch1_c => '0', + sb_felb_rst_ch1_c => '0', + tx_pwrup_ch1_c => tx_power(1), + rx_pwrup_ch1_c => rx_power(1), + rx_los_low_ch1_s => los(1), + lsm_status_ch1_s => signal_detected(1), + rx_cdr_lol_ch1_s => rx_cdr_lol(1), + tx_pcs_rst_ch1_c => tx_pcs_rst(1), + rx_pcs_rst_ch1_c => rx_pcs_rst(1), + -- CH2 -- + hdinp_ch2 => SD_RXD_P_IN(2), + hdinn_ch2 => SD_RXD_N_IN(2), + hdoutp_ch2 => SD_TXD_P_OUT(2), + hdoutn_ch2 => SD_TXD_N_OUT(2), + rxiclk_ch2 => sd_rx_clk(2), + txiclk_ch2 => CLK_125_IN, + rx_full_clk_ch2 => sd_rx_clk(2), + rx_half_clk_ch2 => open, + tx_full_clk_ch2 => open, + tx_half_clk_ch2 => open, + fpga_rxrefclk_ch2 => CLK_125_IN, + txdata_ch2 => sd_tx_data_q(23 downto 16), + tx_k_ch2 => sd_tx_kcntl_q(2), + xmit_ch2 => xmit(2), + tx_disp_correct_ch2 => sd_tx_correct_disp_q(2), + rxdata_ch2 => sd_rx_data(23 downto 16), + rx_k_ch2 => sd_rx_kcntl(2), + rx_disp_err_ch2 => sd_rx_disp_error(2), + rx_cv_err_ch2 => sd_rx_cv_error(2), + rx_serdes_rst_ch2_c => rx_serdes_rst(2), + sb_felb_ch2_c => '0', + sb_felb_rst_ch2_c => '0', + tx_pwrup_ch2_c => tx_power(2), + rx_pwrup_ch2_c => rx_power(2), + rx_los_low_ch2_s => los(2), + lsm_status_ch2_s => signal_detected(2), + rx_cdr_lol_ch2_s => rx_cdr_lol(2), + tx_pcs_rst_ch2_c => tx_pcs_rst(2), + rx_pcs_rst_ch2_c => rx_pcs_rst(2), + -- CH3 -- + hdinp_ch3 => SD_RXD_P_IN(3), + hdinn_ch3 => SD_RXD_N_IN(3), + hdoutp_ch3 => SD_TXD_P_OUT(3), + hdoutn_ch3 => SD_TXD_N_OUT(3), + rxiclk_ch3 => sd_rx_clk(3), + txiclk_ch3 => CLK_125_IN, + rx_full_clk_ch3 => sd_rx_clk(3), + rx_half_clk_ch3 => open, + tx_full_clk_ch3 => open, + tx_half_clk_ch3 => open, + fpga_rxrefclk_ch3 => CLK_125_IN, + txdata_ch3 => sd_tx_data_q(31 downto 24), + tx_k_ch3 => sd_tx_kcntl_q(3), + xmit_ch3 => xmit(3), + tx_disp_correct_ch3 => sd_tx_correct_disp_q(3), + rxdata_ch3 => sd_rx_data(31 downto 24), + rx_k_ch3 => sd_rx_kcntl(3), + rx_disp_err_ch3 => sd_rx_disp_error(3), + rx_cv_err_ch3 => sd_rx_cv_error(3), + rx_serdes_rst_ch3_c => rx_serdes_rst(3), + sb_felb_ch3_c => '0', + sb_felb_rst_ch3_c => '0', + tx_pwrup_ch3_c => tx_power(3), + rx_pwrup_ch3_c => rx_power(3), + rx_los_low_ch3_s => los(3), + lsm_status_ch3_s => signal_detected(3), + rx_cdr_lol_ch3_s => rx_cdr_lol(3), + tx_pcs_rst_ch3_c => tx_pcs_rst(3), + rx_pcs_rst_ch3_c => rx_pcs_rst(3), + ---- Miscillaneous ports + fpga_txrefclk => CLK_125_IN, + tx_serdes_rst_c => '0', + tx_pll_lol_qd_s => tx_pll_lol, + tx_sync_qd_c => '0', + rst_qd_c => quad_rst, + serdes_rst_qd_c => '0' + ); + end generate serdes_ch4_gen; + + reset_n <= not RESET; + + serdes_ch1_gen : if FPGA_TYPE = 5 generate + gbe_serdes : entity work.GbePcsExtrefclk + port map( + sgmii_ecp5_rx_cv_err => sd_rx_cv_error(0 downto 0), + sgmii_ecp5_rx_disp_err => sd_rx_disp_error(0 downto 0), + sgmii_ecp5_rx_k => sd_rx_kcntl(0 downto 0), + sgmii_ecp5_rxdata => sd_rx_data(7 downto 0), + sgmii_ecp5_sci_addr => sci_addr_i, + sgmii_ecp5_sci_rddata => sci_data_out_i, + sgmii_ecp5_sci_wrdata => sci_data_in_i, + sgmii_ecp5_tx_disp_correct => sd_tx_correct_disp_q(0 downto 0), + sgmii_ecp5_tx_k => sd_tx_kcntl_q(0 downto 0), + sgmii_ecp5_txdata => sd_tx_data_q(7 downto 0), + sgmii_ecp5_xmit => xmit(0 downto 0), + extref_refclkn => SD_REFCLK_N_IN, + extref_refclkp => SD_REFCLK_P_IN, + sgmii_ecp5_ctc_del_s => open, + sgmii_ecp5_ctc_ins_s => open, + sgmii_ecp5_ctc_orun_s => open, + sgmii_ecp5_ctc_urun_s => open, + sgmii_ecp5_cyawstn => '0', + sgmii_ecp5_hdinn => SD_RXD_N_IN(0), + sgmii_ecp5_hdinp => SD_RXD_P_IN(0), + sgmii_ecp5_hdoutn => SD_TXD_N_OUT(0), + sgmii_ecp5_hdoutp => SD_TXD_P_OUT(0), + sgmii_ecp5_lsm_status_s => signal_detected(0), + sgmii_ecp5_pll_lol => tx_pll_lol, + sgmii_ecp5_rsl_disable => '0', + sgmii_ecp5_rsl_rst => '0', + sgmii_ecp5_rsl_rx_rdy => rsl_rx_rdy, + sgmii_ecp5_rsl_tx_rdy => rsl_tx_rdy, + sgmii_ecp5_rst_dual_c => quad_rst, + sgmii_ecp5_rx_cdr_lol_s => rx_cdr_lol(0), + sgmii_ecp5_rx_los_low_s => los(0), + sgmii_ecp5_rx_pcs_rst_c => rx_pcs_rst(0), + sgmii_ecp5_rx_pwrup_c => rx_power(0), + sgmii_ecp5_rx_serdes_rst_c => rx_serdes_rst(0), + sgmii_ecp5_sci_en => reset_n, + sgmii_ecp5_sci_en_dual => reset_n, + sgmii_ecp5_sci_int => open, + sgmii_ecp5_sci_rd => sci_read_i, + sgmii_ecp5_sci_sel => sci_ch_i(0), + sgmii_ecp5_sci_sel_dual => sci_ch_i(4), + sgmii_ecp5_sci_wrn => sci_write_i, + sgmii_ecp5_serdes_pdb => '1', + sgmii_ecp5_serdes_rst_dual_c => '0', + sgmii_ecp5_signal_detect_c => '0', + sgmii_ecp5_tx_pclk => sd_rx_clk(0), + sgmii_ecp5_tx_pcs_rst_c => tx_pcs_rst(0), + sgmii_ecp5_tx_pwrup_c => tx_power(0), + sgmii_ecp5_tx_serdes_rst_c => '0', + sgmii_ecp5_txi_clk => sd_rx_clk(0) + ); + + end generate serdes_ch1_gen; + + wa_position_sel <= x"0"; +--TO DO + THE_PCS_RESET : entity work.pcs_sync_reset + generic map( + IS_SYNC_SLAVE => 0,--????ß + IS_TX_RESET => 1 + ) + port map( + CLK_SYS => CLK_SYS_IN, + CLK_RXI => sd_rx_clk(0), --??correct?? + CLK_REF => CLK_125_IN, + RESET => RESET, + CLEAR => '0', + + SFP_LOS => SD_LOS_IN(0), + TX_LOL => tx_pll_lol, + RX_CDR_LOL => rx_cdr_lol(0), + RX_LOS => los(0), + WA_POSITION => wa_position_sel, + + RX_SERDES_RST => rx_serdes_rst(0), + RX_PCS_RST => rx_pcs_rst(0), + QUAD_RST => quad_rst, + TX_PCS_RST => tx_pcs_rst(0), + + SERDES_RX_READY_IN => rsl_rx_rdy, + SERDES_TX_READY_IN => rsl_tx_rdy, + + STAT_TX_CONTROL => stat_tx_control_i, + STAT_RX_CONTROL => stat_rx_control_i, + DEBUG_TX_CONTROL => open,--debug_tx_control_i, + DEBUG_RX_CONTROL => open,--debug_rx_control_i, + STAT_RESET => stat_fsm_reset_i, + DEBUG_OUT => open--debug_med_sync_control_i + ); + + + + THE_SCI_READER : entity work.sci_reader + port map( + CLK => CLK_SYS_IN, + RESET => RESET, + + --SCI + SCI_WRDATA => sci_data_in_i, + SCI_RDDATA => sci_data_out_i, + SCI_ADDR => sci_addr_i, + SCI_SEL => sci_ch_i, + SCI_RD => sci_read_i, + SCI_WR => sci_write_i, + + WA_POS_OUT => wa_position, + + --Slowcontrol + BUS_RX => BUS_SCI_RX, + BUS_TX => BUS_SCI_TX, + + MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i, + MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i, + MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i, + --MEDIA_STATUS_REG_IN(127 downto 96) => stat_med, + MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'), + DEBUG_OUT => open + ); + + DEBUG_CLK : process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + cnt_125_dbg <= cnt_125_dbg + 1; + end if; + end process DEBUG_CLK; + + DEBUG : process(CLK_SYS_IN) + begin + if rising_edge(CLK_SYS_IN) then + DEBUG_OUT(0) <= xmit(0); + DEBUG_OUT(1) <= los(0); + DEBUG_OUT(2) <= signal_detected(0); + DEBUG_OUT(3) <= tx_pll_lol; + DEBUG_OUT(4) <= rx_cdr_lol(0); + DEBUG_OUT(5) <= sd_rx_cv_error(0); + DEBUG_OUT(6) <= sd_rx_disp_error(0); + DEBUG_OUT(8 downto 7) <= operational_rate(1 downto 0); + DEBUG_OUT(9) <= rx_compensation_err(0); + DEBUG_OUT(10)<= an_link_ok(0); + DEBUG_OUT(11)<= MAC_READY_CONF_OUT(0); + DEBUG_OUT(12)<= an_complete(0); + DEBUG_OUT(13)<= rsl_rx_rdy; + DEBUG_OUT(14)<= rsl_tx_rdy; + DEBUG_OUT(15)<= cnt_125_dbg(30); + DEBUG_OUT(19 downto 16) <= '0' & '0' & '0' & '0'; + DEBUG_OUT(255 downto 20) <= (others => '0'); + end if; + end process DEBUG; + + + SYNC_TX_PROC : process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + sd_tx_data_q <= sd_tx_data; + sd_tx_kcntl_q <= sd_tx_kcntl; + sd_tx_correct_disp_q <= sd_tx_correct_disp; + end if; + end process SYNC_TX_PROC; + + + pcs_gen : for i in 0 to NUMBER_OF_GBE_LINKS - 1 generate + + pcs_active_gen : if LINKS_ACTIVE(i) = '1' generate + + SYNC_RX_PROC : process(sd_rx_clk) + begin + if rising_edge(sd_rx_clk(i)) then + sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8) <= sd_rx_data( (i + 1) * 8 - 1 downto i * 8); + sd_rx_kcntl_q(i) <= sd_rx_kcntl(i); + sd_rx_disp_error_q(i) <= sd_rx_disp_error(i); + sd_rx_cv_error_q(i) <= sd_rx_cv_error(i); + end if; + end process SYNC_RX_PROC; + + SGMII_GBE_PCS : sgmii_gbe_pcs35_core + port map( + rst_n => synced_rst, --rst_n, + signal_detect => signal_detected(i), + gbe_mode => '1', + sgmii_mode => '0', + operational_rate => operational_rate( (i + 1) * 2 - 1 downto (i * 2)), + debug_link_timer_short => '0', + + force_isolate => '0', + force_loopback => '0', + force_unidir => '0', + + rx_compensation_err => rx_compensation_err(i), + + ctc_drop_flag => open, + ctc_add_flag => open, + an_link_ok => an_link_ok(i), + + -- MAC interface + tx_clk_125 => CLK_125_IN, --refclkcore, -- original clock from SerDes + tx_clock_enable_source => tx_clk_en(i), + tx_clock_enable_sink => tx_clk_en(i), + tx_d => pcs_txd( (i + 1) * 8 - 1 downto i * 8), -- TX data from MAC + tx_en => pcs_tx_en(i), -- TX data enable from MAC + tx_er => pcs_tx_er(i), -- TX error from MAC + rx_clk_125 => sd_rx_clk(i), + rx_clock_enable_source => rx_clk_en(i), + rx_clock_enable_sink => rx_clk_en(i), + rx_d => pcs_rxd( (i + 1) * 8 - 1 downto i * 8), -- RX data to MAC + rx_dv => pcs_rx_en(i), -- RX data enable to MAC + rx_er => pcs_rx_er(i), -- RX error to MAC + col => pcs_col(i), + crs => pcs_crs(i), + + -- SerDes interface + tx_data => sd_tx_data( (i + 1) * 8 - 1 downto i * 8), -- TX data to SerDes + tx_kcntl => sd_tx_kcntl(i), -- TX komma control to SerDes + tx_disparity_cntl => sd_tx_correct_disp(i), -- idle parity state control in IPG (to SerDes) + + xmit_autoneg => xmit(i), + + serdes_recovered_clk => sd_rx_clk(i), -- 125MHz recovered from receive bit stream + rx_data => sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8), -- RX data from SerDes + rx_kcntl => sd_rx_kcntl_q(i), -- RX komma control from SerDes + rx_err_decode_mode => '0', -- receive error control mode fixed to normal + rx_even => '0', -- unused (receive error control mode = normal, tie to GND) + rx_disp_err => sd_rx_disp_error_q(i), -- RX disparity error from SerDes + rx_cv_err => sd_rx_cv_error_q(i), -- RX code violation error from SerDes + -- Autonegotiation stuff + mr_an_complete => an_complete(i), + mr_page_rx => mr_page_rx(i), + mr_lp_adv_ability => mr_lp_adv_ability( (i + 1) * 16 - 1 downto i * 16), + mr_main_reset => mr_main_reset(i), + mr_an_enable => '1', + mr_restart_an => '0',--mr_restart_an(i), + mr_adv_ability => mr_adv_ability( (i + 1) * 16 - 1 downto i * 16) + ); + + MAC_AN_READY_OUT(i) <= an_complete(i); + +-- u0_reset_controller_pcs : reset_controller_pcs port map( +-- rst_n => synced_rst, --rst_n, +-- clk => CLK_125_IN, +-- tx_plol => tx_pll_lol, +-- rx_cdr_lol => rx_cdr_lol(i), +-- quad_rst_out => open, --quad_rst, +-- tx_pcs_rst_out => tx_pcs_rst(i), +-- rx_pcs_rst_out => rx_pcs_rst(i) +-- ); +-- +-- u0_reset_controller_cdr : reset_controller_cdr port map( +-- rst_n => synced_rst, --rst_n, +-- clk => CLK_125_IN, +-- cdr_lol => rx_cdr_lol(i), +-- cdr_rst_out => rx_serdes_rst(i) +-- ); + + u0_rate_resolution : rate_resolution port map( + gbe_mode => '1', + sgmii_mode => '0', + an_enable => '1', + advertised_rate => mr_adv_ability(i * 16 + 11 downto i * 16 + 10), + link_partner_rate => mr_lp_adv_ability(i * 16 + 11 downto i * 16 + 10), + non_an_rate => "10", -- 1Gbps is rate when auto-negotiation disabled + + operational_rate => operational_rate( (i + 1) * 2 - 1 downto i * 2) + ); + + u0_ri : register_interface_hb port map( + -- Control Signals + rst_n => synced_rst, --rst_n, + hclk => CLK_125_IN, + gbe_mode => '1', + sgmii_mode => '0', + + -- Host Bus + hcs_n => '1', + hwrite_n => '1', + haddr => (others => '0'), + hdatain => (others => '0'), + + hdataout => open, + hready_n => open, + + -- Register Outputs + mr_an_enable => mr_an_enable(i), + mr_restart_an => mr_restart_an(i), + mr_main_reset => mr_main_reset(i), + mr_adv_ability => mr_adv_ability( (i + 1 ) * 16 - 1 downto i * 16), + + -- Register Inputs + mr_an_complete => an_complete(i), + mr_page_rx => mr_page_rx(i), + mr_lp_adv_ability => mr_lp_adv_ability( (i + 1 ) * 16 - 1 downto i * 16) + ); + + MAC: tsmac35 + port map( + ----------------- clock and reset port declarations ------------------ + hclk => CLK_SYS_IN, + txmac_clk => CLK_125_IN, + rxmac_clk => sd_rx_clk(i), + reset_n => GSR_N, + txmac_clk_en => '1', + rxmac_clk_en => '1', + ------------------- Input signals to the GMII ---------------- + rxd => pcs_rxd_qq( (i + 1) * 8 - 1 downto i * 8), + rx_dv => pcs_rx_en_qq(i), + rx_er => pcs_rx_er_qq(i), + col => pcs_col(i), + crs => pcs_crs(i), + -------------------- Input signals to the CPU I/F ------------------- + haddr => tsm_haddr( (i + 1) * 8 - 1 downto i * 8), + hdatain => tsm_hdata( (i + 1) * 8 - 1 downto i * 8), + hcs_n => tsm_hcs_n(i), + hwrite_n => tsm_hwrite_n(i), + hread_n => tsm_hread_n(i), + ---------------- Input signals to the Tx MAC FIFO I/F --------------- + tx_fifodata => MAC_TX_DATA_IN( (i + 1) * 8 - 1 downto i * 8), + tx_fifoavail => MAC_FIFOAVAIL_IN(i), + tx_fifoeof => MAC_FIFOEOF_IN(i), + tx_fifoempty => MAC_FIFOEMPTY_IN(i), + tx_sndpaustim => x"0000", + tx_sndpausreq => '0', + tx_fifoctrl => '0', -- always data frame + ---------------- Input signals to the Rx MAC FIFO I/F --------------- + rx_fifo_full => MAC_RX_FIFOFULL_IN(i), --'0', + ignore_pkt => '0', + ---------------- Output signals from the GMII ----------------------- + txd => pcs_txd( (i + 1) * 8 - 1 downto i * 8), + tx_en => pcs_tx_en(i), + tx_er => pcs_tx_er(i), + ----------------- Output signals from the CPU I/F ------------------- + hdataout => open, + hdataout_en_n => tsm_hdataout_en_n(i), + hready_n => tsm_hready_n(i), + cpu_if_gbit_en => open, + ------------- Output signals from the Tx MAC FIFO I/F --------------- + tx_macread => MAC_TX_READ_OUT(i), + tx_discfrm => MAC_TX_DISCRFRM_OUT(i), + tx_staten => MAC_TX_STAT_EN_OUT(i), + tx_statvec => MAC_TX_STATS_OUT( (i + 1) * 31 - 1 downto i * 31), + tx_done => MAC_TX_DONE_OUT(i), + ------------- Output signals from the Rx MAC FIFO I/F --------------- + rx_fifo_error => MAC_RX_FIFO_ERR_OUT(i), + rx_stat_vector => MAC_RX_STATS_OUT( (i + 1) * 32 - 1 downto i * 32), + rx_dbout => MAC_RX_DATA_OUT( (i + 1) * 8 - 1 downto i * 8), + rx_write => MAC_RX_WRITE_OUT(i), + rx_stat_en => MAC_RX_STAT_EN_OUT(i), + rx_eof => MAC_RX_EOF_OUT(i), + rx_error => MAC_RX_ERROR_OUT(i) + ); + + TSMAC_CONTROLLER : trb_net16_gbe_mac_control + port map( + CLK => CLK_SYS_IN, + RESET => RESET, + + -- signals to/from main controller + MC_TSMAC_READY_OUT => MAC_READY_CONF_OUT(i), + MC_RECONF_IN => MAC_RECONF_IN(i), + MC_GBE_EN_IN => '1', + MC_RX_DISCARD_FCS => '0', + MC_PROMISC_IN => '1', + MC_MAC_ADDR_IN => (others => '0'), + + -- signal to/from Host interface of TriSpeed MAC + TSM_HADDR_OUT => tsm_haddr( (i + 1) * 8 - 1 downto i * 8), + TSM_HDATA_OUT => tsm_hdata( (i + 1) * 8 - 1 downto i * 8), + TSM_HCS_N_OUT => tsm_hcs_n(i), + TSM_HWRITE_N_OUT => tsm_hwrite_n(i), + TSM_HREAD_N_OUT => tsm_hread_n(i), + TSM_HREADY_N_IN => tsm_hready_n(i), + TSM_HDATA_EN_N_IN => tsm_hdataout_en_n(i), + + DEBUG_OUT => open + ); + + SYNC_GMII_RX_PROC : process(sd_rx_clk) + begin + if rising_edge(sd_rx_clk(i)) then + pcs_rxd_q( (i + 1) * 8 - 1 downto i * 8) <= pcs_rxd( (i + 1) * 8 - 1 downto i * 8); + pcs_rx_en_q(i) <= pcs_rx_en(i); + pcs_rx_er_q(i) <= pcs_rx_er(i); + + pcs_rxd_qq( (i + 1) * 8 - 1 downto i * 8) <= pcs_rxd_q( (i + 1) * 8 - 1 downto i * 8); + pcs_rx_en_qq(i) <= pcs_rx_en_q(i); + pcs_rx_er_qq(i) <= pcs_rx_er_q(i); + end if; + end process SYNC_GMII_RX_PROC; + + SYNC_GMII_TX_PROC : process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + pcs_txd_q( (i + 1) * 8 - 1 downto i * 8) <= pcs_txd( (i + 1) * 8 - 1 downto i * 8); + pcs_tx_en_q <= pcs_tx_en; + pcs_tx_er_q <= pcs_tx_er; + + pcs_txd_qq( (i + 1) * 8 - 1 downto i * 8) <= pcs_txd_q( (i + 1) * 8 - 1 downto i * 8); + pcs_tx_en_qq <= pcs_tx_en_q; + pcs_tx_er_qq <= pcs_tx_er_q; + end if; + end process SYNC_GMII_TX_PROC; + + end generate pcs_active_gen; + + end generate pcs_gen; + + end generate impl_gen; + + sim_gen : if DO_SIMULATION = 1 generate + + process + begin + + MAC_AN_READY_OUT <= (others => '0'); + wait for 2 us; + MAC_AN_READY_OUT <= (others => '1'); + + wait; + end process; + + process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + MAC_TX_READ_OUT <= MAC_FIFOAVAIL_IN; + + fifo_eof_q <= MAC_FIFOEOF_IN; + fifo_eof_qq <= fifo_eof_q; + fifo_eof_qqq <= fifo_eof_qq; + fifo_eof_qqqq <= fifo_eof_qqq; + + MAC_TX_DONE_OUT <= fifo_eof_qqqq; -- MAC_FIFOEOF_IN; + end if; + end process; + + + end generate sim_gen; + + +end architecture RTL; diff --git a/gbe_trb/base/gbe_med_interface_ecp5.vhd b/gbe_trb/base/gbe_med_interface_ecp5.vhd new file mode 100644 index 0000000..a0da7ea --- /dev/null +++ b/gbe_trb/base/gbe_med_interface_ecp5.vhd @@ -0,0 +1,644 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +use work.trb_net_gbe_components.all; +use work.config.all; + +entity gbe_med_interface_ecp5 is + generic ( + DO_SIMULATION : integer range 0 to 1; + NUMBER_OF_GBE_LINKS : integer range 1 to 4; + LINKS_ACTIVE : std_logic_vector(3 downto 0) + ); + port ( + RESET : in std_logic; + GSR_N : in std_logic; + CLK_SYS_IN : in std_logic; + CLK_125_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + CLK_125_IN : in std_logic; + CLK_125_RX_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + -- MAC status and config + MAC_READY_CONF_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RECONF_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_AN_READY_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + -- MAC data interface + MAC_FIFOAVAIL_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_FIFOEOF_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_FIFOEMPTY_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_FIFOFULL_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + MAC_TX_DATA_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + MAC_TX_READ_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_DISCRFRM_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_STAT_EN_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_STATS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 31 - 1 downto 0); + MAC_TX_DONE_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + MAC_RX_FIFO_ERR_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_STATS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 32 - 1 downto 0); + MAC_RX_DATA_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + MAC_RX_WRITE_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_STAT_EN_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_EOF_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_ERROR_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + --SFP Connection + SD_RXD_P_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_RXD_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_TXD_P_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_TXD_N_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_PRSNT_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_LOS_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable + + DEBUG_OUT : out std_logic_vector(255 downto 0) + ); +end entity gbe_med_interface_ecp5; + +architecture RTL of gbe_med_interface_ecp5 is + + component sgmii_channel_smi_core + port( + rst_n : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + operational_rate : in std_logic_vector(1 downto 0); + debug_link_timer_short : in std_logic; + force_isolate : in std_logic; + force_loopback : in std_logic; + force_unidir : in std_logic; + --rx_compensation_err : out std_logic; + --ctc_drop_flag : out std_logic; + --ctc_add_flag : out std_logic; + an_link_ok : out std_logic; + tx_clock_enable_sink : in std_logic; + tx_clock_enable_source : out std_logic; + + rx_clock_enable_sink : in std_logic; + rx_clock_enable_source : out std_logic; + tx_clk_125 : in std_logic; + rx_clk_125 : in std_logic; + tx_d : in std_logic_vector(7 downto 0); + tx_en : in std_logic; + tx_er : in std_logic; + rx_d : out std_logic_vector(7 downto 0); + rx_dv : out std_logic; + rx_er : out std_logic; + col : out std_logic; + crs : out std_logic; + mr_an_complete : out std_logic; + mr_page_rx : out std_logic; + mr_lp_adv_ability : out std_logic_vector(15 downto 0); + mr_main_reset : in std_logic; + mr_an_enable : in std_logic; + mr_restart_an : in std_logic; + mr_adv_ability : in std_logic_vector(15 downto 0); + + hdoutp : out std_logic; + hdoutn : out std_logic; + hdinp : in std_logic; + hdinn : in std_logic; + + sli_rst : in std_logic; + serdes_rst_dual_c : out std_logic; + tx_serdes_rst_c : out std_logic; + serdes_pdb : out std_logic; + tx_pwrup_c : out std_logic; + + pll_refclki : in std_logic; + rxrefclk : in std_logic; + + sci_wrdata : in std_logic_vector(7 downto 0); + sci_addr : in std_logic_vector(5 downto 0); + sci_rddata : out std_logic_vector(7 downto 0); + sci_en_dual : in std_logic; + sci_sel_dual : in std_logic; + sci_en : in std_logic; + sci_sel : in std_logic; + sci_rd : in std_logic; + sci_wrn : in std_logic; + sci_int : out std_logic; + cyawstn : in std_logic; + + rx_cdr_lol_s : out std_logic; + + tx_pcs_rst_c : in std_logic; + rx_pcs_rst_c : in std_logic; + rx_serdes_rst_c : in std_logic; + + rst_dual_c : in std_logic; + pll_lol : out std_logic; + + mr_power_down : in std_logic + ); +end component; + +component rate_resolution port ( + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + an_enable : in std_logic; + advertised_rate : in std_logic_vector(1 downto 0); + link_partner_rate : in std_logic_vector(1 downto 0); + non_an_rate : in std_logic_vector(1 downto 0); + operational_rate : out std_logic_vector(1 downto 0) + ); +end component; + +component register_interface_hb port ( + --Control Signals + rst_n : in std_logic; + hclk : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + --Host Bus + hcs_n : in std_logic; + hwrite_n : in std_logic; + haddr : in std_logic_vector(3 downto 0); + hdatain : in std_logic_vector(7 downto 0); + + hdataout : out std_logic_vector(7 downto 0); + hready_n : out std_logic; + --Register Inputs + mr_stat_1000base_x_fd : in std_logic; + mr_stat_1000base_x_hd : in std_logic; + mr_stat_1000base_t_fd : in std_logic; + mr_stat_1000base_t_hd : in std_logic; + mr_stat_100base_t4 : in std_logic; + mr_stat_100base_x_fd : in std_logic; + mr_stat_100base_x_hd : in std_logic; + mr_stat_10mbps_fd : in std_logic; + mr_stat_10mbps_hd : in std_logic; + mr_stat_100base_t2_fd : in std_logic; + mr_stat_100base_t2_hd : in std_logic; + mr_stat_extended_stat : in std_logic; + mr_stat_unidir_able : in std_logic; + mr_stat_preamb_supr : in std_logic; + mr_stat_an_complete : in std_logic; + mr_stat_remote_fault : in std_logic; + mr_stat_an_able : in std_logic; + mr_stat_link_stat : in std_logic; + mr_stat_jab_det : in std_logic; + mr_stat_extended_cap : in std_logic; + mr_page_rx : in std_logic; + mr_lp_adv_ability : in std_logic_vector(15 downto 0); + --Register Outputs + mr_main_reset : out std_logic; + mr_loopback_enable : out std_logic; + mr_speed_selection : out std_logic_vector(1 downto 0); + mr_an_enable : out std_logic; + mr_power_down : out std_logic; + mr_isolate : out std_logic; + mr_restart_an : out std_logic; + mr_duplex_mode : out std_logic; + mr_col_test : out std_logic; + mr_unidir_enable : out std_logic; + mr_adv_ability : out std_logic_vector(15 downto 0) + ); +end component; + +component tsmac35 --tsmac36 --tsmac35 +port( + --------------- clock and reset port declarations ------------------ + hclk : in std_logic; + txmac_clk : in std_logic; + rxmac_clk : in std_logic; + reset_n : in std_logic; + txmac_clk_en : in std_logic; + rxmac_clk_en : in std_logic; + ------------------- Input signals to the GMII ---------------- + rxd : in std_logic_vector(7 downto 0); + rx_dv : in std_logic; + rx_er : in std_logic; + col : in std_logic; + crs : in std_logic; + -------------------- Input signals to the CPU I/F ------------------- + haddr : in std_logic_vector(7 downto 0); + hdatain : in std_logic_vector(7 downto 0); + hcs_n : in std_logic; + hwrite_n : in std_logic; + hread_n : in std_logic; + ---------------- Input signals to the Tx MAC FIFO I/F --------------- + tx_fifodata : in std_logic_vector(7 downto 0); + tx_fifoavail : in std_logic; + tx_fifoeof : in std_logic; + tx_fifoempty : in std_logic; + tx_sndpaustim : in std_logic_vector(15 downto 0); + tx_sndpausreq : in std_logic; + tx_fifoctrl : in std_logic; + ---------------- Input signals to the Rx MAC FIFO I/F --------------- + rx_fifo_full : in std_logic; + ignore_pkt : in std_logic; + -------------------- Output signals from the GMII ----------------------- + txd : out std_logic_vector(7 downto 0); + tx_en : out std_logic; + tx_er : out std_logic; + -------------------- Output signals from the CPU I/F ------------------- + hdataout : out std_logic_vector(7 downto 0); + hdataout_en_n : out std_logic; + hready_n : out std_logic; + cpu_if_gbit_en : out std_logic; + ---------------- Output signals from the Tx MAC FIFO I/F --------------- + tx_macread : out std_logic; + tx_discfrm : out std_logic; + tx_staten : out std_logic; + tx_done : out std_logic; + tx_statvec : out std_logic_vector(30 downto 0); + ---------------- Output signals from the Rx MAC FIFO I/F --------------- + rx_fifo_error : out std_logic; + rx_stat_vector : out std_logic_vector(31 downto 0); + rx_dbout : out std_logic_vector(7 downto 0); + rx_write : out std_logic; + rx_stat_en : out std_logic; + rx_eof : out std_logic; + rx_error : out std_logic +); +end component; + + signal sd_rx_clk : std_logic; + signal xmit : std_logic; + signal rx_cdr_lol: std_logic; + signal tx_pll_lol, quad_rst : std_logic; + --signal rst_n : std_logic; + signal rx_clk_en : std_logic; + signal tx_clk_en : std_logic; + signal operational_rate : std_logic_vector(1 downto 0); + signal an_complete : std_logic; + signal mr_page_rx : std_logic; + signal mr_lp_adv_ability : std_logic_vector(15 downto 0); + signal mr_main_reset : std_logic; + signal mr_restart_an : std_logic; + signal mr_adv_ability : std_logic_vector(15 downto 0); + signal mr_an_enable : std_logic; + signal pcs_rxd, pcs_rxd_q, pcs_rxd_qq : std_logic_vector(7 downto 0); + signal pcs_rx_en, pcs_rx_en_q, pcs_rx_en_qq : std_logic; + signal pcs_rx_er, pcs_rx_er_q, pcs_rx_er_qq : std_logic; + signal pcs_col, pcs_crs : std_logic; + signal pcs_txd, pcs_txd_q, pcs_txd_qq : std_logic_vector(7 downto 0); + signal pcs_tx_en, pcs_tx_en_q, pcs_tx_en_qq : std_logic; + signal pcs_tx_er, pcs_tx_er_q, pcs_tx_er_qq : std_logic; + signal tsm_hdataout_en_n : std_logic; + signal tsm_hready_n : std_logic; + signal tsm_hread_n : std_logic; + signal tsm_hwrite_n : std_logic; + signal tsm_hcs_n : std_logic; + signal tsm_hdata : std_logic_vector(7 downto 0); + signal tsm_haddr : std_logic_vector(7 downto 0); + + signal synced_rst, ff : std_logic; + + signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic; + + + signal serdes_rst_dual_c : std_logic; + signal sli_rst : std_logic; + signal tx_serdes_rst_c : std_logic; + signal serdes_pdb : std_logic; + signal tx_pwrup_c : std_logic; + signal reset_n : std_logic; + signal mr_power_down : std_logic; + + signal mr_unidir_enable : std_logic; + signal mr_isolate : std_logic; + signal mr_loopback_enable : std_logic; + signal an_link_ok : std_logic; + signal mr_speed_selection : std_logic_vector(1 downto 0); + +begin + + + sli_rst <= serdes_rst_dual_c or tx_serdes_rst_c or (not serdes_pdb) or (not tx_pwrup_c); + --rst_n <= not RESET; + + reset_sync : process(GSR_N, CLK_SYS_IN) + begin + if (GSR_N = '0') then + ff <= '0'; + synced_rst <= '0'; + elsif rising_edge(CLK_SYS_IN) then + ff <= '1'; + synced_rst <= ff; + end if; + end process reset_sync; + + SD_TXDIS_OUT <= "0000"; + + CLK_125_OUT <= CLK_125_IN & CLK_125_IN & CLK_125_IN & CLK_125_IN; + sd_rx_clk <= CLK_125_IN; + CLK_125_RX_OUT <= sd_rx_clk & sd_rx_clk & sd_rx_clk & sd_rx_clk; + + impl_gen : if DO_SIMULATION = 0 generate + + gbe_serdes : sgmii_channel_smi_core + port map( + rst_n => not RESET, + gbe_mode => '1', + sgmii_mode => '0', + operational_rate => operational_rate, + debug_link_timer_short => '0', + force_isolate => '0',--mr_isolate, + force_loopback => '0',--mr_loopback_enable, --0, + force_unidir => '0',--mr_unidir_enable, + --rx_compensation_err : out std_logic; + --ctc_drop_flag : out std_logic; + --ctc_add_flag : out std_logic; + an_link_ok => an_link_ok, + tx_clock_enable_sink => tx_clk_en, + tx_clock_enable_source => tx_clk_en, + rx_clock_enable_sink => rx_clk_en, + rx_clock_enable_source => rx_clk_en, + tx_clk_125 => CLK_125_IN, + rx_clk_125 => CLK_125_IN, + + --START TSMAC + tx_d => pcs_txd, --: in std_logic_vector(7 downto 0); + tx_en => pcs_tx_en, + tx_er => pcs_tx_er, + rx_d => pcs_rxd, + rx_dv => pcs_rx_en, + rx_er => pcs_rx_er, + col => pcs_col, + crs => pcs_crs, + --END TSMAC + + --Managment Control Outputs + mr_an_complete => an_complete, + mr_page_rx => mr_page_rx, + mr_lp_adv_ability => mr_lp_adv_ability, + + --Managment Control Inputs + mr_main_reset => '0',--mr_main_reset, + mr_an_enable => mr_an_enable, + mr_restart_an => '0',--mr_restart_an, + mr_adv_ability => x"0000",--mr_adv_ability, + + hdoutp => SD_TXD_P_OUT(0), + hdoutn => SD_TXD_N_OUT(0), + hdinp => SD_RXD_P_IN(0), + hdinn => SD_RXD_N_IN(0), + + sli_rst => sli_rst, + serdes_rst_dual_c => serdes_rst_dual_c, + tx_serdes_rst_c => tx_serdes_rst_c, + serdes_pdb => serdes_pdb, + tx_pwrup_c => tx_pwrup_c, + + pll_refclki => CLK_125_IN, + rxrefclk => CLK_125_IN, + + sci_wrdata => x"00", + sci_addr => b"000000", + sci_rddata => open, + sci_en_dual => '0', + sci_sel_dual => '0', + sci_en => '0', + sci_sel => '0', + sci_rd => '0', + sci_wrn => '1', + sci_int => open, + cyawstn => '0', + + rx_cdr_lol_s => rx_cdr_lol, + + tx_pcs_rst_c => '0', + rx_pcs_rst_c => '0', + rx_serdes_rst_c => '0', + + rst_dual_c => not GSR_N, + pll_lol => open, + + mr_power_down => '0'--mr_power_down + ); + + SD_TXD_P_OUT(3 downto 1) <= "000"; + SD_TXD_N_OUT(3 downto 1) <= "111"; + + MAC_AN_READY_OUT(0) <= an_complete; + MAC_AN_READY_OUT(3 downto 1) <= (others => '0'); + mr_an_enable <= '1'; + + u0_rate_resolution : rate_resolution port map( + gbe_mode => '1', + sgmii_mode => '0', + an_enable => '1', + advertised_rate => "10",--mr_adv_ability(11 downto 10), + link_partner_rate => "10",--mr_lp_adv_ability(11 downto 10), + non_an_rate => "10", --mr_speed_selection,-- 1Gbps is rate when auto-negotiation disabled + + operational_rate => operational_rate + ); + + u0_ri_hb : register_interface_hb + port map( + rst_n => synced_rst, + hclk => CLK_125_IN, + gbe_mode => '1', + sgmii_mode => '0', + -- Host Bus + hcs_n => '1', + hwrite_n => '1', + haddr => (others => '0'), + hdatain => (others => '0'), + hdataout => open, + hready_n => open, + --Register Inputs + mr_stat_1000base_x_fd => '1', + mr_stat_1000base_x_hd => '0', + mr_stat_1000base_t_fd => '0', + mr_stat_1000base_t_hd => '0', + mr_stat_100base_t4 => '0', + mr_stat_100base_x_fd => '0', + mr_stat_100base_x_hd => '0', + mr_stat_10mbps_fd => '0', + mr_stat_10mbps_hd => '0', + mr_stat_100base_t2_fd => '0', + mr_stat_100base_t2_hd => '0', + mr_stat_extended_stat => '1', + mr_stat_unidir_able => mr_unidir_enable, + mr_stat_preamb_supr => '0', + mr_stat_an_complete => an_complete, + mr_stat_remote_fault => '0', + mr_stat_an_able => '1', + mr_stat_link_stat => an_link_ok, + mr_stat_jab_det => '0', + mr_stat_extended_cap => '0', + mr_page_rx => mr_page_rx, + mr_lp_adv_ability => mr_lp_adv_ability, + --Register Outputs + mr_main_reset => mr_main_reset, + mr_loopback_enable => mr_loopback_enable, + mr_speed_selection => mr_speed_selection, + mr_an_enable => open,--mr_an_enable, + mr_power_down => mr_power_down, + mr_isolate => mr_isolate, + mr_restart_an => mr_restart_an, + mr_duplex_mode => open, + mr_col_test => open, + mr_unidir_enable => mr_unidir_enable, + mr_adv_ability => mr_adv_ability + ); + + MAC: tsmac35 + port map( + ----------------- clock and reset port declarations ------------------ + hclk => CLK_SYS_IN, + txmac_clk => CLK_125_IN, + rxmac_clk => sd_rx_clk, + reset_n => GSR_N, + txmac_clk_en => '1', + rxmac_clk_en => '1', + ------------------- Input signals to the GMII ---------------- + rxd => pcs_rxd_qq( 7 downto 0), + rx_dv => pcs_rx_en_qq, + rx_er => pcs_rx_er_qq, + col => pcs_col, + crs => pcs_crs, + -------------------- Input signals to the CPU I/F ------------------- + haddr => tsm_haddr( 7 downto 0), + hdatain => tsm_hdata( 7 downto 0), + hcs_n => tsm_hcs_n, + hwrite_n => tsm_hwrite_n, + hread_n => tsm_hread_n, + ---------------- Input signals to the Tx MAC FIFO I/F --------------- + tx_fifodata => MAC_TX_DATA_IN( 7 downto 0), + tx_fifoavail => MAC_FIFOAVAIL_IN(0), + tx_fifoeof => MAC_FIFOEOF_IN(0), + tx_fifoempty => MAC_FIFOEMPTY_IN(0), + tx_sndpaustim => x"0000", + tx_sndpausreq => '0', + tx_fifoctrl => '0', -- always data frame + ---------------- Input signals to the Rx MAC FIFO I/F --------------- + rx_fifo_full => MAC_RX_FIFOFULL_IN(0), --'0', + ignore_pkt => '0', + ---------------- Output signals from the GMII ----------------------- + txd => pcs_txd( 7 downto 0), + tx_en => pcs_tx_en, + tx_er => pcs_tx_er, + ----------------- Output signals from the CPU I/F ------------------- + hdataout => open, + hdataout_en_n => tsm_hdataout_en_n, + hready_n => tsm_hready_n, + cpu_if_gbit_en => open, + ------------- Output signals from the Tx MAC FIFO I/F --------------- + tx_macread => MAC_TX_READ_OUT(0), + tx_discfrm => MAC_TX_DISCRFRM_OUT(0), + tx_staten => MAC_TX_STAT_EN_OUT(0), + tx_statvec => MAC_TX_STATS_OUT( 30 downto 0), + tx_done => MAC_TX_DONE_OUT(0), + ------------- Output signals from the Rx MAC FIFO I/F --------------- + rx_fifo_error => MAC_RX_FIFO_ERR_OUT(0), + rx_stat_vector => MAC_RX_STATS_OUT(31 downto 0), + rx_dbout => MAC_RX_DATA_OUT( 7 downto 0), + rx_write => MAC_RX_WRITE_OUT(0), + rx_stat_en => MAC_RX_STAT_EN_OUT(0), + rx_eof => MAC_RX_EOF_OUT(0), + rx_error => MAC_RX_ERROR_OUT(0) + ); + + MAC_TX_READ_OUT(3 downto 1) <= (others => '0'); + MAC_TX_DISCRFRM_OUT(3 downto 1) <= (others => '0'); + MAC_TX_STAT_EN_OUT(3 downto 1) <= (others => '0'); + MAC_TX_STATS_OUT(123 downto 31) <= (others => '0'); + MAC_TX_DONE_OUT(3 downto 1) <= (others => '0'); + + MAC_RX_FIFO_ERR_OUT(3 downto 1) <= (others => '0'); + MAC_RX_STATS_OUT(127 downto 32) <= (others => '0'); + MAC_RX_DATA_OUT(31 downto 8) <= (others => '0'); + MAC_RX_WRITE_OUT(3 downto 1) <= (others => '0'); + MAC_RX_STAT_EN_OUT(3 downto 1) <= (others => '0'); + MAC_RX_EOF_OUT(3 downto 1) <= (others => '0'); + MAC_RX_ERROR_OUT(3 downto 1) <= (others => '0'); + + TSMAC_CONTROLLER : trb_net16_gbe_mac_control + port map( + CLK => CLK_SYS_IN, + RESET => RESET, + + -- signals to/from main controller + MC_TSMAC_READY_OUT => MAC_READY_CONF_OUT(0), + MC_RECONF_IN => MAC_RECONF_IN(0), + MC_GBE_EN_IN => '1', + MC_RX_DISCARD_FCS => '0', + MC_PROMISC_IN => '1', + MC_MAC_ADDR_IN => (others => '0'), + + -- signal to/from Host interface of TriSpeed MAC + TSM_HADDR_OUT => tsm_haddr( 7 downto 0), + TSM_HDATA_OUT => tsm_hdata( 7 downto 0), + TSM_HCS_N_OUT => tsm_hcs_n, + TSM_HWRITE_N_OUT => tsm_hwrite_n, + TSM_HREAD_N_OUT => tsm_hread_n, + TSM_HREADY_N_IN => tsm_hready_n, + TSM_HDATA_EN_N_IN => tsm_hdataout_en_n, + + DEBUG_OUT => open + ); + + MAC_READY_CONF_OUT(3 downto 1) <= (others => '0'); + + SYNC_GMII_RX_PROC : process(sd_rx_clk) + begin + if rising_edge(sd_rx_clk) then + pcs_rxd_q(7 downto 0) <= pcs_rxd( 7 downto 0); + pcs_rx_en_q <= pcs_rx_en; + pcs_rx_er_q <= pcs_rx_er; + + pcs_rxd_qq( 7 downto 0) <= pcs_rxd_q( 7 downto 0); + pcs_rx_en_qq <= pcs_rx_en_q; + pcs_rx_er_qq <= pcs_rx_er_q; + end if; + end process SYNC_GMII_RX_PROC; + + SYNC_GMII_TX_PROC : process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + pcs_txd_q( 7 downto 0) <= pcs_txd(7 downto 0); + pcs_tx_en_q <= pcs_tx_en; + pcs_tx_er_q <= pcs_tx_er; + + pcs_txd_qq( 7 downto 0) <= pcs_txd_q( 7 downto 0); + pcs_tx_en_qq <= pcs_tx_en_q; + pcs_tx_er_qq <= pcs_tx_er_q; + end if; + end process SYNC_GMII_TX_PROC; + + end generate impl_gen; + + sim_gen : if DO_SIMULATION = 1 generate + + process + begin + + MAC_AN_READY_OUT <= (others => '0'); + wait for 2 us; + MAC_AN_READY_OUT <= (others => '1'); + + wait; + end process; + + process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + MAC_TX_READ_OUT <= MAC_FIFOAVAIL_IN; + + fifo_eof_q <= MAC_FIFOEOF_IN; + fifo_eof_qq <= fifo_eof_q; + fifo_eof_qqq <= fifo_eof_qq; + fifo_eof_qqqq <= fifo_eof_qqq; + + MAC_TX_DONE_OUT <= fifo_eof_qqqq; -- MAC_FIFOEOF_IN; + end if; + end process; + + + end generate sim_gen; + + +end architecture RTL; diff --git a/gbe_trb/base/gbe_med_interface_onlyPCS.vhd b/gbe_trb/base/gbe_med_interface_onlyPCS.vhd new file mode 100644 index 0000000..2fdca0a --- /dev/null +++ b/gbe_trb/base/gbe_med_interface_onlyPCS.vhd @@ -0,0 +1,338 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +use work.trb_net_gbe_components.all; +use work.config.all; + +entity gbe_med_interface is + generic ( + DO_SIMULATION : integer range 0 to 1; + NUMBER_OF_GBE_LINKS : integer range 1 to 4; + LINKS_ACTIVE : std_logic_vector(3 downto 0) + ); + port ( + RESET : in std_logic; + GSR_N : in std_logic; + CLK_SYS_IN : in std_logic; + CLK_125_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + CLK_125_IN : in std_logic; + CLK_125_RX_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + -- MAC status and config + MAC_READY_CONF_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RECONF_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_AN_READY_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + -- MAC data interface + MAC_FIFOAVAIL_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_FIFOEOF_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_FIFOEMPTY_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_FIFOFULL_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + MAC_TX_DATA_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + MAC_TX_READ_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_DISCRFRM_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_STAT_EN_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_STATS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 31 - 1 downto 0); + MAC_TX_DONE_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + MAC_RX_FIFO_ERR_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_STATS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 32 - 1 downto 0); + MAC_RX_DATA_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + MAC_RX_WRITE_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_STAT_EN_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_EOF_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_ERROR_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + --SFP Connection + SD_RXD_P_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_RXD_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_TXD_P_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_TXD_N_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_PRSNT_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_LOS_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable + + --CONTROL INTERFACE + BUS_SCI_RX : in CTRLBUS_RX; + BUS_SCI_TX : out CTRLBUS_TX; + + DEBUG_OUT : out std_logic_vector(255 downto 0) + ); +end entity gbe_med_interface; + +architecture RTL of gbe_med_interface is + + signal sd_rx_clk : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_tx_kcntl_q, sd_tx_kcntl : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_tx_data_q, sd_tx_data : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal xmit : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_tx_correct_disp_q, sd_tx_correct_disp : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_rx_data, sd_rx_data_q : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal sd_rx_kcntl, sd_rx_kcntl_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_rx_disp_error, sd_rx_disp_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_rx_cv_error, sd_rx_cv_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tx_power, rx_power : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal los, signal_detected : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal rx_cdr_lol: std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tx_pll_lol, quad_rst : std_logic; + signal tx_pcs_rst, rx_pcs_rst, rx_serdes_rst : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + --signal rst_n : std_logic; + signal rx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal operational_rate : std_logic_vector(NUMBER_OF_GBE_LINKS * 2 - 1 downto 0); + signal an_complete : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_page_rx : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_lp_adv_ability : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0); + signal mr_main_reset : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_restart_an : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_adv_ability : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0); + signal mr_an_enable : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_rxd, pcs_rxd_q, pcs_rxd_qq : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal pcs_rx_en, pcs_rx_en_q, pcs_rx_en_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_rx_er, pcs_rx_er_q, pcs_rx_er_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_col, pcs_crs : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_txd, pcs_txd_q, pcs_txd_qq : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal pcs_tx_en, pcs_tx_en_q, pcs_tx_en_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_tx_er, pcs_tx_er_q, pcs_tx_er_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hdataout_en_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hready_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hread_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hwrite_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hcs_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hdata : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal tsm_haddr : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal rx_compensation_err, an_link_ok : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + signal synced_rst, ff : std_logic; + + signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal rsl_rx_rdy,rsl_tx_rdy : std_logic; + + signal sci_data_in_i : std_logic_vector(7 downto 0); + signal sci_addr_i : std_logic_vector(5 downto 0); + signal sci_data_out_i : std_logic_vector(7 downto 0); + signal reset_n, sci_read_i, sci_write_i : std_logic; + signal sci_ch_i : std_logic_vector(4 downto 0); + signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; + signal wa_position_sel : std_logic_vector(3 downto 0); + + signal stat_fsm_reset_i, stat_tx_control_i, stat_rx_control_i : std_logic_vector(31 downto 0); + signal cnt_125_dbg : unsigned(30 downto 0) := (others => '0'); + +begin + + rx_power <= "1111"; + tx_power <= "1111"; + + --rst_n <= not RESET; + + reset_sync : process(GSR_N, CLK_SYS_IN) + begin + if (GSR_N = '0') then + ff <= '0'; + synced_rst <= '0'; + elsif rising_edge(CLK_SYS_IN) then + ff <= '1'; + synced_rst <= ff; + end if; + end process reset_sync; + + SD_TXDIS_OUT <= "0000"; + + CLK_125_OUT <= CLK_125_IN & CLK_125_IN & CLK_125_IN & CLK_125_IN; + CLK_125_RX_OUT <= sd_rx_clk; + + impl_gen : if DO_SIMULATION = 0 generate + + reset_n <= not RESET; + + serdes_ch1_gen : if FPGA_TYPE = 5 generate + gbe_serdes : entity work.sgmii_ecp5 + port map( + hdoutp => SD_TXD_P_OUT(0),-- + hdoutn => SD_TXD_N_OUT(0),-- + hdinp => SD_RXD_P_IN(0),-- + hdinn => SD_RXD_N_IN(0),-- + rxrefclk => CLK_125_IN,-- + tx_pclk => sd_rx_clk(0),--open, + txi_clk => sd_rx_clk(0),-- + txdata => "00000000",--sd_tx_data_q(7 downto 0),-- + tx_k => "0",--sd_tx_kcntl_q(0 downto 0),-- + xmit => "1",--xmit(0 downto 0),-- + tx_disp_correct => "1",--sd_tx_correct_disp_q(0 downto 0),-- + rxdata => sd_rx_data(7 downto 0),-- + rx_k => sd_rx_kcntl(0 downto 0),-- + rx_disp_err => sd_rx_disp_error(0 downto 0),-- + rx_cv_err => sd_rx_cv_error(0 downto 0),-- + signal_detect_c => '0',--signal_detected(0),-- + rx_los_low_s => los(0),-- + lsm_status_s => signal_detected(0), + ctc_urun_s => open, + ctc_orun_s => open, + rx_cdr_lol_s => rx_cdr_lol(0), + ctc_ins_s => open, + ctc_del_s => open, + sli_rst => '0', + tx_pwrup_c => tx_power(0),-- + rx_pwrup_c => rx_power(0),-- + sci_wrdata => sci_data_in_i, + sci_addr => sci_addr_i, + sci_rddata => sci_data_out_i, + sci_en_dual => reset_n, + sci_sel_dual => sci_ch_i(4), + sci_en => reset_n, + sci_sel => sci_ch_i(0), + sci_rd => sci_read_i, + sci_wrn => sci_write_i, + sci_int => open, + cyawstn => '0', + serdes_pdb => '1', --powerdown control register + pll_refclki => CLK_125_IN,-- + rsl_disable => '0',--changed 2019.05.08;16:42 + rsl_rst => '0', + serdes_rst_dual_c => '0',-- + rst_dual_c => quad_rst,-- + tx_serdes_rst_c => '0',-- + tx_pcs_rst_c => '0',--tx_pcs_rst(0),-- + pll_lol => tx_pll_lol,-- + rsl_tx_rdy => rsl_tx_rdy, + rx_serdes_rst_c => rx_serdes_rst(0),-- + rx_pcs_rst_c => rx_pcs_rst(0),-- + rsl_rx_rdy => rsl_rx_rdy + ); + end generate serdes_ch1_gen; + + wa_position_sel <= x"0"; +--TO DO + THE_PCS_RESET : entity work.pcs_sync_reset + generic map( + IS_SYNC_SLAVE => 1,--????ß + IS_TX_RESET => 1 + ) + port map( + CLK_SYS => CLK_SYS_IN, + CLK_RXI => sd_rx_clk(0), --??correct?? + CLK_REF => CLK_125_IN, + RESET => RESET, + CLEAR => '0', + + SFP_LOS => SD_LOS_IN(0), + TX_LOL => tx_pll_lol, + RX_CDR_LOL => rx_cdr_lol(0), + RX_LOS => los(0), + WA_POSITION => wa_position_sel, + + RX_SERDES_RST => rx_serdes_rst(0), + RX_PCS_RST => rx_pcs_rst(0), + QUAD_RST => quad_rst, + TX_PCS_RST => tx_pcs_rst(0), + + SERDES_RX_READY_IN => rsl_rx_rdy, + SERDES_TX_READY_IN => rsl_tx_rdy, + + STAT_TX_CONTROL => stat_tx_control_i, + STAT_RX_CONTROL => stat_rx_control_i, + DEBUG_TX_CONTROL => open,--debug_tx_control_i, + DEBUG_RX_CONTROL => open,--debug_rx_control_i, + STAT_RESET => stat_fsm_reset_i, + DEBUG_OUT => open--debug_med_sync_control_i + ); + + + + THE_SCI_READER : entity work.sci_reader + port map( + CLK => CLK_SYS_IN, + RESET => RESET, + + --SCI + SCI_WRDATA => sci_data_in_i, + SCI_RDDATA => sci_data_out_i, + SCI_ADDR => sci_addr_i, + SCI_SEL => sci_ch_i, + SCI_RD => sci_read_i, + SCI_WR => sci_write_i, + + WA_POS_OUT => wa_position, + + --Slowcontrol + BUS_RX => BUS_SCI_RX, + BUS_TX => BUS_SCI_TX, + + MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i, + MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i, + MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i, + --MEDIA_STATUS_REG_IN(127 downto 96) => stat_med, + MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'), + DEBUG_OUT => open + ); + + DEBUG_CLK : process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + cnt_125_dbg <= cnt_125_dbg + 1; + end if; + end process DEBUG_CLK; + + DEBUG : process(CLK_SYS_IN) + begin + if rising_edge(CLK_SYS_IN) then + DEBUG_OUT(0) <= xmit(0); + DEBUG_OUT(1) <= los(0); + DEBUG_OUT(2) <= signal_detected(0); + DEBUG_OUT(3) <= tx_pll_lol; + DEBUG_OUT(4) <= rx_cdr_lol(0); + DEBUG_OUT(5) <= sd_rx_cv_error(0); + DEBUG_OUT(6) <= sd_rx_disp_error(0); + DEBUG_OUT(8 downto 7) <= operational_rate(1 downto 0); + DEBUG_OUT(9) <= rx_compensation_err(0); + DEBUG_OUT(10)<= an_link_ok(0); + DEBUG_OUT(11)<= MAC_READY_CONF_OUT(0); + DEBUG_OUT(12)<= an_complete(0); + DEBUG_OUT(13)<= rsl_rx_rdy; + DEBUG_OUT(14)<= rsl_tx_rdy; + DEBUG_OUT(15)<= cnt_125_dbg(30); + end if; + end process DEBUG; + + + end generate impl_gen; + + sim_gen : if DO_SIMULATION = 1 generate + + process + begin + + MAC_AN_READY_OUT <= (others => '0'); + wait for 2 us; + MAC_AN_READY_OUT <= (others => '1'); + + wait; + end process; + + process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + MAC_TX_READ_OUT <= MAC_FIFOAVAIL_IN; + + fifo_eof_q <= MAC_FIFOEOF_IN; + fifo_eof_qq <= fifo_eof_q; + fifo_eof_qqq <= fifo_eof_qq; + fifo_eof_qqqq <= fifo_eof_qqq; + + MAC_TX_DONE_OUT <= fifo_eof_qqqq; -- MAC_FIFOEOF_IN; + end if; + end process; + + + end generate sim_gen; + + +end architecture RTL; diff --git a/gbe_trb/base/gbe_med_interface_sfp.vhd b/gbe_trb/base/gbe_med_interface_sfp.vhd new file mode 100644 index 0000000..b867021 --- /dev/null +++ b/gbe_trb/base/gbe_med_interface_sfp.vhd @@ -0,0 +1,918 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; + +use work.trb_net_gbe_components.all; +use work.config.all; + +entity gbe_med_interface is + generic ( + DO_SIMULATION : integer range 0 to 1; + NUMBER_OF_GBE_LINKS : integer range 1 to 4; + LINKS_ACTIVE : std_logic_vector(3 downto 0) + ); + port ( + RESET : in std_logic; + GSR_N : in std_logic; + CLK_SYS_IN : in std_logic; + CLK_125_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + CLK_125_IN : in std_logic; + CLK_125_RX_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + -- MAC status and config + MAC_READY_CONF_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RECONF_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_AN_READY_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + -- MAC data interface + MAC_FIFOAVAIL_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_FIFOEOF_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_FIFOEMPTY_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_FIFOFULL_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + MAC_TX_DATA_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + MAC_TX_READ_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_DISCRFRM_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_STAT_EN_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_TX_STATS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 31 - 1 downto 0); + MAC_TX_DONE_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + MAC_RX_FIFO_ERR_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_STATS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 32 - 1 downto 0); + MAC_RX_DATA_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + MAC_RX_WRITE_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_STAT_EN_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_EOF_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + MAC_RX_ERROR_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + --SFP Connection + SD_RXD_P_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_RXD_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_TXD_P_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_TXD_N_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_PRSNT_N_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + SD_LOS_IN : in std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable + + --CONTROL INTERFACE + BUS_SCI_RX : in CTRLBUS_RX; + BUS_SCI_TX : out CTRLBUS_TX; + + DEBUG_OUT : out std_logic_vector(255 downto 0) + ); +end entity gbe_med_interface; + +architecture RTL of gbe_med_interface is + + component sgmii_gbe_pcs35_core +port( rst_n : in std_logic; + signal_detect : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + operational_rate : in std_logic_vector(1 downto 0); + debug_link_timer_short : in std_logic; + + force_isolate : in std_logic; + force_loopback : in std_logic; + force_unidir : in std_logic; + + rx_compensation_err : out std_logic; + + ctc_drop_flag : out std_logic; + ctc_add_flag : out std_logic; + an_link_ok : out std_logic; + + tx_clk_125 : in std_logic; + tx_clock_enable_source : out std_logic; + tx_clock_enable_sink : in std_logic; + tx_d : in std_logic_vector(7 downto 0); + tx_en : in std_logic; + tx_er : in std_logic; + rx_clk_125 : in std_logic; + rx_clock_enable_source : out std_logic; + rx_clock_enable_sink : in std_logic; + rx_d : out std_logic_vector(7 downto 0); + rx_dv : out std_logic; + rx_er : out std_logic; + col : out std_logic; + crs : out std_logic; + tx_data : out std_logic_vector(7 downto 0); + tx_kcntl : out std_logic; + tx_disparity_cntl : out std_logic; + + xmit_autoneg : out std_logic; + + serdes_recovered_clk : in std_logic; + rx_data : in std_logic_vector(7 downto 0); + rx_even : in std_logic; + rx_kcntl : in std_logic; + rx_disp_err : in std_logic; + rx_cv_err : in std_logic; + rx_err_decode_mode : in std_logic; + mr_an_complete : out std_logic; + mr_page_rx : out std_logic; + mr_lp_adv_ability : out std_logic_vector(15 downto 0); + mr_main_reset : in std_logic; + mr_an_enable : in std_logic; + mr_restart_an : in std_logic; + mr_adv_ability : in std_logic_vector(15 downto 0) + ); +end component; + +component reset_controller_pcs port ( + rst_n : in std_logic; + clk : in std_logic; + tx_plol : in std_logic; + rx_cdr_lol : in std_logic; + quad_rst_out : out std_logic; + tx_pcs_rst_out : out std_logic; + rx_pcs_rst_out : out std_logic + ); +end component; + +component register_interface_hb port ( + rst_n : in std_logic; + hclk : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + hcs_n : in std_logic; + hwrite_n : in std_logic; + haddr : in std_logic_vector(3 downto 0); + hdatain : in std_logic_vector(7 downto 0); + hdataout : out std_logic_vector(7 downto 0); + hready_n : out std_logic; + mr_an_complete : in std_logic; + mr_page_rx : in std_logic; + mr_lp_adv_ability : in std_logic_vector(15 downto 0); + mr_main_reset : out std_logic; + mr_an_enable : out std_logic; + mr_restart_an : out std_logic; + mr_adv_ability : out std_logic_vector(15 downto 0) + ); +end component; + +component tsmac35 --tsmac36 --tsmac35 +port( + --------------- clock and reset port declarations ------------------ + hclk : in std_logic; + txmac_clk : in std_logic; + rxmac_clk : in std_logic; + reset_n : in std_logic; + txmac_clk_en : in std_logic; + rxmac_clk_en : in std_logic; + ------------------- Input signals to the GMII ---------------- + rxd : in std_logic_vector(7 downto 0); + rx_dv : in std_logic; + rx_er : in std_logic; + col : in std_logic; + crs : in std_logic; + -------------------- Input signals to the CPU I/F ------------------- + haddr : in std_logic_vector(7 downto 0); + hdatain : in std_logic_vector(7 downto 0); + hcs_n : in std_logic; + hwrite_n : in std_logic; + hread_n : in std_logic; + ---------------- Input signals to the Tx MAC FIFO I/F --------------- + tx_fifodata : in std_logic_vector(7 downto 0); + tx_fifoavail : in std_logic; + tx_fifoeof : in std_logic; + tx_fifoempty : in std_logic; + tx_sndpaustim : in std_logic_vector(15 downto 0); + tx_sndpausreq : in std_logic; + tx_fifoctrl : in std_logic; + ---------------- Input signals to the Rx MAC FIFO I/F --------------- + rx_fifo_full : in std_logic; + ignore_pkt : in std_logic; + -------------------- Output signals from the GMII ----------------------- + txd : out std_logic_vector(7 downto 0); + tx_en : out std_logic; + tx_er : out std_logic; + -------------------- Output signals from the CPU I/F ------------------- + hdataout : out std_logic_vector(7 downto 0); + hdataout_en_n : out std_logic; + hready_n : out std_logic; + cpu_if_gbit_en : out std_logic; + ---------------- Output signals from the Tx MAC FIFO I/F --------------- + tx_macread : out std_logic; + tx_discfrm : out std_logic; + tx_staten : out std_logic; + tx_done : out std_logic; + tx_statvec : out std_logic_vector(30 downto 0); + ---------------- Output signals from the Rx MAC FIFO I/F --------------- + rx_fifo_error : out std_logic; + rx_stat_vector : out std_logic_vector(31 downto 0); + rx_dbout : out std_logic_vector(7 downto 0); + rx_write : out std_logic; + rx_stat_en : out std_logic; + rx_eof : out std_logic; + rx_error : out std_logic +); +end component; + + signal sd_rx_clk : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_tx_kcntl_q, sd_tx_kcntl : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_tx_data_q, sd_tx_data : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal xmit : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_tx_correct_disp_q, sd_tx_correct_disp : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_rx_data, sd_rx_data_q : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal sd_rx_kcntl, sd_rx_kcntl_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_rx_disp_error, sd_rx_disp_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal sd_rx_cv_error, sd_rx_cv_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tx_power, rx_power : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal los, signal_detected : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal rx_cdr_lol: std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tx_pll_lol, quad_rst : std_logic; + signal tx_pcs_rst, rx_pcs_rst, rx_serdes_rst : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + --signal rst_n : std_logic; + signal rx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal operational_rate : std_logic_vector(NUMBER_OF_GBE_LINKS * 2 - 1 downto 0); + signal an_complete : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_page_rx : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_lp_adv_ability : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0); + signal mr_main_reset : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_restart_an : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal mr_adv_ability : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0); + signal mr_an_enable : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_rxd, pcs_rxd_q, pcs_rxd_qq : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal pcs_rx_en, pcs_rx_en_q, pcs_rx_en_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_rx_er, pcs_rx_er_q, pcs_rx_er_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_col, pcs_crs : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_txd, pcs_txd_q, pcs_txd_qq : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal pcs_tx_en, pcs_tx_en_q, pcs_tx_en_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal pcs_tx_er, pcs_tx_er_q, pcs_tx_er_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hdataout_en_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hready_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hread_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hwrite_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hcs_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal tsm_hdata : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal tsm_haddr : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0); + signal rx_compensation_err, an_link_ok : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + + signal synced_rst, ff : std_logic; + + signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); + signal rsl_rx_rdy,rsl_tx_rdy : std_logic; + + signal sci_data_in_i : std_logic_vector(7 downto 0); + signal sci_addr_i : std_logic_vector(5 downto 0); + signal sci_data_out_i : std_logic_vector(7 downto 0); + signal reset_n, sci_read_i, sci_write_i : std_logic; + signal sci_ch_i : std_logic_vector(4 downto 0); + signal wa_position : std_logic_vector(15 downto 0) := x"FFFF"; + signal wa_position_sel : std_logic_vector(3 downto 0); + + signal stat_fsm_reset_i, stat_tx_control_i, stat_rx_control_i : std_logic_vector(31 downto 0); + signal cnt_125_dbg : unsigned(30 downto 0) := (others => '0'); + +begin + + rx_power <= "1111"; + tx_power <= "1111"; + + --rst_n <= not RESET; + + reset_sync : process(GSR_N, CLK_SYS_IN) + begin + if (GSR_N = '0') then + ff <= '0'; + synced_rst <= '0'; + elsif rising_edge(CLK_SYS_IN) then + ff <= '1'; + synced_rst <= ff; + end if; + end process reset_sync; + + SD_TXDIS_OUT <= "0000"; + + CLK_125_OUT <= CLK_125_IN & CLK_125_IN & CLK_125_IN & CLK_125_IN; + CLK_125_RX_OUT <= sd_rx_clk; + + impl_gen : if DO_SIMULATION = 0 generate + + serdes_ch4_gen : if FPGA_TYPE /= 5 generate + gbe_serdes : entity work.serdes_gbe_4ch + port map( + ------------------ + -- CH0 -- + hdinp_ch0 => SD_RXD_P_IN(0), + hdinn_ch0 => SD_RXD_N_IN(0), + hdoutp_ch0 => SD_TXD_P_OUT(0), + hdoutn_ch0 => SD_TXD_N_OUT(0), + rxiclk_ch0 => sd_rx_clk(0), + txiclk_ch0 => CLK_125_IN, + rx_full_clk_ch0 => sd_rx_clk(0), + rx_half_clk_ch0 => open, + tx_full_clk_ch0 => open, + tx_half_clk_ch0 => open, + fpga_rxrefclk_ch0 => CLK_125_IN, + txdata_ch0 => sd_tx_data_q(7 downto 0), + tx_k_ch0 => sd_tx_kcntl_q(0), + xmit_ch0 => xmit(0), + tx_disp_correct_ch0 => sd_tx_correct_disp_q(0), + rxdata_ch0 => sd_rx_data(7 downto 0), + rx_k_ch0 => sd_rx_kcntl(0), + rx_disp_err_ch0 => sd_rx_disp_error(0), + rx_cv_err_ch0 => sd_rx_cv_error(0), + rx_serdes_rst_ch0_c => rx_serdes_rst(0), + sb_felb_ch0_c => '0', + sb_felb_rst_ch0_c => '0', + tx_pwrup_ch0_c => tx_power(0), + rx_pwrup_ch0_c => rx_power(0), + rx_los_low_ch0_s => los(0), + lsm_status_ch0_s => signal_detected(0), + rx_cdr_lol_ch0_s => rx_cdr_lol(0), + tx_pcs_rst_ch0_c => tx_pcs_rst(0), + rx_pcs_rst_ch0_c => rx_pcs_rst(0), + -- CH1 -- + hdinp_ch1 => SD_RXD_P_IN(1), + hdinn_ch1 => SD_RXD_N_IN(1), + hdoutp_ch1 => SD_TXD_P_OUT(1), + hdoutn_ch1 => SD_TXD_N_OUT(1), + rxiclk_ch1 => sd_rx_clk(1), + txiclk_ch1 => CLK_125_IN, + rx_full_clk_ch1 => sd_rx_clk(1), + rx_half_clk_ch1 => open, + tx_full_clk_ch1 => open, + tx_half_clk_ch1 => open, + fpga_rxrefclk_ch1 => CLK_125_IN, + txdata_ch1 => sd_tx_data_q(15 downto 8), + tx_k_ch1 => sd_tx_kcntl_q(1), + xmit_ch1 => xmit(1), + tx_disp_correct_ch1 => sd_tx_correct_disp_q(1), + rxdata_ch1 => sd_rx_data(15 downto 8), + rx_k_ch1 => sd_rx_kcntl(1), + rx_disp_err_ch1 => sd_rx_disp_error(1), + rx_cv_err_ch1 => sd_rx_cv_error(1), + rx_serdes_rst_ch1_c => rx_serdes_rst(1), + sb_felb_ch1_c => '0', + sb_felb_rst_ch1_c => '0', + tx_pwrup_ch1_c => tx_power(1), + rx_pwrup_ch1_c => rx_power(1), + rx_los_low_ch1_s => los(1), + lsm_status_ch1_s => signal_detected(1), + rx_cdr_lol_ch1_s => rx_cdr_lol(1), + tx_pcs_rst_ch1_c => tx_pcs_rst(1), + rx_pcs_rst_ch1_c => rx_pcs_rst(1), + -- CH2 -- + hdinp_ch2 => SD_RXD_P_IN(2), + hdinn_ch2 => SD_RXD_N_IN(2), + hdoutp_ch2 => SD_TXD_P_OUT(2), + hdoutn_ch2 => SD_TXD_N_OUT(2), + rxiclk_ch2 => sd_rx_clk(2), + txiclk_ch2 => CLK_125_IN, + rx_full_clk_ch2 => sd_rx_clk(2), + rx_half_clk_ch2 => open, + tx_full_clk_ch2 => open, + tx_half_clk_ch2 => open, + fpga_rxrefclk_ch2 => CLK_125_IN, + txdata_ch2 => sd_tx_data_q(23 downto 16), + tx_k_ch2 => sd_tx_kcntl_q(2), + xmit_ch2 => xmit(2), + tx_disp_correct_ch2 => sd_tx_correct_disp_q(2), + rxdata_ch2 => sd_rx_data(23 downto 16), + rx_k_ch2 => sd_rx_kcntl(2), + rx_disp_err_ch2 => sd_rx_disp_error(2), + rx_cv_err_ch2 => sd_rx_cv_error(2), + rx_serdes_rst_ch2_c => rx_serdes_rst(2), + sb_felb_ch2_c => '0', + sb_felb_rst_ch2_c => '0', + tx_pwrup_ch2_c => tx_power(2), + rx_pwrup_ch2_c => rx_power(2), + rx_los_low_ch2_s => los(2), + lsm_status_ch2_s => signal_detected(2), + rx_cdr_lol_ch2_s => rx_cdr_lol(2), + tx_pcs_rst_ch2_c => tx_pcs_rst(2), + rx_pcs_rst_ch2_c => rx_pcs_rst(2), + -- CH3 -- + hdinp_ch3 => SD_RXD_P_IN(3), + hdinn_ch3 => SD_RXD_N_IN(3), + hdoutp_ch3 => SD_TXD_P_OUT(3), + hdoutn_ch3 => SD_TXD_N_OUT(3), + rxiclk_ch3 => sd_rx_clk(3), + txiclk_ch3 => CLK_125_IN, + rx_full_clk_ch3 => sd_rx_clk(3), + rx_half_clk_ch3 => open, + tx_full_clk_ch3 => open, + tx_half_clk_ch3 => open, + fpga_rxrefclk_ch3 => CLK_125_IN, + txdata_ch3 => sd_tx_data_q(31 downto 24), + tx_k_ch3 => sd_tx_kcntl_q(3), + xmit_ch3 => xmit(3), + tx_disp_correct_ch3 => sd_tx_correct_disp_q(3), + rxdata_ch3 => sd_rx_data(31 downto 24), + rx_k_ch3 => sd_rx_kcntl(3), + rx_disp_err_ch3 => sd_rx_disp_error(3), + rx_cv_err_ch3 => sd_rx_cv_error(3), + rx_serdes_rst_ch3_c => rx_serdes_rst(3), + sb_felb_ch3_c => '0', + sb_felb_rst_ch3_c => '0', + tx_pwrup_ch3_c => tx_power(3), + rx_pwrup_ch3_c => rx_power(3), + rx_los_low_ch3_s => los(3), + lsm_status_ch3_s => signal_detected(3), + rx_cdr_lol_ch3_s => rx_cdr_lol(3), + tx_pcs_rst_ch3_c => tx_pcs_rst(3), + rx_pcs_rst_ch3_c => rx_pcs_rst(3), + ---- Miscillaneous ports + fpga_txrefclk => CLK_125_IN, + tx_serdes_rst_c => '0', + tx_pll_lol_qd_s => tx_pll_lol, + tx_sync_qd_c => '0', + rst_qd_c => quad_rst, + serdes_rst_qd_c => '0' + ); + end generate serdes_ch4_gen; + + reset_n <= not RESET; + + serdes_ch1_gen : if FPGA_TYPE = 5 generate + gbe_serdes : entity work.serdes_sync_1--sgmii_ecp5 + port map( +-- hdoutp => SD_TXD_P_OUT(0),-- +-- hdoutn => SD_TXD_N_OUT(0),-- +-- hdinp => SD_RXD_P_IN(0),-- +-- hdinn => SD_RXD_N_IN(0),-- +-- rxrefclk => CLK_125_IN,-- +-- tx_pclk => sd_rx_clk(0),--open, +-- txi_clk => sd_rx_clk(0),-- +-- txdata => sd_tx_data_q(7 downto 0),-- +-- tx_k => sd_tx_kcntl_q(0 downto 0),-- +-- xmit => xmit(0 downto 0),-- +-- tx_disp_correct => sd_tx_correct_disp_q(0 downto 0),-- +-- rxdata => sd_rx_data(7 downto 0),-- +-- rx_k => sd_rx_kcntl(0 downto 0),-- +-- rx_disp_err => sd_rx_disp_error(0 downto 0),-- +-- rx_cv_err => sd_rx_cv_error(0 downto 0),-- +-- signal_detect_c => '0',--signal_detected(0),-- +-- rx_los_low_s => los(0),-- +-- lsm_status_s => signal_detected(0), +-- ctc_urun_s => open, +-- ctc_orun_s => open, +-- rx_cdr_lol_s => rx_cdr_lol(0), +-- ctc_ins_s => open, +-- ctc_del_s => open, +-- sli_rst => '0', +-- tx_pwrup_c => tx_power(0),-- +-- rx_pwrup_c => rx_power(0),-- +-- sci_wrdata => sci_data_in_i, +-- sci_addr => sci_addr_i, +-- sci_rddata => sci_data_out_i, +-- sci_en_dual => reset_n, +-- sci_sel_dual => sci_ch_i(4), +-- sci_en => reset_n, +-- sci_sel => sci_ch_i(0), +-- sci_rd => sci_read_i, +-- sci_wrn => sci_write_i, +-- sci_int => open, +-- cyawstn => '0', +-- serdes_pdb => '1', --powerdown control register +-- pll_refclki => CLK_125_IN,-- +-- rsl_disable => '0',--changed 2019.05.08;16:42 +-- rsl_rst => '0', +-- serdes_rst_dual_c => '0',-- +-- rst_dual_c => quad_rst,-- +-- tx_serdes_rst_c => '0',-- +-- tx_pcs_rst_c => '0',--tx_pcs_rst(0),-- +-- pll_lol => tx_pll_lol,-- +-- rsl_tx_rdy => rsl_tx_rdy, +-- rx_serdes_rst_c => rx_serdes_rst(0),-- +-- rx_pcs_rst_c => rx_pcs_rst(0),-- +-- rsl_rx_rdy => rsl_rx_rdy + + hdoutp => SD_TXD_P_OUT(0), + hdoutn => SD_TXD_N_OUT(0),-- + hdinp => SD_RXD_P_IN(0),--: in std_logic; + hdinn => SD_RXD_N_IN(0),--: in std_logic; + rxrefclk=> CLK_125_IN, + rx_pclk => sd_rx_clk(0),--open, + tx_pclk => open, + txdata => x"00", + tx_k => "0", + tx_force_disp => "0", + tx_disp_sel => "0", + rxdata => open, + rx_k=> open, + rx_disp_err=> open, + rx_cv_err=> open, + tx_idle_c => '1', + signal_detect_c => '0', + rx_los_low_s=> los(0),-- + lsm_status_s=> signal_detected(0), + rx_cdr_lol_s=> rx_cdr_lol(0), + sli_rst => '0', + tx_pwrup_c => '1', + rx_pwrup_c => '1', + sci_wrdata => sci_data_in_i, + sci_addr => sci_addr_i, + sci_rddata => sci_data_out_i, + sci_en_dual => reset_n, + sci_sel_dual => sci_ch_i(4), + sci_en => reset_n, + sci_sel => sci_ch_i(0), + sci_rd => sci_read_i, + sci_wrn => sci_write_i, + sci_int => open, + cyawstn => '0', + serdes_pdb => '0', + pll_refclki => CLK_125_IN, + rsl_disable => '0', + rsl_rst => '0', + serdes_rst_dual_c => '0', + rst_dual_c => quad_rst, + tx_serdes_rst_c => '0', + tx_pcs_rst_c => '0', + pll_lol => tx_pll_lol, + rsl_tx_rdy => rsl_tx_rdy, + rx_serdes_rst_c => rx_serdes_rst(0),-- + rx_pcs_rst_c => rx_pcs_rst(0),-- + rsl_rx_rdy => rsl_rx_rdy + ); + end generate serdes_ch1_gen; + + wa_position_sel <= x"0"; +--TO DO + THE_PCS_RESET : entity work.pcs_sync_reset + generic map( + IS_SYNC_SLAVE => 1,--????ß + IS_TX_RESET => 1 + ) + port map( + CLK_SYS => CLK_SYS_IN, + CLK_RXI => sd_rx_clk(0), --??correct?? + CLK_REF => CLK_125_IN, + RESET => RESET, + CLEAR => '0', + + SFP_LOS => SD_LOS_IN(0), + TX_LOL => tx_pll_lol, + RX_CDR_LOL => rx_cdr_lol(0), + RX_LOS => los(0), + WA_POSITION => wa_position_sel, + + RX_SERDES_RST => rx_serdes_rst(0), + RX_PCS_RST => rx_pcs_rst(0), + QUAD_RST => quad_rst, + TX_PCS_RST => tx_pcs_rst(0), + + SERDES_RX_READY_IN => rsl_rx_rdy, + SERDES_TX_READY_IN => rsl_tx_rdy, + + STAT_TX_CONTROL => stat_tx_control_i, + STAT_RX_CONTROL => stat_rx_control_i, + DEBUG_TX_CONTROL => open,--debug_tx_control_i, + DEBUG_RX_CONTROL => open,--debug_rx_control_i, + STAT_RESET => stat_fsm_reset_i, + DEBUG_OUT => open--debug_med_sync_control_i + ); + + + + THE_SCI_READER : entity work.sci_reader + port map( + CLK => CLK_SYS_IN, + RESET => RESET, + + --SCI + SCI_WRDATA => sci_data_in_i, + SCI_RDDATA => sci_data_out_i, + SCI_ADDR => sci_addr_i, + SCI_SEL => sci_ch_i, + SCI_RD => sci_read_i, + SCI_WR => sci_write_i, + + WA_POS_OUT => wa_position, + + --Slowcontrol + BUS_RX => BUS_SCI_RX, + BUS_TX => BUS_SCI_TX, + + MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i, + MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i, + MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i, + --MEDIA_STATUS_REG_IN(127 downto 96) => stat_med, + MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'), + DEBUG_OUT => open + ); + + DEBUG_CLK : process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + cnt_125_dbg <= cnt_125_dbg + 1; + end if; + end process DEBUG_CLK; + + DEBUG : process(CLK_SYS_IN) + begin + if rising_edge(CLK_SYS_IN) then + DEBUG_OUT(0) <= xmit(0); + DEBUG_OUT(1) <= los(0); + DEBUG_OUT(2) <= signal_detected(0); + DEBUG_OUT(3) <= tx_pll_lol; + DEBUG_OUT(4) <= rx_cdr_lol(0); + DEBUG_OUT(5) <= sd_rx_cv_error(0); + DEBUG_OUT(6) <= sd_rx_disp_error(0); + DEBUG_OUT(8 downto 7) <= operational_rate(1 downto 0); + DEBUG_OUT(9) <= rx_compensation_err(0); + DEBUG_OUT(10)<= an_link_ok(0); + DEBUG_OUT(11)<= MAC_READY_CONF_OUT(0); + DEBUG_OUT(12)<= an_complete(0); + DEBUG_OUT(13)<= rsl_rx_rdy; + DEBUG_OUT(14)<= rsl_tx_rdy; + DEBUG_OUT(15)<= cnt_125_dbg(30); + end if; + end process DEBUG; + + + SYNC_TX_PROC : process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + sd_tx_data_q <= sd_tx_data; + sd_tx_kcntl_q <= sd_tx_kcntl; + sd_tx_correct_disp_q <= sd_tx_correct_disp; + end if; + end process SYNC_TX_PROC; + + + pcs_gen : for i in 0 to NUMBER_OF_GBE_LINKS - 1 generate + + pcs_active_gen : if LINKS_ACTIVE(i) = '1' generate + + SYNC_RX_PROC : process(sd_rx_clk) + begin + if rising_edge(sd_rx_clk(i)) then + sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8) <= sd_rx_data( (i + 1) * 8 - 1 downto i * 8); + sd_rx_kcntl_q(i) <= sd_rx_kcntl(i); + sd_rx_disp_error_q(i) <= sd_rx_disp_error(i); + sd_rx_cv_error_q(i) <= sd_rx_cv_error(i); + end if; + end process SYNC_RX_PROC; + + SGMII_GBE_PCS : sgmii_gbe_pcs35_core + port map( + rst_n => synced_rst, --rst_n, + signal_detect => signal_detected(i), + gbe_mode => '1', + sgmii_mode => '0', + operational_rate => operational_rate( (i + 1) * 2 - 1 downto (i * 2)), + debug_link_timer_short => '0', + + force_isolate => '0', + force_loopback => '0', + force_unidir => '0', + + rx_compensation_err => rx_compensation_err(i), + + ctc_drop_flag => open, + ctc_add_flag => open, + an_link_ok => an_link_ok(i), + + -- MAC interface + tx_clk_125 => CLK_125_IN, --refclkcore, -- original clock from SerDes + tx_clock_enable_source => tx_clk_en(i), + tx_clock_enable_sink => tx_clk_en(i), + tx_d => pcs_txd( (i + 1) * 8 - 1 downto i * 8), -- TX data from MAC + tx_en => pcs_tx_en(i), -- TX data enable from MAC + tx_er => pcs_tx_er(i), -- TX error from MAC + rx_clk_125 => sd_rx_clk(i), + rx_clock_enable_source => rx_clk_en(i), + rx_clock_enable_sink => rx_clk_en(i), + rx_d => pcs_rxd( (i + 1) * 8 - 1 downto i * 8), -- RX data to MAC + rx_dv => pcs_rx_en(i), -- RX data enable to MAC + rx_er => pcs_rx_er(i), -- RX error to MAC + col => pcs_col(i), + crs => pcs_crs(i), + + -- SerDes interface + tx_data => sd_tx_data( (i + 1) * 8 - 1 downto i * 8), -- TX data to SerDes + tx_kcntl => sd_tx_kcntl(i), -- TX komma control to SerDes + tx_disparity_cntl => sd_tx_correct_disp(i), -- idle parity state control in IPG (to SerDes) + + xmit_autoneg => xmit(i), + + serdes_recovered_clk => sd_rx_clk(i), -- 125MHz recovered from receive bit stream + rx_data => sd_rx_data_q( (i + 1) * 8 - 1 downto i * 8), -- RX data from SerDes + rx_kcntl => sd_rx_kcntl_q(i), -- RX komma control from SerDes + rx_err_decode_mode => '0', -- receive error control mode fixed to normal + rx_even => '0', -- unused (receive error control mode = normal, tie to GND) + rx_disp_err => sd_rx_disp_error_q(i), -- RX disparity error from SerDes + rx_cv_err => sd_rx_cv_error_q(i), -- RX code violation error from SerDes + -- Autonegotiation stuff + mr_an_complete => an_complete(i), + mr_page_rx => mr_page_rx(i), + mr_lp_adv_ability => mr_lp_adv_ability( (i + 1) * 16 - 1 downto i * 16), + mr_main_reset => mr_main_reset(i), + mr_an_enable => '1', + mr_restart_an => '0',--mr_restart_an(i), + mr_adv_ability => mr_adv_ability( (i + 1) * 16 - 1 downto i * 16) + ); + + MAC_AN_READY_OUT(i) <= an_complete(i); + +-- u0_reset_controller_pcs : reset_controller_pcs port map( +-- rst_n => synced_rst, --rst_n, +-- clk => CLK_125_IN, +-- tx_plol => tx_pll_lol, +-- rx_cdr_lol => rx_cdr_lol(i), +-- quad_rst_out => open, --quad_rst, +-- tx_pcs_rst_out => tx_pcs_rst(i), +-- rx_pcs_rst_out => rx_pcs_rst(i) +-- ); +-- +-- u0_reset_controller_cdr : reset_controller_cdr port map( +-- rst_n => synced_rst, --rst_n, +-- clk => CLK_125_IN, +-- cdr_lol => rx_cdr_lol(i), +-- cdr_rst_out => rx_serdes_rst(i) +-- ); + +-- u0_rate_resolution : rate_resolution port map( +-- gbe_mode => '1', +-- sgmii_mode => '0', +-- an_enable => '1', +-- advertised_rate => mr_adv_ability(i * 16 + 11 downto i * 16 + 10), +-- link_partner_rate => mr_lp_adv_ability(i * 16 + 11 downto i * 16 + 10), +-- non_an_rate => "10", -- 1Gbps is rate when auto-negotiation disabled +-- +-- operational_rate => operational_rate( (i + 1) * 2 - 1 downto i * 2) +-- ); + + u0_ri : register_interface_hb port map( + -- Control Signals + rst_n => synced_rst, --rst_n, + hclk => CLK_125_IN, + gbe_mode => '1', + sgmii_mode => '0', + + -- Host Bus + hcs_n => '1', + hwrite_n => '1', + haddr => (others => '0'), + hdatain => (others => '0'), + + hdataout => open, + hready_n => open, + + -- Register Outputs + mr_an_enable => mr_an_enable(i), + mr_restart_an => mr_restart_an(i), + mr_main_reset => mr_main_reset(i), + mr_adv_ability => mr_adv_ability( (i + 1 ) * 16 - 1 downto i * 16), + + -- Register Inputs + mr_an_complete => an_complete(i), + mr_page_rx => mr_page_rx(i), + mr_lp_adv_ability => mr_lp_adv_ability( (i + 1 ) * 16 - 1 downto i * 16) + ); + + MAC: tsmac35 + port map( + ----------------- clock and reset port declarations ------------------ + hclk => CLK_SYS_IN, + txmac_clk => CLK_125_IN, + rxmac_clk => sd_rx_clk(i), + reset_n => GSR_N, + txmac_clk_en => '1', + rxmac_clk_en => '1', + ------------------- Input signals to the GMII ---------------- + rxd => pcs_rxd_qq( (i + 1) * 8 - 1 downto i * 8), + rx_dv => pcs_rx_en_qq(i), + rx_er => pcs_rx_er_qq(i), + col => pcs_col(i), + crs => pcs_crs(i), + -------------------- Input signals to the CPU I/F ------------------- + haddr => tsm_haddr( (i + 1) * 8 - 1 downto i * 8), + hdatain => tsm_hdata( (i + 1) * 8 - 1 downto i * 8), + hcs_n => tsm_hcs_n(i), + hwrite_n => tsm_hwrite_n(i), + hread_n => tsm_hread_n(i), + ---------------- Input signals to the Tx MAC FIFO I/F --------------- + tx_fifodata => MAC_TX_DATA_IN( (i + 1) * 8 - 1 downto i * 8), + tx_fifoavail => MAC_FIFOAVAIL_IN(i), + tx_fifoeof => MAC_FIFOEOF_IN(i), + tx_fifoempty => MAC_FIFOEMPTY_IN(i), + tx_sndpaustim => x"0000", + tx_sndpausreq => '0', + tx_fifoctrl => '0', -- always data frame + ---------------- Input signals to the Rx MAC FIFO I/F --------------- + rx_fifo_full => MAC_RX_FIFOFULL_IN(i), --'0', + ignore_pkt => '0', + ---------------- Output signals from the GMII ----------------------- + txd => pcs_txd( (i + 1) * 8 - 1 downto i * 8), + tx_en => pcs_tx_en(i), + tx_er => pcs_tx_er(i), + ----------------- Output signals from the CPU I/F ------------------- + hdataout => open, + hdataout_en_n => tsm_hdataout_en_n(i), + hready_n => tsm_hready_n(i), + cpu_if_gbit_en => open, + ------------- Output signals from the Tx MAC FIFO I/F --------------- + tx_macread => MAC_TX_READ_OUT(i), + tx_discfrm => MAC_TX_DISCRFRM_OUT(i), + tx_staten => MAC_TX_STAT_EN_OUT(i), + tx_statvec => MAC_TX_STATS_OUT( (i + 1) * 31 - 1 downto i * 31), + tx_done => MAC_TX_DONE_OUT(i), + ------------- Output signals from the Rx MAC FIFO I/F --------------- + rx_fifo_error => MAC_RX_FIFO_ERR_OUT(i), + rx_stat_vector => MAC_RX_STATS_OUT( (i + 1) * 32 - 1 downto i * 32), + rx_dbout => MAC_RX_DATA_OUT( (i + 1) * 8 - 1 downto i * 8), + rx_write => MAC_RX_WRITE_OUT(i), + rx_stat_en => MAC_RX_STAT_EN_OUT(i), + rx_eof => MAC_RX_EOF_OUT(i), + rx_error => MAC_RX_ERROR_OUT(i) + ); + + TSMAC_CONTROLLER : trb_net16_gbe_mac_control + port map( + CLK => CLK_SYS_IN, + RESET => RESET, + + -- signals to/from main controller + MC_TSMAC_READY_OUT => MAC_READY_CONF_OUT(i), + MC_RECONF_IN => MAC_RECONF_IN(i), + MC_GBE_EN_IN => '1', + MC_RX_DISCARD_FCS => '0', + MC_PROMISC_IN => '1', + MC_MAC_ADDR_IN => (others => '0'), + + -- signal to/from Host interface of TriSpeed MAC + TSM_HADDR_OUT => tsm_haddr( (i + 1) * 8 - 1 downto i * 8), + TSM_HDATA_OUT => tsm_hdata( (i + 1) * 8 - 1 downto i * 8), + TSM_HCS_N_OUT => tsm_hcs_n(i), + TSM_HWRITE_N_OUT => tsm_hwrite_n(i), + TSM_HREAD_N_OUT => tsm_hread_n(i), + TSM_HREADY_N_IN => tsm_hready_n(i), + TSM_HDATA_EN_N_IN => tsm_hdataout_en_n(i), + + DEBUG_OUT => open + ); + + SYNC_GMII_RX_PROC : process(sd_rx_clk) + begin + if rising_edge(sd_rx_clk(i)) then + pcs_rxd_q( (i + 1) * 8 - 1 downto i * 8) <= pcs_rxd( (i + 1) * 8 - 1 downto i * 8); + pcs_rx_en_q(i) <= pcs_rx_en(i); + pcs_rx_er_q(i) <= pcs_rx_er(i); + + pcs_rxd_qq( (i + 1) * 8 - 1 downto i * 8) <= pcs_rxd_q( (i + 1) * 8 - 1 downto i * 8); + pcs_rx_en_qq(i) <= pcs_rx_en_q(i); + pcs_rx_er_qq(i) <= pcs_rx_er_q(i); + end if; + end process SYNC_GMII_RX_PROC; + + SYNC_GMII_TX_PROC : process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + pcs_txd_q( (i + 1) * 8 - 1 downto i * 8) <= pcs_txd( (i + 1) * 8 - 1 downto i * 8); + pcs_tx_en_q <= pcs_tx_en; + pcs_tx_er_q <= pcs_tx_er; + + pcs_txd_qq( (i + 1) * 8 - 1 downto i * 8) <= pcs_txd_q( (i + 1) * 8 - 1 downto i * 8); + pcs_tx_en_qq <= pcs_tx_en_q; + pcs_tx_er_qq <= pcs_tx_er_q; + end if; + end process SYNC_GMII_TX_PROC; + + end generate pcs_active_gen; + + end generate pcs_gen; + + end generate impl_gen; + + sim_gen : if DO_SIMULATION = 1 generate + + process + begin + + MAC_AN_READY_OUT <= (others => '0'); + wait for 2 us; + MAC_AN_READY_OUT <= (others => '1'); + + wait; + end process; + + process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + MAC_TX_READ_OUT <= MAC_FIFOAVAIL_IN; + + fifo_eof_q <= MAC_FIFOEOF_IN; + fifo_eof_qq <= fifo_eof_q; + fifo_eof_qqq <= fifo_eof_qq; + fifo_eof_qqqq <= fifo_eof_qqq; + + MAC_TX_DONE_OUT <= fifo_eof_qqqq; -- MAC_FIFOEOF_IN; + end if; + end process; + + + end generate sim_gen; + + +end architecture RTL; diff --git a/gbe_trb/ipcores/ecp5/_math_real.vhd b/gbe_trb/ipcores/ecp5/_math_real.vhd new file mode 100644 index 0000000..ad185b2 --- /dev/null +++ b/gbe_trb/ipcores/ecp5/_math_real.vhd @@ -0,0 +1,2574 @@ + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. +-- +-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package defines a standard for designers to use in +-- describing VHDL models that make use of common REAL constants +-- and common REAL elementary mathematical functions. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076- +-- 1993. +-- +-- Notes: +-- No declarations or definitions shall be included in, or +-- excluded from, this package. +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to provide a guideline for implementations to +-- verify their implementation of MATH_REAL. Tool developers may +-- choose to implement the package body in the most efficient +-- manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package MATH_REAL is + constant CopyRightNotice: STRING + := "Copyright 1996 IEEE. All rights reserved."; + + -- + -- Constant Definitions + -- + constant MATH_E : REAL := 2.71828_18284_59045_23536; + -- Value of e + constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160; + -- Value of 1/e + constant MATH_PI : REAL := 3.14159_26535_89793_23846; + -- Value of pi + constant MATH_2_PI : REAL := 6.28318_53071_79586_47693; + -- Value of 2*pi + constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154; + -- Value of 1/pi + constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923; + -- Value of pi/2 + constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615; + -- Value of pi/3 + constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962; + -- Value of pi/4 + constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769; + -- Value 3*pi/2 + constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942; + -- Natural log of 2 + constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402; + -- Natural log of 10 + constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074; + -- Log base 2 of e + constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765; + -- Log base 10 of e + constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880; + -- square root of 2 + constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440; + -- square root of 1/2 + constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730; + -- square root of pi + constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577; + -- Conversion factor from degree to radian + constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680; + -- Conversion factor from radian to degree + + -- + -- Function Declarations + -- + function SIGN (X: in REAL ) return REAL; + -- Purpose: + -- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0 + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIGN(X)) <= 1.0 + -- Notes: + -- None + + function CEIL (X : in REAL ) return REAL; + -- Purpose: + -- Returns smallest INTEGER value (as REAL) not less than X + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CEIL(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function FLOOR (X : in REAL ) return REAL; + -- Purpose: + -- Returns largest INTEGER value (as REAL) not greater than X + -- Special values: + -- FLOOR(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- FLOOR(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function ROUND (X : in REAL ) return REAL; + -- Purpose: + -- Rounds X to the nearest integer value (as real). If X is + -- halfway between two integers, rounding is away from 0.0 + -- Special values: + -- ROUND(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ROUND(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function TRUNC (X : in REAL ) return REAL; + -- Purpose: + -- Truncates X towards 0.0 and returns truncated value + -- Special values: + -- TRUNC(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- TRUNC(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function "MOD" (X, Y: in REAL ) return REAL; + -- Purpose: + -- Returns floating point modulus of X/Y, with the same sign as + -- Y, and absolute value less than the absolute value of Y, and + -- for some INTEGER value N the result satisfies the relation + -- X = Y*N + MOD(X,Y) + -- Special values: + -- None + -- Domain: + -- X in REAL; Y in REAL and Y /= 0.0 + -- Error conditions: + -- Error if Y = 0.0 + -- Range: + -- ABS(MOD(X,Y)) < ABS(Y) + -- Notes: + -- None + + function REALMAX (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically larger of X and Y + -- Special values: + -- REALMAX(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMAX(X,Y) is mathematically unbounded + -- Notes: + -- None + + function REALMIN (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically smaller of X and Y + -- Special values: + -- REALMIN(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMIN(X,Y) is mathematically unbounded + -- Notes: + -- None + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL); + -- Purpose: + -- Returns, in X, a pseudo-random number with uniform + -- distribution in the open interval (0.0, 1.0). + -- Special values: + -- None + -- Domain: + -- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398 + -- Error conditions: + -- Error if SEED1 or SEED2 outside of valid domain + -- Range: + -- 0.0 < X < 1.0 + -- Notes: + -- a) The semantics for this function are described by the + -- algorithm published by Pierre L'Ecuyer in "Communications + -- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774. + -- The algorithm is based on the combination of two + -- multiplicative linear congruential generators for 32-bit + -- platforms. + -- + -- b) Before the first call to UNIFORM, the seed values + -- (SEED1, SEED2) have to be initialized to values in the range + -- [1, 2147483562] and [1, 2147483398] respectively. The + -- seed values are modified after each call to UNIFORM. + -- + -- c) This random number generator is portable for 32-bit + -- computers, and it has a period of ~2.30584*(10**18) for each + -- set of seed values. + -- + -- d) For information on spectral tests for the algorithm, refer + -- to the L'Ecuyer article. + + function SQRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns square root of X + -- Special values: + -- SQRT(0.0) = 0.0 + -- SQRT(1.0) = 1.0 + -- Domain: + -- X >= 0.0 + -- Error conditions: + -- Error if X < 0.0 + -- Range: + -- SQRT(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of SQRT is + -- approximately given by: + -- SQRT(X) <= SQRT(REAL'HIGH) + + function CBRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns cube root of X + -- Special values: + -- CBRT(0.0) = 0.0 + -- CBRT(1.0) = 1.0 + -- CBRT(-1.0) = -1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CBRT(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of CBRT is approximately given by: + -- ABS(CBRT(X)) <= CBRT(REAL'HIGH) + + function "**" (X : in INTEGER; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0 + -- 0**Y = 0.0; Y > 0.0 + -- X**1.0 = REAL(X); X >= 0 + -- 1**Y = 1.0 + -- Domain: + -- X > 0 + -- X = 0 for Y > 0.0 + -- X < 0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0 and Y /= 0.0 + -- Error if X = 0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function "**" (X : in REAL; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0.0 + -- 0.0**Y = 0.0; Y > 0.0 + -- X**1.0 = X; X >= 0.0 + -- 1.0**Y = 1.0 + -- Domain: + -- X > 0.0 + -- X = 0.0 for Y > 0.0 + -- X < 0.0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0.0 and Y /= 0.0 + -- Error if X = 0.0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function EXP (X : in REAL ) return REAL; + -- Purpose: + -- Returns e**X; where e = MATH_E + -- Special values: + -- EXP(0.0) = 1.0 + -- EXP(1.0) = MATH_E + -- EXP(-1.0) = MATH_1_OVER_E + -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH) + -- Domain: + -- X in REAL such that EXP(X) <= REAL'HIGH + -- Error conditions: + -- Error if X > LOG(REAL'HIGH) + -- Range: + -- EXP(X) >= 0.0 + -- Notes: + -- a) The usable domain of EXP is approximately given by: + -- X <= LOG(REAL'HIGH) + + function LOG (X : in REAL ) return REAL; + -- Purpose: + -- Returns natural logarithm of X + -- Special values: + -- LOG(1.0) = 0.0 + -- LOG(MATH_E) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG is approximately given by: + -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH) + + function LOG2 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 2 of X + -- Special values: + -- LOG2(1.0) = 0.0 + -- LOG2(2.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG2(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG2 is approximately given by: + -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH) + + function LOG10 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 10 of X + -- Special values: + -- LOG10(1.0) = 0.0 + -- LOG10(10.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG10(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG10 is approximately given by: + -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH) + + function LOG (X: in REAL; BASE: in REAL) return REAL; + -- Purpose: + -- Returns logarithm base BASE of X + -- Special values: + -- LOG(1.0, BASE) = 0.0 + -- LOG(BASE, BASE) = 1.0 + -- Domain: + -- X > 0.0 + -- BASE > 0.0 + -- BASE /= 1.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Error if BASE <= 0.0 + -- Error if BASE = 1.0 + -- Range: + -- LOG(X, BASE) is mathematically unbounded + -- Notes: + -- a) When BASE > 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE) + -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE) + + function SIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns sine of X; X in radians + -- Special values: + -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIN(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function COS ( X : in REAL ) return REAL; + -- Purpose: + -- Returns cosine of X; X in radians + -- Special values: + -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER + -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(COS(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function TAN (X : in REAL ) return REAL; + -- Purpose: + -- Returns tangent of X; X in radians + -- Special values: + -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL and + -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER + -- Error conditions: + -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an + -- INTEGER + -- Range: + -- TAN(X) is mathematically unbounded + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function ARCSIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse sine of X + -- Special values: + -- ARCSIN(0.0) = 0.0 + -- ARCSIN(1.0) = MATH_PI_OVER_2 + -- ARCSIN(-1.0) = -MATH_PI_OVER_2 + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- ABS(ARCSIN(X) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCCOS (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse cosine of X + -- Special values: + -- ARCCOS(1.0) = 0.0 + -- ARCCOS(0.0) = MATH_PI_OVER_2 + -- ARCCOS(-1.0) = MATH_PI + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- 0.0 <= ARCCOS(X) <= MATH_PI + -- Notes: + -- None + + function ARCTAN (Y : in REAL) return REAL; + -- Purpose: + -- Returns the value of the angle in radians of the point + -- (1.0, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0) = 0.0 + -- Domain: + -- Y in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCTAN (Y : in REAL; X : in REAL) return REAL; + -- Purpose: + -- Returns the principal value of the angle in radians of + -- the point (X, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0, X) = 0.0 if X > 0.0 + -- ARCTAN(0.0, X) = MATH_PI if X < 0.0 + -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0 + -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0 + -- Domain: + -- Y in REAL + -- X in REAL, X /= 0.0 when Y = 0.0 + -- Error conditions: + -- Error if X = 0.0 and Y = 0.0 + -- Range: + -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI + -- Notes: + -- None + + function SINH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic sine of X + -- Special values: + -- SINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- SINH(X) is mathematically unbounded + -- Notes: + -- a) The usable domain of SINH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + + function COSH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic cosine of X + -- Special values: + -- COSH(0.0) = 1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- COSH(X) >= 1.0 + -- Notes: + -- a) The usable domain of COSH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + function TANH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic tangent of X + -- Special values: + -- TANH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(TANH(X)) <= 1.0 + -- Notes: + -- None + + function ARCSINH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic sine of X + -- Special values: + -- ARCSINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ARCSINH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCSINH is approximately given by: + -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH) + + function ARCCOSH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic cosine of X + -- Special values: + -- ARCCOSH(1.0) = 0.0 + -- Domain: + -- X >= 1.0 + -- Error conditions: + -- Error if X < 1.0 + -- Range: + -- ARCCOSH(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of ARCCOSH is + -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH) + + function ARCTANH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic tangent of X + -- Special values: + -- ARCTANH(0.0) = 0.0 + -- Domain: + -- ABS(X) < 1.0 + -- Error conditions: + -- Error if ABS(X) >= 1.0 + -- Range: + -- ARCTANH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCTANH is approximately given by: + -- ABS(ARCTANH(X)) < LOG(REAL'HIGH) + +end MATH_REAL; + + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. + +-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. + +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package body is a nonnormative implementation of the +-- functionality defined in the MATH_REAL package declaration. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076 +-- -1993. +-- +-- Notes: +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to clarify such semantics and provide a +-- guideline for implementations to verify their implementation +-- of MATH_REAL. Tool developers may choose to implement +-- the package body in the most efficient manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package body MATH_REAL is + + -- + -- Local Constants for Use in the Package Body Only + -- + constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2 + constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10 + constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi + constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic + constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries + constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria + constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic + + -- + -- Local Type Declarations for Cordic Operations + -- + type REAL_VECTOR is array (NATURAL range <>) of REAL; + type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; + subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER); + subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); + subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); + subtype QUADRANT is INTEGER range 0 to 3; + type CORDIC_MODE_TYPE is (ROTATION, VECTORING); + + -- + -- Auxiliary Functions for Cordic Algorithms + -- + function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL; + NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is + -- Description: + -- Returns power of two for a vector of values + -- Notes: + -- None + -- + variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES); + variable TEMP : REAL := INITIAL_VALUE; + variable FLAG : BOOLEAN := TRUE; + begin + for I in 0 to NUMBER_OF_VALUES loop + V(I) := TEMP; + for P in D'RANGE loop + if I = D(P) then + FLAG := FALSE; + exit; + end if; + end loop; + if FLAG then + TEMP := TEMP/2.0; + end if; + FLAG := TRUE; + end loop; + return V; + end POWER_OF_2_SERIES; + + + constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES( + NATURAL_VECTOR'(100, 90),1.0, + MAX_ITER); + + constant EPSILON : REAL_VECTOR_N := ( + 7.8539816339744827e-01, + 4.6364760900080606e-01, + 2.4497866312686413e-01, + 1.2435499454676144e-01, + 6.2418809995957351e-02, + 3.1239833430268277e-02, + 1.5623728620476830e-02, + 7.8123410601011116e-03, + 3.9062301319669717e-03, + 1.9531225164788189e-03, + 9.7656218955931937e-04, + 4.8828121119489829e-04, + 2.4414062014936175e-04, + 1.2207031189367021e-04, + 6.1035156174208768e-05, + 3.0517578115526093e-05, + 1.5258789061315760e-05, + 7.6293945311019699e-06, + 3.8146972656064960e-06, + 1.9073486328101870e-06, + 9.5367431640596080e-07, + 4.7683715820308876e-07, + 2.3841857910155801e-07, + 1.1920928955078067e-07, + 5.9604644775390553e-08, + 2.9802322387695303e-08, + 1.4901161193847654e-08, + 7.4505805969238281e-09 + ); + + function CORDIC ( X0 : in REAL; + Y0 : in REAL; + Z0 : in REAL; + N : in NATURAL; -- Precision factor + CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0) + -- or vectoring (Y -> 0) + ) return REAL_ARR_3 is + -- Description: + -- Compute cordic values + -- Notes: + -- None + variable X : REAL := X0; + variable Y : REAL := Y0; + variable Z : REAL := Z0; + variable X_TEMP : REAL; + begin + if CORDIC_MODE = ROTATION then + for K in 0 to N loop + X_TEMP := X; + if ( Z >= 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + else + for K in 0 to N loop + X_TEMP := X; + if ( Y < 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + end if; + return REAL_ARR_3'(X, Y, Z); + end CORDIC; + + -- + -- Bodies for Global Mathematical Functions Start Here + -- + function SIGN (X: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + if ( X > 0.0 ) then + return 1.0; + elsif ( X < 0.0 ) then + return -1.0; + else + return 0.0; + end if; + end SIGN; + + function CEIL (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is X <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS(X) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD >= X then + return RD; + else + return RD + 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD <= X then + return RD + 1.0; + else + return RD; + end if; + end if; + end CEIL; + + function FLOOR (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is ABS(X) <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS( X ) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD <= X then + return RD; + else + return RD - 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD >= X then + return RD - 1.0; + else + return RD; + end if; + end if; + end FLOOR; + + function ROUND (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X + 0.5) if X > 0 + -- c) Returns CEIL(X - 0.5) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X + 0.5); + elsif X < 0.0 then + return CEIL( X - 0.5); + else + return 0.0; + end if; + end ROUND; + + function TRUNC (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X) if X > 0 + -- c) Returns CEIL(X) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X); + elsif X < 0.0 then + return CEIL( X); + else + return 0.0; + end if; + end TRUNC; + + + + + function "MOD" (X, Y: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable XNEGATIVE : BOOLEAN := X < 0.0; + variable YNEGATIVE : BOOLEAN := Y < 0.0; + variable VALUE : REAL; + begin + -- Check validity of input arguments + if (Y = 0.0) then + assert FALSE + report "MOD(X, 0.0) is undefined" + severity ERROR; + return 0.0; + end if; + + -- Compute value + if ( XNEGATIVE ) then + if ( YNEGATIVE ) then + VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + end if; + else + if ( YNEGATIVE ) then + VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + end if; + end if; + + return VALUE; + end "MOD"; + + + function REALMAX (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMAX(X,Y) = X when X = Y + -- + begin + if X >= Y then + return X; + else + return Y; + end if; + end REALMAX; + + function REALMIN (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMIN(X,Y) = X when X = Y + -- + begin + if X <= Y then + return X; + else + return Y; + end if; + end REALMIN; + + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL) + is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + -- + variable Z, K: INTEGER; + variable TSEED1 : INTEGER := INTEGER'(SEED1); + variable TSEED2 : INTEGER := INTEGER'(SEED2); + begin + -- Check validity of arguments + if SEED1 > 2147483562 then + assert FALSE + report "SEED1 > 2147483562 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + if SEED2 > 2147483398 then + assert FALSE + report "SEED2 > 2147483398 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + -- Compute new seed values and pseudo-random number + K := TSEED1/53668; + TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211; + + if TSEED1 < 0 then + TSEED1 := TSEED1 + 2147483563; + end if; + + K := TSEED2/52774; + TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791; + + if TSEED2 < 0 then + TSEED2 := TSEED2 + 2147483399; + end if; + + Z := TSEED1 - TSEED2; + if Z < 1 then + Z := Z + 2147483562; + end if; + + -- Get output values + SEED1 := POSITIVE'(TSEED1); + SEED2 := POSITIVE'(TSEED2); + X := REAL(Z)*4.656613e-10; + end UNIFORM; + + + + function SQRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = 0.5*[F(n) + x/F(n)] + -- b) Returns 0.0 on error + -- + + constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor + + variable INIVAL: REAL; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + -- Check validity of argument + if ( X < 0.0 ) then + assert FALSE + report "X < 0.0 in SQRT(X)" + severity ERROR; + return 0.0; + end if; + + -- Get the square root for special cases + if X = 0.0 then + return 0.0; + else + if ( X = 1.0 ) then + return 1.0; + end if; + end if; + + -- Get the square root for general cases + INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise + OLDVAL := INIVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + + -- Check for relative and absolute error and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT) ) loop + OLDVAL := NEWVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + COUNT := COUNT + 1; + end loop; + return NEWVAL; + end SQRT; + + function CBRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; + -- + constant EPS : REAL := BASE_EPS*BASE_EPS; + + variable INIVAL: REAL; + variable XLOCAL : REAL := X; + variable NEGATIVE : BOOLEAN := X < 0.0; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + + -- Compute root for special cases + if X = 0.0 then + return 0.0; + elsif ( X = 1.0 ) then + return 1.0; + else + if X = -1.0 then + return -1.0; + end if; + end if; + + -- Compute root for general cases + if NEGATIVE then + XLOCAL := -X; + end if; + + INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but + -- imprecise + OLDVAL := INIVAL; + NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR + (ABS(NEWVAL - OLDVAL) > EPS ) ) AND + ( COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + COUNT := COUNT + 1; + end loop; + + if NEGATIVE then + NEWVAL := -NEWVAL; + end if; + + return NEWVAL; + end CBRT; + + function "**" (X : in INTEGER; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (REAL(X)); + end if; + + -- Get value for general case + return EXP (Y * LOG (REAL(X))); + end "**"; + + function "**" (X : in REAL; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0.0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0.0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0.0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1.0 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0.0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (X); + end if; + + -- Get value for general case + return EXP (Y * LOG (X)); + end "**"; + + function EXP (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) This function computes the exponential using the following + -- series: + -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0 + -- and reduces argument X to take advantage of exp(x+y) = + -- exp(x)*exp(y) + -- + -- b) This implementation limits X to be less than LOG(REAL'HIGH) + -- to avoid overflow. Returns REAL'HIGH when X reaches that + -- limit + -- + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria + + variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument + variable XLOCAL : REAL := ABS(X); -- Use positive value + variable OLDVAL: REAL ; + variable COUNT: INTEGER ; + variable NEWVAL: REAL ; + variable LAST_TERM: REAL ; + variable FACTOR : REAL := 1.0; + + begin + -- Compute value for special cases + if X = 0.0 then + return 1.0; + end if; + + if XLOCAL = 1.0 then + if RECIPROCAL then + return MATH_1_OVER_E; + else + return MATH_E; + end if; + end if; + + if XLOCAL = 2.0 then + if RECIPROCAL then + return 1.0/MATH_E_P2; + else + return MATH_E_P2; + end if; + end if; + + if XLOCAL = 10.0 then + if RECIPROCAL then + return 1.0/MATH_E_P10; + else + return MATH_E_P10; + end if; + end if; + + if XLOCAL > LOG(REAL'HIGH) then + if RECIPROCAL then + return 0.0; + else + assert FALSE + report "X > LOG(REAL'HIGH) in EXP(X)" + severity NOTE; + return REAL'HIGH; + end if; + end if; + + -- Reduce argument to ABS(X) < 1.0 + while XLOCAL > 10.0 loop + XLOCAL := XLOCAL - 10.0; + FACTOR := FACTOR*MATH_E_P10; + end loop; + + while XLOCAL > 1.0 loop + XLOCAL := XLOCAL - 1.0; + FACTOR := FACTOR*MATH_E; + end loop; + + -- Compute value for case 0 < XLOCAL < 1 + OLDVAL := 1.0; + LAST_TERM := XLOCAL; + NEWVAL:= OLDVAL + LAST_TERM; + COUNT := 2; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT))); + NEWVAL := OLDVAL + LAST_TERM; + COUNT := COUNT + 1; + end loop; + + -- Compute final value using exp(x+y) = exp(x)*exp(y) + NEWVAL := NEWVAL*FACTOR; + + if RECIPROCAL then + NEWVAL := 1.0/NEWVAL; + end if; + + return NEWVAL; + end EXP; + + + -- + -- Auxiliary Functions to Compute LOG + -- + function ILOGB(X: in REAL) return INTEGER IS + -- Description: + -- Returns n such that -1 <= ABS(X)/2^n < 2 + -- Notes: + -- None + + variable N: INTEGER := 0; + variable Y: REAL := ABS(X); + + begin + if(Y = 1.0 or Y = 0.0) then + return 0; + end if; + + if( Y > 1.0) then + while Y >= 2.0 loop + Y := Y/2.0; + N := N+1; + end loop; + return N; + end if; + + -- O < Y < 1 + while Y < 1.0 loop + Y := Y*2.0; + N := N -1; + end loop; + return N; + end ILOGB; + + function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS + -- Description: + -- Returns X*2^n + -- Notes: + -- None + begin + return X*(2.0 ** N); + end LDEXP; + + function LOG (X : in REAL ) return REAL IS + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- + -- Notes: + -- a) Returns REAL'LOW on error + -- + -- Copyright (c) 1992 Regents of the University of California. + -- All rights reserved. + -- + -- Redistribution and use in source and binary forms, with or without + -- modification, are permitted provided that the following conditions + -- are met: + -- 1. Redistributions of source code must retain the above copyright + -- notice, this list of conditions and the following disclaimer. + -- 2. Redistributions in binary form must reproduce the above copyright + -- notice, this list of conditions and the following disclaimer in the + -- documentation and/or other materials provided with the distribution. + -- 3. All advertising materials mentioning features or use of this + -- software must display the following acknowledgement: + -- This product includes software developed by the University of + -- California, Berkeley and its contributors. + -- 4. Neither the name of the University nor the names of its + -- contributors may be used to endorse or promote products derived + -- from this software without specific prior written permission. + -- + -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' + -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR + -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + -- DAMAGE. + -- + -- NOTE: This VHDL version was generated using the C version of the + -- original function by the IEEE VHDL Mathematical Package + -- Working Group (CS/JT) + + constant N: INTEGER := 128; + + -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. + -- Used for generation of extend precision logarithms. + -- The constant 35184372088832 is 2^45, so the divide is exact. + -- It ensures correct reading of logF_head, even for inaccurate + -- decimal-to-binary conversion routines. (Everybody gets the + -- right answer for INTEGERs less than 2^53.) + -- Values for LOG(F) were generated using error < 10^-57 absolute + -- with the bc -l package. + + type REAL_VECTOR is array (NATURAL range <>) of REAL; + + constant A1:REAL := 0.08333333333333178827; + constant A2:REAL := 0.01250000000377174923; + constant A3:REAL := 0.002232139987919447809; + constant A4:REAL := 0.0004348877777076145742; + + constant LOGF_HEAD: REAL_VECTOR(0 TO N) := ( + 0.0, + 0.007782140442060381246, + 0.015504186535963526694, + 0.023167059281547608406, + 0.030771658666765233647, + 0.038318864302141264488, + 0.045809536031242714670, + 0.053244514518837604555, + 0.060624621816486978786, + 0.067950661908525944454, + 0.075223421237524235039, + 0.082443669210988446138, + 0.089612158689760690322, + 0.096729626458454731618, + 0.103796793681567578460, + 0.110814366340264314203, + 0.117783035656430001836, + 0.124703478501032805070, + 0.131576357788617315236, + 0.138402322859292326029, + 0.145182009844575077295, + 0.151916042025732167530, + 0.158605030176659056451, + 0.165249572895390883786, + 0.171850256926518341060, + 0.178407657472689606947, + 0.184922338493834104156, + 0.191394852999565046047, + 0.197825743329758552135, + 0.204215541428766300668, + 0.210564769107350002741, + 0.216873938300523150246, + 0.223143551314024080056, + 0.229374101064877322642, + 0.235566071312860003672, + 0.241719936886966024758, + 0.247836163904594286577, + 0.253915209980732470285, + 0.259957524436686071567, + 0.265963548496984003577, + 0.271933715484010463114, + 0.277868451003087102435, + 0.283768173130738432519, + 0.289633292582948342896, + 0.295464212893421063199, + 0.301261330578199704177, + 0.307025035294827830512, + 0.312755710004239517729, + 0.318453731118097493890, + 0.324119468654316733591, + 0.329753286372579168528, + 0.335355541920762334484, + 0.340926586970454081892, + 0.346466767346100823488, + 0.351976423156884266063, + 0.357455888922231679316, + 0.362905493689140712376, + 0.368325561158599157352, + 0.373716409793814818840, + 0.379078352934811846353, + 0.384411698910298582632, + 0.389716751140440464951, + 0.394993808240542421117, + 0.400243164127459749579, + 0.405465108107819105498, + 0.410659924985338875558, + 0.415827895143593195825, + 0.420969294644237379543, + 0.426084395310681429691, + 0.431173464818130014464, + 0.436236766774527495726, + 0.441274560805140936281, + 0.446287102628048160113, + 0.451274644139630254358, + 0.456237433481874177232, + 0.461175715122408291790, + 0.466089729924533457960, + 0.470979715219073113985, + 0.475845904869856894947, + 0.480688529345570714212, + 0.485507815781602403149, + 0.490303988045525329653, + 0.495077266798034543171, + 0.499827869556611403822, + 0.504556010751912253908, + 0.509261901790523552335, + 0.513945751101346104405, + 0.518607764208354637958, + 0.523248143765158602036, + 0.527867089620485785417, + 0.532464798869114019908, + 0.537041465897345915436, + 0.541597282432121573947, + 0.546132437597407260909, + 0.550647117952394182793, + 0.555141507540611200965, + 0.559615787935399566777, + 0.564070138285387656651, + 0.568504735352689749561, + 0.572919753562018740922, + 0.577315365035246941260, + 0.581691739635061821900, + 0.586049045003164792433, + 0.590387446602107957005, + 0.594707107746216934174, + 0.599008189645246602594, + 0.603290851438941899687, + 0.607555250224322662688, + 0.611801541106615331955, + 0.616029877215623855590, + 0.620240409751204424537, + 0.624433288012369303032, + 0.628608659422752680256, + 0.632766669570628437213, + 0.636907462236194987781, + 0.641031179420679109171, + 0.645137961373620782978, + 0.649227946625615004450, + 0.653301272011958644725, + 0.657358072709030238911, + 0.661398482245203922502, + 0.665422632544505177065, + 0.669430653942981734871, + 0.673422675212350441142, + 0.677398823590920073911, + 0.681359224807238206267, + 0.685304003098281100392, + 0.689233281238557538017, + 0.693147180560117703862); + + constant LOGF_TAIL: REAL_VECTOR(0 TO N) := ( + 0.0, + -0.00000000000000543229938420049, + 0.00000000000000172745674997061, + -0.00000000000001323017818229233, + -0.00000000000001154527628289872, + -0.00000000000000466529469958300, + 0.00000000000005148849572685810, + -0.00000000000002532168943117445, + -0.00000000000005213620639136504, + -0.00000000000001819506003016881, + 0.00000000000006329065958724544, + 0.00000000000008614512936087814, + -0.00000000000007355770219435028, + 0.00000000000009638067658552277, + 0.00000000000007598636597194141, + 0.00000000000002579999128306990, + -0.00000000000004654729747598444, + -0.00000000000007556920687451336, + 0.00000000000010195735223708472, + -0.00000000000017319034406422306, + -0.00000000000007718001336828098, + 0.00000000000010980754099855238, + -0.00000000000002047235780046195, + -0.00000000000008372091099235912, + 0.00000000000014088127937111135, + 0.00000000000012869017157588257, + 0.00000000000017788850778198106, + 0.00000000000006440856150696891, + 0.00000000000016132822667240822, + -0.00000000000007540916511956188, + -0.00000000000000036507188831790, + 0.00000000000009120937249914984, + 0.00000000000018567570959796010, + -0.00000000000003149265065191483, + -0.00000000000009309459495196889, + 0.00000000000017914338601329117, + -0.00000000000001302979717330866, + 0.00000000000023097385217586939, + 0.00000000000023999540484211737, + 0.00000000000015393776174455408, + -0.00000000000036870428315837678, + 0.00000000000036920375082080089, + -0.00000000000009383417223663699, + 0.00000000000009433398189512690, + 0.00000000000041481318704258568, + -0.00000000000003792316480209314, + 0.00000000000008403156304792424, + -0.00000000000034262934348285429, + 0.00000000000043712191957429145, + -0.00000000000010475750058776541, + -0.00000000000011118671389559323, + 0.00000000000037549577257259853, + 0.00000000000013912841212197565, + 0.00000000000010775743037572640, + 0.00000000000029391859187648000, + -0.00000000000042790509060060774, + 0.00000000000022774076114039555, + 0.00000000000010849569622967912, + -0.00000000000023073801945705758, + 0.00000000000015761203773969435, + 0.00000000000003345710269544082, + -0.00000000000041525158063436123, + 0.00000000000032655698896907146, + -0.00000000000044704265010452446, + 0.00000000000034527647952039772, + -0.00000000000007048962392109746, + 0.00000000000011776978751369214, + -0.00000000000010774341461609578, + 0.00000000000021863343293215910, + 0.00000000000024132639491333131, + 0.00000000000039057462209830700, + -0.00000000000026570679203560751, + 0.00000000000037135141919592021, + -0.00000000000017166921336082431, + -0.00000000000028658285157914353, + -0.00000000000023812542263446809, + 0.00000000000006576659768580062, + -0.00000000000028210143846181267, + 0.00000000000010701931762114254, + 0.00000000000018119346366441110, + 0.00000000000009840465278232627, + -0.00000000000033149150282752542, + -0.00000000000018302857356041668, + -0.00000000000016207400156744949, + 0.00000000000048303314949553201, + -0.00000000000071560553172382115, + 0.00000000000088821239518571855, + -0.00000000000030900580513238244, + -0.00000000000061076551972851496, + 0.00000000000035659969663347830, + 0.00000000000035782396591276383, + -0.00000000000046226087001544578, + 0.00000000000062279762917225156, + 0.00000000000072838947272065741, + 0.00000000000026809646615211673, + -0.00000000000010960825046059278, + 0.00000000000002311949383800537, + -0.00000000000058469058005299247, + -0.00000000000002103748251144494, + -0.00000000000023323182945587408, + -0.00000000000042333694288141916, + -0.00000000000043933937969737844, + 0.00000000000041341647073835565, + 0.00000000000006841763641591466, + 0.00000000000047585534004430641, + 0.00000000000083679678674757695, + -0.00000000000085763734646658640, + 0.00000000000021913281229340092, + -0.00000000000062242842536431148, + -0.00000000000010983594325438430, + 0.00000000000065310431377633651, + -0.00000000000047580199021710769, + -0.00000000000037854251265457040, + 0.00000000000040939233218678664, + 0.00000000000087424383914858291, + 0.00000000000025218188456842882, + -0.00000000000003608131360422557, + -0.00000000000050518555924280902, + 0.00000000000078699403323355317, + -0.00000000000067020876961949060, + 0.00000000000016108575753932458, + 0.00000000000058527188436251509, + -0.00000000000035246757297904791, + -0.00000000000018372084495629058, + 0.00000000000088606689813494916, + 0.00000000000066486268071468700, + 0.00000000000063831615170646519, + 0.00000000000025144230728376072, + -0.00000000000017239444525614834); + + variable M, J:INTEGER; + variable F1, F2, G, Q, U, U2, V: REAL; + variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs + variable ONE: REAL := 1.0; --Made variable so no constant folding occurs + + -- double logb(), ldexp(); + + variable U1:REAL; + + begin + + -- Check validity of argument + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = MATH_E ) then + return 1.0; + end if; + + -- Argument reduction: 1 <= g < 2; x/2^m = g; + -- y = F*(1 + f/F) for |f| <= 2^-8 + + M := ILOGB(X); + G := LDEXP(X, -M); + J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding + F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512] + F2 := G - F1; + + -- Approximate expansion for log(1+f2/F1) ~= u + q + G := 1.0/(2.0*F1+F2); + U := 2.0*F2*G; + V := U*U; + Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4))); + + -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, + -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. + -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750. + -- + if ( J /= 0 or M /= 0) then + U1 := U + 513.0; + U1 := U1 - 513.0; + + -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero + -- u1 = u to 24 bits. + -- + else + U1 := U; + --TRUNC(U1); --In c this is u1 = (double) (float) (u1) + end if; + + U2 := (2.0*(F2 - F1*U1) - U1*F2) * G; + -- u1 + u2 = 2f/(2F+f) to extra precision. + + -- log(x) = log(2^m*F1*(1+f2/F1)) = + -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q); + -- (exact) + (tiny) + + U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact + U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny + U2 := U2 + LOGF_TAIL(N)*REAL(M); + return (U1 + U2); + end LOG; + + + function LOG2 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG2(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 2.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG2_OF_E*LOG(X) ); + end LOG2; + + + function LOG10 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG10(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 10.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG10_OF_E*LOG(X) ); + end LOG10; + + + function LOG (X: in REAL; BASE: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + if ( BASE <= 0.0 or BASE = 1.0 ) then + assert FALSE + report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = BASE ) then + return 1.0; + end if; + + -- Compute value for general case + return ( LOG(X)/LOG(BASE)); + end LOG; + + + function SIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) SIN(-X) = -SIN(X) + -- b) SIN(X) = X if ABS(X) < EPS + -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS + -- d) SIN(MATH_PI_OVER_2 - X) = COS(X) + -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS + -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in SIN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then + return 0.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 then + if NEGATIVE then + return -1.0; + else + return 1.0; + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + if NEGATIVE then + return 1.0; + else + return -1.0; + end if; + end if; + + if XLOCAL < EPS then + if NEGATIVE then + return -XLOCAL; + else + return XLOCAL; + end if; + else + if XLOCAL < BASE_EPS then + TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_2_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + -- Compute value for general cases + if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then + VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1); + end if; + + N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2)); + case QUADRANT( N mod 4) is + when 0 => + VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1); + when 1 => + VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27, + ROTATION)(0); + when 2 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1); + when 3 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27, + ROTATION)(0); + end case; + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end SIN; + + + function COS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) COS(-X) = COS(X) + -- b) COS(X) = SIN(MATH_PI_OVER_2 - X) + -- c) COS(MATH_PI + X) = -COS(X) + -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS + -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in COS(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then + return 1.0; + end if; + + if XLOCAL = MATH_PI then + return -1.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then + return 0.0; + end if; + + TEMP := ABS(XLOCAL); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS(XLOCAL -MATH_2_PI); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS (XLOCAL - MATH_PI); + if TEMP < EPS then + return (-1.0 + 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + -- Compute value for general cases + return SIN(MATH_PI_OVER_2 - XLOCAL); + end COS; + + function TAN (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) TAN(0.0) = 0.0 + -- b) TAN(-X) = -TAN(X) + -- c) Returns REAL'LOW on error if X < 0.0 + -- d) Returns REAL'HIGH on error if X > 0.0 + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X) ; + variable VALUE: REAL; + variable TEMP : REAL; + + begin + -- Make 0.0 <= XLOCAL <= MATH_2_PI + if XLOCAL > MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in TAN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Check validity of argument + if XLOCAL = MATH_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'LOW); + else + return(REAL'HIGH); + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'HIGH); + else + return(REAL'LOW); + end if; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_PI then + return 0.0; + end if; + + -- Compute value for general cases + VALUE := SIN(XLOCAL)/COS(XLOCAL); + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TAN; + + function ARCSIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCSIN(-X) = -ARCSIN(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of arguments + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCSIN(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + elsif XLOCAL = 1.0 then + if NEGATIVE then + return -MATH_PI_OVER_2; + else + return MATH_PI_OVER_2; + end if; + end if; + + -- Compute value for general cases + if XLOCAL < 0.9 then + VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL))); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCSIN; + + function ARCCOS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of argument + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCCOS(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + elsif X = 0.0 then + return MATH_PI_OVER_2; + elsif X = -1.0 then + return MATH_PI; + end if; + + -- Compute value for general cases + if XLOCAL > 0.9 then + VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL)); + end if; + + + if NEGATIVE then + VALUE := MATH_PI - VALUE; + end if; + + return VALUE; + end ARCCOS; + + + function ARCTAN (Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCTAN(-Y) = -ARCTAN(Y) + -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0 + -- c) ARCTAN(Y) = Y for |Y| < EPS + + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS; + + variable NEGATIVE : BOOLEAN := Y < 0.0; + variable RECIPROCAL : BOOLEAN; + variable YLOCAL : REAL := ABS(Y); + variable VALUE : REAL; + + begin + -- Make argument |Y| <=1.0 + if YLOCAL > 1.0 then + YLOCAL := 1.0/YLOCAL; + RECIPROCAL := TRUE; + else + RECIPROCAL := FALSE; + end if; + + -- Compute value for special cases + if YLOCAL = 0.0 then + if RECIPROCAL then + if NEGATIVE then + return (-MATH_PI_OVER_2); + else + return (MATH_PI_OVER_2); + end if; + else + return 0.0; + end if; + end if; + + if YLOCAL < EPS then + if NEGATIVE then + if RECIPROCAL then + return (-MATH_PI_OVER_2 + YLOCAL); + else + return -YLOCAL; + end if; + else + if RECIPROCAL then + return (MATH_PI_OVER_2 - YLOCAL); + else + return YLOCAL; + end if; + end if; + end if; + + -- Compute value for general cases + VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2); + + if RECIPROCAL then + VALUE := MATH_PI_OVER_2 - VALUE; + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function ARCTAN (Y : in REAL; X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable YLOCAL : REAL; + variable VALUE : REAL; + begin + + -- Check validity of arguments + if (Y = 0.0 and X = 0.0 ) then + assert FALSE report + "ARCTAN(0.0, 0.0) is undetermined" + severity ERROR; + return 0.0; + end if; + + -- Compute value for special cases + if Y = 0.0 then + if X > 0.0 then + return 0.0; + else + return MATH_PI; + end if; + end if; + + if X = 0.0 then + if Y > 0.0 then + return MATH_PI_OVER_2; + else + return -MATH_PI_OVER_2; + end if; + end if; + + + -- Compute value for general cases + YLOCAL := ABS(Y/X); + + VALUE := ARCTAN(YLOCAL); + + if X < 0.0 then + VALUE := MATH_PI - VALUE; + end if; + + if Y < 0.0 then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function SINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/2.0 + -- b) SINH(-X) = SINH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)*0.5; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end SINH; + + function COSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) + EXP(-X))/2.0 + -- b) COSH(-X) = COSH(X) + + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 1.0; + end if; + + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP + 1.0/TEMP)*0.5; + + return VALUE; + end COSH; + + function TANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) + -- b) TANH(-X) = -TANH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP); + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TANH; + + function ARCSINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X + 1.0)) + + begin + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X + 1.0)) ); + end ARCSINH; + + + + function ARCCOSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0 + -- b) Returns X on error + + begin + -- Check validity of arguments + if X < 1.0 then + assert FALSE + report "X < 1.0 in ARCCOSH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X - 1.0))); + end ARCCOSH; + + function ARCTANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0 + -- b) Returns X on error + begin + -- Check validity of arguments + if ABS(X) >= 1.0 then + assert FALSE + report "ABS(X) >= 1.0 in ARCTANH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return( 0.5*LOG( (1.0+X)/(1.0-X) ) ); + end ARCTANH; + +end MATH_REAL; diff --git a/gbe_trb/ipcores/ecp5/fifo_2048x8x16.lpc b/gbe_trb/ipcores/ecp5/fifo_2048x8x16.lpc new file mode 100644 index 0000000..85b1d34 --- /dev/null +++ b/gbe_trb/ipcores/ecp5/fifo_2048x8x16.lpc @@ -0,0 +1,53 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.8 +ModuleName=fifo_2048x8x16 +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=04/24/2019 +Time=10:55:11 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=2048 +Width=9 +RDepth=1024 +RWidth=18 +regout=0 +ClockEn=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_2048x8x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 2048 -width 9 -rwidth 18 -reset_rel SYNC -pe -1 -pf -1 diff --git a/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd b/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd new file mode 100644 index 0000000..2d2455f --- /dev/null +++ b/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd @@ -0,0 +1,1330 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144 +-- Module Version: 5.8 +--/home/soft/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n fifo_2048x8x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 2048 -width 9 -rwidth 18 -reset_rel SYNC -pe -1 -pf -1 -fdc /home/adrian/git/trb5sc/template/project/mediFifo/fifo_2048x8x16/fifo_2048x8x16.fdc + +-- Wed Apr 24 10:55:14 2019 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity fifo_2048x8x16 is + port ( + Data: in std_logic_vector(8 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_2048x8x16; + +architecture Structure of fifo_2048x8x16 is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal wcount_r0: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co5: std_logic; + signal co4: std_logic; + signal wcount_11: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal co5_1: std_logic; + signal co4_1: std_logic; + signal rcount_10: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal wcount_r7: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_2: std_logic; + signal wcount_r9: std_logic; + signal wcount_r10: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_3: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w8: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_3: std_logic; + signal rcount_w9: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_10: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal full_d_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2048x8x16.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t23: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t22: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t21: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t20: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t19: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t18: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t17: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t16: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t15: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t14: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t13: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t12: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t11: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t10: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t9: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t8: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t7: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t6: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t5: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t4: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t3: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t2: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t1: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t0: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_0); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_1); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_2); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r10); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>r_gcount_w210, + DO0=>r_g2b_xor_cluster_0); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_gcount_w26, + DO0=>r_g2b_xor_cluster_1); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w4); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w21, AD0=>r_gcount_w22, DO0=>rcount_w1); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r211, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w210, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 9) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>scuba_vlo, DIA12=>scuba_vlo, + DIA11=>scuba_vlo, DIA10=>scuba_vlo, DIA9=>scuba_vlo, + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_10, ADA12=>wptr_9, ADA11=>wptr_8, + ADA10=>wptr_7, ADA9=>wptr_6, ADA8=>wptr_5, ADA7=>wptr_4, + ADA6=>wptr_3, ADA5=>wptr_2, ADA4=>wptr_1, ADA3=>wptr_0, + ADA2=>scuba_vlo, ADA1=>scuba_vlo, ADA0=>scuba_vlo, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_9, ADB12=>rptr_8, ADB11=>rptr_7, + ADB10=>rptr_6, ADB9=>rptr_5, ADB8=>rptr_4, ADB7=>rptr_3, + ADB6=>rptr_2, ADB5=>rptr_1, ADB4=>rptr_0, ADB3=>scuba_vlo, + ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vlo, + CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, + RSTB=>Reset, DOA17=>open, DOA16=>open, DOA15=>open, + DOA14=>open, DOA13=>open, DOA12=>open, DOA11=>open, + DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, DOA6=>open, + DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, DOA1=>open, + DOA0=>open, DOB17=>Q(17), DOB16=>Q(16), DOB15=>Q(15), + DOB14=>Q(14), DOB13=>Q(13), DOB12=>Q(12), DOB11=>Q(11), + DOB10=>Q(10), DOB9=>Q(9), DOB8=>Q(8), DOB7=>Q(7), DOB6=>Q(6), + DOB5=>Q(5), DOB4=>Q(4), DOB3=>Q(3), DOB2=>Q(2), DOB1=>Q(1), + DOB0=>Q(0)); + + FF_116: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_115: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_114: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_113: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_112: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_111: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_110: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_109: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_108: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_107: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_106: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_105: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_104: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_103: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_102: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_101: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_100: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_99: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_98: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_97: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_96: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_95: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_94: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_93: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_92: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_91: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_90: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_89: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_88: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_87: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_86: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_85: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_84: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_83: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_82: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_81: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_80: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_79: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_78: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_77: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_76: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_75: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_74: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_73: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_72: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_71: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_70: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_69: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_68: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_67: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_66: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_65: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_64: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_63: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_62: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_61: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_60: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_59: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_58: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_57: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_56: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_55: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_54: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_53: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_52: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_51: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_50: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_49: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_48: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_47: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_46: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_45: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_44: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_43: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_42: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_41: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_40: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_39: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_38: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_37: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_36: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_35: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_34: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_33: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_32: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_31: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_30: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_29: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_28: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_27: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_26: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_25: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_24: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_23: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_22: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_21: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_20: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_19: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_18: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_17: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_16: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_15: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_14: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_13: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_12: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_11: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_10: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_9: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_8: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_7: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_6: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_5: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_4: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_3: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_2: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_gctr_ci); + + w_gctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_gctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0); + + w_gctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1); + + w_gctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2); + + w_gctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3); + + w_gctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4); + + w_gctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4, S0=>iwcount_10, S1=>iwcount_11, + COUT=>co5); + + r_gctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_gctr_ci); + + r_gctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_gctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_1); + + r_gctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_1); + + r_gctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_1); + + r_gctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_1); + + r_gctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_1); + + r_gctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_10, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_1, S0=>ircount_10, S1=>open, + COUT=>co5_1); + + empty_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + empty_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r1, + B1=>wcount_r2, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_2); + + empty_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r3, + B1=>wcount_r4, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_2, S0=>open, S1=>open, COUT=>co1_2); + + empty_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r5, + B1=>wcount_r6, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_2, S0=>open, S1=>open, COUT=>co2_2); + + empty_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r7, + B1=>w_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_2, S0=>open, S1=>open, + COUT=>co3_2); + + empty_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r9, + B1=>wcount_r10, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_2, S0=>open, S1=>open, COUT=>co4_2); + + empty_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_2, S0=>open, S1=>open, + COUT=>empty_d_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>empty_d_c, S0=>empty_d, S1=>open, + COUT=>open); + + full_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + full_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>rcount_w0, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_1, S0=>open, S1=>open, + COUT=>co0_3); + + full_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w1, + B1=>rcount_w2, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>open, S1=>open, COUT=>co1_3); + + full_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w3, + B1=>rcount_w4, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>open, S1=>open, COUT=>co2_3); + + full_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w5, + B1=>rcount_w6, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>open, S1=>open, COUT=>co3_3); + + full_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w8, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>open, S1=>open, COUT=>co4_3); + + full_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w9, + B1=>full_cmp_clr, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_3, S0=>open, S1=>open, + COUT=>full_d_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>full_d_c, S0=>full_d, S1=>open, + COUT=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.ipx b/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.ipx new file mode 100644 index 0000000..2651bf5 --- /dev/null +++ b/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.lpc b/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.lpc new file mode 100644 index 0000000..df0f1b7 --- /dev/null +++ b/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.lpc @@ -0,0 +1,53 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.8 +ModuleName=fifo_64kx18x9_wcnt +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/15/2021 +Time=10:18:42 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=32768 +Width=18 +RDepth=65536 +RWidth=9 +regout=0 +ClockEn=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=0 +WDataCount=1 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_64kx18x9_wcnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 32768 -width 18 -rwidth 9 -reset_rel SYNC -pe -1 -pf -1 -fill diff --git a/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd b/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd new file mode 100644 index 0000000..2d58bd2 --- /dev/null +++ b/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd @@ -0,0 +1,4644 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.8 +--/home/soft/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n fifo_64kx18x9_wcnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 32768 -width 18 -rwidth 9 -reset_rel SYNC -pe -1 -pf -1 -fill + +-- Mon Nov 15 10:18:42 2021 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity fifo_64kx18x9_wcnt is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(8 downto 0); + WCNT: out std_logic_vector(15 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_64kx18x9_wcnt; + +architecture Structure of fifo_64kx18x9_wcnt is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal func_and_inet: std_logic; + signal func_and_inet_1: std_logic; + signal func_and_inet_2: std_logic; + signal func_and_inet_3: std_logic; + signal func_and_inet_4: std_logic; + signal func_and_inet_5: std_logic; + signal func_and_inet_6: std_logic; + signal func_and_inet_7: std_logic; + signal func_and_inet_8: std_logic; + signal func_and_inet_9: std_logic; + signal func_and_inet_10: std_logic; + signal func_and_inet_11: std_logic; + signal func_and_inet_12: std_logic; + signal func_and_inet_13: std_logic; + signal func_and_inet_14: std_logic; + signal func_and_inet_15: std_logic; + signal func_and_inet_16: std_logic; + signal func_and_inet_17: std_logic; + signal func_and_inet_18: std_logic; + signal func_and_inet_19: std_logic; + signal func_and_inet_20: std_logic; + signal func_and_inet_21: std_logic; + signal func_and_inet_22: std_logic; + signal func_and_inet_23: std_logic; + signal func_and_inet_24: std_logic; + signal func_and_inet_25: std_logic; + signal func_and_inet_26: std_logic; + signal func_and_inet_27: std_logic; + signal func_and_inet_28: std_logic; + signal func_and_inet_29: std_logic; + signal wptr_14_inv: std_logic; + signal func_and_inet_30: std_logic; + signal rptr_15_inv: std_logic; + signal func_and_inet_31: std_logic; + signal func_and_inet_32: std_logic; + signal func_and_inet_33: std_logic; + signal func_and_inet_34: std_logic; + signal func_and_inet_35: std_logic; + signal func_and_inet_36: std_logic; + signal func_and_inet_37: std_logic; + signal func_and_inet_38: std_logic; + signal func_and_inet_39: std_logic; + signal func_and_inet_40: std_logic; + signal func_and_inet_41: std_logic; + signal func_and_inet_42: std_logic; + signal func_and_inet_43: std_logic; + signal func_and_inet_44: std_logic; + signal func_and_inet_45: std_logic; + signal wptr_13_inv: std_logic; + signal func_and_inet_46: std_logic; + signal rptr_14_inv: std_logic; + signal func_and_inet_47: std_logic; + signal func_and_inet_48: std_logic; + signal func_and_inet_49: std_logic; + signal func_and_inet_50: std_logic; + signal func_and_inet_51: std_logic; + signal func_and_inet_52: std_logic; + signal func_and_inet_53: std_logic; + signal wptr_12_inv: std_logic; + signal func_and_inet_54: std_logic; + signal rptr_13_inv: std_logic; + signal func_and_inet_55: std_logic; + signal func_and_inet_56: std_logic; + signal func_and_inet_57: std_logic; + signal wptr_11_inv: std_logic; + signal func_and_inet_58: std_logic; + signal rptr_12_inv: std_logic; + signal func_and_inet_59: std_logic; + signal wptr_10_inv: std_logic; + signal func_and_inet_60: std_logic; + signal rptr_11_inv: std_logic; + signal func_and_inet_61: std_logic; + signal func_and_inet_62: std_logic; + signal func_and_inet_63: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3_1: std_logic; + signal w_g2b_xor_cluster_3_2: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_3_2: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal func_xor_inet_3: std_logic; + signal func_xor_inet_2: std_logic; + signal func_xor_inet_1: std_logic; + signal func_xor_inet: std_logic; + signal rcount_w0: std_logic; + signal func_xor_inet_4: std_logic; + signal func_xor_inet_5: std_logic; + signal dec1_r10: std_logic; + signal dec0_p00: std_logic; + signal dec3_r11: std_logic; + signal dec2_p01: std_logic; + signal dec5_r12: std_logic; + signal dec4_p02: std_logic; + signal dec7_r13: std_logic; + signal dec6_p03: std_logic; + signal dec9_r14: std_logic; + signal dec8_p04: std_logic; + signal dec11_r15: std_logic; + signal dec10_p05: std_logic; + signal dec13_r16: std_logic; + signal dec12_p06: std_logic; + signal dec15_r17: std_logic; + signal dec14_p07: std_logic; + signal dec17_r18: std_logic; + signal dec16_p08: std_logic; + signal dec19_r19: std_logic; + signal dec18_p09: std_logic; + signal dec21_r110: std_logic; + signal dec20_p010: std_logic; + signal dec23_r111: std_logic; + signal dec22_p011: std_logic; + signal dec25_r112: std_logic; + signal dec24_p012: std_logic; + signal dec27_r113: std_logic; + signal dec26_p013: std_logic; + signal dec29_r114: std_logic; + signal dec28_p014: std_logic; + signal dec31_r115: std_logic; + signal dec30_p015: std_logic; + signal dec33_r116: std_logic; + signal dec32_p016: std_logic; + signal dec35_r117: std_logic; + signal dec34_p017: std_logic; + signal dec37_r118: std_logic; + signal dec36_p018: std_logic; + signal dec39_r119: std_logic; + signal dec38_p019: std_logic; + signal dec41_r120: std_logic; + signal dec40_p020: std_logic; + signal dec43_r121: std_logic; + signal dec42_p021: std_logic; + signal dec45_r122: std_logic; + signal dec44_p022: std_logic; + signal dec47_r123: std_logic; + signal dec46_p023: std_logic; + signal dec49_r124: std_logic; + signal dec48_p024: std_logic; + signal dec51_r125: std_logic; + signal dec50_p025: std_logic; + signal dec53_r126: std_logic; + signal dec52_p026: std_logic; + signal dec55_r127: std_logic; + signal dec54_p027: std_logic; + signal dec57_r128: std_logic; + signal dec56_p028: std_logic; + signal dec59_r129: std_logic; + signal dec58_p029: std_logic; + signal dec61_r130: std_logic; + signal dec60_p030: std_logic; + signal dec63_r131: std_logic; + signal dec62_p031: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal w_gdata_13: std_logic; + signal w_gdata_14: std_logic; + signal wptr_15: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal r_gdata_14: std_logic; + signal r_gdata_15: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_16: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rptr_13: std_logic; + signal rptr_14: std_logic; + signal rptr_15: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal w_gcount_14: std_logic; + signal w_gcount_15: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal r_gcount_15: std_logic; + signal r_gcount_16: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal w_gcount_r214: std_logic; + signal w_gcount_r14: std_logic; + signal w_gcount_r215: std_logic; + signal w_gcount_r15: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal r_gcount_w215: std_logic; + signal r_gcount_w15: std_logic; + signal r_gcount_w216: std_logic; + signal r_gcount_w16: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co5: std_logic; + signal iwcount_14: std_logic; + signal iwcount_15: std_logic; + signal co7: std_logic; + signal co6: std_logic; + signal wcount_15: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal ircount_15: std_logic; + signal co6_1: std_logic; + signal ircount_16: std_logic; + signal co8: std_logic; + signal co7_1: std_logic; + signal rcount_16: std_logic; + signal mdout1_31_0: std_logic; + signal mdout1_30_0: std_logic; + signal mdout1_29_0: std_logic; + signal mdout1_28_0: std_logic; + signal mdout1_27_0: std_logic; + signal mdout1_26_0: std_logic; + signal mdout1_25_0: std_logic; + signal mdout1_24_0: std_logic; + signal mdout1_23_0: std_logic; + signal mdout1_22_0: std_logic; + signal mdout1_21_0: std_logic; + signal mdout1_20_0: std_logic; + signal mdout1_19_0: std_logic; + signal mdout1_18_0: std_logic; + signal mdout1_17_0: std_logic; + signal mdout1_16_0: std_logic; + signal mdout1_15_0: std_logic; + signal mdout1_14_0: std_logic; + signal mdout1_13_0: std_logic; + signal mdout1_12_0: std_logic; + signal mdout1_11_0: std_logic; + signal mdout1_10_0: std_logic; + signal mdout1_9_0: std_logic; + signal mdout1_8_0: std_logic; + signal mdout1_7_0: std_logic; + signal mdout1_6_0: std_logic; + signal mdout1_5_0: std_logic; + signal mdout1_4_0: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_31_1: std_logic; + signal mdout1_30_1: std_logic; + signal mdout1_29_1: std_logic; + signal mdout1_28_1: std_logic; + signal mdout1_27_1: std_logic; + signal mdout1_26_1: std_logic; + signal mdout1_25_1: std_logic; + signal mdout1_24_1: std_logic; + signal mdout1_23_1: std_logic; + signal mdout1_22_1: std_logic; + signal mdout1_21_1: std_logic; + signal mdout1_20_1: std_logic; + signal mdout1_19_1: std_logic; + signal mdout1_18_1: std_logic; + signal mdout1_17_1: std_logic; + signal mdout1_16_1: std_logic; + signal mdout1_15_1: std_logic; + signal mdout1_14_1: std_logic; + signal mdout1_13_1: std_logic; + signal mdout1_12_1: std_logic; + signal mdout1_11_1: std_logic; + signal mdout1_10_1: std_logic; + signal mdout1_9_1: std_logic; + signal mdout1_8_1: std_logic; + signal mdout1_7_1: std_logic; + signal mdout1_6_1: std_logic; + signal mdout1_5_1: std_logic; + signal mdout1_4_1: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_31_2: std_logic; + signal mdout1_30_2: std_logic; + signal mdout1_29_2: std_logic; + signal mdout1_28_2: std_logic; + signal mdout1_27_2: std_logic; + signal mdout1_26_2: std_logic; + signal mdout1_25_2: std_logic; + signal mdout1_24_2: std_logic; + signal mdout1_23_2: std_logic; + signal mdout1_22_2: std_logic; + signal mdout1_21_2: std_logic; + signal mdout1_20_2: std_logic; + signal mdout1_19_2: std_logic; + signal mdout1_18_2: std_logic; + signal mdout1_17_2: std_logic; + signal mdout1_16_2: std_logic; + signal mdout1_15_2: std_logic; + signal mdout1_14_2: std_logic; + signal mdout1_13_2: std_logic; + signal mdout1_12_2: std_logic; + signal mdout1_11_2: std_logic; + signal mdout1_10_2: std_logic; + signal mdout1_9_2: std_logic; + signal mdout1_8_2: std_logic; + signal mdout1_7_2: std_logic; + signal mdout1_6_2: std_logic; + signal mdout1_5_2: std_logic; + signal mdout1_4_2: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_31_3: std_logic; + signal mdout1_30_3: std_logic; + signal mdout1_29_3: std_logic; + signal mdout1_28_3: std_logic; + signal mdout1_27_3: std_logic; + signal mdout1_26_3: std_logic; + signal mdout1_25_3: std_logic; + signal mdout1_24_3: std_logic; + signal mdout1_23_3: std_logic; + signal mdout1_22_3: std_logic; + signal mdout1_21_3: std_logic; + signal mdout1_20_3: std_logic; + signal mdout1_19_3: std_logic; + signal mdout1_18_3: std_logic; + signal mdout1_17_3: std_logic; + signal mdout1_16_3: std_logic; + signal mdout1_15_3: std_logic; + signal mdout1_14_3: std_logic; + signal mdout1_13_3: std_logic; + signal mdout1_12_3: std_logic; + signal mdout1_11_3: std_logic; + signal mdout1_10_3: std_logic; + signal mdout1_9_3: std_logic; + signal mdout1_8_3: std_logic; + signal mdout1_7_3: std_logic; + signal mdout1_6_3: std_logic; + signal mdout1_5_3: std_logic; + signal mdout1_4_3: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_31_4: std_logic; + signal mdout1_30_4: std_logic; + signal mdout1_29_4: std_logic; + signal mdout1_28_4: std_logic; + signal mdout1_27_4: std_logic; + signal mdout1_26_4: std_logic; + signal mdout1_25_4: std_logic; + signal mdout1_24_4: std_logic; + signal mdout1_23_4: std_logic; + signal mdout1_22_4: std_logic; + signal mdout1_21_4: std_logic; + signal mdout1_20_4: std_logic; + signal mdout1_19_4: std_logic; + signal mdout1_18_4: std_logic; + signal mdout1_17_4: std_logic; + signal mdout1_16_4: std_logic; + signal mdout1_15_4: std_logic; + signal mdout1_14_4: std_logic; + signal mdout1_13_4: std_logic; + signal mdout1_12_4: std_logic; + signal mdout1_11_4: std_logic; + signal mdout1_10_4: std_logic; + signal mdout1_9_4: std_logic; + signal mdout1_8_4: std_logic; + signal mdout1_7_4: std_logic; + signal mdout1_6_4: std_logic; + signal mdout1_5_4: std_logic; + signal mdout1_4_4: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_31_5: std_logic; + signal mdout1_30_5: std_logic; + signal mdout1_29_5: std_logic; + signal mdout1_28_5: std_logic; + signal mdout1_27_5: std_logic; + signal mdout1_26_5: std_logic; + signal mdout1_25_5: std_logic; + signal mdout1_24_5: std_logic; + signal mdout1_23_5: std_logic; + signal mdout1_22_5: std_logic; + signal mdout1_21_5: std_logic; + signal mdout1_20_5: std_logic; + signal mdout1_19_5: std_logic; + signal mdout1_18_5: std_logic; + signal mdout1_17_5: std_logic; + signal mdout1_16_5: std_logic; + signal mdout1_15_5: std_logic; + signal mdout1_14_5: std_logic; + signal mdout1_13_5: std_logic; + signal mdout1_12_5: std_logic; + signal mdout1_11_5: std_logic; + signal mdout1_10_5: std_logic; + signal mdout1_9_5: std_logic; + signal mdout1_8_5: std_logic; + signal mdout1_7_5: std_logic; + signal mdout1_6_5: std_logic; + signal mdout1_5_5: std_logic; + signal mdout1_4_5: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_31_6: std_logic; + signal mdout1_30_6: std_logic; + signal mdout1_29_6: std_logic; + signal mdout1_28_6: std_logic; + signal mdout1_27_6: std_logic; + signal mdout1_26_6: std_logic; + signal mdout1_25_6: std_logic; + signal mdout1_24_6: std_logic; + signal mdout1_23_6: std_logic; + signal mdout1_22_6: std_logic; + signal mdout1_21_6: std_logic; + signal mdout1_20_6: std_logic; + signal mdout1_19_6: std_logic; + signal mdout1_18_6: std_logic; + signal mdout1_17_6: std_logic; + signal mdout1_16_6: std_logic; + signal mdout1_15_6: std_logic; + signal mdout1_14_6: std_logic; + signal mdout1_13_6: std_logic; + signal mdout1_12_6: std_logic; + signal mdout1_11_6: std_logic; + signal mdout1_10_6: std_logic; + signal mdout1_9_6: std_logic; + signal mdout1_8_6: std_logic; + signal mdout1_7_6: std_logic; + signal mdout1_6_6: std_logic; + signal mdout1_5_6: std_logic; + signal mdout1_4_6: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_31_7: std_logic; + signal mdout1_30_7: std_logic; + signal mdout1_29_7: std_logic; + signal mdout1_28_7: std_logic; + signal mdout1_27_7: std_logic; + signal mdout1_26_7: std_logic; + signal mdout1_25_7: std_logic; + signal mdout1_24_7: std_logic; + signal mdout1_23_7: std_logic; + signal mdout1_22_7: std_logic; + signal mdout1_21_7: std_logic; + signal mdout1_20_7: std_logic; + signal mdout1_19_7: std_logic; + signal mdout1_18_7: std_logic; + signal mdout1_17_7: std_logic; + signal mdout1_16_7: std_logic; + signal mdout1_15_7: std_logic; + signal mdout1_14_7: std_logic; + signal mdout1_13_7: std_logic; + signal mdout1_12_7: std_logic; + signal mdout1_11_7: std_logic; + signal mdout1_10_7: std_logic; + signal mdout1_9_7: std_logic; + signal mdout1_8_7: std_logic; + signal mdout1_7_7: std_logic; + signal mdout1_6_7: std_logic; + signal mdout1_5_7: std_logic; + signal mdout1_4_7: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_15_ff: std_logic; + signal rptr_14_ff: std_logic; + signal rptr_13_ff: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_31_8: std_logic; + signal mdout1_30_8: std_logic; + signal mdout1_29_8: std_logic; + signal mdout1_28_8: std_logic; + signal mdout1_27_8: std_logic; + signal mdout1_26_8: std_logic; + signal mdout1_25_8: std_logic; + signal mdout1_24_8: std_logic; + signal mdout1_23_8: std_logic; + signal mdout1_22_8: std_logic; + signal mdout1_21_8: std_logic; + signal mdout1_20_8: std_logic; + signal mdout1_19_8: std_logic; + signal mdout1_18_8: std_logic; + signal mdout1_17_8: std_logic; + signal mdout1_16_8: std_logic; + signal mdout1_15_8: std_logic; + signal mdout1_14_8: std_logic; + signal mdout1_13_8: std_logic; + signal mdout1_12_8: std_logic; + signal mdout1_11_8: std_logic; + signal mdout1_10_8: std_logic; + signal mdout1_9_8: std_logic; + signal mdout1_8_8: std_logic; + signal mdout1_7_8: std_logic; + signal mdout1_6_8: std_logic; + signal mdout1_5_8: std_logic; + signal mdout1_4_8: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal wfill_sub_0: std_logic; + signal wptr_0: std_logic; + signal precin: std_logic; + signal wfill_sub_1: std_logic; + signal wfill_sub_2: std_logic; + signal wptr_2: std_logic; + signal wptr_1: std_logic; + signal co0_2: std_logic; + signal wfill_sub_3: std_logic; + signal wfill_sub_4: std_logic; + signal wptr_4: std_logic; + signal wptr_3: std_logic; + signal co1_2: std_logic; + signal wfill_sub_5: std_logic; + signal wfill_sub_6: std_logic; + signal wptr_6: std_logic; + signal wptr_5: std_logic; + signal co2_2: std_logic; + signal wfill_sub_7: std_logic; + signal wfill_sub_8: std_logic; + signal wptr_8: std_logic; + signal wptr_7: std_logic; + signal co3_2: std_logic; + signal wfill_sub_9: std_logic; + signal wfill_sub_10: std_logic; + signal wptr_10: std_logic; + signal wptr_9: std_logic; + signal co4_2: std_logic; + signal wfill_sub_11: std_logic; + signal wfill_sub_12: std_logic; + signal wptr_12: std_logic; + signal wptr_11: std_logic; + signal co5_2: std_logic; + signal wfill_sub_13: std_logic; + signal wfill_sub_14: std_logic; + signal wptr_14: std_logic; + signal wptr_13: std_logic; + signal co6_2: std_logic; + signal wfill_sub_15: std_logic; + signal wfill_sub_msb: std_logic; + signal co7_2: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_3: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_3: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_3: std_logic; + signal wcount_r7: std_logic; + signal wcount_r8: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_3: std_logic; + signal wcount_r9: std_logic; + signal wcount_r10: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_3: std_logic; + signal wcount_r11: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_3: std_logic; + signal wcount_r13: std_logic; + signal wcount_r14: std_logic; + signal rcount_14: std_logic; + signal rcount_15: std_logic; + signal co7_3: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_4: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_4: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_4: std_logic; + signal rcount_w7: std_logic; + signal rcount_w8: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_4: std_logic; + signal rcount_w9: std_logic; + signal rcount_w10: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_4: std_logic; + signal rcount_w11: std_logic; + signal rcount_w12: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_4: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w14: std_logic; + signal wcount_12: std_logic; + signal wcount_13: std_logic; + signal co6_4: std_logic; + signal rcount_w15: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_14: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal full_d_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_1_0_30 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_30 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_2_0_29 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_29 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_3_0_28 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_28 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_4_0_27 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_0_27 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_5_0_26 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_0_26 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_6_0_25 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_0_25 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_7_0_24 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_0_24 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_8_0_23 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_8_0_23 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_9_0_22 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_9_0_22 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_10_0_21 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_10_0_21 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_11_0_20 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_11_0_20 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_12_0_19 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_12_0_19 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_13_0_18 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_13_0_18 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_14_0_17 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_14_0_17 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_15_0_16 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_15_0_16 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_16_0_15 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_16_0_15 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_17_0_14 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_17_0_14 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_18_0_13 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_18_0_13 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_19_0_12 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_19_0_12 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_20_0_11 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_20_0_11 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_21_0_10 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_21_0_10 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_22_0_9 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_22_0_9 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_23_0_8 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_23_0_8 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_24_0_7 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_24_0_7 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_25_0_6 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_25_0_6 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_26_0_5 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_26_0_5 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_27_0_4 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_27_0_4 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_28_0_3 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_28_0_3 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_29_0_2 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_29_0_2 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_30_0_1 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_30_0_1 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_31_0_0 : label is "fifo_64kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_31_0_0 : label is ""; + attribute GSR of FF_187 : label is "ENABLED"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t34: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_11: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t33: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_10: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t32: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t31: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t30: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t29: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t28: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t27: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t26: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t25: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t24: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t23: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t22: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t21: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t20: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t19: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t18: XOR2 + port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13); + + XOR2_t17: XOR2 + port map (A=>wcount_14, B=>wcount_15, Z=>w_gdata_14); + + XOR2_t16: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t15: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t14: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t13: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t12: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t11: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t10: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t9: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t8: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t7: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t6: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t5: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t4: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t3: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + XOR2_t2: XOR2 + port map (A=>rcount_14, B=>rcount_15, Z=>r_gdata_14); + + XOR2_t1: XOR2 + port map (A=>rcount_15, B=>rcount_16, Z=>r_gdata_15); + + INV_9: INV + port map (A=>wptr_10, Z=>wptr_10_inv); + + INV_8: INV + port map (A=>wptr_11, Z=>wptr_11_inv); + + INV_7: INV + port map (A=>wptr_12, Z=>wptr_12_inv); + + INV_6: INV + port map (A=>wptr_13, Z=>wptr_13_inv); + + INV_5: INV + port map (A=>wptr_14, Z=>wptr_14_inv); + + LUT4_180: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet); + + LUT4_179: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_p00); + + INV_4: INV + port map (A=>rptr_11, Z=>rptr_11_inv); + + INV_3: INV + port map (A=>rptr_12, Z=>rptr_12_inv); + + INV_2: INV + port map (A=>rptr_13, Z=>rptr_13_inv); + + INV_1: INV + port map (A=>rptr_14, Z=>rptr_14_inv); + + INV_0: INV + port map (A=>rptr_15, Z=>rptr_15_inv); + + LUT4_178: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_1); + + LUT4_177: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_1, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec1_r10); + + LUT4_176: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_2); + + LUT4_175: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_2, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec2_p01); + + LUT4_174: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_3); + + LUT4_173: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_3, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec3_r11); + + LUT4_172: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_4); + + LUT4_171: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_4, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec4_p02); + + LUT4_170: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_5); + + LUT4_169: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_5, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec5_r12); + + LUT4_168: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_6); + + LUT4_167: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_6, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec6_p03); + + LUT4_166: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_7); + + LUT4_165: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_7, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec7_r13); + + LUT4_164: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_8); + + LUT4_163: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_8, AD2=>wptr_14_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec8_p04); + + LUT4_162: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_9); + + LUT4_161: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_9, AD2=>rptr_15_inv, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec9_r14); + + LUT4_160: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_10); + + LUT4_159: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_10, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec10_p05); + + LUT4_158: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_11); + + LUT4_157: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_11, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec11_r15); + + LUT4_156: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_12); + + LUT4_155: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_12, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec12_p06); + + LUT4_154: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_13); + + LUT4_153: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_13, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec13_r16); + + LUT4_152: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_14); + + LUT4_151: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_14, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec14_p07); + + LUT4_150: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_15); + + LUT4_149: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_15, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec15_r17); + + LUT4_148: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_16); + + LUT4_147: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_16, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec16_p08); + + LUT4_146: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_17); + + LUT4_145: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_17, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec17_r18); + + LUT4_144: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_18); + + LUT4_143: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_18, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec18_p09); + + LUT4_142: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_19); + + LUT4_141: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_19, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec19_r19); + + LUT4_140: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_20); + + LUT4_139: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_20, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec20_p010); + + LUT4_138: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_21); + + LUT4_137: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_21, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec21_r110); + + LUT4_136: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_22); + + LUT4_135: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_22, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec22_p011); + + LUT4_134: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_23); + + LUT4_133: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_23, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec23_r111); + + LUT4_132: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_24); + + LUT4_131: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_24, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec24_p012); + + LUT4_130: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_25); + + LUT4_129: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_25, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec25_r112); + + LUT4_128: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_26); + + LUT4_127: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_26, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec26_p013); + + LUT4_126: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_27); + + LUT4_125: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_27, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec27_r113); + + LUT4_124: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_28); + + LUT4_123: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_28, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec28_p014); + + LUT4_122: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_29); + + LUT4_121: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_29, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec29_r114); + + LUT4_120: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, + DO0=>func_and_inet_30); + + LUT4_119: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_30, AD2=>wptr_14_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec30_p015); + + LUT4_118: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_31); + + LUT4_117: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_31, AD2=>rptr_15_inv, + AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec31_r115); + + LUT4_116: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_32); + + LUT4_115: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_32, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec32_p016); + + LUT4_114: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_33); + + LUT4_113: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_33, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec33_r116); + + LUT4_112: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_34); + + LUT4_111: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_34, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec34_p017); + + LUT4_110: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_35); + + LUT4_109: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_35, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec35_r117); + + LUT4_108: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_36); + + LUT4_107: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_36, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec36_p018); + + LUT4_106: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_37); + + LUT4_105: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_37, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec37_r118); + + LUT4_104: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13_inv, DO0=>func_and_inet_38); + + LUT4_103: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_38, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec38_p019); + + LUT4_102: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14_inv, DO0=>func_and_inet_39); + + LUT4_101: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_39, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec39_r119); + + LUT4_100: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_40); + + LUT4_99: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_40, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec40_p020); + + LUT4_98: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_41); + + LUT4_97: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_41, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec41_r120); + + LUT4_96: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_42); + + LUT4_95: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_42, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec42_p021); + + LUT4_94: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_43); + + LUT4_93: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_43, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec43_r121); + + LUT4_92: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_44); + + LUT4_91: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_44, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec44_p022); + + LUT4_90: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_45); + + LUT4_89: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_45, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec45_r122); + + LUT4_88: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13_inv, DO0=>func_and_inet_46); + + LUT4_87: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_46, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec46_p023); + + LUT4_86: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14_inv, DO0=>func_and_inet_47); + + LUT4_85: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_47, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec47_r123); + + LUT4_84: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_48); + + LUT4_83: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_48, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec48_p024); + + LUT4_82: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_49); + + LUT4_81: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_49, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec49_r124); + + LUT4_80: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_50); + + LUT4_79: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_50, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec50_p025); + + LUT4_78: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_51); + + LUT4_77: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_51, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec51_r125); + + LUT4_76: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_52); + + LUT4_75: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_52, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec52_p026); + + LUT4_74: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_53); + + LUT4_73: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_53, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec53_r126); + + LUT4_72: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12_inv, + AD0=>wptr_13, DO0=>func_and_inet_54); + + LUT4_71: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_54, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec54_p027); + + LUT4_70: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv, + AD0=>rptr_14, DO0=>func_and_inet_55); + + LUT4_69: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_55, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec55_r127); + + LUT4_68: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_56); + + LUT4_67: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_56, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec56_p028); + + LUT4_66: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_57); + + LUT4_65: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_57, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec57_r128); + + LUT4_64: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11_inv, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_58); + + LUT4_63: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_58, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec58_p029); + + LUT4_62: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_59); + + LUT4_61: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_59, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec59_r129); + + LUT4_60: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10_inv, AD2=>wptr_11, AD1=>wptr_12, + AD0=>wptr_13, DO0=>func_and_inet_60); + + LUT4_59: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_60, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec60_p030); + + LUT4_58: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13, + AD0=>rptr_14, DO0=>func_and_inet_61); + + LUT4_57: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_61, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec61_r130); + + LUT4_56: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>wptr_10, AD2=>wptr_11, AD1=>wptr_12, AD0=>wptr_13, + DO0=>func_and_inet_62); + + LUT4_55: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_62, AD2=>wptr_14, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec62_p031); + + LUT4_54: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14, + DO0=>func_and_inet_63); + + LUT4_53: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>func_and_inet_63, AD2=>rptr_15, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec63_r131); + + LUT4_52: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, + AD1=>w_gcount_r214, AD0=>w_gcount_r215, + DO0=>w_g2b_xor_cluster_0); + + LUT4_51: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>w_gcount_r211, + DO0=>w_g2b_xor_cluster_1); + + LUT4_50: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, + DO0=>w_g2b_xor_cluster_2); + + LUT4_49: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_gcount_r23, + DO0=>w_g2b_xor_cluster_3); + + LUT4_48: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r214, AD2=>w_gcount_r215, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r14); + + LUT4_47: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, + AD1=>w_gcount_r215, AD0=>scuba_vlo, DO0=>wcount_r13); + + LUT4_46: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>wcount_r14, DO0=>wcount_r11); + + LUT4_45: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10); + + LUT4_44: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r9); + + LUT4_43: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r8); + + LUT4_42: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r27, AD0=>scuba_vlo, DO0=>wcount_r7); + + LUT4_41: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r26, AD0=>w_gcount_r27, DO0=>wcount_r6); + + LUT4_40: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, + AD1=>w_gcount_r27, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r23, DO0=>wcount_r3); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3_1); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1, + DO0=>wcount_r2); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_3_2); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_2, + DO0=>wcount_r1); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r0); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, + AD1=>r_gcount_w215, AD0=>r_gcount_w216, + DO0=>r_g2b_xor_cluster_0); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>r_gcount_w212, + DO0=>r_g2b_xor_cluster_1); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, + DO0=>r_g2b_xor_cluster_2); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_3); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w215, AD2=>r_gcount_w216, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w15); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w214, AD2=>r_gcount_w215, + AD1=>r_gcount_w216, AD0=>scuba_vlo, DO0=>rcount_w14); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>rcount_w15, DO0=>rcount_w12); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>rcount_w14, DO0=>rcount_w11); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>r_g2b_xor_cluster_0, + DO0=>rcount_w10); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w9); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w28, AD0=>scuba_vlo, DO0=>rcount_w8); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w27, AD0=>r_gcount_w28, DO0=>rcount_w7); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, + AD1=>r_gcount_w28, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w24, DO0=>rcount_w4); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3_1); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w3); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_2); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_2, + DO0=>rcount_w2); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_gcount_w23, DO0=>func_xor_inet); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>r_gcount_w27, DO0=>func_xor_inet_1); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_gcount_w211, DO0=>func_xor_inet_2); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>r_gcount_w215, DO0=>func_xor_inet_3); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w216, AD2=>scuba_vlo, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>func_xor_inet_4); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet, AD2=>func_xor_inet_1, + AD1=>func_xor_inet_2, AD0=>func_xor_inet_3, + DO0=>func_xor_inet_5); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>func_xor_inet_5, AD2=>func_xor_inet_4, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); + + XOR2_t0: XOR2 + port map (A=>wptr_15, B=>r_gcount_w216, Z=>wfill_sub_msb); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_16, AD2=>rcount_16, AD1=>w_gcount_r215, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_15, AD2=>wcount_15, AD1=>r_gcount_w216, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_31: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec0_p00, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec1_r10, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_0_8, + DOB7=>mdout1_0_7, DOB6=>mdout1_0_6, DOB5=>mdout1_0_5, + DOB4=>mdout1_0_4, DOB3=>mdout1_0_3, DOB2=>mdout1_0_2, + DOB1=>mdout1_0_1, DOB0=>mdout1_0_0); + + pdp_ram_1_0_30: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec2_p01, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec3_r11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_1_8, + DOB7=>mdout1_1_7, DOB6=>mdout1_1_6, DOB5=>mdout1_1_5, + DOB4=>mdout1_1_4, DOB3=>mdout1_1_3, DOB2=>mdout1_1_2, + DOB1=>mdout1_1_1, DOB0=>mdout1_1_0); + + pdp_ram_2_0_29: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec4_p02, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec5_r12, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_2_8, + DOB7=>mdout1_2_7, DOB6=>mdout1_2_6, DOB5=>mdout1_2_5, + DOB4=>mdout1_2_4, DOB3=>mdout1_2_3, DOB2=>mdout1_2_2, + DOB1=>mdout1_2_1, DOB0=>mdout1_2_0); + + pdp_ram_3_0_28: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec6_p03, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec7_r13, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_3_8, + DOB7=>mdout1_3_7, DOB6=>mdout1_3_6, DOB5=>mdout1_3_5, + DOB4=>mdout1_3_4, DOB3=>mdout1_3_3, DOB2=>mdout1_3_2, + DOB1=>mdout1_3_1, DOB0=>mdout1_3_0); + + pdp_ram_4_0_27: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec8_p04, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec9_r14, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_4_8, + DOB7=>mdout1_4_7, DOB6=>mdout1_4_6, DOB5=>mdout1_4_5, + DOB4=>mdout1_4_4, DOB3=>mdout1_4_3, DOB2=>mdout1_4_2, + DOB1=>mdout1_4_1, DOB0=>mdout1_4_0); + + pdp_ram_5_0_26: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec10_p05, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec11_r15, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_5_8, + DOB7=>mdout1_5_7, DOB6=>mdout1_5_6, DOB5=>mdout1_5_5, + DOB4=>mdout1_5_4, DOB3=>mdout1_5_3, DOB2=>mdout1_5_2, + DOB1=>mdout1_5_1, DOB0=>mdout1_5_0); + + pdp_ram_6_0_25: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec12_p06, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec13_r16, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_6_8, + DOB7=>mdout1_6_7, DOB6=>mdout1_6_6, DOB5=>mdout1_6_5, + DOB4=>mdout1_6_4, DOB3=>mdout1_6_3, DOB2=>mdout1_6_2, + DOB1=>mdout1_6_1, DOB0=>mdout1_6_0); + + pdp_ram_7_0_24: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec14_p07, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec15_r17, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_7_8, + DOB7=>mdout1_7_7, DOB6=>mdout1_7_6, DOB5=>mdout1_7_5, + DOB4=>mdout1_7_4, DOB3=>mdout1_7_3, DOB2=>mdout1_7_2, + DOB1=>mdout1_7_1, DOB0=>mdout1_7_0); + + pdp_ram_8_0_23: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec16_p08, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec17_r18, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_8_8, + DOB7=>mdout1_8_7, DOB6=>mdout1_8_6, DOB5=>mdout1_8_5, + DOB4=>mdout1_8_4, DOB3=>mdout1_8_3, DOB2=>mdout1_8_2, + DOB1=>mdout1_8_1, DOB0=>mdout1_8_0); + + pdp_ram_9_0_22: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec18_p09, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec19_r19, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_9_8, + DOB7=>mdout1_9_7, DOB6=>mdout1_9_6, DOB5=>mdout1_9_5, + DOB4=>mdout1_9_4, DOB3=>mdout1_9_3, DOB2=>mdout1_9_2, + DOB1=>mdout1_9_1, DOB0=>mdout1_9_0); + + pdp_ram_10_0_21: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec20_p010, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec21_r110, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_10_8, + DOB7=>mdout1_10_7, DOB6=>mdout1_10_6, DOB5=>mdout1_10_5, + DOB4=>mdout1_10_4, DOB3=>mdout1_10_3, DOB2=>mdout1_10_2, + DOB1=>mdout1_10_1, DOB0=>mdout1_10_0); + + pdp_ram_11_0_20: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec22_p011, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec23_r111, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_11_8, + DOB7=>mdout1_11_7, DOB6=>mdout1_11_6, DOB5=>mdout1_11_5, + DOB4=>mdout1_11_4, DOB3=>mdout1_11_3, DOB2=>mdout1_11_2, + DOB1=>mdout1_11_1, DOB0=>mdout1_11_0); + + pdp_ram_12_0_19: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec24_p012, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec25_r112, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_12_8, + DOB7=>mdout1_12_7, DOB6=>mdout1_12_6, DOB5=>mdout1_12_5, + DOB4=>mdout1_12_4, DOB3=>mdout1_12_3, DOB2=>mdout1_12_2, + DOB1=>mdout1_12_1, DOB0=>mdout1_12_0); + + pdp_ram_13_0_18: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec26_p013, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec27_r113, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_13_8, + DOB7=>mdout1_13_7, DOB6=>mdout1_13_6, DOB5=>mdout1_13_5, + DOB4=>mdout1_13_4, DOB3=>mdout1_13_3, DOB2=>mdout1_13_2, + DOB1=>mdout1_13_1, DOB0=>mdout1_13_0); + + pdp_ram_14_0_17: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec28_p014, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec29_r114, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_14_8, + DOB7=>mdout1_14_7, DOB6=>mdout1_14_6, DOB5=>mdout1_14_5, + DOB4=>mdout1_14_4, DOB3=>mdout1_14_3, DOB2=>mdout1_14_2, + DOB1=>mdout1_14_1, DOB0=>mdout1_14_0); + + pdp_ram_15_0_16: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec30_p015, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec31_r115, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_15_8, + DOB7=>mdout1_15_7, DOB6=>mdout1_15_6, DOB5=>mdout1_15_5, + DOB4=>mdout1_15_4, DOB3=>mdout1_15_3, DOB2=>mdout1_15_2, + DOB1=>mdout1_15_1, DOB0=>mdout1_15_0); + + pdp_ram_16_0_15: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec32_p016, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec33_r116, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_16_8, + DOB7=>mdout1_16_7, DOB6=>mdout1_16_6, DOB5=>mdout1_16_5, + DOB4=>mdout1_16_4, DOB3=>mdout1_16_3, DOB2=>mdout1_16_2, + DOB1=>mdout1_16_1, DOB0=>mdout1_16_0); + + pdp_ram_17_0_14: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec34_p017, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec35_r117, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_17_8, + DOB7=>mdout1_17_7, DOB6=>mdout1_17_6, DOB5=>mdout1_17_5, + DOB4=>mdout1_17_4, DOB3=>mdout1_17_3, DOB2=>mdout1_17_2, + DOB1=>mdout1_17_1, DOB0=>mdout1_17_0); + + pdp_ram_18_0_13: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec36_p018, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec37_r118, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_18_8, + DOB7=>mdout1_18_7, DOB6=>mdout1_18_6, DOB5=>mdout1_18_5, + DOB4=>mdout1_18_4, DOB3=>mdout1_18_3, DOB2=>mdout1_18_2, + DOB1=>mdout1_18_1, DOB0=>mdout1_18_0); + + pdp_ram_19_0_12: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec38_p019, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec39_r119, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_19_8, + DOB7=>mdout1_19_7, DOB6=>mdout1_19_6, DOB5=>mdout1_19_5, + DOB4=>mdout1_19_4, DOB3=>mdout1_19_3, DOB2=>mdout1_19_2, + DOB1=>mdout1_19_1, DOB0=>mdout1_19_0); + + pdp_ram_20_0_11: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec40_p020, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec41_r120, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_20_8, + DOB7=>mdout1_20_7, DOB6=>mdout1_20_6, DOB5=>mdout1_20_5, + DOB4=>mdout1_20_4, DOB3=>mdout1_20_3, DOB2=>mdout1_20_2, + DOB1=>mdout1_20_1, DOB0=>mdout1_20_0); + + pdp_ram_21_0_10: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec42_p021, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec43_r121, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_21_8, + DOB7=>mdout1_21_7, DOB6=>mdout1_21_6, DOB5=>mdout1_21_5, + DOB4=>mdout1_21_4, DOB3=>mdout1_21_3, DOB2=>mdout1_21_2, + DOB1=>mdout1_21_1, DOB0=>mdout1_21_0); + + pdp_ram_22_0_9: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec44_p022, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec45_r122, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_22_8, + DOB7=>mdout1_22_7, DOB6=>mdout1_22_6, DOB5=>mdout1_22_5, + DOB4=>mdout1_22_4, DOB3=>mdout1_22_3, DOB2=>mdout1_22_2, + DOB1=>mdout1_22_1, DOB0=>mdout1_22_0); + + pdp_ram_23_0_8: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec46_p023, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec47_r123, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_23_8, + DOB7=>mdout1_23_7, DOB6=>mdout1_23_6, DOB5=>mdout1_23_5, + DOB4=>mdout1_23_4, DOB3=>mdout1_23_3, DOB2=>mdout1_23_2, + DOB1=>mdout1_23_1, DOB0=>mdout1_23_0); + + pdp_ram_24_0_7: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec48_p024, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec49_r124, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_24_8, + DOB7=>mdout1_24_7, DOB6=>mdout1_24_6, DOB5=>mdout1_24_5, + DOB4=>mdout1_24_4, DOB3=>mdout1_24_3, DOB2=>mdout1_24_2, + DOB1=>mdout1_24_1, DOB0=>mdout1_24_0); + + pdp_ram_25_0_6: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec50_p025, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec51_r125, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_25_8, + DOB7=>mdout1_25_7, DOB6=>mdout1_25_6, DOB5=>mdout1_25_5, + DOB4=>mdout1_25_4, DOB3=>mdout1_25_3, DOB2=>mdout1_25_2, + DOB1=>mdout1_25_1, DOB0=>mdout1_25_0); + + pdp_ram_26_0_5: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec52_p026, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec53_r126, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_26_8, + DOB7=>mdout1_26_7, DOB6=>mdout1_26_6, DOB5=>mdout1_26_5, + DOB4=>mdout1_26_4, DOB3=>mdout1_26_3, DOB2=>mdout1_26_2, + DOB1=>mdout1_26_1, DOB0=>mdout1_26_0); + + pdp_ram_27_0_4: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec54_p027, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec55_r127, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_27_8, + DOB7=>mdout1_27_7, DOB6=>mdout1_27_6, DOB5=>mdout1_27_5, + DOB4=>mdout1_27_4, DOB3=>mdout1_27_3, DOB2=>mdout1_27_2, + DOB1=>mdout1_27_1, DOB0=>mdout1_27_0); + + pdp_ram_28_0_3: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec56_p028, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec57_r128, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_28_8, + DOB7=>mdout1_28_7, DOB6=>mdout1_28_6, DOB5=>mdout1_28_5, + DOB4=>mdout1_28_4, DOB3=>mdout1_28_3, DOB2=>mdout1_28_2, + DOB1=>mdout1_28_1, DOB0=>mdout1_28_0); + + pdp_ram_29_0_2: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec58_p029, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec59_r129, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_29_8, + DOB7=>mdout1_29_7, DOB6=>mdout1_29_6, DOB5=>mdout1_29_5, + DOB4=>mdout1_29_4, DOB3=>mdout1_29_3, DOB2=>mdout1_29_2, + DOB1=>mdout1_29_1, DOB0=>mdout1_29_0); + + pdp_ram_30_0_1: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec60_p030, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec61_r130, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_30_8, + DOB7=>mdout1_30_7, DOB6=>mdout1_30_6, DOB5=>mdout1_30_5, + DOB4=>mdout1_30_4, DOB3=>mdout1_30_3, DOB2=>mdout1_30_2, + DOB1=>mdout1_30_1, DOB0=>mdout1_30_0); + + pdp_ram_31_0_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>dec62_p031, + RSTA=>Reset, DIB17=>scuba_vlo, DIB16=>scuba_vlo, + DIB15=>scuba_vlo, DIB14=>scuba_vlo, DIB13=>scuba_vlo, + DIB12=>scuba_vlo, DIB11=>scuba_vlo, DIB10=>scuba_vlo, + DIB9=>scuba_vlo, DIB8=>scuba_vlo, DIB7=>scuba_vlo, + DIB6=>scuba_vlo, DIB5=>scuba_vlo, DIB4=>scuba_vlo, + DIB3=>scuba_vlo, DIB2=>scuba_vlo, DIB1=>scuba_vlo, + DIB0=>scuba_vlo, ADB13=>rptr_10, ADB12=>rptr_9, + ADB11=>rptr_8, ADB10=>rptr_7, ADB9=>rptr_6, ADB8=>rptr_5, + ADB7=>rptr_4, ADB6=>rptr_3, ADB5=>rptr_2, ADB4=>rptr_1, + ADB3=>rptr_0, ADB2=>scuba_vlo, ADB1=>scuba_vlo, + ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, CLKB=>RdClock, + WEB=>scuba_vlo, CSB2=>scuba_vlo, CSB1=>scuba_vlo, + CSB0=>dec63_r131, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_31_8, + DOB7=>mdout1_31_7, DOB6=>mdout1_31_6, DOB5=>mdout1_31_5, + DOB4=>mdout1_31_4, DOB3=>mdout1_31_3, DOB2=>mdout1_31_2, + DOB1=>mdout1_31_1, DOB0=>mdout1_31_0); + + FF_187: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_186: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_185: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_184: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_183: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_182: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_181: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_180: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_179: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_178: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_177: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_176: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_175: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_174: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_173: FD1P3DX + port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_14); + + FF_172: FD1P3DX + port map (D=>iwcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_15); + + FF_171: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_170: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_169: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_168: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_167: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_166: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_165: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_164: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_163: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_162: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_161: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_160: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_159: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_158: FD1P3DX + port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_157: FD1P3DX + port map (D=>w_gdata_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_14); + + FF_156: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_15); + + FF_155: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_154: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_153: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_152: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_151: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_150: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_149: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_148: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_147: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_146: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_145: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_144: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_143: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_142: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_141: FD1P3DX + port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_14); + + FF_140: FD1P3DX + port map (D=>wcount_15, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_15); + + FF_139: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_138: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_137: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_136: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_135: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_134: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_133: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_132: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_131: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_130: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_129: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_128: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_127: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_126: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_125: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_124: FD1P3DX + port map (D=>ircount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_15); + + FF_123: FD1P3DX + port map (D=>ircount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_16); + + FF_122: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_121: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_120: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_119: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_118: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_117: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_116: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_115: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_114: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_113: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_112: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_111: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_110: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_109: FD1P3DX + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_108: FD1P3DX + port map (D=>r_gdata_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_107: FD1P3DX + port map (D=>r_gdata_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_15); + + FF_106: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_16); + + FF_105: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_104: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_103: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_102: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_101: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_100: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_99: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_98: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_97: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_96: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_95: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_94: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_93: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_92: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_91: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_90: FD1P3DX + port map (D=>rcount_15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_15); + + FF_89: FD1P3DX + port map (D=>rcount_16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_16); + + FF_88: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_87: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_86: FD1P3DX + port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_13_ff); + + FF_85: FD1P3DX + port map (D=>rptr_14, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_14_ff); + + FF_84: FD1P3DX + port map (D=>rptr_15, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_15_ff); + + FF_83: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_82: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_81: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_80: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_79: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_78: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_77: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_76: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_75: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_74: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_73: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_72: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_71: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_70: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_69: FD1S3DX + port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r14); + + FF_68: FD1S3DX + port map (D=>w_gcount_15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r15); + + FF_67: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_66: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_65: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_64: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_63: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_62: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_61: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_60: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_59: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_58: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_57: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_56: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_55: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_54: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_53: FD1S3DX + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_52: FD1S3DX + port map (D=>r_gcount_15, CK=>WrClock, CD=>rRst, Q=>r_gcount_w15); + + FF_51: FD1S3DX + port map (D=>r_gcount_16, CK=>WrClock, CD=>rRst, Q=>r_gcount_w16); + + FF_50: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_49: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_48: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_47: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_46: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_45: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_44: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_43: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_42: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_41: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_40: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_39: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_38: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_37: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_36: FD1S3DX + port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r214); + + FF_35: FD1S3DX + port map (D=>w_gcount_r15, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r215); + + FF_34: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_33: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_32: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_31: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_30: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_29: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_28: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_27: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_26: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_25: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_24: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_23: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_22: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_21: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_20: FD1S3DX + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_19: FD1S3DX + port map (D=>r_gcount_w15, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w215); + + FF_18: FD1S3DX + port map (D=>r_gcount_w16, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w216); + + FF_17: FD1S3DX + port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); + + FF_16: FD1S3DX + port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); + + FF_15: FD1S3DX + port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); + + FF_14: FD1S3DX + port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); + + FF_13: FD1S3DX + port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); + + FF_12: FD1S3DX + port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); + + FF_11: FD1S3DX + port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); + + FF_10: FD1S3DX + port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); + + FF_9: FD1S3DX + port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); + + FF_8: FD1S3DX + port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); + + FF_7: FD1S3DX + port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); + + FF_6: FD1S3DX + port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); + + FF_5: FD1S3DX + port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); + + FF_4: FD1S3DX + port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); + + FF_3: FD1S3DX + port map (D=>wfill_sub_14, CK=>WrClock, CD=>Reset, Q=>WCNT(14)); + + FF_2: FD1S3DX + port map (D=>wfill_sub_15, CK=>WrClock, CD=>Reset, Q=>WCNT(15)); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_gctr_ci); + + w_gctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_gctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0); + + w_gctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1); + + w_gctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2); + + w_gctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3); + + w_gctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4); + + w_gctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4, S0=>iwcount_10, S1=>iwcount_11, + COUT=>co5); + + w_gctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_12, A1=>wcount_13, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5, S0=>iwcount_12, S1=>iwcount_13, + COUT=>co6); + + w_gctr_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_14, A1=>wcount_15, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6, S0=>iwcount_14, S1=>iwcount_15, + COUT=>co7); + + r_gctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_gctr_ci); + + r_gctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_gctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_1); + + r_gctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_1); + + r_gctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_1); + + r_gctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_1); + + r_gctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_1); + + r_gctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_1, S0=>ircount_10, S1=>ircount_11, + COUT=>co5_1); + + r_gctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_12, A1=>rcount_13, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_1, S0=>ircount_12, S1=>ircount_13, + COUT=>co6_1); + + r_gctr_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_14, A1=>rcount_15, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_1, S0=>ircount_14, S1=>ircount_15, + COUT=>co7_1); + + r_gctr_8: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_16, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co7_1, S0=>ircount_16, S1=>open, + COUT=>co8); + + mux_8: MUX321 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, + D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0, + D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0, + D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0, + D15=>mdout1_15_0, D16=>mdout1_16_0, D17=>mdout1_17_0, + D18=>mdout1_18_0, D19=>mdout1_19_0, D20=>mdout1_20_0, + D21=>mdout1_21_0, D22=>mdout1_22_0, D23=>mdout1_23_0, + D24=>mdout1_24_0, D25=>mdout1_25_0, D26=>mdout1_26_0, + D27=>mdout1_27_0, D28=>mdout1_28_0, D29=>mdout1_29_0, + D30=>mdout1_30_0, D31=>mdout1_31_0, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(0)); + + mux_7: MUX321 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, + D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1, + D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1, + D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1, + D15=>mdout1_15_1, D16=>mdout1_16_1, D17=>mdout1_17_1, + D18=>mdout1_18_1, D19=>mdout1_19_1, D20=>mdout1_20_1, + D21=>mdout1_21_1, D22=>mdout1_22_1, D23=>mdout1_23_1, + D24=>mdout1_24_1, D25=>mdout1_25_1, D26=>mdout1_26_1, + D27=>mdout1_27_1, D28=>mdout1_28_1, D29=>mdout1_29_1, + D30=>mdout1_30_1, D31=>mdout1_31_1, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(1)); + + mux_6: MUX321 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, + D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2, + D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2, + D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2, + D15=>mdout1_15_2, D16=>mdout1_16_2, D17=>mdout1_17_2, + D18=>mdout1_18_2, D19=>mdout1_19_2, D20=>mdout1_20_2, + D21=>mdout1_21_2, D22=>mdout1_22_2, D23=>mdout1_23_2, + D24=>mdout1_24_2, D25=>mdout1_25_2, D26=>mdout1_26_2, + D27=>mdout1_27_2, D28=>mdout1_28_2, D29=>mdout1_29_2, + D30=>mdout1_30_2, D31=>mdout1_31_2, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(2)); + + mux_5: MUX321 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, + D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3, + D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3, + D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3, + D15=>mdout1_15_3, D16=>mdout1_16_3, D17=>mdout1_17_3, + D18=>mdout1_18_3, D19=>mdout1_19_3, D20=>mdout1_20_3, + D21=>mdout1_21_3, D22=>mdout1_22_3, D23=>mdout1_23_3, + D24=>mdout1_24_3, D25=>mdout1_25_3, D26=>mdout1_26_3, + D27=>mdout1_27_3, D28=>mdout1_28_3, D29=>mdout1_29_3, + D30=>mdout1_30_3, D31=>mdout1_31_3, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(3)); + + mux_4: MUX321 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, + D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4, + D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4, + D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4, + D15=>mdout1_15_4, D16=>mdout1_16_4, D17=>mdout1_17_4, + D18=>mdout1_18_4, D19=>mdout1_19_4, D20=>mdout1_20_4, + D21=>mdout1_21_4, D22=>mdout1_22_4, D23=>mdout1_23_4, + D24=>mdout1_24_4, D25=>mdout1_25_4, D26=>mdout1_26_4, + D27=>mdout1_27_4, D28=>mdout1_28_4, D29=>mdout1_29_4, + D30=>mdout1_30_4, D31=>mdout1_31_4, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(4)); + + mux_3: MUX321 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, + D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5, + D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5, + D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5, + D15=>mdout1_15_5, D16=>mdout1_16_5, D17=>mdout1_17_5, + D18=>mdout1_18_5, D19=>mdout1_19_5, D20=>mdout1_20_5, + D21=>mdout1_21_5, D22=>mdout1_22_5, D23=>mdout1_23_5, + D24=>mdout1_24_5, D25=>mdout1_25_5, D26=>mdout1_26_5, + D27=>mdout1_27_5, D28=>mdout1_28_5, D29=>mdout1_29_5, + D30=>mdout1_30_5, D31=>mdout1_31_5, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(5)); + + mux_2: MUX321 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, + D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6, + D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6, + D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6, + D15=>mdout1_15_6, D16=>mdout1_16_6, D17=>mdout1_17_6, + D18=>mdout1_18_6, D19=>mdout1_19_6, D20=>mdout1_20_6, + D21=>mdout1_21_6, D22=>mdout1_22_6, D23=>mdout1_23_6, + D24=>mdout1_24_6, D25=>mdout1_25_6, D26=>mdout1_26_6, + D27=>mdout1_27_6, D28=>mdout1_28_6, D29=>mdout1_29_6, + D30=>mdout1_30_6, D31=>mdout1_31_6, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(6)); + + mux_1: MUX321 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, + D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7, + D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7, + D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7, + D15=>mdout1_15_7, D16=>mdout1_16_7, D17=>mdout1_17_7, + D18=>mdout1_18_7, D19=>mdout1_19_7, D20=>mdout1_20_7, + D21=>mdout1_21_7, D22=>mdout1_22_7, D23=>mdout1_23_7, + D24=>mdout1_24_7, D25=>mdout1_25_7, D26=>mdout1_26_7, + D27=>mdout1_27_7, D28=>mdout1_28_7, D29=>mdout1_29_7, + D30=>mdout1_30_7, D31=>mdout1_31_7, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(7)); + + mux_0: MUX321 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, + D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8, + D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8, + D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8, + D15=>mdout1_15_8, D16=>mdout1_16_8, D17=>mdout1_17_8, + D18=>mdout1_18_8, D19=>mdout1_19_8, D20=>mdout1_20_8, + D21=>mdout1_21_8, D22=>mdout1_22_8, D23=>mdout1_23_8, + D24=>mdout1_24_8, D25=>mdout1_25_8, D26=>mdout1_26_8, + D27=>mdout1_27_8, D28=>mdout1_28_8, D29=>mdout1_29_8, + D30=>mdout1_30_8, D31=>mdout1_31_8, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, SD4=>rptr_14_ff, + SD5=>rptr_15_ff, Z=>Q(8)); + + precin_inst812: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wfill_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, + B1=>rcount_w1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>precin, S0=>open, S1=>wfill_sub_0, + COUT=>co0_2); + + wfill_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_2, S0=>wfill_sub_1, S1=>wfill_sub_2, COUT=>co1_2); + + wfill_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_2, S0=>wfill_sub_3, S1=>wfill_sub_4, COUT=>co2_2); + + wfill_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_2, S0=>wfill_sub_5, S1=>wfill_sub_6, COUT=>co3_2); + + wfill_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_2, S0=>wfill_sub_7, S1=>wfill_sub_8, COUT=>co4_2); + + wfill_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10, + B1=>rcount_w11, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_2, S0=>wfill_sub_9, S1=>wfill_sub_10, + COUT=>co5_2); + + wfill_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12, + B1=>r_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co5_2, S0=>wfill_sub_11, + S1=>wfill_sub_12, COUT=>co6_2); + + wfill_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wptr_13, A1=>wptr_14, B0=>rcount_w14, + B1=>rcount_w15, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_2, S0=>wfill_sub_13, + S1=>wfill_sub_14, COUT=>co7_2); + + wfill_8: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co7_2, S0=>wfill_sub_15, S1=>open, + COUT=>open); + + empty_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + empty_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>wcount_r0, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_3); + + empty_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, + B1=>wcount_r2, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>open, S1=>open, COUT=>co1_3); + + empty_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, + B1=>wcount_r4, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>open, S1=>open, COUT=>co2_3); + + empty_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, + B1=>wcount_r6, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>open, S1=>open, COUT=>co3_3); + + empty_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, + B1=>wcount_r8, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>open, S1=>open, COUT=>co4_3); + + empty_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, + B1=>wcount_r10, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_3, S0=>open, S1=>open, COUT=>co5_3); + + empty_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, + B1=>w_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co5_3, S0=>open, S1=>open, + COUT=>co6_3); + + empty_cmp_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_14, A1=>rcount_15, B0=>wcount_r13, + B1=>wcount_r14, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_3, S0=>open, S1=>open, COUT=>co7_3); + + empty_cmp_8: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co7_3, S0=>open, S1=>open, + COUT=>empty_d_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>empty_d_c, S0=>empty_d, S1=>open, + COUT=>open); + + full_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + full_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, + B1=>rcount_w2, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_1, S0=>open, S1=>open, + COUT=>co0_4); + + full_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, + B1=>rcount_w4, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_4, S0=>open, S1=>open, COUT=>co1_4); + + full_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, + B1=>rcount_w6, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_4, S0=>open, S1=>open, COUT=>co2_4); + + full_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, + B1=>rcount_w8, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_4, S0=>open, S1=>open, COUT=>co3_4); + + full_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, + B1=>rcount_w10, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_4, S0=>open, S1=>open, COUT=>co4_4); + + full_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w11, + B1=>rcount_w12, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_4, S0=>open, S1=>open, COUT=>co5_4); + + full_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_12, A1=>wcount_13, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w14, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_4, S0=>open, S1=>open, COUT=>co6_4); + + full_cmp_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_14, A1=>full_cmp_set, B0=>rcount_w15, + B1=>full_cmp_clr, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co6_4, S0=>open, S1=>open, + COUT=>full_d_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>full_d_c, S0=>full_d, S1=>open, + COUT=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/gbe_trb/ipcores/ecp5/fifo_8kx18x9_wcnt.lpc b/gbe_trb/ipcores/ecp5/fifo_8kx18x9_wcnt.lpc new file mode 100644 index 0000000..aef78ed --- /dev/null +++ b/gbe_trb/ipcores/ecp5/fifo_8kx18x9_wcnt.lpc @@ -0,0 +1,53 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.8 +ModuleName=fifo_8kx18x9_wcnt +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=04/30/2019 +Time=10:17:20 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=8192 +Width=18 +RDepth=16384 +RWidth=9 +regout=0 +ClockEn=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Dynamic - Single Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=508 +PfDeassert=506 +Reset=Async +Reset1=Sync +RDataCount=0 +WDataCount=1 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_8kx18x9_wcnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 8192 -width 18 -rwidth 9 -reset_rel SYNC -pe 0 -pf 0 -fill diff --git a/gbe_trb/ipcores/ecp5/fifo_8kx18x9_wcnt.vhd b/gbe_trb/ipcores/ecp5/fifo_8kx18x9_wcnt.vhd new file mode 100644 index 0000000..4dd9372 --- /dev/null +++ b/gbe_trb/ipcores/ecp5/fifo_8kx18x9_wcnt.vhd @@ -0,0 +1,2772 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144 +-- Module Version: 5.8 +--/home/soft/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n fifo_8kx18x9_wcnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 8192 -width 18 -rwidth 9 -reset_rel SYNC -pe 0 -pf 0 -fill -fdc /home/adrian/git/trb5sc/template/project/mediFifo/fifo_8kx18x9_wcnt/fifo_8kx18x9_wcnt.fdc + +-- Tue Apr 30 10:17:22 2019 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity fifo_8kx18x9_wcnt is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + AmEmptyThresh: in std_logic_vector(13 downto 0); + AmFullThresh: in std_logic_vector(12 downto 0); + Q: out std_logic_vector(8 downto 0); + WCNT: out std_logic_vector(13 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); +end fifo_8kx18x9_wcnt; + +architecture Structure of fifo_8kx18x9_wcnt is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_g2b_xor_cluster_2_1: std_logic; + signal w_g2b_xor_cluster_3: std_logic; + signal w_g2b_xor_cluster_2: std_logic; + signal w_g2b_xor_cluster_1: std_logic; + signal r_g2b_xor_cluster_2_1: std_logic; + signal r_g2b_xor_cluster_3: std_logic; + signal rcount_w0: std_logic; + signal r_g2b_xor_cluster_3_1: std_logic; + signal r_g2b_xor_cluster_2: std_logic; + signal r_g2b_xor_cluster_1: std_logic; + signal rcnt_reg_13_inv: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal w_gdata_6: std_logic; + signal w_gdata_7: std_logic; + signal w_gdata_8: std_logic; + signal w_gdata_9: std_logic; + signal w_gdata_10: std_logic; + signal w_gdata_11: std_logic; + signal w_gdata_12: std_logic; + signal wptr_13: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal r_gdata_6: std_logic; + signal r_gdata_7: std_logic; + signal r_gdata_8: std_logic; + signal r_gdata_9: std_logic; + signal r_gdata_10: std_logic; + signal r_gdata_11: std_logic; + signal r_gdata_12: std_logic; + signal r_gdata_13: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal rptr_14: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal rptr_13: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal w_gcount_7: std_logic; + signal w_gcount_8: std_logic; + signal w_gcount_9: std_logic; + signal w_gcount_10: std_logic; + signal w_gcount_11: std_logic; + signal w_gcount_12: std_logic; + signal w_gcount_13: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal r_gcount_7: std_logic; + signal r_gcount_8: std_logic; + signal r_gcount_9: std_logic; + signal r_gcount_10: std_logic; + signal r_gcount_11: std_logic; + signal r_gcount_12: std_logic; + signal r_gcount_13: std_logic; + signal r_gcount_14: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal w_gcount_r27: std_logic; + signal w_gcount_r7: std_logic; + signal w_gcount_r28: std_logic; + signal w_gcount_r8: std_logic; + signal w_gcount_r29: std_logic; + signal w_gcount_r9: std_logic; + signal w_gcount_r210: std_logic; + signal w_gcount_r10: std_logic; + signal w_gcount_r211: std_logic; + signal w_gcount_r11: std_logic; + signal w_gcount_r212: std_logic; + signal w_gcount_r12: std_logic; + signal w_gcount_r213: std_logic; + signal w_gcount_r13: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal r_gcount_w27: std_logic; + signal r_gcount_w7: std_logic; + signal r_gcount_w28: std_logic; + signal r_gcount_w8: std_logic; + signal r_gcount_w29: std_logic; + signal r_gcount_w9: std_logic; + signal r_gcount_w210: std_logic; + signal r_gcount_w10: std_logic; + signal r_gcount_w211: std_logic; + signal r_gcount_w11: std_logic; + signal r_gcount_w212: std_logic; + signal r_gcount_w12: std_logic; + signal r_gcount_w213: std_logic; + signal r_gcount_w13: std_logic; + signal r_gcount_w214: std_logic; + signal r_gcount_w14: std_logic; + signal rcnt_reg_14: std_logic; + signal empty_i: std_logic; + signal full_i: std_logic; + signal rRst: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal co2: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal co3: std_logic; + signal iwcount_10: std_logic; + signal iwcount_11: std_logic; + signal co4: std_logic; + signal iwcount_12: std_logic; + signal iwcount_13: std_logic; + signal co6: std_logic; + signal co5: std_logic; + signal wcount_13: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal co2_1: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal co3_1: std_logic; + signal ircount_10: std_logic; + signal ircount_11: std_logic; + signal co4_1: std_logic; + signal ircount_12: std_logic; + signal ircount_13: std_logic; + signal co5_1: std_logic; + signal ircount_14: std_logic; + signal co7: std_logic; + signal co6_1: std_logic; + signal rcount_14: std_logic; + signal mdout1_7_0: std_logic; + signal mdout1_6_0: std_logic; + signal mdout1_5_0: std_logic; + signal mdout1_4_0: std_logic; + signal mdout1_3_0: std_logic; + signal mdout1_2_0: std_logic; + signal mdout1_1_0: std_logic; + signal mdout1_0_0: std_logic; + signal mdout1_7_1: std_logic; + signal mdout1_6_1: std_logic; + signal mdout1_5_1: std_logic; + signal mdout1_4_1: std_logic; + signal mdout1_3_1: std_logic; + signal mdout1_2_1: std_logic; + signal mdout1_1_1: std_logic; + signal mdout1_0_1: std_logic; + signal mdout1_7_2: std_logic; + signal mdout1_6_2: std_logic; + signal mdout1_5_2: std_logic; + signal mdout1_4_2: std_logic; + signal mdout1_3_2: std_logic; + signal mdout1_2_2: std_logic; + signal mdout1_1_2: std_logic; + signal mdout1_0_2: std_logic; + signal mdout1_7_3: std_logic; + signal mdout1_6_3: std_logic; + signal mdout1_5_3: std_logic; + signal mdout1_4_3: std_logic; + signal mdout1_3_3: std_logic; + signal mdout1_2_3: std_logic; + signal mdout1_1_3: std_logic; + signal mdout1_0_3: std_logic; + signal mdout1_7_4: std_logic; + signal mdout1_6_4: std_logic; + signal mdout1_5_4: std_logic; + signal mdout1_4_4: std_logic; + signal mdout1_3_4: std_logic; + signal mdout1_2_4: std_logic; + signal mdout1_1_4: std_logic; + signal mdout1_0_4: std_logic; + signal mdout1_7_5: std_logic; + signal mdout1_6_5: std_logic; + signal mdout1_5_5: std_logic; + signal mdout1_4_5: std_logic; + signal mdout1_3_5: std_logic; + signal mdout1_2_5: std_logic; + signal mdout1_1_5: std_logic; + signal mdout1_0_5: std_logic; + signal mdout1_7_6: std_logic; + signal mdout1_6_6: std_logic; + signal mdout1_5_6: std_logic; + signal mdout1_4_6: std_logic; + signal mdout1_3_6: std_logic; + signal mdout1_2_6: std_logic; + signal mdout1_1_6: std_logic; + signal mdout1_0_6: std_logic; + signal mdout1_7_7: std_logic; + signal mdout1_6_7: std_logic; + signal mdout1_5_7: std_logic; + signal mdout1_4_7: std_logic; + signal mdout1_3_7: std_logic; + signal mdout1_2_7: std_logic; + signal mdout1_1_7: std_logic; + signal mdout1_0_7: std_logic; + signal rptr_13_ff: std_logic; + signal rptr_12_ff: std_logic; + signal rptr_11_ff: std_logic; + signal mdout1_7_8: std_logic; + signal mdout1_6_8: std_logic; + signal mdout1_5_8: std_logic; + signal mdout1_4_8: std_logic; + signal mdout1_3_8: std_logic; + signal mdout1_2_8: std_logic; + signal mdout1_1_8: std_logic; + signal mdout1_0_8: std_logic; + signal wcnt_sub_0: std_logic; + signal precin: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; + signal co0_2: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; + signal co1_2: std_logic; + signal wcnt_sub_5: std_logic; + signal wcnt_sub_6: std_logic; + signal co2_2: std_logic; + signal wcnt_sub_7: std_logic; + signal wcnt_sub_8: std_logic; + signal co3_2: std_logic; + signal wcnt_sub_9: std_logic; + signal wcnt_sub_10: std_logic; + signal co4_2: std_logic; + signal wcnt_sub_11: std_logic; + signal wcnt_sub_12: std_logic; + signal co5_2: std_logic; + signal wcnt_sub_13: std_logic; + signal wcnt_sub_msb: std_logic; + signal co6_2: std_logic; + signal rcnt_sub_0: std_logic; + signal precin_1: std_logic; + signal rcnt_sub_1: std_logic; + signal rcnt_sub_2: std_logic; + signal co0_3: std_logic; + signal rcnt_sub_3: std_logic; + signal rcnt_sub_4: std_logic; + signal co1_3: std_logic; + signal rcnt_sub_5: std_logic; + signal rcnt_sub_6: std_logic; + signal co2_3: std_logic; + signal rcnt_sub_7: std_logic; + signal rcnt_sub_8: std_logic; + signal co3_3: std_logic; + signal rcnt_sub_9: std_logic; + signal rcnt_sub_10: std_logic; + signal co4_3: std_logic; + signal rcnt_sub_11: std_logic; + signal rcnt_sub_12: std_logic; + signal co5_3: std_logic; + signal rcnt_sub_13: std_logic; + signal rcnt_sub_14: std_logic; + signal rcnt_sub_msb: std_logic; + signal co6_3: std_logic; + signal co7_1d: std_logic; + signal co7_1: std_logic; + signal wfill_sub_0: std_logic; + signal wptr_0: std_logic; + signal precin_2: std_logic; + signal wfill_sub_1: std_logic; + signal wfill_sub_2: std_logic; + signal wptr_2: std_logic; + signal wptr_1: std_logic; + signal co0_4: std_logic; + signal wfill_sub_3: std_logic; + signal wfill_sub_4: std_logic; + signal wptr_4: std_logic; + signal wptr_3: std_logic; + signal co1_4: std_logic; + signal wfill_sub_5: std_logic; + signal wfill_sub_6: std_logic; + signal wptr_6: std_logic; + signal wptr_5: std_logic; + signal co2_4: std_logic; + signal wfill_sub_7: std_logic; + signal wfill_sub_8: std_logic; + signal wptr_8: std_logic; + signal wptr_7: std_logic; + signal co3_4: std_logic; + signal wfill_sub_9: std_logic; + signal wfill_sub_10: std_logic; + signal wptr_10: std_logic; + signal wptr_9: std_logic; + signal co4_4: std_logic; + signal wfill_sub_11: std_logic; + signal wfill_sub_12: std_logic; + signal wptr_12: std_logic; + signal wptr_11: std_logic; + signal co5_4: std_logic; + signal wfill_sub_13: std_logic; + signal wfill_sub_msb: std_logic; + signal co6_4: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_5: std_logic; + signal wcount_r1: std_logic; + signal wcount_r2: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_5: std_logic; + signal wcount_r3: std_logic; + signal wcount_r4: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_5: std_logic; + signal wcount_r5: std_logic; + signal wcount_r6: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co3_5: std_logic; + signal wcount_r7: std_logic; + signal wcount_r8: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co4_5: std_logic; + signal wcount_r9: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_10: std_logic; + signal rcount_11: std_logic; + signal co5_5: std_logic; + signal wcount_r11: std_logic; + signal wcount_r12: std_logic; + signal rcount_12: std_logic; + signal rcount_13: std_logic; + signal co6_5: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_6: std_logic; + signal rcount_w3: std_logic; + signal rcount_w4: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_6: std_logic; + signal rcount_w5: std_logic; + signal rcount_w6: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_6: std_logic; + signal rcount_w7: std_logic; + signal rcount_w8: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co3_6: std_logic; + signal rcount_w9: std_logic; + signal rcount_w10: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co4_6: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w12: std_logic; + signal wcount_10: std_logic; + signal wcount_11: std_logic; + signal co5_6: std_logic; + signal rcount_w13: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_12: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal rden_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcnt_reg_0: std_logic; + signal rcnt_reg_1: std_logic; + signal co0_7: std_logic; + signal rcnt_reg_2: std_logic; + signal rcnt_reg_3: std_logic; + signal co1_7: std_logic; + signal rcnt_reg_4: std_logic; + signal rcnt_reg_5: std_logic; + signal co2_7: std_logic; + signal rcnt_reg_6: std_logic; + signal rcnt_reg_7: std_logic; + signal co3_7: std_logic; + signal rcnt_reg_8: std_logic; + signal rcnt_reg_9: std_logic; + signal co4_7: std_logic; + signal rcnt_reg_10: std_logic; + signal rcnt_reg_11: std_logic; + signal co5_7: std_logic; + signal rcnt_reg_12: std_logic; + signal rcnt_reg_13: std_logic; + signal co6_6: std_logic; + signal ae_clrsig: std_logic; + signal ae_setsig: std_logic; + signal ae_d: std_logic; + signal ae_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_3: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; + signal co0_8: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; + signal co1_8: std_logic; + signal wcnt_reg_4: std_logic; + signal wcnt_reg_5: std_logic; + signal co2_8: std_logic; + signal wcnt_reg_6: std_logic; + signal wcnt_reg_7: std_logic; + signal co3_8: std_logic; + signal wcnt_reg_8: std_logic; + signal wcnt_reg_9: std_logic; + signal co4_8: std_logic; + signal wcnt_reg_10: std_logic; + signal wcnt_reg_11: std_logic; + signal co5_8: std_logic; + signal wcnt_reg_12: std_logic; + signal wcnt_reg_13: std_logic; + signal af_d: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + signal af_d_c: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_8kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_1_0_6 : label is "fifo_8kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_1_0_6 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_2_0_5 : label is "fifo_8kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_2_0_5 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_3_0_4 : label is "fifo_8kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_3_0_4 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_4_0_3 : label is "fifo_8kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_4_0_3 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_5_0_2 : label is "fifo_8kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_5_0_2 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_6_0_1 : label is "fifo_8kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_6_0_1 : label is ""; + attribute MEM_LPC_FILE of pdp_ram_7_0_0 : label is "fifo_8kx18x9_wcnt.lpc"; + attribute MEM_INIT_FILE of pdp_ram_7_0_0 : label is ""; + attribute GSR of FF_194 : label is "ENABLED"; + attribute GSR of FF_193 : label is "ENABLED"; + attribute GSR of FF_192 : label is "ENABLED"; + attribute GSR of FF_191 : label is "ENABLED"; + attribute GSR of FF_190 : label is "ENABLED"; + attribute GSR of FF_189 : label is "ENABLED"; + attribute GSR of FF_188 : label is "ENABLED"; + attribute GSR of FF_187 : label is "ENABLED"; + attribute GSR of FF_186 : label is "ENABLED"; + attribute GSR of FF_185 : label is "ENABLED"; + attribute GSR of FF_184 : label is "ENABLED"; + attribute GSR of FF_183 : label is "ENABLED"; + attribute GSR of FF_182 : label is "ENABLED"; + attribute GSR of FF_181 : label is "ENABLED"; + attribute GSR of FF_180 : label is "ENABLED"; + attribute GSR of FF_179 : label is "ENABLED"; + attribute GSR of FF_178 : label is "ENABLED"; + attribute GSR of FF_177 : label is "ENABLED"; + attribute GSR of FF_176 : label is "ENABLED"; + attribute GSR of FF_175 : label is "ENABLED"; + attribute GSR of FF_174 : label is "ENABLED"; + attribute GSR of FF_173 : label is "ENABLED"; + attribute GSR of FF_172 : label is "ENABLED"; + attribute GSR of FF_171 : label is "ENABLED"; + attribute GSR of FF_170 : label is "ENABLED"; + attribute GSR of FF_169 : label is "ENABLED"; + attribute GSR of FF_168 : label is "ENABLED"; + attribute GSR of FF_167 : label is "ENABLED"; + attribute GSR of FF_166 : label is "ENABLED"; + attribute GSR of FF_165 : label is "ENABLED"; + attribute GSR of FF_164 : label is "ENABLED"; + attribute GSR of FF_163 : label is "ENABLED"; + attribute GSR of FF_162 : label is "ENABLED"; + attribute GSR of FF_161 : label is "ENABLED"; + attribute GSR of FF_160 : label is "ENABLED"; + attribute GSR of FF_159 : label is "ENABLED"; + attribute GSR of FF_158 : label is "ENABLED"; + attribute GSR of FF_157 : label is "ENABLED"; + attribute GSR of FF_156 : label is "ENABLED"; + attribute GSR of FF_155 : label is "ENABLED"; + attribute GSR of FF_154 : label is "ENABLED"; + attribute GSR of FF_153 : label is "ENABLED"; + attribute GSR of FF_152 : label is "ENABLED"; + attribute GSR of FF_151 : label is "ENABLED"; + attribute GSR of FF_150 : label is "ENABLED"; + attribute GSR of FF_149 : label is "ENABLED"; + attribute GSR of FF_148 : label is "ENABLED"; + attribute GSR of FF_147 : label is "ENABLED"; + attribute GSR of FF_146 : label is "ENABLED"; + attribute GSR of FF_145 : label is "ENABLED"; + attribute GSR of FF_144 : label is "ENABLED"; + attribute GSR of FF_143 : label is "ENABLED"; + attribute GSR of FF_142 : label is "ENABLED"; + attribute GSR of FF_141 : label is "ENABLED"; + attribute GSR of FF_140 : label is "ENABLED"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; + attribute GSR of FF_125 : label is "ENABLED"; + attribute GSR of FF_124 : label is "ENABLED"; + attribute GSR of FF_123 : label is "ENABLED"; + attribute GSR of FF_122 : label is "ENABLED"; + attribute GSR of FF_121 : label is "ENABLED"; + attribute GSR of FF_120 : label is "ENABLED"; + attribute GSR of FF_119 : label is "ENABLED"; + attribute GSR of FF_118 : label is "ENABLED"; + attribute GSR of FF_117 : label is "ENABLED"; + attribute GSR of FF_116 : label is "ENABLED"; + attribute GSR of FF_115 : label is "ENABLED"; + attribute GSR of FF_114 : label is "ENABLED"; + attribute GSR of FF_113 : label is "ENABLED"; + attribute GSR of FF_112 : label is "ENABLED"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t34: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_2: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t33: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_1: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t32: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t31: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t30: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t29: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t28: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t27: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t26: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t25: XOR2 + port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + + XOR2_t24: XOR2 + port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + + XOR2_t23: XOR2 + port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8); + + XOR2_t22: XOR2 + port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9); + + XOR2_t21: XOR2 + port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10); + + XOR2_t20: XOR2 + port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11); + + XOR2_t19: XOR2 + port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12); + + XOR2_t18: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t17: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t16: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t15: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t14: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t13: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + XOR2_t12: XOR2 + port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); + + XOR2_t11: XOR2 + port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7); + + XOR2_t10: XOR2 + port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8); + + XOR2_t9: XOR2 + port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9); + + XOR2_t8: XOR2 + port map (A=>rcount_10, B=>rcount_11, Z=>r_gdata_10); + + XOR2_t7: XOR2 + port map (A=>rcount_11, B=>rcount_12, Z=>r_gdata_11); + + XOR2_t6: XOR2 + port map (A=>rcount_12, B=>rcount_13, Z=>r_gdata_12); + + XOR2_t5: XOR2 + port map (A=>rcount_13, B=>rcount_14, Z=>r_gdata_13); + + LUT4_39: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, + AD1=>w_gcount_r212, AD0=>w_gcount_r213, + DO0=>w_g2b_xor_cluster_0); + + LUT4_38: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, + AD1=>w_gcount_r28, AD0=>w_gcount_r29, + DO0=>w_g2b_xor_cluster_1); + + LUT4_37: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>w_gcount_r25, + DO0=>w_g2b_xor_cluster_2); + + LUT4_36: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r12); + + LUT4_35: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, + AD1=>w_gcount_r213, AD0=>scuba_vlo, DO0=>wcount_r11); + + LUT4_34: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, + AD1=>w_gcount_r211, AD0=>wcount_r12, DO0=>wcount_r9); + + LUT4_33: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, + AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8); + + LUT4_32: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, + AD1=>w_gcount_r29, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r7); + + LUT4_31: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r6); + + LUT4_30: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_29: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_gcount_r24, AD0=>w_gcount_r25, DO0=>wcount_r4); + + LUT4_28: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>scuba_vlo, + DO0=>w_g2b_xor_cluster_2_1); + + LUT4_27: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_26: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_25: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r21, DO0=>wcount_r1); + + LUT4_24: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3); + + LUT4_23: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, + AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3, + DO0=>wcount_r0); + + LUT4_22: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w211, AD2=>r_gcount_w212, + AD1=>r_gcount_w213, AD0=>r_gcount_w214, + DO0=>r_g2b_xor_cluster_0); + + LUT4_21: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28, + AD1=>r_gcount_w29, AD0=>r_gcount_w210, + DO0=>r_g2b_xor_cluster_1); + + LUT4_20: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_gcount_w26, + DO0=>r_g2b_xor_cluster_2); + + LUT4_19: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w213, AD2=>r_gcount_w214, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w13); + + LUT4_18: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w212, AD2=>r_gcount_w213, + AD1=>r_gcount_w214, AD0=>scuba_vlo, DO0=>rcount_w12); + + LUT4_17: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w210, AD2=>r_gcount_w211, + AD1=>r_gcount_w212, AD0=>rcount_w13, DO0=>rcount_w10); + + LUT4_16: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, + AD1=>r_gcount_w211, AD0=>rcount_w12, DO0=>rcount_w9); + + LUT4_15: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, + AD1=>r_gcount_w210, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w8); + + LUT4_14: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w7); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w6); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_gcount_w25, AD0=>r_gcount_w26, DO0=>rcount_w5); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_2_1); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_gcount_w22, DO0=>rcount_w2); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_3); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3, + DO0=>rcount_w1); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, + DO0=>r_g2b_xor_cluster_3_1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, + AD1=>r_g2b_xor_cluster_2, AD0=>r_g2b_xor_cluster_3_1, + DO0=>rcount_w0); + + XOR2_t4: XOR2 + port map (A=>wcount_13, B=>r_gcount_w214, Z=>wcnt_sub_msb); + + XOR2_t3: XOR2 + port map (A=>w_gcount_r213, B=>rcount_14, Z=>rcnt_sub_msb); + + XOR2_t2: XOR2 + port map (A=>wptr_13, B=>r_gcount_w214, Z=>wfill_sub_msb); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r213, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_14, AD2=>rcount_14, AD1=>w_gcount_r213, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_13, AD2=>wcount_13, AD1=>r_gcount_w214, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_13, AD2=>wcount_13, AD1=>r_gcount_w214, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + INV_0: INV + port map (A=>rcnt_reg_13, Z=>rcnt_reg_13_inv); + + AND2_t1: AND2 + port map (A=>rcnt_reg_14, B=>rcnt_reg_13_inv, Z=>ae_clrsig); + + AND2_t0: AND2 + port map (A=>rcnt_reg_14, B=>rcnt_reg_13, Z=>ae_setsig); + + pdp_ram_0_0_7: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>wptr_12, CSA1=>wptr_11, CSA0=>wptr_10, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, + CLKB=>RdClock, WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_0_8, + DOB7=>mdout1_0_7, DOB6=>mdout1_0_6, DOB5=>mdout1_0_5, + DOB4=>mdout1_0_4, DOB3=>mdout1_0_3, DOB2=>mdout1_0_2, + DOB1=>mdout1_0_1, DOB0=>mdout1_0_0); + + pdp_ram_1_0_6: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>wptr_12, CSA1=>wptr_11, CSA0=>wptr_10, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, + CLKB=>RdClock, WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_1_8, + DOB7=>mdout1_1_7, DOB6=>mdout1_1_6, DOB5=>mdout1_1_5, + DOB4=>mdout1_1_4, DOB3=>mdout1_1_3, DOB2=>mdout1_1_2, + DOB1=>mdout1_1_1, DOB0=>mdout1_1_0); + + pdp_ram_2_0_5: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>wptr_12, CSA1=>wptr_11, CSA0=>wptr_10, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, + CLKB=>RdClock, WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_2_8, + DOB7=>mdout1_2_7, DOB6=>mdout1_2_6, DOB5=>mdout1_2_5, + DOB4=>mdout1_2_4, DOB3=>mdout1_2_3, DOB2=>mdout1_2_2, + DOB1=>mdout1_2_1, DOB0=>mdout1_2_0); + + pdp_ram_3_0_4: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>wptr_12, CSA1=>wptr_11, CSA0=>wptr_10, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, + CLKB=>RdClock, WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_3_8, + DOB7=>mdout1_3_7, DOB6=>mdout1_3_6, DOB5=>mdout1_3_5, + DOB4=>mdout1_3_4, DOB3=>mdout1_3_3, DOB2=>mdout1_3_2, + DOB1=>mdout1_3_1, DOB0=>mdout1_3_0); + + pdp_ram_4_0_3: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b100", CSDECODE_A=> "0b100", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>wptr_12, CSA1=>wptr_11, CSA0=>wptr_10, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, + CLKB=>RdClock, WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_4_8, + DOB7=>mdout1_4_7, DOB6=>mdout1_4_6, DOB5=>mdout1_4_5, + DOB4=>mdout1_4_4, DOB3=>mdout1_4_3, DOB2=>mdout1_4_2, + DOB1=>mdout1_4_1, DOB0=>mdout1_4_0); + + pdp_ram_5_0_2: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b101", CSDECODE_A=> "0b101", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>wptr_12, CSA1=>wptr_11, CSA0=>wptr_10, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, + CLKB=>RdClock, WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_5_8, + DOB7=>mdout1_5_7, DOB6=>mdout1_5_6, DOB5=>mdout1_5_5, + DOB4=>mdout1_5_4, DOB3=>mdout1_5_3, DOB2=>mdout1_5_2, + DOB1=>mdout1_5_1, DOB0=>mdout1_5_0); + + pdp_ram_6_0_1: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b110", CSDECODE_A=> "0b110", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>wptr_12, CSA1=>wptr_11, CSA0=>wptr_10, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, + CLKB=>RdClock, WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_6_8, + DOB7=>mdout1_6_7, DOB6=>mdout1_6_6, DOB5=>mdout1_6_5, + DOB4=>mdout1_6_4, DOB3=>mdout1_6_3, DOB2=>mdout1_6_2, + DOB1=>mdout1_6_1, DOB0=>mdout1_6_0); + + pdp_ram_7_0_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + CSDECODE_B=> "0b111", CSDECODE_A=> "0b111", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 18) + port map (DIA17=>Data(17), DIA16=>Data(16), DIA15=>Data(15), + DIA14=>Data(14), DIA13=>Data(13), DIA12=>Data(12), + DIA11=>Data(11), DIA10=>Data(10), DIA9=>Data(9), + DIA8=>Data(8), DIA7=>Data(7), DIA6=>Data(6), DIA5=>Data(5), + DIA4=>Data(4), DIA3=>Data(3), DIA2=>Data(2), DIA1=>Data(1), + DIA0=>Data(0), ADA13=>wptr_9, ADA12=>wptr_8, ADA11=>wptr_7, + ADA10=>wptr_6, ADA9=>wptr_5, ADA8=>wptr_4, ADA7=>wptr_3, + ADA6=>wptr_2, ADA5=>wptr_1, ADA4=>wptr_0, ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>wren_i, OCEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA2=>wptr_12, CSA1=>wptr_11, CSA0=>wptr_10, RSTA=>Reset, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>scuba_vlo, DIB12=>scuba_vlo, + DIB11=>scuba_vlo, DIB10=>scuba_vlo, DIB9=>scuba_vlo, + DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo, + DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo, + DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo, + ADB13=>rptr_10, ADB12=>rptr_9, ADB11=>rptr_8, ADB10=>rptr_7, + ADB9=>rptr_6, ADB8=>rptr_5, ADB7=>rptr_4, ADB6=>rptr_3, + ADB5=>rptr_2, ADB4=>rptr_1, ADB3=>rptr_0, ADB2=>scuba_vlo, + ADB1=>scuba_vlo, ADB0=>scuba_vlo, CEB=>rden_i, OCEB=>rden_i, + CLKB=>RdClock, WEB=>scuba_vlo, CSB2=>rptr_13, CSB1=>rptr_12, + CSB0=>rptr_11, RSTB=>Reset, DOA17=>open, DOA16=>open, + DOA15=>open, DOA14=>open, DOA13=>open, DOA12=>open, + DOA11=>open, DOA10=>open, DOA9=>open, DOA8=>open, DOA7=>open, + DOA6=>open, DOA5=>open, DOA4=>open, DOA3=>open, DOA2=>open, + DOA1=>open, DOA0=>open, DOB17=>open, DOB16=>open, + DOB15=>open, DOB14=>open, DOB13=>open, DOB12=>open, + DOB11=>open, DOB10=>open, DOB9=>open, DOB8=>mdout1_7_8, + DOB7=>mdout1_7_7, DOB6=>mdout1_7_6, DOB5=>mdout1_7_5, + DOB4=>mdout1_7_4, DOB3=>mdout1_7_3, DOB2=>mdout1_7_2, + DOB1=>mdout1_7_1, DOB0=>mdout1_7_0); + + FF_194: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_193: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_192: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_191: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_190: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_189: FD1P3DX + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_188: FD1P3DX + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_187: FD1P3DX + port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_7); + + FF_186: FD1P3DX + port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_8); + + FF_185: FD1P3DX + port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_9); + + FF_184: FD1P3DX + port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_10); + + FF_183: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_11); + + FF_182: FD1P3DX + port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_12); + + FF_181: FD1P3DX + port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_13); + + FF_180: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_179: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_178: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_177: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_176: FD1P3DX + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_175: FD1P3DX + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_174: FD1P3DX + port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_173: FD1P3DX + port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_7); + + FF_172: FD1P3DX + port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_8); + + FF_171: FD1P3DX + port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_9); + + FF_170: FD1P3DX + port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_10); + + FF_169: FD1P3DX + port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_11); + + FF_168: FD1P3DX + port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_12); + + FF_167: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_13); + + FF_166: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_165: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_164: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_163: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_162: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_161: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_160: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_159: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_7); + + FF_158: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_8); + + FF_157: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_9); + + FF_156: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_10); + + FF_155: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_11); + + FF_154: FD1P3DX + port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_12); + + FF_153: FD1P3DX + port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_13); + + FF_152: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_151: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_150: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_149: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_148: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_147: FD1P3DX + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_146: FD1P3DX + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_145: FD1P3DX + port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_7); + + FF_144: FD1P3DX + port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_8); + + FF_143: FD1P3DX + port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_9); + + FF_142: FD1P3DX + port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_10); + + FF_141: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_11); + + FF_140: FD1P3DX + port map (D=>ircount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_12); + + FF_139: FD1P3DX + port map (D=>ircount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_13); + + FF_138: FD1P3DX + port map (D=>ircount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_14); + + FF_137: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_136: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_135: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_134: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_133: FD1P3DX + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_132: FD1P3DX + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_131: FD1P3DX + port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_130: FD1P3DX + port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_7); + + FF_129: FD1P3DX + port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_8); + + FF_128: FD1P3DX + port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_9); + + FF_127: FD1P3DX + port map (D=>r_gdata_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_10); + + FF_126: FD1P3DX + port map (D=>r_gdata_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_11); + + FF_125: FD1P3DX + port map (D=>r_gdata_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_12); + + FF_124: FD1P3DX + port map (D=>r_gdata_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_13); + + FF_123: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_14); + + FF_122: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_121: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_120: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_119: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_118: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_117: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_116: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_115: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_7); + + FF_114: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_8); + + FF_113: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_9); + + FF_112: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_10); + + FF_111: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_11); + + FF_110: FD1P3DX + port map (D=>rcount_12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_12); + + FF_109: FD1P3DX + port map (D=>rcount_13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_13); + + FF_108: FD1P3DX + port map (D=>rcount_14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_14); + + FF_107: FD1P3DX + port map (D=>rptr_11, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_11_ff); + + FF_106: FD1P3DX + port map (D=>rptr_12, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_12_ff); + + FF_105: FD1P3DX + port map (D=>rptr_13, SP=>rden_i, CK=>RdClock, CD=>scuba_vlo, + Q=>rptr_13_ff); + + FF_104: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_103: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_102: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_101: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_100: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_99: FD1S3DX + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_98: FD1S3DX + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_97: FD1S3DX + port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + + FF_96: FD1S3DX + port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + + FF_95: FD1S3DX + port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9); + + FF_94: FD1S3DX + port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r10); + + FF_93: FD1S3DX + port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r11); + + FF_92: FD1S3DX + port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r12); + + FF_91: FD1S3DX + port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r13); + + FF_90: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_89: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_88: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_87: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_86: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_85: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_84: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_83: FD1S3DX + port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7); + + FF_82: FD1S3DX + port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8); + + FF_81: FD1S3DX + port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9); + + FF_80: FD1S3DX + port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10); + + FF_79: FD1S3DX + port map (D=>r_gcount_11, CK=>WrClock, CD=>rRst, Q=>r_gcount_w11); + + FF_78: FD1S3DX + port map (D=>r_gcount_12, CK=>WrClock, CD=>rRst, Q=>r_gcount_w12); + + FF_77: FD1S3DX + port map (D=>r_gcount_13, CK=>WrClock, CD=>rRst, Q=>r_gcount_w13); + + FF_76: FD1S3DX + port map (D=>r_gcount_14, CK=>WrClock, CD=>rRst, Q=>r_gcount_w14); + + FF_75: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_74: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_73: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_72: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_71: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_70: FD1S3DX + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_69: FD1S3DX + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_68: FD1S3DX + port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r27); + + FF_67: FD1S3DX + port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r28); + + FF_66: FD1S3DX + port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r29); + + FF_65: FD1S3DX + port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r210); + + FF_64: FD1S3DX + port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r211); + + FF_63: FD1S3DX + port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r212); + + FF_62: FD1S3DX + port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r213); + + FF_61: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_60: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_59: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_58: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_57: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_56: FD1S3DX + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_55: FD1S3DX + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_54: FD1S3DX + port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); + + FF_53: FD1S3DX + port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28); + + FF_52: FD1S3DX + port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29); + + FF_51: FD1S3DX + port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w210); + + FF_50: FD1S3DX + port map (D=>r_gcount_w11, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w211); + + FF_49: FD1S3DX + port map (D=>r_gcount_w12, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w212); + + FF_48: FD1S3DX + port map (D=>r_gcount_w13, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w213); + + FF_47: FD1S3DX + port map (D=>r_gcount_w14, CK=>WrClock, CD=>rRst, + Q=>r_gcount_w214); + + FF_46: FD1S3DX + port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); + + FF_45: FD1S3DX + port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); + + FF_44: FD1S3DX + port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); + + FF_43: FD1S3DX + port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); + + FF_42: FD1S3DX + port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); + + FF_41: FD1S3DX + port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); + + FF_40: FD1S3DX + port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); + + FF_39: FD1S3DX + port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); + + FF_38: FD1S3DX + port map (D=>wcnt_sub_8, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_8); + + FF_37: FD1S3DX + port map (D=>wcnt_sub_9, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_9); + + FF_36: FD1S3DX + port map (D=>wcnt_sub_10, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_10); + + FF_35: FD1S3DX + port map (D=>wcnt_sub_11, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_11); + + FF_34: FD1S3DX + port map (D=>wcnt_sub_12, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_12); + + FF_33: FD1S3DX + port map (D=>wcnt_sub_13, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_13); + + FF_32: FD1S3DX + port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); + + FF_31: FD1S3DX + port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); + + FF_30: FD1S3DX + port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); + + FF_29: FD1S3DX + port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); + + FF_28: FD1S3DX + port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); + + FF_27: FD1S3DX + port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); + + FF_26: FD1S3DX + port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); + + FF_25: FD1S3DX + port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); + + FF_24: FD1S3DX + port map (D=>rcnt_sub_8, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_8); + + FF_23: FD1S3DX + port map (D=>rcnt_sub_9, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_9); + + FF_22: FD1S3DX + port map (D=>rcnt_sub_10, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_10); + + FF_21: FD1S3DX + port map (D=>rcnt_sub_11, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_11); + + FF_20: FD1S3DX + port map (D=>rcnt_sub_12, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_12); + + FF_19: FD1S3DX + port map (D=>rcnt_sub_13, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_13); + + FF_18: FD1S3DX + port map (D=>rcnt_sub_14, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_14); + + FF_17: FD1S3DX + port map (D=>wfill_sub_0, CK=>WrClock, CD=>Reset, Q=>WCNT(0)); + + FF_16: FD1S3DX + port map (D=>wfill_sub_1, CK=>WrClock, CD=>Reset, Q=>WCNT(1)); + + FF_15: FD1S3DX + port map (D=>wfill_sub_2, CK=>WrClock, CD=>Reset, Q=>WCNT(2)); + + FF_14: FD1S3DX + port map (D=>wfill_sub_3, CK=>WrClock, CD=>Reset, Q=>WCNT(3)); + + FF_13: FD1S3DX + port map (D=>wfill_sub_4, CK=>WrClock, CD=>Reset, Q=>WCNT(4)); + + FF_12: FD1S3DX + port map (D=>wfill_sub_5, CK=>WrClock, CD=>Reset, Q=>WCNT(5)); + + FF_11: FD1S3DX + port map (D=>wfill_sub_6, CK=>WrClock, CD=>Reset, Q=>WCNT(6)); + + FF_10: FD1S3DX + port map (D=>wfill_sub_7, CK=>WrClock, CD=>Reset, Q=>WCNT(7)); + + FF_9: FD1S3DX + port map (D=>wfill_sub_8, CK=>WrClock, CD=>Reset, Q=>WCNT(8)); + + FF_8: FD1S3DX + port map (D=>wfill_sub_9, CK=>WrClock, CD=>Reset, Q=>WCNT(9)); + + FF_7: FD1S3DX + port map (D=>wfill_sub_10, CK=>WrClock, CD=>Reset, Q=>WCNT(10)); + + FF_6: FD1S3DX + port map (D=>wfill_sub_11, CK=>WrClock, CD=>Reset, Q=>WCNT(11)); + + FF_5: FD1S3DX + port map (D=>wfill_sub_12, CK=>WrClock, CD=>Reset, Q=>WCNT(12)); + + FF_4: FD1S3DX + port map (D=>wfill_sub_13, CK=>WrClock, CD=>Reset, Q=>WCNT(13)); + + FF_3: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_2: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_1: FD1S3BX + port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + + w_gctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>w_gctr_ci); + + w_gctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>w_gctr_ci, S0=>iwcount_0, S1=>iwcount_1, + COUT=>co0); + + w_gctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0, S0=>iwcount_2, S1=>iwcount_3, + COUT=>co1); + + w_gctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1, S0=>iwcount_4, S1=>iwcount_5, + COUT=>co2); + + w_gctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2, S0=>iwcount_6, S1=>iwcount_7, + COUT=>co3); + + w_gctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3, S0=>iwcount_8, S1=>iwcount_9, + COUT=>co4); + + w_gctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_10, A1=>wcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4, S0=>iwcount_10, S1=>iwcount_11, + COUT=>co5); + + w_gctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>wcount_12, A1=>wcount_13, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5, S0=>iwcount_12, S1=>iwcount_13, + COUT=>co6); + + r_gctr_cia: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>r_gctr_ci); + + r_gctr_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>r_gctr_ci, S0=>ircount_0, S1=>ircount_1, + COUT=>co0_1); + + r_gctr_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_1, S0=>ircount_2, S1=>ircount_3, + COUT=>co1_1); + + r_gctr_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_1, S0=>ircount_4, S1=>ircount_5, + COUT=>co2_1); + + r_gctr_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_1, S0=>ircount_6, S1=>ircount_7, + COUT=>co3_1); + + r_gctr_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_1, S0=>ircount_8, S1=>ircount_9, + COUT=>co4_1); + + r_gctr_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_10, A1=>rcount_11, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_1, S0=>ircount_10, S1=>ircount_11, + COUT=>co5_1); + + r_gctr_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_12, A1=>rcount_13, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_1, S0=>ircount_12, S1=>ircount_13, + COUT=>co6_1); + + r_gctr_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>rcount_14, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_1, S0=>ircount_14, S1=>open, + COUT=>co7); + + mux_8: MUX81 + port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, + D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, + D6=>mdout1_6_0, D7=>mdout1_7_0, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(0)); + + mux_7: MUX81 + port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, + D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, + D6=>mdout1_6_1, D7=>mdout1_7_1, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(1)); + + mux_6: MUX81 + port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, + D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, + D6=>mdout1_6_2, D7=>mdout1_7_2, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(2)); + + mux_5: MUX81 + port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, + D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, + D6=>mdout1_6_3, D7=>mdout1_7_3, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(3)); + + mux_4: MUX81 + port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, + D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, + D6=>mdout1_6_4, D7=>mdout1_7_4, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(4)); + + mux_3: MUX81 + port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, + D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, + D6=>mdout1_6_5, D7=>mdout1_7_5, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(5)); + + mux_2: MUX81 + port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, + D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, + D6=>mdout1_6_6, D7=>mdout1_7_6, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(6)); + + mux_1: MUX81 + port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, + D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, + D6=>mdout1_6_7, D7=>mdout1_7_7, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(7)); + + mux_0: MUX81 + port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, + D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, + D6=>mdout1_6_8, D7=>mdout1_7_8, SD1=>rptr_11_ff, + SD2=>rptr_12_ff, SD3=>rptr_13_ff, Z=>Q(8)); + + precin_inst436: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); + + wcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo, + B1=>rcount_w1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>precin, S0=>open, S1=>wcnt_sub_0, + COUT=>co0_2); + + wcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w2, + B1=>rcount_w3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_2, S0=>wcnt_sub_1, S1=>wcnt_sub_2, + COUT=>co1_2); + + wcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w4, + B1=>rcount_w5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_2, S0=>wcnt_sub_3, S1=>wcnt_sub_4, + COUT=>co2_2); + + wcnt_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w6, + B1=>rcount_w7, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_2, S0=>wcnt_sub_5, S1=>wcnt_sub_6, + COUT=>co3_2); + + wcnt_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_w8, + B1=>rcount_w9, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_2, S0=>wcnt_sub_7, S1=>wcnt_sub_8, + COUT=>co4_2); + + wcnt_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_w10, + B1=>r_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_2, S0=>wcnt_sub_9, + S1=>wcnt_sub_10, COUT=>co5_2); + + wcnt_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_w12, + B1=>rcount_w13, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_2, S0=>wcnt_sub_11, S1=>wcnt_sub_12, + COUT=>co6_2); + + wcnt_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_2, S0=>wcnt_sub_13, S1=>open, + COUT=>open); + + precin_inst474: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin_1); + + rcnt_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vhi, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>rcount_0, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>precin_1, S0=>open, S1=>rcnt_sub_0, + COUT=>co0_3); + + rcnt_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_r0, A1=>wcount_r1, B0=>rcount_1, + B1=>rcount_2, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_3, S0=>rcnt_sub_1, S1=>rcnt_sub_2, + COUT=>co1_3); + + rcnt_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rcount_3, + B1=>rcount_4, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_3, S0=>rcnt_sub_3, S1=>rcnt_sub_4, + COUT=>co2_3); + + rcnt_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rcount_5, + B1=>rcount_6, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_3, S0=>rcnt_sub_5, S1=>rcnt_sub_6, + COUT=>co3_3); + + rcnt_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rcount_7, + B1=>rcount_8, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_3, S0=>rcnt_sub_7, S1=>rcnt_sub_8, + COUT=>co4_3); + + rcnt_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rcount_9, + B1=>rcount_10, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_3, S0=>rcnt_sub_9, S1=>rcnt_sub_10, + COUT=>co5_3); + + rcnt_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r11, B0=>rcount_11, + B1=>rcount_12, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_3, S0=>rcnt_sub_11, S1=>rcnt_sub_12, + COUT=>co6_3); + + rcnt_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_r12, A1=>rcnt_sub_msb, B0=>rcount_13, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_3, S0=>rcnt_sub_13, S1=>rcnt_sub_14, + COUT=>co7_1); + + rcntd: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co7_1, S0=>co7_1d, S1=>open, COUT=>open); + + precin_inst514: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"0000", + INIT0=> X"0000") + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin_2); + + wfill_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>scuba_vhi, A1=>wptr_0, B0=>scuba_vlo, + B1=>rcount_w1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>precin_2, S0=>open, S1=>wfill_sub_0, + COUT=>co0_4); + + wfill_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wptr_1, A1=>wptr_2, B0=>rcount_w2, B1=>rcount_w3, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co0_4, S0=>wfill_sub_1, S1=>wfill_sub_2, COUT=>co1_4); + + wfill_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wptr_3, A1=>wptr_4, B0=>rcount_w4, B1=>rcount_w5, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co1_4, S0=>wfill_sub_3, S1=>wfill_sub_4, COUT=>co2_4); + + wfill_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wptr_5, A1=>wptr_6, B0=>rcount_w6, B1=>rcount_w7, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co2_4, S0=>wfill_sub_5, S1=>wfill_sub_6, COUT=>co3_4); + + wfill_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wptr_7, A1=>wptr_8, B0=>rcount_w8, B1=>rcount_w9, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>co3_4, S0=>wfill_sub_7, S1=>wfill_sub_8, COUT=>co4_4); + + wfill_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wptr_9, A1=>wptr_10, B0=>rcount_w10, + B1=>r_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_4, S0=>wfill_sub_9, + S1=>wfill_sub_10, COUT=>co5_4); + + wfill_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wptr_11, A1=>wptr_12, B0=>rcount_w12, + B1=>rcount_w13, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_4, S0=>wfill_sub_11, + S1=>wfill_sub_12, COUT=>co6_4); + + wfill_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_4, S0=>wfill_sub_13, S1=>open, + COUT=>open); + + empty_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci); + + empty_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_0, A1=>rcount_1, B0=>scuba_vlo, + B1=>wcount_r0, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci, S0=>open, S1=>open, COUT=>co0_5); + + empty_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r1, + B1=>wcount_r2, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_5, S0=>open, S1=>open, COUT=>co1_5); + + empty_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r3, + B1=>wcount_r4, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_5, S0=>open, S1=>open, COUT=>co2_5); + + empty_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r5, + B1=>wcount_r6, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_5, S0=>open, S1=>open, COUT=>co3_5); + + empty_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r7, + B1=>wcount_r8, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_5, S0=>open, S1=>open, COUT=>co4_5); + + empty_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_10, A1=>rcount_11, B0=>wcount_r9, + B1=>w_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_5, S0=>open, S1=>open, + COUT=>co5_5); + + empty_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>rcount_12, A1=>rcount_13, B0=>wcount_r11, + B1=>wcount_r12, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_5, S0=>open, S1=>open, COUT=>co6_5); + + empty_cmp_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_5, S0=>open, S1=>open, + COUT=>empty_d_c); + + a0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>empty_d_c, S0=>empty_d, S1=>open, + COUT=>open); + + full_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_1); + + full_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w1, + B1=>rcount_w2, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>cmp_ci_1, S0=>open, S1=>open, + COUT=>co0_6); + + full_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w3, + B1=>rcount_w4, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_6, S0=>open, S1=>open, COUT=>co1_6); + + full_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w5, + B1=>rcount_w6, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_6, S0=>open, S1=>open, COUT=>co2_6); + + full_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w7, + B1=>rcount_w8, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_6, S0=>open, S1=>open, COUT=>co3_6); + + full_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w9, + B1=>rcount_w10, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co3_6, S0=>open, S1=>open, COUT=>co4_6); + + full_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_10, A1=>wcount_11, B0=>r_g2b_xor_cluster_0, + B1=>rcount_w12, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co4_6, S0=>open, S1=>open, COUT=>co5_6); + + full_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcount_12, A1=>full_cmp_set, B0=>rcount_w13, + B1=>full_cmp_clr, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co5_6, S0=>open, S1=>open, + COUT=>full_d_c); + + a1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>full_d_c, S0=>full_d, S1=>open, + COUT=>open); + + ae_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); + + ae_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), + B0=>rcnt_reg_0, B1=>rcnt_reg_1, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, + S1=>open, COUT=>co0_7); + + ae_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), + B0=>rcnt_reg_2, B1=>rcnt_reg_3, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_7, S0=>open, S1=>open, + COUT=>co1_7); + + ae_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), + B0=>rcnt_reg_4, B1=>rcnt_reg_5, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_7, S0=>open, S1=>open, + COUT=>co2_7); + + ae_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7), + B0=>rcnt_reg_6, B1=>rcnt_reg_7, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_7, S0=>open, S1=>open, + COUT=>co3_7); + + ae_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9), + B0=>rcnt_reg_8, B1=>rcnt_reg_9, C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_7, S0=>open, S1=>open, + COUT=>co4_7); + + ae_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11), + B0=>rcnt_reg_10, B1=>rcnt_reg_11, C0=>scuba_vhi, + C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_7, + S0=>open, S1=>open, COUT=>co5_7); + + ae_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>AmEmptyThresh(12), A1=>AmEmptyThresh(13), + B0=>rcnt_reg_12, B1=>rcnt_reg_13, C0=>scuba_vhi, + C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co5_7, + S0=>open, S1=>open, COUT=>co6_6); + + ae_cmp_7: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co6_6, S0=>open, S1=>open, COUT=>ae_d_c); + + a2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>ae_d_c, S0=>ae_d, S1=>open, COUT=>open); + + af_d_cmp_ci_a: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, + CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_3); + + af_d_cmp_0: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_3, S0=>open, + S1=>open, COUT=>co0_8); + + af_d_cmp_1: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_8, S0=>open, S1=>open, + COUT=>co1_8); + + af_d_cmp_2: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_8, S0=>open, S1=>open, + COUT=>co2_8); + + af_d_cmp_3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co2_8, S0=>open, S1=>open, + COUT=>co3_8); + + af_d_cmp_4: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>AmFullThresh(9), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co3_8, S0=>open, S1=>open, + COUT=>co4_8); + + af_d_cmp_5: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), + B1=>AmFullThresh(11), C0=>scuba_vhi, C1=>scuba_vhi, + D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co4_8, S0=>open, S1=>open, + COUT=>co5_8); + + af_d_cmp_6: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", + INIT0=> X"99AA") + port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co5_8, S0=>open, S1=>open, COUT=>af_d_c); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a3: CCU2C + generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", + INIT0=> X"66AA") + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>af_d_c, S0=>af_d, S1=>open, COUT=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; diff --git a/gbe_trb/ipcores/ecp5/ip_mem.lpc b/gbe_trb/ipcores/ecp5/ip_mem.lpc new file mode 100644 index 0000000..dabe2e3 --- /dev/null +++ b/gbe_trb/ipcores/ecp5/ip_mem.lpc @@ -0,0 +1,56 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_DP_TRUE +CoreRevision=7.5 +ModuleName=ip_mem +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=04/24/2019 +Time=11:30:09 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +RAddress=256 +RData=32 +WAddress=256 +WData=32 +ROutputEn=0 +RClockEn=0 +WOutputEn=1 +WClockEn=0 +enByte=0 +ByteSize=9 +Optimization=Speed +Reset=Sync +Reset1=Sync +Init=mem +MemFile=/home/adrian/git/trbnet/gbe2_ecp3/ipcores/ip_mem.mem +MemFormat=orca +EnECC=0 +Pipeline=0 +WriteA=Normal +WriteB=Normal +init_data=0 + +[FilesGenerated] +/home/adrian/git/trbnet/gbe2_ecp3/ipcores/ip_mem.mem=mem + +[Command] +cmd_line= -w -n ip_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ramdp -device LFE5UM-85F -aaddr_width 8 -widtha 32 -baddr_width 8 -widthb 32 -anum_words 256 -bnum_words 256 -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile /home/adrian/git/trbnet/gbe2_ecp3/ipcores/ip_mem.mem -memformat orca -writemodeA NORMAL -writemodeB NORMAL diff --git a/gbe_trb/ipcores/ecp5/ip_mem.vhd b/gbe_trb/ipcores/ecp5/ip_mem.vhd new file mode 100644 index 0000000..3daf007 --- /dev/null +++ b/gbe_trb/ipcores/ecp5/ip_mem.vhd @@ -0,0 +1,266 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144 +-- Module Version: 7.5 +--/home/soft/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n ip_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type bram -wp 11 -rp 1010 -data_width 32 -rdata_width 32 -num_rows 256 -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile /home/adrian/git/trbnet/gbe2_ecp3/ipcores/ip_mem.mem -memformat orca -writemodeA NORMAL -writemodeB NORMAL -fdc /home/adrian/git/trb5sc/template/project/mediFifo/ip_mem/ip_mem.fdc + +-- Wed Apr 24 11:30:11 2019 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity ip_mem is + port ( + DataInA: in std_logic_vector(31 downto 0); + DataInB: in std_logic_vector(31 downto 0); + AddressA: in std_logic_vector(7 downto 0); + AddressB: in std_logic_vector(7 downto 0); + ClockA: in std_logic; + ClockB: in std_logic; + ClockEnA: in std_logic; + ClockEnB: in std_logic; + WrA: in std_logic; + WrB: in std_logic; + ResetA: in std_logic; + ResetB: in std_logic; + QA: out std_logic_vector(31 downto 0); + QB: out std_logic_vector(31 downto 0)); +end ip_mem; + +architecture Structure of ip_mem is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute MEM_LPC_FILE of ip_mem_0_0_1 : label is "ip_mem.lpc"; + attribute MEM_INIT_FILE of ip_mem_0_0_1 : label is "ip_mem.mem"; + attribute MEM_LPC_FILE of ip_mem_0_1_0 : label is "ip_mem.lpc"; + attribute MEM_INIT_FILE of ip_mem_0_1_0 : label is "ip_mem.mem"; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + ip_mem_0_0_1: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000005780000000000000000000000000000000000000000", + INITVAL_03=> "0x00000000000000000000000000000000000005780C35000008000133DC030C353000020001B397E9", + INITVAL_02=> "0x00000000000000000000000000000000000005780C35000007000133DC020C352000020001B397E9", + INITVAL_01=> "0x00000000000000000000000000000000000005780C35000006000133DC010C351000020001B397E9", + INITVAL_00=> "0x00000000000000000000000000000000000005780C35000005000133DC000C350000020001B397E9", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + port map (DIA17=>DataInA(17), DIA16=>DataInA(16), + DIA15=>DataInA(15), DIA14=>DataInA(14), DIA13=>DataInA(13), + DIA12=>DataInA(12), DIA11=>DataInA(11), DIA10=>DataInA(10), + DIA9=>DataInA(9), DIA8=>DataInA(8), DIA7=>DataInA(7), + DIA6=>DataInA(6), DIA5=>DataInA(5), DIA4=>DataInA(4), + DIA3=>DataInA(3), DIA2=>DataInA(2), DIA1=>DataInA(1), + DIA0=>DataInA(0), ADA13=>scuba_vlo, ADA12=>scuba_vlo, + ADA11=>AddressA(7), ADA10=>AddressA(6), ADA9=>AddressA(5), + ADA8=>AddressA(4), ADA7=>AddressA(3), ADA6=>AddressA(2), + ADA5=>AddressA(1), ADA4=>AddressA(0), ADA3=>scuba_vlo, + ADA2=>scuba_vlo, ADA1=>scuba_vhi, ADA0=>scuba_vhi, + CEA=>ClockEnA, OCEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, + CSA2=>scuba_vlo, CSA1=>scuba_vlo, CSA0=>scuba_vlo, + RSTA=>ResetA, DIB17=>DataInB(17), DIB16=>DataInB(16), + DIB15=>DataInB(15), DIB14=>DataInB(14), DIB13=>DataInB(13), + DIB12=>DataInB(12), DIB11=>DataInB(11), DIB10=>DataInB(10), + DIB9=>DataInB(9), DIB8=>DataInB(8), DIB7=>DataInB(7), + DIB6=>DataInB(6), DIB5=>DataInB(5), DIB4=>DataInB(4), + DIB3=>DataInB(3), DIB2=>DataInB(2), DIB1=>DataInB(1), + DIB0=>DataInB(0), ADB13=>scuba_vlo, ADB12=>scuba_vlo, + ADB11=>AddressB(7), ADB10=>AddressB(6), ADB9=>AddressB(5), + ADB8=>AddressB(4), ADB7=>AddressB(3), ADB6=>AddressB(2), + ADB5=>AddressB(1), ADB4=>AddressB(0), ADB3=>scuba_vlo, + ADB2=>scuba_vlo, ADB1=>scuba_vhi, ADB0=>scuba_vhi, + CEB=>ClockEnB, OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, + CSB2=>scuba_vlo, CSB1=>scuba_vlo, CSB0=>scuba_vlo, + RSTB=>ResetB, DOA17=>QA(17), DOA16=>QA(16), DOA15=>QA(15), + DOA14=>QA(14), DOA13=>QA(13), DOA12=>QA(12), DOA11=>QA(11), + DOA10=>QA(10), DOA9=>QA(9), DOA8=>QA(8), DOA7=>QA(7), + DOA6=>QA(6), DOA5=>QA(5), DOA4=>QA(4), DOA3=>QA(3), + DOA2=>QA(2), DOA1=>QA(1), DOA0=>QA(0), DOB17=>QB(17), + DOB16=>QB(16), DOB15=>QB(15), DOB14=>QB(14), DOB13=>QB(13), + DOB12=>QB(12), DOB11=>QB(11), DOB10=>QB(10), DOB9=>QB(9), + DOB8=>QB(8), DOB7=>QB(7), DOB6=>QB(6), DOB5=>QB(5), + DOB4=>QB(4), DOB3=>QB(3), DOB2=>QB(2), DOB1=>QB(1), + DOB0=>QB(0)); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + ip_mem_0_1_0: DP16KD + generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", + INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_03=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + INITVAL_02=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + INITVAL_01=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + INITVAL_00=> "0x0000000000000000000000000000000000000000000000302A000000008E000000302A0000000850", + CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + port map (DIA17=>scuba_vlo, DIA16=>scuba_vlo, DIA15=>scuba_vlo, + DIA14=>scuba_vlo, DIA13=>DataInA(31), DIA12=>DataInA(30), + DIA11=>DataInA(29), DIA10=>DataInA(28), DIA9=>DataInA(27), + DIA8=>DataInA(26), DIA7=>DataInA(25), DIA6=>DataInA(24), + DIA5=>DataInA(23), DIA4=>DataInA(22), DIA3=>DataInA(21), + DIA2=>DataInA(20), DIA1=>DataInA(19), DIA0=>DataInA(18), + ADA13=>scuba_vlo, ADA12=>scuba_vlo, ADA11=>AddressA(7), + ADA10=>AddressA(6), ADA9=>AddressA(5), ADA8=>AddressA(4), + ADA7=>AddressA(3), ADA6=>AddressA(2), ADA5=>AddressA(1), + ADA4=>AddressA(0), ADA3=>scuba_vlo, ADA2=>scuba_vlo, + ADA1=>scuba_vhi, ADA0=>scuba_vhi, CEA=>ClockEnA, + OCEA=>ClockEnA, CLKA=>ClockA, WEA=>WrA, CSA2=>scuba_vlo, + CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>ResetA, + DIB17=>scuba_vlo, DIB16=>scuba_vlo, DIB15=>scuba_vlo, + DIB14=>scuba_vlo, DIB13=>DataInB(31), DIB12=>DataInB(30), + DIB11=>DataInB(29), DIB10=>DataInB(28), DIB9=>DataInB(27), + DIB8=>DataInB(26), DIB7=>DataInB(25), DIB6=>DataInB(24), + DIB5=>DataInB(23), DIB4=>DataInB(22), DIB3=>DataInB(21), + DIB2=>DataInB(20), DIB1=>DataInB(19), DIB0=>DataInB(18), + ADB13=>scuba_vlo, ADB12=>scuba_vlo, ADB11=>AddressB(7), + ADB10=>AddressB(6), ADB9=>AddressB(5), ADB8=>AddressB(4), + ADB7=>AddressB(3), ADB6=>AddressB(2), ADB5=>AddressB(1), + ADB4=>AddressB(0), ADB3=>scuba_vlo, ADB2=>scuba_vlo, + ADB1=>scuba_vhi, ADB0=>scuba_vhi, CEB=>ClockEnB, + OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, CSB2=>scuba_vlo, + CSB1=>scuba_vlo, CSB0=>scuba_vlo, RSTB=>ResetB, DOA17=>open, + DOA16=>open, DOA15=>open, DOA14=>open, DOA13=>QA(31), + DOA12=>QA(30), DOA11=>QA(29), DOA10=>QA(28), DOA9=>QA(27), + DOA8=>QA(26), DOA7=>QA(25), DOA6=>QA(24), DOA5=>QA(23), + DOA4=>QA(22), DOA3=>QA(21), DOA2=>QA(20), DOA1=>QA(19), + DOA0=>QA(18), DOB17=>open, DOB16=>open, DOB15=>open, + DOB14=>open, DOB13=>QB(31), DOB12=>QB(30), DOB11=>QB(29), + DOB10=>QB(28), DOB9=>QB(27), DOB8=>QB(26), DOB7=>QB(25), + DOB6=>QB(24), DOB5=>QB(23), DOB4=>QB(22), DOB3=>QB(21), + DOB2=>QB(20), DOB1=>QB(19), DOB0=>QB(18)); + +end Structure; diff --git a/gbe_trb/media/ecp5/pcs_sync_reset.vhd b/gbe_trb/media/ecp5/pcs_sync_reset.vhd new file mode 100644 index 0000000..b0df8f3 --- /dev/null +++ b/gbe_trb/media/ecp5/pcs_sync_reset.vhd @@ -0,0 +1,211 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.med_sync_define.all; + +entity pcs_sync_reset is + generic( + IS_SYNC_SLAVE : integer := 1; + IS_TX_RESET : integer := 1 + ); + port( + CLK_SYS : in std_logic; + CLK_RXI : in std_logic; + CLK_REF : in std_logic; + RESET : in std_logic; + CLEAR : in std_logic; + + SFP_LOS : in std_logic; + TX_LOL : in std_logic; + RX_CDR_LOL : in std_logic; + RX_LOS : in std_logic; + WA_POSITION : in std_logic_vector(3 downto 0); + + RX_SERDES_RST : out std_logic; + RX_PCS_RST : out std_logic; + QUAD_RST : out std_logic; + TX_PCS_RST : out std_logic; + + SERDES_RX_READY_IN : in std_logic := '1'; + SERDES_TX_READY_IN : in std_logic := '1'; + + STAT_TX_CONTROL : out std_logic_vector(31 downto 0); + STAT_RX_CONTROL : out std_logic_vector(31 downto 0); + DEBUG_TX_CONTROL : out std_logic_vector(31 downto 0); + DEBUG_RX_CONTROL : out std_logic_vector(31 downto 0); + STAT_RESET : out std_logic_vector(31 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + +architecture pcs_sync_reset_arch of pcs_sync_reset is + +signal rx_fsm_state : std_logic_vector(3 downto 0); +signal tx_fsm_state : std_logic_vector(3 downto 0); +signal wa_position_rx : std_logic_vector(3 downto 0); +signal start_timer : unsigned(21 downto 0) := (others => '0'); + +signal request_retr_i : std_logic; +signal start_retr_i : std_logic; +signal request_retr_position_i : std_logic_vector(7 downto 0); +signal start_retr_position_i : std_logic_vector(7 downto 0); +signal rx_dlm_i : std_logic; + +signal timer : unsigned(20 downto 0); +signal sd_los_i : std_logic; + +signal rx_allow : std_logic; +signal tx_allow : std_logic; +signal got_link_ready_i : std_logic; +signal make_link_reset_i : std_logic; +signal send_link_reset_i : std_logic; +signal make_link_reset_real_i : std_logic := '0'; +signal make_link_reset_sys_i : std_logic := '0'; +signal send_link_reset_real_i : std_logic := '0'; +signal send_link_reset_sys_i : std_logic := '0'; + +signal reset_i, rst_n, rst_n_tx : std_logic; +signal finished_reset_rx, finished_reset_rx_q : std_logic; +signal finished_reset_tx, finished_reset_tx_q : std_logic; + +begin + +rst_n_tx <= not (CLEAR or sd_los_i or make_link_reset_real_i or RESET) when (IS_SYNC_SLAVE = 1 and IS_TX_RESET = 1) + else not (CLEAR or make_link_reset_real_i or RESET); + + + +rst_n <= not (CLEAR or sd_los_i or make_link_reset_real_i or RESET); +reset_i <= (RESET or sd_los_i or make_link_reset_real_i); + + + + +------------------------------------------------- +-- Reset FSM & Link states +------------------------------------------------- +THE_RX_FSM : rx_reset_fsm + port map( + RST_N => rst_n, + RX_REFCLK => CLK_REF, + TX_PLL_LOL_QD_S => TX_LOL, + RX_SERDES_RST_CH_C => RX_SERDES_RST, + RX_CDR_LOL_CH_S => RX_CDR_LOL, + RX_LOS_LOW_CH_S => RX_LOS, + RX_PCS_RST_CH_C => RX_PCS_RST, + WA_POSITION => wa_position_rx, + NORMAL_OPERATION_OUT => finished_reset_rx, + STATE_OUT => rx_fsm_state + ); + +THE_TX_FSM : tx_reset_fsm + port map( + RST_N => rst_n_tx, + TX_REFCLK => CLK_REF, + TX_PLL_LOL_QD_S => TX_LOL, + RST_QD_C => QUAD_RST, + TX_PCS_RST_CH_C => TX_PCS_RST, + NORMAL_OPERATION_OUT => finished_reset_tx, + STATE_OUT => tx_fsm_state + ); + + +SYNC_WA_POSITION : process begin + wait until rising_edge(CLK_REF); + if IS_SYNC_SLAVE = 1 then + wa_position_rx <= WA_POSITION; + else + wa_position_rx <= x"0"; + end if; +end process; + +------------------------------------------------- +-- RX & TX allow +------------------------------------------------- +--Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable +PROC_ALLOW : process begin + wait until rising_edge(CLK_SYS); + if finished_reset_rx_q = '1' --SERDES_RX_READY_IN= '1' --and + and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then + rx_allow <= '1'; + else + rx_allow <= '0'; + end if; + if --SERDES_RX_READY_IN = '1' and SERDES_TX_READY_IN = '1' + finished_reset_tx_q = '1' and finished_reset_rx_q = '1' + and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then + tx_allow <= '1'; + else + tx_allow <= '0'; + end if; +end process; + + + link_reset_fin_tx : signal_sync port map(RESET => '0',CLK0 => CLK_SYS, CLK1 => CLK_SYS, + D_IN(0) => finished_reset_tx, + D_OUT(0) => finished_reset_tx_q); + link_reset_fin_rx : signal_sync port map(RESET => '0',CLK0 => CLK_SYS, CLK1 => CLK_SYS, + D_IN(0) => finished_reset_rx, + D_OUT(0) => finished_reset_rx_q); + + +PROC_START_TIMER : process begin + wait until rising_edge(CLK_SYS); + -- if got_link_ready_i = '1' then + if finished_reset_tx_q = '1' and finished_reset_rx_q = '1' then + if start_timer(start_timer'left) = '0' then + start_timer <= start_timer + 1; + end if; + else + start_timer <= (others => '0'); + end if; +end process; + +------------------------------------------------- +-- Status signals +------------------------------------------------- + +STAT_RESET(3 downto 0) <= rx_fsm_state; +STAT_RESET(7 downto 4) <= tx_fsm_state; +STAT_RESET(8) <= tx_allow; +STAT_RESET(9) <= rx_allow; +STAT_RESET(15 downto 10) <= (others => '0'); +STAT_RESET(16) <= RX_CDR_LOL; +STAT_RESET(17) <= RX_LOS; +STAT_RESET(18) <= '0';--QUAD_RST; --RX_PCS_RST; +STAT_RESET(19) <= '0';--TX_PCS_RST; +STAT_RESET(20) <= TX_LOL; +STAT_RESET(21) <= rst_n; +STAT_RESET(22) <= rst_n_tx; +STAT_RESET(30 downto 23) <= (others => '0'); +STAT_RESET(31) <= start_timer(start_timer'left); + + +gen_link_reset : if IS_SYNC_SLAVE = 1 generate + link_reset_pulse : pulse_sync port map( CLK_A_IN => CLK_RXI, CLK_B_IN => CLK_SYS, + PULSE_A_IN => make_link_reset_i, + PULSE_B_OUT => make_link_reset_sys_i); + link_reset_send : signal_sync port map(RESET => '0',CLK0 => CLK_RXI,CLK1 => CLK_SYS, + D_IN(0) => send_link_reset_i, + D_OUT(0) => send_link_reset_sys_i); +end generate; + +make_link_reset_real_i <= make_link_reset_sys_i or sd_los_i when IS_SYNC_SLAVE = 1 + else '0'; +send_link_reset_real_i <= send_link_reset_sys_i when IS_SYNC_SLAVE = 1 + else '0'; + +sd_los_i <= SFP_LOS when rising_edge(CLK_SYS); + + +DEBUG_OUT(0) <= tx_allow; +DEBUG_OUT(1) <= rx_allow; +DEBUG_OUT(2) <= sd_los_i; +DEBUG_OUT(3) <= '0'; --DEBUG_RX_CONTROL(4); + +end architecture; diff --git a/gbe_trb/media/ecp5/pcstest/sgmii_ecp5.lpc b/gbe_trb/media/ecp5/pcstest/sgmii_ecp5.lpc new file mode 100644 index 0000000..7b1f021 --- /dev/null +++ b/gbe_trb/media/ecp5/pcstest/sgmii_ecp5.lpc @@ -0,0 +1,97 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA756 +PartName=LFE5UM-85F-8BG756C +PartType=LFE5UM-85F +SpeedGrade=8 +Status=P +[IP] +CoreName=PCS +CoreRevision=8.2 +CoreStatus=Demo +CoreType=LPM +Date=05/09/2019 +ModuleName=sgmii_ecp5 +ParameterFileVersion=1.0 +SourceFormat=vhdl +Time=16:52:08 +VendorName=Lattice Semiconductor Corporation +[Parameters] +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +;RXMCAENABLE=Disabled +CDRLOLACTION=Full Recalibration +CDRLOLRANGE=3 +CDR_MAX_RATE=1.25 +CDR_MULT=10X +CDR_REF_RATE=125.0000 +CH_MODE=Rx and Tx +Destination=Synplicity +EDIF=1 +Expression=BusA(0 to 7) +IO=0 +IO_TYPE=GbE +LEQ=0 +LOOPBACK=Disabled +LOSPORT=Enabled +NUM_CHS=1 +Order=Big Endian [MSB:LSB] +PPORT_RX_RDY=Enabled +PPORT_TX_RDY=Enabled +PROTOCOL=GbE +PWAIT_RX_RDY=3000 +PWAIT_TX_RDY=3000 +RCSRC=Disabled +REFCLK_RATE=125.0000 +RSTSEQSEL=Enabled +RX8B10B=Enabled +RXCOMMAA=1010000011 +RXCOMMAB=0101111100 +RXCOMMAM=1111111111 +RXCOUPLING=AC +RXCTC=Enabled +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=1 BCH +RXCTCBYTEN3=0 50H +RXCTCMATCHPATTERN=M2-S2 +RXDIFFTERM=50 ohms +RXFIFO_ENABLE=Enabled +RXINVPOL=Non-invert +RXLDR=Off +RXLOSTHRESHOLD=4 +RXLSM=Enabled +RXSC=K28P5 +RXWA=Barrel Shift +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=125.0000 +RX_LINE_RATE=1.2500 +RX_RATE_DIV=Full Rate +SCIPORT=Enabled +SOFTLOL=Enabled +TX8B10B=Enabled +TXAMPLITUDE=1100 +TXDEPOST=Disabled +TXDEPRE=Disabled +TXDIFFTERM=50 ohms +TXFIFO_ENABLE=Enabled +TXINVPOL=Non-invert +TXLDR=Off +TXPLLLOLTHRESHOLD=1 +TXPLLMULT=10X +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=125.0000 +TX_LINE_RATE=1.2500 +TX_MAX_RATE=1.25 +TX_RATE_DIV=Full Rate +VHDL=1 +Verilog=0 +[FilesGenerated] +sgmii_ecp5.pp=pp +sgmii_ecp5.sym=sym +sgmii_ecp5.tft=tft +sgmii_ecp5.txt=pcs_module +[SYSTEMPNR] +LN0=DCU1_CH1 diff --git a/gbe_trb/media/ecp5/pcstest/sgmii_ecp5.ngd b/gbe_trb/media/ecp5/pcstest/sgmii_ecp5.ngd new file mode 100644 index 0000000..154048f Binary files /dev/null and b/gbe_trb/media/ecp5/pcstest/sgmii_ecp5.ngd differ diff --git a/gbe_trb/media/ecp5/pcstest/sgmii_ecp5.vhd b/gbe_trb/media/ecp5/pcstest/sgmii_ecp5.vhd new file mode 100644 index 0000000..91f3eb6 --- /dev/null +++ b/gbe_trb/media/ecp5/pcstest/sgmii_ecp5.vhd @@ -0,0 +1,433 @@ + +-- +-- Verific VHDL Description of module DCUA +-- + +-- DCUA is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module sgmii_ecp5rsl_core +-- + +-- sgmii_ecp5rsl_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module sgmii_ecp5sll_core +-- + +-- sgmii_ecp5sll_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module sgmii_ecp5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +library ecp5um ; +use ecp5um.components.all ; + +entity sgmii_ecp5 is + port (hdoutp: out std_logic; + hdoutn: out std_logic; + hdinp: in std_logic; + hdinn: in std_logic; + rxrefclk: in std_logic; + tx_pclk: out std_logic; + txi_clk: in std_logic; + txdata: in std_logic_vector(7 downto 0); + tx_k: in std_logic_vector(0 downto 0); + xmit: in std_logic_vector(0 downto 0); + tx_disp_correct: in std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_cv_err: out std_logic_vector(0 downto 0); + signal_detect_c: in std_logic; + rx_los_low_s: out std_logic; + lsm_status_s: out std_logic; + ctc_urun_s: out std_logic; + ctc_orun_s: out std_logic; + rx_cdr_lol_s: out std_logic; + ctc_ins_s: out std_logic; + ctc_del_s: out std_logic; + sli_rst: in std_logic; + tx_pwrup_c: in std_logic; + rx_pwrup_c: in std_logic; + sci_wrdata: in std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_en_dual: in std_logic; + sci_sel_dual: in std_logic; + sci_en: in std_logic; + sci_sel: in std_logic; + sci_rd: in std_logic; + sci_wrn: in std_logic; + sci_int: out std_logic; + cyawstn: in std_logic; + serdes_pdb: in std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + serdes_rst_dual_c: in std_logic; + rst_dual_c: in std_logic; + tx_serdes_rst_c: in std_logic; + tx_pcs_rst_c: in std_logic; + pll_lol: out std_logic; + rsl_tx_rdy: out std_logic; + rx_serdes_rst_c: in std_logic; + rx_pcs_rst_c: in std_logic; + rsl_rx_rdy: out std_logic + ); + +end entity sgmii_ecp5; + +architecture v1 of sgmii_ecp5 is + component sgmii_ecp5rsl_core is + generic (pnum_channels: integer := 1; + pprotocol: string := "GBE"; + pserdes_mode: string := "RX AND TX"; + pport_tx_rdy: string := "ENABLED"; + pwait_tx_rdy: integer := 3000; + pport_rx_rdy: string := "ENABLED"; + pwait_rx_rdy: integer := 3000); + port (rui_rst: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132) + rui_serdes_rst_dual_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133) + rui_rst_dual_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134) + rui_rsl_disable: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135) + rui_tx_ref_clk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137) + rui_tx_serdes_rst_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138) + rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139) + rdi_pll_lol: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140) + rui_rx_ref_clk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142) + rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143) + rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144) + rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145) + rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146) + rdo_serdes_rst_dual_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149) + rdo_rst_dual_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150) + ruo_tx_rdy: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152) + rdo_tx_serdes_rst_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153) + rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154) + ruo_rx_rdy: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156) + rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157) + rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158) + ); + + end component sgmii_ecp5rsl_core; -- syn_black_box=1 -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88) + component sgmii_ecp5sll_core is + generic (PPROTOCOL: string := "GBE"; + PLOL_SETTING: integer := 1; + PDYN_RATE_CTRL: string := "DISABLED"; + PPCIE_MAX_RATE: string := "2.5"; + PDIFF_VAL_LOCK: integer := 39; + PDIFF_VAL_UNLOCK: integer := 262; + PPCLK_TC: integer := 131072; + PDIFF_DIV11_VAL_LOCK: integer := 0; + PDIFF_DIV11_VAL_UNLOCK: integer := 0; + PPCLK_DIV11_TC: integer := 0); + port (sli_rst: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(125) + sli_refclk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(126) + sli_pclk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(127) + sli_div2_rate: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(128) + sli_div11_rate: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(129) + sli_gear_mode: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(130) + sli_cpri_mode: in std_logic_vector(2 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(131) + sli_pcie_mode: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(132) + slo_plol: out std_logic -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(135) + ); + + end component sgmii_ecp5sll_core; -- syn_black_box=1 -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(107) + signal n45,n44,n1,n2,n3,n4,tx_pclk_c,n5,n6,n7,n8,n9,n10,n11, + n12,n13,rx_los_low_s_c,n14,n15,rx_cdr_lol_s_c,rsl_tx_pcs_rst_c, + rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c,rsl_serdes_rst_dual_c, + rsl_tx_serdes_rst_c,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25, + n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39, + n40,n41,n42,n43,n46,n103,n102,n47,n48,n49,n50,n51,n52,n53, + n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67, + n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81, + n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95, + n96,n97,n98,n99,n100,n101,n112,n111,n110,pll_lol_c,n122,n121, + n113,n114,n115,n116,n117,n118,n119,n120,\_Z\,n124,n123,gnd, + pwr : std_logic; + attribute LOC : string; + attribute LOC of DCU1_inst : label is "DCU1"; + attribute CHAN : string; + attribute CHAN of DCU1_inst : label is "CH1"; +begin + tx_pclk <= tx_pclk_c; + rx_los_low_s <= rx_los_low_s_c; + rx_cdr_lol_s <= rx_cdr_lol_s_c; + pll_lol <= pll_lol_c; + DCU1_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", + D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", + D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", + D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b0",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", + CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", + CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0", + CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0", + CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0", + CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0", + CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b0", + CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b1", + CH1_MATCH_4_ENABLE=>"0b0",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x000", + CH1_CC_MATCH_2=>"0x000",CH1_CC_MATCH_3=>"0x1BC",CH1_CC_MATCH_4=>"0x050", + CH1_UDF_COMMA_MASK=>"0x3ff",CH1_UDF_COMMA_A=>"0x283",CH1_UDF_COMMA_B=>"0x17C", + CH1_RX_DCO_CK_DIV=>"0b010",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1", + CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00", + CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b01",CH1_TDRV_SLICE1_SEL=>"0b00", + CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01", + CH1_TDRV_SLICE5_SEL=>"0b01",CH1_TDRV_SLICE0_CUR=>"0b101",CH1_TDRV_SLICE1_CUR=>"0b000", + CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b11", + CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0", + CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0", + CH1_SEL_SD_RX_CLK=>"0b0",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0", + CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0", + CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00", + CH1_REQ_EN=>"0b1",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1", + CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000", + CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b100",CH1_RX_LOS_CEQ=>"0b11", + CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0", + CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"1.25",CH1_CDR_MAX_RATE=>"1.25", + CH1_TXAMPLITUDE=>"0d1100",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED", + CH1_PROTOCOL=>"GBE",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00", + D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000", + D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00", + CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00", + CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b001",CH1_DCOCTLGI=>"0b010", + CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b01",CH1_DCOFTNRG=>"0b110", + CH1_DCOIOSTUNE=>"0b000",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b111", + CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b101",CH1_DCOSCALEI=>"0b00", + CH1_DCOSTARTVAL=>"0b000",CH1_DCOSTEP=>"0b00",CH1_BAND_THRESHOLD=>"0d0", + CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0", + CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0", + CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00", + D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", + D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", + D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d8", + D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b010",D_PLL_LOL_SET=>"0b01", + D_RG_EN=>"0b0",D_RG_SET=>"0b00") + port map (CH0_HDINP=>n103,CH1_HDINP=>hdinp,CH0_HDINN=>n103,CH1_HDINN=>hdinn, + D_TXBIT_CLKP_FROM_ND=>n44,D_TXBIT_CLKN_FROM_ND=>n44,D_SYNC_ND=>n44,D_TXPLL_LOL_FROM_ND=>n44, + CH0_RX_REFCLK=>n103,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n102,CH1_FF_RXI_CLK=>tx_pclk_c, + CH0_FF_TXI_CLK=>n102,CH1_FF_TXI_CLK=>txi_clk,CH0_FF_EBRD_CLK=>n102,CH1_FF_EBRD_CLK=>tx_pclk_c, + CH0_FF_TX_D_0=>n103,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n103,CH1_FF_TX_D_1=>txdata(1), + CH0_FF_TX_D_2=>n103,CH1_FF_TX_D_2=>txdata(2),CH0_FF_TX_D_3=>n103,CH1_FF_TX_D_3=>txdata(3), + CH0_FF_TX_D_4=>n103,CH1_FF_TX_D_4=>txdata(4),CH0_FF_TX_D_5=>n103,CH1_FF_TX_D_5=>txdata(5), + CH0_FF_TX_D_6=>n103,CH1_FF_TX_D_6=>txdata(6),CH0_FF_TX_D_7=>n103,CH1_FF_TX_D_7=>txdata(7), + CH0_FF_TX_D_8=>n103,CH1_FF_TX_D_8=>tx_k(0),CH0_FF_TX_D_9=>n103,CH1_FF_TX_D_9=>n44, + CH0_FF_TX_D_10=>n103,CH1_FF_TX_D_10=>xmit(0),CH0_FF_TX_D_11=>n103,CH1_FF_TX_D_11=>tx_disp_correct(0), + CH0_FF_TX_D_12=>n103,CH1_FF_TX_D_12=>n103,CH0_FF_TX_D_13=>n103,CH1_FF_TX_D_13=>n103, + CH0_FF_TX_D_14=>n103,CH1_FF_TX_D_14=>n103,CH0_FF_TX_D_15=>n103,CH1_FF_TX_D_15=>n103, + CH0_FF_TX_D_16=>n103,CH1_FF_TX_D_16=>n103,CH0_FF_TX_D_17=>n103,CH1_FF_TX_D_17=>n103, + CH0_FF_TX_D_18=>n103,CH1_FF_TX_D_18=>n103,CH0_FF_TX_D_19=>n103,CH1_FF_TX_D_19=>n103, + CH0_FF_TX_D_20=>n103,CH1_FF_TX_D_20=>n103,CH0_FF_TX_D_21=>n103,CH1_FF_TX_D_21=>n44, + CH0_FF_TX_D_22=>n103,CH1_FF_TX_D_22=>n103,CH0_FF_TX_D_23=>n103,CH1_FF_TX_D_23=>n103, + CH0_FFC_EI_EN=>n103,CH1_FFC_EI_EN=>n44,CH0_FFC_PCIE_DET_EN=>n103,CH1_FFC_PCIE_DET_EN=>n44, + CH0_FFC_PCIE_CT=>n103,CH1_FFC_PCIE_CT=>n44,CH0_FFC_SB_INV_RX=>n103,CH1_FFC_SB_INV_RX=>n103, + CH0_FFC_ENABLE_CGALIGN=>n103,CH1_FFC_ENABLE_CGALIGN=>n103,CH0_FFC_SIGNAL_DETECT=>n103, + CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n103,CH1_FFC_FB_LOOPBACK=>n44, + CH0_FFC_SB_PFIFO_LP=>n103,CH1_FFC_SB_PFIFO_LP=>n44,CH0_FFC_PFIFO_CLR=>n103, + CH1_FFC_PFIFO_CLR=>n44,CH0_FFC_RATE_MODE_RX=>n103,CH1_FFC_RATE_MODE_RX=>n44, + CH0_FFC_RATE_MODE_TX=>n103,CH1_FFC_RATE_MODE_TX=>n44,CH0_FFC_DIV11_MODE_RX=>n103, + CH1_FFC_DIV11_MODE_RX=>n44,CH0_FFC_DIV11_MODE_TX=>n103,CH1_FFC_DIV11_MODE_TX=>n44, + CH0_FFC_RX_GEAR_MODE=>n103,CH1_FFC_RX_GEAR_MODE=>n44,CH0_FFC_TX_GEAR_MODE=>n103, + CH1_FFC_TX_GEAR_MODE=>n44,CH0_FFC_LDR_CORE2TX_EN=>n103,CH1_FFC_LDR_CORE2TX_EN=>n103, + CH0_FFC_LANE_TX_RST=>n103,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,CH0_FFC_LANE_RX_RST=>n103, + CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n103,CH1_FFC_RRST=>rsl_rx_serdes_rst_c, + CH0_FFC_TXPWDNB=>n103,CH1_FFC_TXPWDNB=>tx_pwrup_c,CH0_FFC_RXPWDNB=>n103, + CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n103,CH1_LDR_CORE2TX=>n103, + D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1),D_SCIWDATA2=>sci_wrdata(2), + D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4),D_SCIWDATA5=>sci_wrdata(5), + D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7),D_SCIADDR0=>sci_addr(0), + D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2),D_SCIADDR3=>sci_addr(3), + D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5),D_SCIENAUX=>sci_en_dual, + D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n103,CH1_SCIEN=>sci_en,CH0_SCISEL=>n103, + CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,D_CYAWSTN=>cyawstn, + D_FFC_SYNC_TOGGLE=>n103,D_FFC_DUAL_RST=>rsl_rst_dual_c,D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c, + D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n103, + CH1_FFC_CDR_EN_BITSLIP=>n44,D_SCAN_ENABLE=>n44,D_SCAN_IN_0=>n44,D_SCAN_IN_1=>n44, + D_SCAN_IN_2=>n44,D_SCAN_IN_3=>n44,D_SCAN_IN_4=>n44,D_SCAN_IN_5=>n44, + D_SCAN_IN_6=>n44,D_SCAN_IN_7=>n44,D_SCAN_MODE=>n44,D_SCAN_RESET=>n44, + D_CIN0=>n44,D_CIN1=>n44,D_CIN2=>n44,D_CIN3=>n44,D_CIN4=>n44,D_CIN5=>n44, + D_CIN6=>n44,D_CIN7=>n44,D_CIN8=>n44,D_CIN9=>n44,D_CIN10=>n44,D_CIN11=>n44, + CH0_HDOUTP=>n47,CH1_HDOUTP=>hdoutp,CH0_HDOUTN=>n48,CH1_HDOUTN=>hdoutn, + D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4, + CH0_FF_RX_F_CLK=>n49,CH1_FF_RX_F_CLK=>n5,CH0_FF_RX_H_CLK=>n50,CH1_FF_RX_H_CLK=>n6, + CH0_FF_TX_F_CLK=>n51,CH1_FF_TX_F_CLK=>n7,CH0_FF_TX_H_CLK=>n52,CH1_FF_TX_H_CLK=>n8, + CH0_FF_RX_PCLK=>n53,CH1_FF_RX_PCLK=>n9,CH0_FF_TX_PCLK=>n54,CH1_FF_TX_PCLK=>tx_pclk_c, + CH0_FF_RX_D_0=>n55,CH1_FF_RX_D_0=>rxdata(0),CH0_FF_RX_D_1=>n56,CH1_FF_RX_D_1=>rxdata(1), + CH0_FF_RX_D_2=>n57,CH1_FF_RX_D_2=>rxdata(2),CH0_FF_RX_D_3=>n58,CH1_FF_RX_D_3=>rxdata(3), + CH0_FF_RX_D_4=>n59,CH1_FF_RX_D_4=>rxdata(4),CH0_FF_RX_D_5=>n60,CH1_FF_RX_D_5=>rxdata(5), + CH0_FF_RX_D_6=>n61,CH1_FF_RX_D_6=>rxdata(6),CH0_FF_RX_D_7=>n62,CH1_FF_RX_D_7=>rxdata(7), + CH0_FF_RX_D_8=>n63,CH1_FF_RX_D_8=>rx_k(0),CH0_FF_RX_D_9=>n64,CH1_FF_RX_D_9=>rx_disp_err(0), + CH0_FF_RX_D_10=>n65,CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n66, + CH1_FF_RX_D_11=>n10,CH0_FF_RX_D_12=>n67,CH1_FF_RX_D_12=>n68,CH0_FF_RX_D_13=>n69, + CH1_FF_RX_D_13=>n70,CH0_FF_RX_D_14=>n71,CH1_FF_RX_D_14=>n72,CH0_FF_RX_D_15=>n73, + CH1_FF_RX_D_15=>n74,CH0_FF_RX_D_16=>n75,CH1_FF_RX_D_16=>n76,CH0_FF_RX_D_17=>n77, + CH1_FF_RX_D_17=>n78,CH0_FF_RX_D_18=>n79,CH1_FF_RX_D_18=>n80,CH0_FF_RX_D_19=>n81, + CH1_FF_RX_D_19=>n82,CH0_FF_RX_D_20=>n83,CH1_FF_RX_D_20=>n84,CH0_FF_RX_D_21=>n85, + CH1_FF_RX_D_21=>n86,CH0_FF_RX_D_22=>n87,CH1_FF_RX_D_22=>n88,CH0_FF_RX_D_23=>n89, + CH1_FF_RX_D_23=>n11,CH0_FFS_PCIE_DONE=>n90,CH1_FFS_PCIE_DONE=>n12,CH0_FFS_PCIE_CON=>n91, + CH1_FFS_PCIE_CON=>n13,CH0_FFS_RLOS=>n92,CH1_FFS_RLOS=>rx_los_low_s_c, + CH0_FFS_LS_SYNC_STATUS=>n93,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s,CH0_FFS_CC_UNDERRUN=>n94, + CH1_FFS_CC_UNDERRUN=>ctc_urun_s,CH0_FFS_CC_OVERRUN=>n95,CH1_FFS_CC_OVERRUN=>ctc_orun_s, + CH0_FFS_RXFBFIFO_ERROR=>n96,CH1_FFS_RXFBFIFO_ERROR=>n14,CH0_FFS_TXFBFIFO_ERROR=>n97, + CH1_FFS_TXFBFIFO_ERROR=>n15,CH0_FFS_RLOL=>n98,CH1_FFS_RLOL=>rx_cdr_lol_s_c, + CH0_FFS_SKP_ADDED=>n99,CH1_FFS_SKP_ADDED=>ctc_ins_s,CH0_FFS_SKP_DELETED=>n100, + CH1_FFS_SKP_DELETED=>ctc_del_s,CH0_LDR_RX2CORE=>n101,CH1_LDR_RX2CORE=>n112, + D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),D_SCIRDATA2=>sci_rddata(2), + D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),D_SCIRDATA5=>sci_rddata(5), + D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),D_SCIINT=>sci_int, + D_SCAN_OUT_0=>n16,D_SCAN_OUT_1=>n17,D_SCAN_OUT_2=>n18,D_SCAN_OUT_3=>n19, + D_SCAN_OUT_4=>n20,D_SCAN_OUT_5=>n21,D_SCAN_OUT_6=>n22,D_SCAN_OUT_7=>n23, + D_COUT0=>n24,D_COUT1=>n25,D_COUT2=>n26,D_COUT3=>n27,D_COUT4=>n28,D_COUT5=>n29, + D_COUT6=>n30,D_COUT7=>n31,D_COUT8=>n32,D_COUT9=>n33,D_COUT10=>n34,D_COUT11=>n35, + D_COUT12=>n36,D_COUT13=>n37,D_COUT14=>n38,D_COUT15=>n39,D_COUT16=>n40, + D_COUT17=>n41,D_COUT18=>n42,D_COUT19=>n43,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n46); + n45 <= '1' ; + n44 <= '0' ; + n1 <= 'Z' ; + n2 <= 'Z' ; + n3 <= 'Z' ; + n4 <= 'Z' ; + n5 <= 'Z' ; + n6 <= 'Z' ; + n7 <= 'Z' ; + n8 <= 'Z' ; + n9 <= 'Z' ; + n10 <= 'Z' ; + n11 <= 'Z' ; + n12 <= 'Z' ; + n13 <= 'Z' ; + n14 <= 'Z' ; + n15 <= 'Z' ; + n16 <= 'Z' ; + n17 <= 'Z' ; + n18 <= 'Z' ; + n19 <= 'Z' ; + n20 <= 'Z' ; + n21 <= 'Z' ; + n22 <= 'Z' ; + n23 <= 'Z' ; + n24 <= 'Z' ; + n25 <= 'Z' ; + n26 <= 'Z' ; + n27 <= 'Z' ; + n28 <= 'Z' ; + n29 <= 'Z' ; + n30 <= 'Z' ; + n31 <= 'Z' ; + n32 <= 'Z' ; + n33 <= 'Z' ; + n34 <= 'Z' ; + n35 <= 'Z' ; + n36 <= 'Z' ; + n37 <= 'Z' ; + n38 <= 'Z' ; + n39 <= 'Z' ; + n40 <= 'Z' ; + n41 <= 'Z' ; + n42 <= 'Z' ; + n43 <= 'Z' ; + n46 <= 'Z' ; + n103 <= '0' ; + n102 <= '1' ; + n47 <= 'Z' ; + n48 <= 'Z' ; + n49 <= 'Z' ; + n50 <= 'Z' ; + n51 <= 'Z' ; + n52 <= 'Z' ; + n53 <= 'Z' ; + n54 <= 'Z' ; + n55 <= 'Z' ; + n56 <= 'Z' ; + n57 <= 'Z' ; + n58 <= 'Z' ; + n59 <= 'Z' ; + n60 <= 'Z' ; + n61 <= 'Z' ; + n62 <= 'Z' ; + n63 <= 'Z' ; + n64 <= 'Z' ; + n65 <= 'Z' ; + n66 <= 'Z' ; + n67 <= 'Z' ; + n68 <= 'Z' ; + n69 <= 'Z' ; + n70 <= 'Z' ; + n71 <= 'Z' ; + n72 <= 'Z' ; + n73 <= 'Z' ; + n74 <= 'Z' ; + n75 <= 'Z' ; + n76 <= 'Z' ; + n77 <= 'Z' ; + n78 <= 'Z' ; + n79 <= 'Z' ; + n80 <= 'Z' ; + n81 <= 'Z' ; + n82 <= 'Z' ; + n83 <= 'Z' ; + n84 <= 'Z' ; + n85 <= 'Z' ; + n86 <= 'Z' ; + n87 <= 'Z' ; + n88 <= 'Z' ; + n89 <= 'Z' ; + n90 <= 'Z' ; + n91 <= 'Z' ; + n92 <= 'Z' ; + n93 <= 'Z' ; + n94 <= 'Z' ; + n95 <= 'Z' ; + n96 <= 'Z' ; + n97 <= 'Z' ; + n98 <= 'Z' ; + n99 <= 'Z' ; + n100 <= 'Z' ; + n101 <= 'Z' ; + n112 <= 'Z' ; + rsl_inst: component sgmii_ecp5rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c, + rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki, + rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n122, + rui_tx_pcs_rst_c(2)=>n122,rui_tx_pcs_rst_c(1)=>n122,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c, + rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n122, + rui_rx_serdes_rst_c(2)=>n122,rui_rx_serdes_rst_c(1)=>n122,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c, + rui_rx_pcs_rst_c(3)=>n122,rui_rx_pcs_rst_c(2)=>n122,rui_rx_pcs_rst_c(1)=>n122, + rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n122,rdi_rx_los_low_s(2)=>n122, + rdi_rx_los_low_s(1)=>n122,rdi_rx_los_low_s(0)=>rx_los_low_s_c, + rdi_rx_cdr_lol_s(3)=>n122,rdi_rx_cdr_lol_s(2)=>n122,rdi_rx_cdr_lol_s(1)=>n122, + rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c, + rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c, + rdo_tx_pcs_rst_c(3)=>n113,rdo_tx_pcs_rst_c(2)=>n114,rdo_tx_pcs_rst_c(1)=>n115, + rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n116, + rdo_rx_serdes_rst_c(2)=>n117,rdo_rx_serdes_rst_c(1)=>n118,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c, + rdo_rx_pcs_rst_c(3)=>n119,rdo_rx_pcs_rst_c(2)=>n120,rdo_rx_pcs_rst_c(1)=>\_Z\, + rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c); + n111 <= '1' ; + n110 <= '0' ; + n122 <= '0' ; + n121 <= '1' ; + n113 <= 'Z' ; + n114 <= 'Z' ; + n115 <= 'Z' ; + n116 <= 'Z' ; + n117 <= 'Z' ; + n118 <= 'Z' ; + n119 <= 'Z' ; + n120 <= 'Z' ; + \_Z\ <= 'Z' ; + sll_inst: component sgmii_ecp5sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki, + sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd, + sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd, + sli_pcie_mode=>gnd,slo_plol=>pll_lol_c); + n124 <= '1' ; + n123 <= '0' ; + gnd <= '0' ; + pwr <= '1' ; + +end architecture v1; + diff --git a/gbe_trb/media/ecp5/pcstest/sgmii_ecp5_softlogic.v b/gbe_trb/media/ecp5/pcstest/sgmii_ecp5_softlogic.v new file mode 100644 index 0000000..69a023d --- /dev/null +++ b/gbe_trb/media/ecp5/pcstest/sgmii_ecp5_softlogic.v @@ -0,0 +1,2003 @@ + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2016 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : RSL- Reset Sequence Logic +// File : rsl_core.v +// Title : Top-level file for RSL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : BM +// Mod. Date : October 28, 2013 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : BM +// Mod. Date : November 06, 2013 +// Changes Made : Tx/Rx separation, ready port code exclusion +// ----------------------------------------------------------------------------- +// Version : 1.2 +// Author(s) : BM +// Mod. Date : June 13, 2014 +// Changes Made : Updated Rx PCS reset method +// ----------------------------------------------------------------------------- +// ----------------------------------------------------------------------------- +// Version : 1.3 +// Author(s) : UA +// Mod. Date : Dec 19, 2014 +// Changes Made : Added new parameter fro PCIE +// ----------------------------------------------------------------------------- +// Version : 1.31 +// Author(s) : BM/UM +// Mod. Date : Feb 23, 2016 +// Changes Made : Behavior of rx_rdy output modified. The output rx_rdy +// and the rx_rdy wait counter are reset to zero on +// LOL or LOS. Reverted back the counter value change for PCIE. +// ----------------------------------------------------------------------------- +// Version : 1.4 +// Author(s) : EB +// Mod. Date: : March 21, 2017 +// Changes Made : +// ----------------------------------------------------------------------------- +// Version : 1.5 +// Author(s) : ES +// Mod. Date: : May 8, 2017 +// Changes Made : Implemented common RSL behaviour as proposed by BM. +// ============================================================================= + +`timescale 1ns/10ps + +module sgmii_ecp5rsl_core ( + // ------------ Inputs + // Common + rui_rst, // Active high reset for the RSL module + rui_serdes_rst_dual_c, // SERDES macro reset user command + rui_rst_dual_c, // PCS dual reset user command + rui_rsl_disable, // Active high signal that disables all reset outputs of RSL + // Tx + rui_tx_ref_clk, // Tx reference clock + rui_tx_serdes_rst_c, // Tx SERDES reset user command + rui_tx_pcs_rst_c, // Tx lane reset user command + rdi_pll_lol, // Tx PLL Loss of Lock status input from the SERDES + // Rx + rui_rx_ref_clk, // Rx reference clock + rui_rx_serdes_rst_c, // SERDES Receive channel reset user command + rui_rx_pcs_rst_c, // Rx lane reset user command + rdi_rx_los_low_s, // Receive loss of signal status input from SERDES + rdi_rx_cdr_lol_s, // Receive CDR loss of lock status input from SERDES + + // ------------ Outputs + // Common + rdo_serdes_rst_dual_c, // SERDES macro reset command output + rdo_rst_dual_c, // PCS dual reset command output + // Tx + ruo_tx_rdy, // Tx lane ready status output + rdo_tx_serdes_rst_c, // SERDES Tx reset command output + rdo_tx_pcs_rst_c, // PCS Tx lane reset command output + // Rx + ruo_rx_rdy, // Rx lane ready status output + rdo_rx_serdes_rst_c, // SERDES Rx channel reset command output + rdo_rx_pcs_rst_c // PCS Rx lane reset command output + ); + +// ------------ Module parameters +`ifdef NUM_CHANNELS + parameter pnum_channels = `NUM_CHANNELS; // 1,2,4 +`else + parameter pnum_channels = 1; +`endif + +`ifdef PCIE + parameter pprotocol = "PCIE"; +`else + parameter pprotocol = ""; +`endif + +`ifdef RX_ONLY + parameter pserdes_mode = "RX ONLY"; +`else + `ifdef TX_ONLY + parameter pserdes_mode = "TX ONLY"; + `else + parameter pserdes_mode = "RX AND TX"; + `endif +`endif + +`ifdef PORT_TX_RDY + parameter pport_tx_rdy = "ENABLED"; +`else + parameter pport_tx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_TX_RDY + parameter pwait_tx_rdy = `WAIT_TX_RDY; +`else + parameter pwait_tx_rdy = 3000; +`endif + +`ifdef PORT_RX_RDY + parameter pport_rx_rdy = "ENABLED"; +`else + parameter pport_rx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_RX_RDY + parameter pwait_rx_rdy = `WAIT_RX_RDY; +`else + parameter pwait_rx_rdy = 3000; +`endif + +// ------------ Local parameters + localparam wa_num_cycles = 1024; + localparam dac_num_cycles = 3; + localparam lreset_pwidth = 3; // reset pulse width-1, default=4-1=3 + localparam lwait_b4_trst = 781250; // 5ms wait with worst-case Fmax=156 MHz + localparam lwait_b4_trst_s = 781; // for simulation + localparam lplol_cnt_width = 20; // width for lwait_b4_trst + localparam lwait_after_plol0 = 4; + localparam lwait_b4_rrst = 180224; // total calibration time + localparam lrrst_wait_width = 20; + localparam lwait_after_rrst = 800000; // For CPRI- unused + localparam lwait_b4_rrst_s = 460; // wait cycles provided by design team + localparam lrlol_cnt_width = 19; // width for lwait_b4_rrst + localparam lwait_after_lols = (16384 * dac_num_cycles) + wa_num_cycles; // 16384 cycles * dac_num_cycles + 1024 cycles + localparam lwait_after_lols_s = 150; // wait cycles provided by design team + localparam llols_cnt_width = 18; // lols count width + localparam lrdb_max = 15; // maximum debounce count + localparam ltxr_wait_width = 12; // width of tx ready wait counter + localparam lrxr_wait_width = 12; // width of tx ready wait counter + +// ------------ input ports + input rui_rst; + input rui_serdes_rst_dual_c; + input rui_rst_dual_c; + input rui_rsl_disable; + + input rui_tx_ref_clk; + input rui_tx_serdes_rst_c; + input [3:0] rui_tx_pcs_rst_c; + input rdi_pll_lol; + + input rui_rx_ref_clk; + input [3:0] rui_rx_serdes_rst_c; + input [3:0] rui_rx_pcs_rst_c; + input [3:0] rdi_rx_los_low_s; + input [3:0] rdi_rx_cdr_lol_s; + +// ------------ output ports + output rdo_serdes_rst_dual_c; + output rdo_rst_dual_c; + + output ruo_tx_rdy; + output rdo_tx_serdes_rst_c; + output [3:0] rdo_tx_pcs_rst_c; + + output ruo_rx_rdy; + output [3:0] rdo_rx_serdes_rst_c; + output [3:0] rdo_rx_pcs_rst_c; + +// ------------ Internal registers and wires + // inputs + wire rui_rst; + wire rui_serdes_rst_dual_c; + wire rui_rst_dual_c; + wire rui_rsl_disable; + wire rui_tx_ref_clk; + wire rui_tx_serdes_rst_c; + wire [3:0] rui_tx_pcs_rst_c; + wire rdi_pll_lol; + wire rui_rx_ref_clk; + wire [3:0] rui_rx_serdes_rst_c; + wire [3:0] rui_rx_pcs_rst_c; + wire [3:0] rdi_rx_los_low_s; + wire [3:0] rdi_rx_cdr_lol_s; + + // outputs + wire rdo_serdes_rst_dual_c; + wire rdo_rst_dual_c; + wire ruo_tx_rdy; + wire rdo_tx_serdes_rst_c; + wire [3:0] rdo_tx_pcs_rst_c; + wire ruo_rx_rdy; + wire [3:0] rdo_rx_serdes_rst_c; + wire [3:0] rdo_rx_pcs_rst_c; + + // internal signals + // common + wire rsl_enable; + wire [lplol_cnt_width-1:0] wait_b4_trst; + wire [lrlol_cnt_width-1:0] wait_b4_rrst; + wire [llols_cnt_width-1:0] wait_after_lols; + reg pll_lol_p1; + reg pll_lol_p2; + reg pll_lol_p3; + // ------------ Tx + // rdo_tx_serdes_rst_c + reg [lplol_cnt_width-1:0] plol_cnt; + wire plol_cnt_tc; + + reg [2:0] txs_cnt; + reg txs_rst; + wire txs_cnt_tc; + // rdo_tx_pcs_rst_c + wire plol_fedge; + wire plol_redge; + reg waita_plol0; + reg [2:0] plol0_cnt; + wire plol0_cnt_tc; + reg [2:0] txp_cnt; + reg txp_rst; + wire txp_cnt_tc; + // ruo_tx_rdy + wire dual_or_serd_rst; + wire tx_any_pcs_rst; + wire tx_any_rst; + reg txsr_appd /* synthesis syn_keep=1 */; + reg txdpr_appd; + reg [pnum_channels-1:0] txpr_appd; + reg txr_wt_en; + reg [ltxr_wait_width-1:0] txr_wt_cnt; + wire txr_wt_tc; + reg ruo_tx_rdyr; + + // ------------ Rx + wire comb_rlos; + wire comb_rlol; + //wire rlols; + wire rx_all_well; + + //reg rlols_p1; + //reg rlols_p2; + //reg rlols_p3; + + reg rlol_p1; + reg rlol_p2; + reg rlol_p3; + reg rlos_p1; + reg rlos_p2; + reg rlos_p3; + + //reg [3:0] rdb_cnt; + //wire rdb_cnt_max; + //wire rdb_cnt_zero; + //reg rlols_db; + //reg rlols_db_p1; + + reg [3:0] rlol_db_cnt; + wire rlol_db_cnt_max; + wire rlol_db_cnt_zero; + reg rlol_db; + reg rlol_db_p1; + + reg [3:0] rlos_db_cnt; + wire rlos_db_cnt_max; + wire rlos_db_cnt_zero; + reg rlos_db; + reg rlos_db_p1; + + // rdo_rx_serdes_rst_c + reg [lrlol_cnt_width-1:0] rlol1_cnt; + wire rlol1_cnt_tc; + reg [2:0] rxs_cnt; + reg rxs_rst; + wire rxs_cnt_tc; + reg [lrrst_wait_width-1:0] rrst_cnt; + wire rrst_cnt_tc; + reg rrst_wait; + // rdo_rx_pcs_rst_c + //wire rlols_fedge; + //wire rlols_redge; + wire rlol_fedge; + wire rlol_redge; + wire rlos_fedge; + wire rlos_redge; + + reg wait_calib; + reg waita_rlols0; + reg [llols_cnt_width-1:0] rlols0_cnt; + wire rlols0_cnt_tc; + reg [2:0] rxp_cnt; + reg rxp_rst; + wire rxp_cnt_tc; + + wire rx_any_serd_rst; + reg [llols_cnt_width-1:0] rlolsz_cnt; + wire rlolsz_cnt_tc; + reg [2:0] rxp_cnt2; + reg rxp_rst2; + wire rxp_cnt2_tc; + reg [15:0] data_loop_b_cnt; + reg data_loop_b; + wire data_loop_b_tc; + + // ruo_rx_rdy + reg [pnum_channels-1:0] rxsr_appd; + reg [pnum_channels-1:0] rxpr_appd; + reg rxsdr_appd /* synthesis syn_keep=1 */; + reg rxdpr_appd; + wire rxsdr_or_sr_appd; + wire dual_or_rserd_rst; + wire rx_any_pcs_rst; + wire rx_any_rst; + reg rxr_wt_en; + reg [lrxr_wait_width-1:0] rxr_wt_cnt; + wire rxr_wt_tc; + reg ruo_rx_rdyr; + +// ================================================================== +// Start of code +// ================================================================== + assign rsl_enable = ~rui_rsl_disable; + +// ------------ rdo_serdes_rst_dual_c + assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c; + +// ------------ rdo_rst_dual_c + assign rdo_rst_dual_c = rui_rst_dual_c; + +// ------------ Setting counter values for RSL_SIM_MODE + `ifdef RSL_SIM_MODE + assign wait_b4_trst = lwait_b4_trst_s; + assign wait_b4_rrst = lwait_b4_rrst_s; + assign wait_after_lols = lwait_after_lols_s; + `else + assign wait_b4_trst = lwait_b4_trst; + assign wait_b4_rrst = lwait_b4_rrst; + assign wait_after_lols = lwait_after_lols; + `endif + +// ================================================================== +// Tx +// ================================================================== + generate + if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin + +// ------------ Synchronizing pll_lol to the tx clock + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + pll_lol_p1 <= 1'd0; + pll_lol_p2 <= 1'd0; + pll_lol_p3 <= 1'd0; + end + else begin + pll_lol_p1 <= rdi_pll_lol; + pll_lol_p2 <= pll_lol_p1; + pll_lol_p3 <= pll_lol_p2; + end + end + +// ------------ rdo_tx_serdes_rst_c + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol_cnt <= 'd0; + else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1)) + plol_cnt <= 'd0; + else + plol_cnt <= plol_cnt+1; + end + assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txs_cnt <= 'd0; // tx serdes reset pulse count + txs_rst <= 1'b0; // tx serdes reset + end + else if(plol_cnt_tc==1) + txs_rst <= 1'b1; + else if(txs_cnt_tc==1) begin + txs_cnt <= 'd0; + txs_rst <= 1'b0; + end + else if(txs_rst==1) + txs_cnt <= txs_cnt+1; + end + assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0; + + assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c; + +// ------------ rdo_tx_pcs_rst_c + assign plol_fedge = ~pll_lol_p2 & pll_lol_p3; + assign plol_redge = pll_lol_p2 & ~pll_lol_p3; + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + waita_plol0 <= 1'd0; + else if(plol_fedge==1'b1) + waita_plol0 <= 1'b1; + else if((plol0_cnt_tc==1)||(plol_redge==1)) + waita_plol0 <= 1'd0; + end + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol0_cnt <= 'd0; + else if((pll_lol_p2==1)||(plol0_cnt_tc==1)) + plol0_cnt <= 'd0; + else if(waita_plol0==1'b1) + plol0_cnt <= plol0_cnt+1; + end + assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txp_cnt <= 'd0; // tx serdes reset pulse count + txp_rst <= 1'b0; // tx serdes reset + end + else if(plol0_cnt_tc==1) + txp_rst <= 1'b1; + else if(txp_cnt_tc==1) begin + txp_cnt <= 'd0; + txp_rst <= 1'b0; + end + else if(txp_rst==1) + txp_cnt <= txp_cnt+1; + end + assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0; + + genvar i; + for(i=0;i>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : SLL - Soft Loss Of Lock(LOL) Logic +// File : sll_core.v +// Title : Top-level file for SLL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : March 2, 2015 +// Changes Made : Initial Creation +// ============================================================================= +// REVISION HISTORY +// Version : 1.1 +// Author(s) : AV +// Mod. Date : June 8, 2015 +// Changes Made : Following updates were made +// : 1. Changed all the PLOL status logic and FSM to run +// : on sli_refclk. +// : 2. Added the HB logic for presence of tx_pclk +// : 3. Changed the lparam assignment scheme for +// : simulation purposes. +// ============================================================================= +// REVISION HISTORY +// Version : 1.2 +// Author(s) : AV +// Mod. Date : June 24, 2015 +// Changes Made : Updated the gearing logic for SDI dynamic rate change +// ============================================================================= +// REVISION HISTORY +// Version : 1.3 +// Author(s) : AV +// Mod. Date : July 14, 2015 +// Changes Made : Added the logic for dynamic rate change in CPRI +// ============================================================================= +// REVISION HISTORY +// Version : 1.4 +// Author(s) : AV +// Mod. Date : August 21, 2015 +// Changes Made : Added the logic for dynamic rate change of 5G CPRI & +// PCIe. +// ============================================================================= +// REVISION HISTORY +// Version : 1.5 +// Author(s) : ES/EB +// Mod. Date : March 21, 2017 +// Changes Made : 1. Added pdiff_sync signal to syncrhonize pcount_diff +// : to sli_refclk. +// : 2. Updated terminal count logic for PCIe 5G +// : 3. Modified checking of pcount_diff in SLL state +// : machine to cover actual count +// : (from 16-bits to 22-bits) +// ============================================================================= +// REVISION HISTORY +// Version : 1.6 +// Author(s) : ES +// Mod. Date : April 19, 2017 +// Changes Made : 1. Added registered lock and unlock signal from +// pdiff_sync to totally decouple pcount_diff from +// SLL state machine. +// : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI +// is operating @ 4.9125Gbps data rate. +// ============================================================================= +`timescale 1ns/10ps + +module sgmii_ecp5sll_core ( + //Reset and Clock inputs + sli_rst, //Active high asynchronous reset input + sli_refclk, //Refclk input to the Tx PLL + sli_pclk, //Tx pclk output from the PCS + + //Control inputs + sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate + sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11 + sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20 + sli_cpri_mode, //Mode of operation specific to CPRI protocol + sli_pcie_mode, //Mode of operation specific to PCIe mode (2.5G or 5G) + + //LOL Output + slo_plol //Tx PLL Loss of Lock output to the user logic + ); + +// Inputs +input sli_rst; +input sli_refclk; +input sli_pclk; +input sli_div2_rate; +input sli_div11_rate; +input sli_gear_mode; +input [2:0] sli_cpri_mode; +input sli_pcie_mode; + +// Outputs +output slo_plol; + + +// Parameters +parameter PPROTOCOL = "PCIE"; //Protocol selected by the User +parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3 +parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control +parameter PPCIE_MAX_RATE = "2.5"; //PCIe max data rate +parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock +parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock +parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk +parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11 +parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11 +parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk + + +// Local Parameters +localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state +localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state +localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state +localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state +`ifdef RSL_SIM_MODE +localparam [15:0] LRCLK_TC = 16'd63; //Terminal count value for counter running on sli_refclk +`else +localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk +`endif +localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse +localparam [7:0] LHB_WAIT_CNT = 8'd255; //Wait count for the Heartbeat signal + +// Local Parameters related to the CPRI dynamic modes +// Terminal count values for the four CPRI modes +localparam LPCLK_TC_0 = 32768; +localparam LPCLK_TC_1 = 65536; +localparam LPCLK_TC_2 = 131072; +localparam LPCLK_TC_3 = 163840; +localparam LPCLK_TC_4 = 65536; + +// Lock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_LOCK_00 = 9; localparam LPDIFF_LOCK_10 = 19; localparam LPDIFF_LOCK_20 = 39; localparam LPDIFF_LOCK_30 = 49; localparam LPDIFF_LOCK_40 = 19; +localparam LPDIFF_LOCK_01 = 9; localparam LPDIFF_LOCK_11 = 19; localparam LPDIFF_LOCK_21 = 39; localparam LPDIFF_LOCK_31 = 49; localparam LPDIFF_LOCK_41 = 19; +localparam LPDIFF_LOCK_02 = 49; localparam LPDIFF_LOCK_12 = 98; localparam LPDIFF_LOCK_22 = 196; localparam LPDIFF_LOCK_32 = 245; localparam LPDIFF_LOCK_42 = 98; +localparam LPDIFF_LOCK_03 = 131; localparam LPDIFF_LOCK_13 = 262; localparam LPDIFF_LOCK_23 = 524; localparam LPDIFF_LOCK_33 = 655; localparam LPDIFF_LOCK_43 = 262; + +// Unlock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_UNLOCK_00 = 19; localparam LPDIFF_UNLOCK_10 = 39; localparam LPDIFF_UNLOCK_20 = 78; localparam LPDIFF_UNLOCK_30 = 98; localparam LPDIFF_UNLOCK_40 = 39; +localparam LPDIFF_UNLOCK_01 = 65; localparam LPDIFF_UNLOCK_11 = 131; localparam LPDIFF_UNLOCK_21 = 262; localparam LPDIFF_UNLOCK_31 = 327; localparam LPDIFF_UNLOCK_41 = 131; +localparam LPDIFF_UNLOCK_02 = 72; localparam LPDIFF_UNLOCK_12 = 144; localparam LPDIFF_UNLOCK_22 = 288; localparam LPDIFF_UNLOCK_32 = 360; localparam LPDIFF_UNLOCK_42 = 144; +localparam LPDIFF_UNLOCK_03 = 196; localparam LPDIFF_UNLOCK_13 = 393; localparam LPDIFF_UNLOCK_23 = 786; localparam LPDIFF_UNLOCK_33 = 983; localparam LPDIFF_UNLOCK_43 = 393; + +// Input and Output reg and wire declarations +wire sli_rst; +wire sli_refclk; +wire sli_pclk; +wire sli_div2_rate; +wire sli_div11_rate; +wire sli_gear_mode; +wire [2:0] sli_cpri_mode; +wire sli_pcie_mode; +wire slo_plol; + +//-------------- Internal signals reg and wire declarations -------------------- + +//Signals running on sli_refclk +reg [15:0] rcount; //16-bit Counter +reg rtc_pul; //Terminal count pulse +reg rtc_pul_p1; //Terminal count pulse pipeline +reg rtc_ctrl; //Terminal count pulse control + +reg [7:0] rhb_wait_cnt; //Heartbeat wait counter + +//Heatbeat synchronization and pipeline registers +wire rhb_sync; +reg rhb_sync_p2; +reg rhb_sync_p1; + +//Pipeling registers for dynamic control mode +wire rgear; +wire rdiv2; +wire rdiv11; +reg rgear_p1; +reg rdiv2_p1; +reg rdiv11_p1; + +reg rstat_pclk; //Pclk presence/absence status + +reg [21:0] rcount_tc; //Tx_pclk terminal count register +reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock +reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock + +wire rpcie_mode; //PCIe mode signal synchronized to refclk +reg rpcie_mode_p1; //PCIe mode pipeline register + +wire rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk +reg rcpri_mod_ch_p1; //CPRI mode change pipeline register +reg rcpri_mod_ch_p2; //CPRI mode change pipeline register +reg rcpri_mod_ch_st; //CPRI mode change status + +reg [1:0] sll_state; //Current-state register for LOL FSM + +reg pll_lock; //PLL Lock signal + +//Signals running on sli_pclk +//Synchronization and pipeline registers +wire ppul_sync; +reg ppul_sync_p1; +reg ppul_sync_p2; +reg ppul_sync_p3; + +wire pdiff_sync; +reg pdiff_sync_p1; + +reg [21:0] pcount; //22-bit counter +reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value + +//Heartbeat counter and heartbeat signal running on pclk +reg [2:0] phb_cnt; +reg phb; + +//CPRI dynamic mode releated signals +reg [2:0] pcpri_mode; +reg pcpri_mod_ch; + +//Assignment scheme changed mainly for simulation purpose +wire [15:0] LRCLK_TC_w; +assign LRCLK_TC_w = LRCLK_TC; + +reg unlock; +reg lock; + +//Heartbeat synchronization +sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (phb), + .data_out(rhb_sync) + ); + + +//Terminal count pulse synchronization +sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( + .clk (sli_pclk), + .rst (sli_rst), + .data_in (rtc_pul), + .data_out(ppul_sync) + ); + +//Differential value logic update synchronization +sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (ppul_sync), + .data_out(pdiff_sync) + ); + +//Gear mode synchronization +sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_gear_mode), + .data_out(rgear) + ); + +//Div2 synchronization +sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div2_rate), + .data_out(rdiv2) + ); + +//Div11 synchronization +sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div11_rate), + .data_out(rdiv11) + ); + +//CPRI mode change synchronization +sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (pcpri_mod_ch), + .data_out(rcpri_mod_ch_sync) + ); + +//PCIe mode change synchronization +sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_pcie_mode), + .data_out(rpcie_mode) + ); + +// ============================================================================= +// Synchronized Lock/Unlock signals +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + unlock <= 1'b0; + lock <= 1'b0; + pdiff_sync_p1 <= 1'b0; + end + else begin + pdiff_sync_p1 <= pdiff_sync; + if (unlock) begin + unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock; + end + else begin + unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0; + end + if (lock) begin + lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock; + end + else begin + lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0; + end + end +end + +// ============================================================================= +// Refclk Counter, pulse generation logic and Heartbeat monitor logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount <= 16'd0; + rtc_pul <= 1'b0; + rtc_ctrl <= 1'b0; + rtc_pul_p1 <= 1'b0; + end + else begin + //Counter logic + if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + if (rtc_ctrl == 1'b1) begin + rcount <= LRCLK_TC_PUL_WIDTH; + end + end + else begin + if (rcount != LRCLK_TC_w) begin + rcount <= rcount + 1; + end + else begin + rcount <= 16'd0; + end + end + + //Pulse control logic + if (rcount == LRCLK_TC_w - 1) begin + rtc_ctrl <= 1'b1; + end + + //Pulse Generation logic + if (rtc_ctrl == 1'b1) begin + if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin + rtc_pul <= 1'b1; + end + else begin + rtc_pul <= 1'b0; + end + end + + rtc_pul_p1 <= rtc_pul; + end +end + + +// ============================================================================= +// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rhb_sync_p1 <= 1'b0; + rhb_sync_p2 <= 1'b0; + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + rgear_p1 <= 1'b0; + rdiv2_p1 <= 1'b0; + rdiv11_p1 <= 1'b0; + rcpri_mod_ch_p1 <= 1'b0; + rcpri_mod_ch_p2 <= 1'b0; + rcpri_mod_ch_st <= 1'b0; + rpcie_mode_p1 <= 1'b0; + + end + else begin + //Pipeline stages for the Heartbeat + rhb_sync_p1 <= rhb_sync; + rhb_sync_p2 <= rhb_sync_p1; + + //Pipeline stages of the Dynamic rate control signals + rgear_p1 <= rgear; + rdiv2_p1 <= rdiv2; + rdiv11_p1 <= rdiv11; + + //Pipeline stage for PCIe mode + rpcie_mode_p1 <= rpcie_mode; + + //Pipeline stage for CPRI mode change + rcpri_mod_ch_p1 <= rcpri_mod_ch_sync; + rcpri_mod_ch_p2 <= rcpri_mod_ch_p1; + + //CPRI mode change status logic + if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin + rcpri_mod_ch_st <= 1'b1; + end + + //Heartbeat wait counter and monitor logic + if (rtc_ctrl == 1'b1) begin + if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b1; + end + else if (rhb_wait_cnt == LHB_WAIT_CNT) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + end + else begin + rhb_wait_cnt <= rhb_wait_cnt + 1; + end + end + end +end + + +// ============================================================================= +// Pipleline registers for the TC pulse and CPRI mode change logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + ppul_sync_p1 <= 1'b0; + ppul_sync_p2 <= 1'b0; + ppul_sync_p3 <= 1'b0; + pcpri_mode <= 3'b0; + pcpri_mod_ch <= 1'b0; + end + else begin + ppul_sync_p1 <= ppul_sync; + ppul_sync_p2 <= ppul_sync_p1; + ppul_sync_p3 <= ppul_sync_p2; + + //CPRI mode change logic + pcpri_mode <= sli_cpri_mode; + + if (pcpri_mode != sli_cpri_mode) begin + pcpri_mod_ch <= ~pcpri_mod_ch; + end + end +end + + +// ============================================================================= +// Terminal count logic +// ============================================================================= + +//For SDI protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 11 is enabled + if (rdiv11 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_DIV11_TC; + rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0}; + rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0}; + rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0}; + end + end + //Div by 2 is enabled + else if (rdiv2 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end + //Both div by 11 and div by 2 are disabled + else begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_TC[20:0],1'b0}; + rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0}; + rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0}; + end + end + end +end +end +endgenerate + +//For G8B10B protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 2 is enabled + if (rdiv2 == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + + +//For CPRI protocol with Dynamic rate control is disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for CPRI protocol + //Only if there is a change in the rate mode from the default + if (rcpri_mod_ch_st == 1'b1) begin + if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin + case(sli_cpri_mode) + 3'd0 : begin //For 0.6Gbps + rcount_tc <= LPCLK_TC_0; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_01; + rdiff_comp_unlock <= LPDIFF_UNLOCK_01; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_02; + rdiff_comp_unlock <= LPDIFF_UNLOCK_02; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_03; + rdiff_comp_unlock <= LPDIFF_UNLOCK_03; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + + 3'd1 : begin //For 1.2Gbps + rcount_tc <= LPCLK_TC_1; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_11; + rdiff_comp_unlock <= LPDIFF_UNLOCK_11; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_12; + rdiff_comp_unlock <= LPDIFF_UNLOCK_12; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_13; + rdiff_comp_unlock <= LPDIFF_UNLOCK_13; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + endcase + end + + 3'd2 : begin //For 2.4Gbps + rcount_tc <= LPCLK_TC_2; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_21; + rdiff_comp_unlock <= LPDIFF_UNLOCK_21; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_22; + rdiff_comp_unlock <= LPDIFF_UNLOCK_22; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_23; + rdiff_comp_unlock <= LPDIFF_UNLOCK_23; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + endcase + end + + 3'd3 : begin //For 3.07Gbps + rcount_tc <= LPCLK_TC_3; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_30; + rdiff_comp_unlock <= LPDIFF_UNLOCK_30; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_31; + rdiff_comp_unlock <= LPDIFF_UNLOCK_31; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_32; + rdiff_comp_unlock <= LPDIFF_UNLOCK_32; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_33; + rdiff_comp_unlock <= LPDIFF_UNLOCK_33; + end + endcase + end + + 3'd4 : begin //For 4.9125bps + rcount_tc <= LPCLK_TC_4; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_41; + rdiff_comp_unlock <= LPDIFF_UNLOCK_41; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_42; + rdiff_comp_unlock <= LPDIFF_UNLOCK_42; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_43; + rdiff_comp_unlock <= LPDIFF_UNLOCK_43; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + endcase + end + + default : begin + rcount_tc <= LPCLK_TC_0; + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + end + else begin + //If there is no change in the CPRI rate mode from default + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + +//For PCIe protocol with Dynamic rate control disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + if (PPCIE_MAX_RATE == "2.5") begin + //2.5G mode is enabled + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //5G mode is enabled + if (rpcie_mode == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //2.5G mode is enabled + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + end + end +end +end +endgenerate + +//For all protocols other than CPRI & PCIe +generate +if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for all protocols other than CPRI & PCIe + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end +end +end +endgenerate + + +// ============================================================================= +// Tx_pclk counter, Heartbeat and Differential value logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pcount <= 22'd0; + pcount_diff <= 22'd65535; + phb_cnt <= 3'd0; + phb <= 1'b0; + end + else begin + //Counter logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount <= 22'd0; + end + else begin + pcount <= pcount + 1; + end + + //Heartbeat logic + phb_cnt <= phb_cnt + 1; + + if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin + phb <= 1'b1; + end + else begin + phb <= 1'b0; + end + + //Differential value logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount_diff <= rcount_tc + ~(pcount) + 1; + end + else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin + if (pcount_diff[21] == 1'b1) begin + pcount_diff <= ~(pcount_diff) + 1; + end + end + end +end + + +// ============================================================================= +// State transition logic for SLL FSM +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI + if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || + (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_LOSS_ST; + end + else if (lock) begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_PRELOCK_ST; + end + else begin + sll_state <= LPLL_LOCK_ST; + end + end + end + end + + LPLL_LOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + end + + LPLL_PRELOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + + LPLL_PRELOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_PRELOSS_ST; + end + else if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + end + end + + default: begin + sll_state <= LPLL_LOSS_ST; + end + endcase + end + end +end + + +// ============================================================================= +// Logic for Tx PLL Lock +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pll_lock <= 1'b0; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + pll_lock <= 1'b0; + end + + LPLL_LOCK_ST : begin + pll_lock <= 1'b1; + end + + LPLL_PRELOSS_ST : begin + pll_lock <= 1'b0; + end + + default: begin + pll_lock <= 1'b0; + end + endcase + end +end + +assign slo_plol = ~(pll_lock); + +endmodule + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : Synchronizer Logic +// File : sync.v +// Title : Synchronizer module +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : July 7, 2015 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : EB +// Mod. Date : March 21, 2017 +// Changes Made : +// ============================================================================= + +`ifndef PCS_SYNC_MODULE +`define PCS_SYNC_MODULE +module sync ( + clk, + rst, + data_in, + data_out + ); + +input clk; //Clock in which the async data needs to be synchronized to +input rst; //Active high reset +input data_in; //Asynchronous data +output data_out; //Synchronized data + +parameter PDATA_RST_VAL = 0; //Reset value for the registers + +reg data_p1; +reg data_p2; + +// ============================================================================= +// Synchronization logic +// ============================================================================= +always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + data_p1 <= PDATA_RST_VAL; + data_p2 <= PDATA_RST_VAL; + end + else begin + data_p1 <= data_in; + data_p2 <= data_p1; + end +end + +assign data_out = data_p2; + +endmodule +`endif + diff --git a/gbe_trb/media/ecp5/pmi_fifo_dcEEan163201024102410241818p12701671.ngo b/gbe_trb/media/ecp5/pmi_fifo_dcEEan163201024102410241818p12701671.ngo new file mode 100644 index 0000000..4114d27 Binary files /dev/null and b/gbe_trb/media/ecp5/pmi_fifo_dcEEan163201024102410241818p12701671.ngo differ diff --git a/gbe_trb/media/ecp5/pmi_ram_dpEbnonessdn208256208256p138702ef.ngo b/gbe_trb/media/ecp5/pmi_ram_dpEbnonessdn208256208256p138702ef.ngo new file mode 100644 index 0000000..fa13656 Binary files /dev/null and b/gbe_trb/media/ecp5/pmi_ram_dpEbnonessdn208256208256p138702ef.ngo differ diff --git a/gbe_trb/media/ecp5/pmi_ram_dpEbnonessdn96649664p13506f63.ngo b/gbe_trb/media/ecp5/pmi_ram_dpEbnonessdn96649664p13506f63.ngo new file mode 100644 index 0000000..0d70f89 Binary files /dev/null and b/gbe_trb/media/ecp5/pmi_ram_dpEbnonessdn96649664p13506f63.ngo differ diff --git a/gbe_trb/media/ecp5/rate_resolution.v b/gbe_trb/media/ecp5/rate_resolution.v new file mode 100755 index 0000000..b9edbef --- /dev/null +++ b/gbe_trb/media/ecp5/rate_resolution.v @@ -0,0 +1,66 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`timescale 1ns/100ps + +module rate_resolution ( + gbe_mode, + sgmii_mode, + an_enable, + advertised_rate, + link_partner_rate, + non_an_rate, + + operational_rate +); + +input gbe_mode; +input sgmii_mode; +input an_enable; +input [1:0] advertised_rate; // 00=10Mbps 01=100Mbps 10=1Gbps +input [1:0] link_partner_rate; +input [1:0] non_an_rate; + +output [1:0] operational_rate; +reg [1:0] operational_rate; + + + +always @(gbe_mode or sgmii_mode or an_enable or advertised_rate or link_partner_rate or non_an_rate) begin + if (gbe_mode) begin + operational_rate <= 2'b10; // 1Gbps + end + else begin + if (an_enable) begin + if (sgmii_mode) begin + // PHY Mode + operational_rate <= advertised_rate; + end + else begin + // MAC Mode + operational_rate <= link_partner_rate; + end + end + else begin + // If auto-negotiation disabled, then this becomes active rate + operational_rate <= non_an_rate; + end + end +end + + + +endmodule + diff --git a/gbe_trb/media/ecp5/register_interface_hb.v b/gbe_trb/media/ecp5/register_interface_hb.v new file mode 100755 index 0000000..028d806 --- /dev/null +++ b/gbe_trb/media/ecp5/register_interface_hb.v @@ -0,0 +1,1393 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`timescale 1ns/100ps + +module register_interface_hb ( + + // Control Signals + rst_n, + hclk, + gbe_mode, + sgmii_mode, + + // Host Bus + hcs_n, + hwrite_n, + haddr, + hdatain, + + hdataout, + hready_n, + + // Register Inputs + mr_stat_1000base_x_fd, + mr_stat_1000base_x_hd, + mr_stat_1000base_t_fd, + mr_stat_1000base_t_hd, + + mr_stat_100base_t4, + mr_stat_100base_x_fd, + mr_stat_100base_x_hd, + mr_stat_10mbps_fd, + mr_stat_10mbps_hd, + mr_stat_100base_t2_fd, + mr_stat_100base_t2_hd, + + mr_stat_extended_stat, + mr_stat_unidir_able, + mr_stat_preamb_supr, + mr_stat_an_complete, + mr_stat_remote_fault, + mr_stat_an_able, + mr_stat_link_stat, + mr_stat_jab_det, + mr_stat_extended_cap, + + mr_page_rx, + mr_lp_adv_ability, + + // Register Outputs + mr_main_reset, + mr_loopback_enable, + mr_speed_selection, + mr_an_enable, + mr_power_down, + mr_isolate, + mr_restart_an, + mr_duplex_mode, + mr_col_test, + mr_unidir_enable, + mr_adv_ability + ); + + +input rst_n ; +input hclk ; +input gbe_mode ; +input sgmii_mode ; + +input hcs_n; +input hwrite_n; +input [5:0] haddr; +input [7:0] hdatain; + +output [7:0] hdataout; +output hready_n; + +input mr_stat_1000base_x_fd; +input mr_stat_1000base_x_hd; +input mr_stat_1000base_t_fd; +input mr_stat_1000base_t_hd; + +input mr_stat_100base_t4; +input mr_stat_100base_x_fd; +input mr_stat_100base_x_hd; +input mr_stat_10mbps_fd; +input mr_stat_10mbps_hd; +input mr_stat_100base_t2_fd; +input mr_stat_100base_t2_hd; + +input mr_stat_extended_stat; +input mr_stat_unidir_able; +input mr_stat_preamb_supr; +input mr_stat_an_complete; +input mr_stat_remote_fault; +input mr_stat_an_able; +input mr_stat_link_stat; +input mr_stat_jab_det; +input mr_stat_extended_cap; + +input mr_page_rx; +input [15:0] mr_lp_adv_ability; + +output mr_main_reset; +output mr_loopback_enable; +output [1:0] mr_speed_selection; +output mr_an_enable; +output mr_power_down; +output mr_isolate; +output mr_restart_an; +output mr_duplex_mode; +output mr_col_test; +output mr_unidir_enable; +output [15:0] mr_adv_ability; + +regs_hb regs ( + .rst_n (rst_n), + .hclk (hclk), + + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + + .hcs_n (hcs_n), + .hwrite_n (hwrite_n), + .haddr (haddr), + .hdatain (hdatain), + + .hdataout (hdataout), + .hready_n (hready_n), + + .mr_stat_1000base_x_fd (mr_stat_1000base_x_fd), + .mr_stat_1000base_x_hd (mr_stat_1000base_x_hd), + .mr_stat_1000base_t_fd (mr_stat_1000base_t_fd), + .mr_stat_1000base_t_hd (mr_stat_1000base_t_hd), + + .mr_stat_100base_t4 (mr_stat_100base_t4), + .mr_stat_100base_x_fd (mr_stat_100base_x_fd), + .mr_stat_100base_x_hd (mr_stat_100base_x_hd), + .mr_stat_10mbps_fd (mr_stat_10mbps_fd), + .mr_stat_10mbps_hd (mr_stat_10mbps_hd), + .mr_stat_100base_t2_fd (mr_stat_100base_t2_fd), + .mr_stat_100base_t2_hd (mr_stat_100base_t2_hd), + + .mr_stat_extended_stat (mr_stat_extended_stat), + .mr_stat_unidir_able (mr_stat_unidir_able), + .mr_stat_preamb_supr (mr_stat_preamb_supr), + .mr_stat_an_complete (mr_stat_an_complete), + .mr_stat_remote_fault (mr_stat_remote_fault), + .mr_stat_an_able (mr_stat_an_able), + .mr_stat_link_stat (mr_stat_link_stat), + .mr_stat_jab_det (mr_stat_jab_det), + .mr_stat_extended_cap (mr_stat_extended_cap), + + .mr_page_rx (mr_page_rx), + .mr_lp_adv_ability (mr_lp_adv_ability), + + .mr_main_reset (mr_main_reset), + .mr_loopback_enable (mr_loopback_enable), + .mr_speed_selection (mr_speed_selection), + .mr_an_enable (mr_an_enable), + .mr_power_down (mr_power_down), + .mr_isolate (mr_isolate), + .mr_restart_an (mr_restart_an), + .mr_duplex_mode (mr_duplex_mode), + .mr_col_test (mr_col_test), + .mr_unidir_enable (mr_unidir_enable), + + .mr_adv_ability (mr_adv_ability) +); +endmodule + + + + + + +module register_0_hb ( + rst_n, + clk, + gbe_mode, + cs_0, + cs_1, + write, + ready, + data_in, + + data_out, + mr_main_reset, + mr_loopback_enable, + mr_speed_selection, + mr_an_enable, + mr_power_down, + mr_isolate, + mr_restart_an, + mr_duplex_mode, + mr_col_test, + mr_unidir_enable +); + +input rst_n; +input clk; +input gbe_mode; +input cs_0; +input cs_1; +input write; +input ready; +input [15:0] data_in; + +output [15:0] data_out; +output mr_main_reset; // bit D15 // R/W // Self Clearing +output mr_loopback_enable; // bit D14 // R/W +output [1:0] mr_speed_selection; // bit D13 LSB bit D6 MSB // R/W +output mr_an_enable; // bit D12 // R/W +output mr_power_down; // bit D11 // R/W +output mr_isolate; // bit D10 // R/W +output mr_restart_an; // bit D09 // R/W // Self Clearing +output mr_duplex_mode; // bit D08 // STUCK HIGH +output mr_col_test; // bit D08 // STUCK LOW +output mr_unidir_enable; // bit D05 // STUCK LOW + +reg [15:0] data_out; +reg mr_main_reset; +reg mr_loopback_enable; +reg [1:0] mr_speed_selection; +reg mr_an_enable; +reg mr_power_down = 1'b0; +reg mr_isolate; +reg mr_restart_an; +reg mr_duplex_mode; +reg mr_col_test; +reg mr_unidir_enable; +reg m_m_r; +reg m_r_a; +reg gbe_mode_d1; +reg gbe_mode_d2; + + + +// Deboggle +always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + gbe_mode_d1 <= 0; + gbe_mode_d2 <= 0; + end + else begin + gbe_mode_d1 <= gbe_mode; + gbe_mode_d2 <= gbe_mode_d1; + end +end + + + +// Write Operations + + // Low Portion of Register[D7:D0] has no + // implemented bits. Therefore, no write + // operations here. + + // High Portion of Register[D15:D8] + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + mr_main_reset <= 1'b0; + mr_loopback_enable <= 1'b0; + mr_speed_selection <= 2'b10; + mr_an_enable <= 1'b1; + mr_power_down <= 1'b0; + mr_isolate <= 1'b0; + mr_restart_an <= 1'b0; + mr_duplex_mode <= 1'b1; + mr_col_test <= 1'b0; + mr_unidir_enable <= 1'b0; + m_m_r <= 0; + m_r_a <= 0; + end + else begin + + // defaults + mr_duplex_mode <= 1'b1; // STUCK HIGH + mr_col_test <= 1'b0; // STUCK LOW + + // Do the Writes + if (cs_1 && ready && write) begin + mr_main_reset <= data_in[15]; + mr_loopback_enable <= data_in[14]; + mr_an_enable <= data_in[12]; + mr_power_down <= data_in[11]; + mr_isolate <= data_in[10]; + mr_restart_an <= data_in[9]; + end + + + // Manage Writes to Speed Selection Based on GBE MODE + if (gbe_mode_d2) begin + mr_speed_selection[1:0] <= 2'b10; // STUCK AT 1GBPS + end + else begin + if (cs_1 && ready && write) begin + mr_speed_selection[0] <= data_in[13]; + end + if (cs_0 && ready && write) begin + mr_speed_selection[1] <= data_in[6]; + mr_unidir_enable <= data_in[5]; + end + end + + + + // Delay the Self Clearing Register Bits + m_m_r <= mr_main_reset; + m_r_a <= mr_restart_an; + + // Do the Self Clearing + if (m_m_r) + mr_main_reset <= 0; + + if (m_r_a) + mr_restart_an <= 0; + end + end + + + + + +// Read Operations + always @(*) begin + data_out[7] <= mr_col_test; + data_out[6] <= mr_speed_selection[1]; + data_out[5] <= mr_unidir_enable; + data_out[4] <= 1'b0; + data_out[3] <= 1'b0; + data_out[2] <= 1'b0; + data_out[1] <= 1'b0; + data_out[0] <= 1'b0; + + data_out[15] <= mr_main_reset; + data_out[14] <= mr_loopback_enable; + data_out[13] <= mr_speed_selection[0]; + data_out[12] <= mr_an_enable; + data_out[11] <= mr_power_down; + data_out[10] <= mr_isolate; + data_out[9] <= mr_restart_an; + data_out[8] <= mr_duplex_mode; + end +endmodule + +module register_1_hb ( + rst_n, + clk, + cs_0, + cs_1, + write, + ready, + + + mr_stat_100base_t4, + mr_stat_100base_x_fd, + mr_stat_100base_x_hd, + mr_stat_10mbps_fd, + mr_stat_10mbps_hd, + mr_stat_100base_t2_fd, + mr_stat_100base_t2_hd, + + mr_stat_extended_stat, + mr_stat_unidir_able, + mr_stat_preamb_supr, + mr_stat_an_complete, + mr_stat_remote_fault, + mr_stat_an_able, + mr_stat_link_stat, + mr_stat_jab_det, + mr_stat_extended_cap, + + data_out +); + +input rst_n; +input clk; +input cs_0; +input cs_1; +input write; +input ready; +input mr_stat_100base_t4; // bit D15 // Read-Only +input mr_stat_100base_x_fd; // bit D14 // Read-Only +input mr_stat_100base_x_hd; // bit D13 // Read-Only +input mr_stat_10mbps_fd; // bit D12 // Read-Only +input mr_stat_10mbps_hd; // bit D11 // Read-Only +input mr_stat_100base_t2_fd; // bit D10 // Read-Only +input mr_stat_100base_t2_hd; // bit D9 // Read-Only + +input mr_stat_extended_stat; // bit D8 // Read-Only +input mr_stat_unidir_able; // bit D7 // Read-Only +input mr_stat_preamb_supr; // bit D6 // Read-Only +input mr_stat_an_complete; // bit D5 // Read-Only +input mr_stat_remote_fault; // bit D4 // Read-Only +input mr_stat_an_able; // bit D3 // Read-Only +input mr_stat_link_stat; // bit D2 // Read-Only // Latch-On-Zero // Clear-On-Read +input mr_stat_jab_det; // bit D1 // Read-Only +input mr_stat_extended_cap; // bit D0 // Read-Only + +output [15:0] data_out; + +reg [15:0] data_out; + +reg link_stat_d1; +reg link_stat_d2; +reg clear_on_read; +reg read_detect; +reg rd_d1; +reg rd_d2; +reg allow_link_stat; +reg link_ok_status; +// metastability filter + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + link_stat_d1 <= 1'b0; + link_stat_d2 <= 1'b0; + end + else begin + link_stat_d1 <= mr_stat_link_stat; + link_stat_d2 <= link_stat_d1; + end + end + +// generate clear-on-read signal + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + clear_on_read <= 1'b0; + read_detect <= 1'b0; + rd_d1 <= 1'b0; + rd_d2 <= 1'b0; + end + else begin + if (!write && ready && cs_0) + read_detect <= 1'b1; + else + read_detect <= 1'b0; + + rd_d1 <= read_detect; + rd_d2 <= rd_d1; + + // assert on falling edge of rd_d2 + clear_on_read <= !rd_d1 & rd_d2; + end + end + + +// Latch and Clear + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + allow_link_stat <= 1'b0; + link_ok_status <= 1'b0; + end + else begin + + case (allow_link_stat) + 1'b0: begin + if (clear_on_read) begin + allow_link_stat<= 1'b1; + end + end + + 1'b1: begin + if (!link_stat_d2) begin + allow_link_stat <= 1'b0; + end + end + endcase + + + if (allow_link_stat) begin + // allow status shoot-thru after clear-on-read + link_ok_status <= link_stat_d2; + end + else begin + // force status low when link IS NOT_OKAY + link_ok_status <= 1'b0; + end + + end + end + + +// Read Operations + + always @(*) begin + data_out[7] <= mr_stat_unidir_able; + data_out[6] <= mr_stat_preamb_supr; + data_out[5] <= mr_stat_an_complete; + data_out[4] <= mr_stat_remote_fault; + data_out[3] <= mr_stat_an_able; + data_out[2] <= link_ok_status; + data_out[1] <= mr_stat_jab_det; + data_out[0] <= mr_stat_extended_cap; + + data_out[15] <= mr_stat_100base_t4; + data_out[14] <= mr_stat_100base_x_fd; + data_out[13] <= mr_stat_100base_x_hd; + data_out[12] <= mr_stat_10mbps_fd; + data_out[11] <= mr_stat_10mbps_hd; + data_out[10] <= mr_stat_100base_t2_fd; + data_out[9] <= mr_stat_100base_t2_hd; + data_out[8] <= mr_stat_extended_stat; + end +endmodule + +module register_4_hb ( + rst_n, + clk, + gbe_mode, + sgmii_mode, + cs_0, + cs_1, + write, + ready, + data_in, + + data_out, + mr_adv_ability +); + +parameter [15:0] initval_gbe = 16'h0020; +parameter [15:0] initval_phy = 16'hd801; +parameter [15:0] initval_mac = 16'h4001; + +input rst_n; +input clk; +input gbe_mode; +input sgmii_mode; +input cs_0; +input cs_1; +input write; +input ready; +input [15:0] data_in; + +output [15:0] data_out; +output [15:0] mr_adv_ability; // When sgmii_mode == 1 == PHY + // all bits D15-D0 are R/W, + /////////////////////////////////// + // D15 = Link Status (1=up, 0=down) + // D14 = Can be written but has no effect + // on autonegotiation. Instead + // the autonegotiation state machine + // controls the utilization of this bit. + // D12 = Duplex Mode (1=full, 0=half) + // D11:10 = Speed (11=reserved) + // (10=1000Mbps) + // (01=100 Mbps) + // (00=10 Mbps) + // D0 = 1 + // all other bits = 0 + /////////////////////////////////// + //When sgmii_mode == 0 = MAC + // all bits D15-D0 are R/W, + // D14 = Can be written but has no effect + // on autonegotiation. Instead + // the autonegotiation state machine + // controls the utilization of this bit. + // D0 = 1 + // all other bits = 0 + /////////////////////////////////// + + +reg [15:0] data_out; +reg [15:0] mr_adv_ability; +reg rst_d1; +reg rst_d2; +reg rst_d3; +reg rst_d4; +reg rst_d5; +reg rst_d6; +reg rst_d7; +reg rst_d8; +reg sync_reset; +reg sgmii_mode_d1; +reg sgmii_mode_d2; +reg sgmii_mode_d3; +reg sgmii_mode_d4; +reg sgmii_mode_change; +reg gbe_mode_d1; +reg gbe_mode_d2; +reg gbe_mode_d3; +reg gbe_mode_d4; +reg gbe_mode_change; + +// generate a synchronous reset signal +// note: this method is used so that +// an initval can be applied during +// device run-time, instead of at compile time +always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + rst_d1 <= 0; + rst_d2 <= 0; + rst_d3 <= 0; + rst_d4 <= 0; + rst_d5 <= 0; + rst_d6 <= 0; + rst_d7 <= 0; + rst_d8 <= 0; + sync_reset <= 0; + end + else begin + rst_d1 <= 1; + rst_d2 <= rst_d1; + rst_d3 <= rst_d2; + rst_d4 <= rst_d3; + rst_d5 <= rst_d4; + rst_d6 <= rst_d5; + rst_d7 <= rst_d6; + rst_d8 <= rst_d7; + + // asserts on rising edge of rst_d8 + sync_reset <= !rst_d8 & rst_d7; + end +end + + +// Detect change in sgmii_mode +always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + sgmii_mode_d1 <= 0; + sgmii_mode_d2 <= 0; + sgmii_mode_d3 <= 0; + sgmii_mode_d4 <= 0; + sgmii_mode_change <= 0; + end + else begin + + // deboggle + sgmii_mode_d1 <= sgmii_mode; + sgmii_mode_d2 <= sgmii_mode_d1; + + // delay + sgmii_mode_d3 <= sgmii_mode_d2; + sgmii_mode_d4 <= sgmii_mode_d3; + + // detect change + if (sgmii_mode_d3 != sgmii_mode_d4) + sgmii_mode_change <= 1; + else + sgmii_mode_change <= 0; + end +end + + +// Detect change in gbe_mode +always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + gbe_mode_d1 <= 0; + gbe_mode_d2 <= 0; + gbe_mode_d3 <= 0; + gbe_mode_d4 <= 0; + gbe_mode_change <= 0; + end + else begin + + // deboggle + gbe_mode_d1 <= gbe_mode; + gbe_mode_d2 <= gbe_mode_d1; + + // delay + gbe_mode_d3 <= gbe_mode_d2; + gbe_mode_d4 <= gbe_mode_d3; + + // detect change + if (gbe_mode_d3 != gbe_mode_d4) + gbe_mode_change <= 1; + else + gbe_mode_change <= 0; + end +end + + +// Write Operations + // Low Portion of Register[D7:D0] + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + mr_adv_ability[7:0] <= 8'h01; + end + else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin + if (gbe_mode_d4) + mr_adv_ability[7:0] <= initval_gbe[7:0]; + else if (sgmii_mode) + mr_adv_ability[7:0] <= initval_phy[7:0]; + else + mr_adv_ability[7:0] <= initval_mac[7:0]; + end + else begin + if (cs_0 && ready && write && (sgmii_mode || gbe_mode)) begin + mr_adv_ability[7:0] <= data_in[7:0]; + end + end + end + + + // High Portion of Register[D15:D8] + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + mr_adv_ability[15:8] <= 8'h40; // default + end + else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin + if (gbe_mode_d4) + mr_adv_ability[15:8] <= initval_gbe[15:8]; + else if (sgmii_mode) + mr_adv_ability[15:8] <= initval_phy[15:8]; + else + mr_adv_ability[15:8] <= initval_mac[15:8]; + end + else begin + if (cs_1 && ready && write && (sgmii_mode || gbe_mode)) begin + mr_adv_ability[15:8] <= data_in[15:8]; + end + end + end + + + + + + + + + +// Read Operations + + always @(*) begin + data_out[7:0] <= mr_adv_ability[7:0]; + data_out[15:8] <= mr_adv_ability[15:8]; + end + +endmodule + + + + + + +module register_5_hb ( + rst_n, + mr_lp_adv_ability, + cs_0, + cs_1, + ready, + + data_out +); + +input rst_n; +input cs_0; +input cs_1; +input ready; +input [15:0] mr_lp_adv_ability; + // This entire register is read-only + /////////////////////////////////// + // When sgmii_mode == 0 == MAC + /////////////////////////////////// + // D15 = PHY Link Status (1=up, 0=down) + // D14 = PHY Autonegotiation Handshake + // D12 = PHY Duplex Mode (1=full, 0=half) + // D11:10 = PHY Speed (11=reserved) + // (10=1000Mbps) + // (01=100 Mbps) + // (00=10 Mbps) + // D0 = 1 + // all other bits = 0 + /////////////////////////////////// + //When sgmii_mode == 1 = PHY + // D14 = MAC Autonegotiation Handshake + // D0 = 1 + // all other bits = 0 + /////////////////////////////////// +output [15:0] data_out; + +reg [15:0] data_out; + +// Read Operations + + always @(*) begin + data_out[7:0] <= mr_lp_adv_ability[7:0]; + data_out[15:8] <= mr_lp_adv_ability[15:8]; + end +endmodule + +module register_6_hb ( + rst_n, + clk, + mr_page_rx, + cs_0, + cs_1, + write, + ready, + + data_out +); + +input rst_n; +input clk; +input cs_0; +input cs_1; +input write; +input ready; +input mr_page_rx; +output [15:0] data_out; + +reg [15:0] data_out; +reg mr_page_rx_latched; +reg clear_on_read; +reg read_detect; +reg rd_d1; +reg rd_d2; + +// generate clear-on-read signal + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + clear_on_read <= 0; + read_detect <= 0; + rd_d1 <= 0; + rd_d2 <= 0; + end + else begin + if (!write && ready && cs_0) + read_detect <= 1; + else + read_detect <= 0; + + rd_d1 <= read_detect; + rd_d2 <= rd_d1; + + // assert on falling edge of rd_d2 + clear_on_read <= !rd_d1 & rd_d2; + end + end + + +// Latch and Clear + always @(posedge clk or negedge rst_n) begin + if (rst_n == 1'b0) begin + mr_page_rx_latched <= 0; + end + else begin + if (clear_on_read) + mr_page_rx_latched <= 0; + else if (mr_page_rx) + mr_page_rx_latched <= 1; + end + end + + +// Read Operations + + always @(*) begin + data_out[15:2] <= 14'd0; + data_out[1] <= mr_page_rx_latched; + data_out[0] <= 0; + end +endmodule + + +module register_f_hb ( + rst_n, + cs_0, + cs_1, + + mr_stat_1000base_x_fd, + mr_stat_1000base_x_hd, + mr_stat_1000base_t_fd, + mr_stat_1000base_t_hd, + + data_out +); + +input rst_n; +input cs_0; +input cs_1; + +input mr_stat_1000base_x_fd; // bit D15 // Read-Only +input mr_stat_1000base_x_hd; // bit D14 // Read-Only +input mr_stat_1000base_t_fd; // bit D13 // Read-Only +input mr_stat_1000base_t_hd; // bit D12 // Read-Only + +output [15:0] data_out; + +reg [15:0] data_out; + + +// Read Operations + + always @(*) begin + data_out[7] <= 1'b0; + data_out[6] <= 1'b0; + data_out[5] <= 1'b0; + data_out[4] <= 1'b0; + data_out[3] <= 1'b0; + data_out[2] <= 1'b0; + data_out[1] <= 1'b0; + data_out[0] <= 1'b0; + + data_out[15] <= mr_stat_1000base_x_fd; + data_out[14] <= mr_stat_1000base_x_hd; + data_out[13] <= mr_stat_1000base_t_fd; + data_out[12] <= mr_stat_1000base_t_hd; + data_out[11] <= 1'b0; + data_out[10] <= 1'b0; + data_out[9] <= 1'b0; + data_out[8] <= 1'b0; + end +endmodule + + +module regs_hb ( + rst_n, + hclk, + gbe_mode, + sgmii_mode, + hcs_n, + hwrite_n, + haddr, + hdatain, + + hdataout, + hready_n, + + mr_stat_1000base_x_fd, + mr_stat_1000base_x_hd, + mr_stat_1000base_t_fd, + mr_stat_1000base_t_hd, + + mr_stat_100base_t4, + mr_stat_100base_x_fd, + mr_stat_100base_x_hd, + mr_stat_10mbps_fd, + mr_stat_10mbps_hd, + mr_stat_100base_t2_fd, + mr_stat_100base_t2_hd, + + mr_stat_extended_stat, + mr_stat_unidir_able, + mr_stat_preamb_supr, + mr_stat_an_complete, + mr_stat_remote_fault, + mr_stat_an_able, + mr_stat_link_stat, + mr_stat_jab_det, + mr_stat_extended_cap, + + mr_page_rx, + mr_lp_adv_ability, + + mr_main_reset, + mr_loopback_enable, + mr_speed_selection, + mr_an_enable, + mr_power_down, + mr_isolate, + mr_restart_an, + mr_duplex_mode, + mr_col_test, + mr_unidir_enable, + mr_adv_ability +); + +input rst_n; +input hclk; +input gbe_mode; +input sgmii_mode; +input hcs_n; +input hwrite_n; +input [5:0] haddr; +input [7:0] hdatain; + +output [7:0] hdataout; +output hready_n; + +input mr_stat_1000base_x_fd; +input mr_stat_1000base_x_hd; +input mr_stat_1000base_t_fd; +input mr_stat_1000base_t_hd; + +input mr_stat_100base_t4; +input mr_stat_100base_x_fd; +input mr_stat_100base_x_hd; +input mr_stat_10mbps_fd; +input mr_stat_10mbps_hd; +input mr_stat_100base_t2_fd; +input mr_stat_100base_t2_hd; + +input mr_stat_extended_stat; +input mr_stat_unidir_able; +input mr_stat_preamb_supr; +input mr_stat_an_complete; +input mr_stat_remote_fault; +input mr_stat_an_able; +input mr_stat_link_stat; +input mr_stat_jab_det; +input mr_stat_extended_cap; + +input mr_page_rx; +input [15:0] mr_lp_adv_ability; + +output mr_main_reset; +output mr_loopback_enable; +output [1:0] mr_speed_selection; +output mr_an_enable; +output mr_power_down; +output mr_isolate; +output mr_restart_an; +output mr_duplex_mode; +output mr_col_test; +output mr_unidir_enable; +output [15:0] mr_adv_ability; + +/////////////////////////////////// + + + +reg [7:0] hdataout; +reg hr; +reg hready_n; + +reg hcs_n_delayed; + +wire reg0_cs_0; +wire reg0_cs_1; + +wire reg1_cs_0; +wire reg1_cs_1; + +wire reg4_cs_0; +wire reg4_cs_1; + +wire reg5_cs_0; +wire reg5_cs_1; + +wire reg6_cs_0; +wire reg6_cs_1; + +wire regf_cs_0; +wire regf_cs_1; + +wire [15:0] data_out_reg_0; +wire [15:0] data_out_reg_1; +wire [15:0] data_out_reg_4; +wire [15:0] data_out_reg_5; +wire [15:0] data_out_reg_6; +wire [15:0] data_out_reg_f; + + + +register_addr_decoder ad_dec ( + .rst_n(rst_n), + .addr(haddr), + .cs_in(~hcs_n), + + .reg0_cs_0 (reg0_cs_0), + .reg0_cs_1 (reg0_cs_1), + .reg1_cs_0 (reg1_cs_0), + .reg1_cs_1 (reg1_cs_1), + .reg4_cs_0 (reg4_cs_0), + .reg4_cs_1 (reg4_cs_1), + .reg5_cs_0 (reg5_cs_0), + .reg5_cs_1 (reg5_cs_1), + .reg6_cs_0 (reg6_cs_0), + .reg6_cs_1 (reg6_cs_1), + .regf_cs_0 (regf_cs_0), + .regf_cs_1 (regf_cs_1) +); + + +register_0_hb register_0 ( + .rst_n (rst_n), + .clk (hclk), + .gbe_mode (gbe_mode), + .cs_0 (reg0_cs_0), + .cs_1 (reg0_cs_1), + .write (~hwrite_n), + .ready (1'b1), + .data_in ({hdatain, hdatain}), + + .data_out (data_out_reg_0), + .mr_main_reset (mr_main_reset), + .mr_loopback_enable (mr_loopback_enable), + .mr_speed_selection (mr_speed_selection), + .mr_an_enable (mr_an_enable), + .mr_power_down (mr_power_down), + .mr_isolate (mr_isolate), + .mr_restart_an (mr_restart_an), + .mr_duplex_mode (mr_duplex_mode), + .mr_col_test (mr_col_test), + .mr_unidir_enable (mr_unidir_enable) +); + + +register_1_hb register_1 ( + .rst_n (rst_n), + .clk (hclk), + .cs_0 (reg1_cs_0), + .cs_1 (reg1_cs_1), + .write (~hwrite_n), + .ready (1'b1), + + .mr_stat_100base_t4 (mr_stat_100base_t4), + .mr_stat_100base_x_fd (mr_stat_100base_x_fd), + .mr_stat_100base_x_hd (mr_stat_100base_x_hd), + .mr_stat_10mbps_fd (mr_stat_10mbps_fd), + .mr_stat_10mbps_hd (mr_stat_10mbps_hd), + .mr_stat_100base_t2_fd (mr_stat_100base_t2_fd), + .mr_stat_100base_t2_hd (mr_stat_100base_t2_hd), + + .mr_stat_extended_stat (mr_stat_extended_stat), + .mr_stat_unidir_able (mr_stat_unidir_able), + .mr_stat_preamb_supr (mr_stat_preamb_supr), + .mr_stat_an_complete (mr_stat_an_complete), + .mr_stat_remote_fault (mr_stat_remote_fault), + .mr_stat_an_able (mr_stat_an_able), + .mr_stat_link_stat (mr_stat_link_stat), + .mr_stat_jab_det (mr_stat_jab_det), + .mr_stat_extended_cap (mr_stat_extended_cap), + + .data_out (data_out_reg_1) +); + + +register_4_hb register_4 ( + .rst_n (rst_n), + .clk (hclk), + .gbe_mode (gbe_mode), + .sgmii_mode (sgmii_mode), + .cs_0 (reg4_cs_0), + .cs_1 (reg4_cs_1), + .write (~hwrite_n), + .ready (1'b1), + .data_in ({hdatain, hdatain}), + + .data_out (data_out_reg_4), + .mr_adv_ability (mr_adv_ability) +); + + +register_5_hb register_5 ( + .rst_n (rst_n), + .mr_lp_adv_ability (mr_lp_adv_ability), + .cs_0 (reg5_cs_0), + .cs_1 (reg5_cs_1), + .ready (1'b1), + + .data_out (data_out_reg_5) +); + + +register_6_hb register_6 ( + .rst_n (rst_n), + .clk (hclk), + .mr_page_rx (mr_page_rx), + .cs_0 (reg6_cs_0), + .cs_1 (reg6_cs_1), + .write (~hwrite_n), + .ready (1'b1), + + .data_out (data_out_reg_6) +); + + + +register_f_hb register_f ( + .rst_n (rst_n), + .cs_0 (regf_cs_0), + .cs_1 (regf_cs_1), + + .mr_stat_1000base_x_fd (mr_stat_1000base_x_fd), + .mr_stat_1000base_x_hd (mr_stat_1000base_x_hd), + .mr_stat_1000base_t_fd (mr_stat_1000base_t_fd), + .mr_stat_1000base_t_hd (mr_stat_1000base_t_hd), + + .data_out (data_out_reg_f) +); + + +// generate an ack +always @(posedge hclk or negedge rst_n) begin + if (rst_n == 1'b0) begin + hcs_n_delayed <= 1'b1; + hr <= 1'b1; + hready_n <= 1'b1; + end + else begin + hcs_n_delayed <= hcs_n; + + //assert on falling edge of delayed chip select + hr <= ~hcs_n & hcs_n_delayed; + hready_n <= ~hr; + end +end + + + +// Mux Register Read-Data Outputs +always @(posedge hclk or negedge rst_n) +begin + if (rst_n == 1'b0) begin + hdataout <= 8'd0; + end + else begin + case (haddr[5:0]) + + 6'd0: + begin + hdataout <= data_out_reg_0[7:0]; + end + + + 6'd1: + begin + hdataout <= data_out_reg_0[15:8]; + end + + ///////////////////////////////////////////// + + 6'd2: + begin + hdataout <= data_out_reg_1[7:0]; + end + + + 6'd3: + begin + hdataout <= data_out_reg_1[15:8]; + end + + ///////////////////////////////////////////// + + 6'd8: + begin + hdataout <= data_out_reg_4[7:0]; + end + + + 6'd9: + begin + hdataout <= data_out_reg_4[15:8]; + end + + ///////////////////////////////////////////// + + 6'd10: + begin + hdataout <= data_out_reg_5[7:0]; + end + + + 6'd11: + begin + hdataout <= data_out_reg_5[15:8]; + end + + ///////////////////////////////////////////// + + 6'd12: + begin + hdataout <= data_out_reg_6[7:0]; + end + + + 6'd13: + begin + hdataout <= data_out_reg_6[15:8]; + end + + ///////////////////////////////////////////// + + 6'd30: + begin + hdataout <= data_out_reg_f[7:0]; + end + + + 6'd31: + begin + hdataout <= data_out_reg_f[15:8]; + end + + ///////////////////////////////////////////// + + default: + begin + hdataout <= 8'd0; + end + endcase + end +end + +endmodule + +module register_addr_decoder ( + rst_n, + addr, + cs_in, + + reg0_cs_0, + reg0_cs_1, + + reg1_cs_0, + reg1_cs_1, + + reg4_cs_0, + reg4_cs_1, + + reg5_cs_0, + reg5_cs_1, + + reg6_cs_0, + reg6_cs_1, + + regf_cs_0, + regf_cs_1 +); + +input rst_n; +input cs_in; +input [5:0] addr; + +output reg0_cs_0; +output reg0_cs_1; + +output reg1_cs_0; +output reg1_cs_1; + +output reg4_cs_0; +output reg4_cs_1; + +output reg5_cs_0; +output reg5_cs_1; + +output reg6_cs_0; +output reg6_cs_1; + +output regf_cs_0; +output regf_cs_1; + +////////////////////////// + +wire reg0_cs_0; +wire reg0_cs_1; + +wire reg1_cs_0; +wire reg1_cs_1; + +wire reg4_cs_0; +wire reg4_cs_1; + +wire reg5_cs_0; +wire reg5_cs_1; + +wire reg6_cs_0; +wire reg6_cs_1; + +wire regf_cs_0; +wire regf_cs_1; + +////////////////////////// + +assign reg0_cs_0 = (addr == 6'h00) ? cs_in : 1'b0; +assign reg0_cs_1 = (addr == 6'h01) ? cs_in : 1'b0; + +assign reg1_cs_0 = (addr == 6'h02) ? cs_in : 1'b0; +assign reg1_cs_1 = (addr == 6'h03) ? cs_in : 1'b0; + +assign reg4_cs_0 = (addr == 6'h08) ? cs_in : 1'b0; +assign reg4_cs_1 = (addr == 6'h09) ? cs_in : 1'b0; + +assign reg5_cs_0 = (addr == 6'h0a) ? cs_in : 1'b0; +assign reg5_cs_1 = (addr == 6'h0b) ? cs_in : 1'b0; + +assign reg6_cs_0 = (addr == 6'h0c) ? cs_in : 1'b0; +assign reg6_cs_1 = (addr == 6'h0d) ? cs_in : 1'b0; + +assign regf_cs_0 = (addr == 6'h1e) ? cs_in : 1'b0; +assign regf_cs_1 = (addr == 6'h1f) ? cs_in : 1'b0; + + +endmodule + diff --git a/gbe_trb/media/ecp5/sgmii_channel_smi.v b/gbe_trb/media/ecp5/sgmii_channel_smi.v new file mode 100644 index 0000000..7727c68 --- /dev/null +++ b/gbe_trb/media/ecp5/sgmii_channel_smi.v @@ -0,0 +1,230 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`define SGMII_YES_SINGLE_CLOCK + +module sgmii_channel_smi (//_core + + // Control Interface + rst_n, + signal_detect, + gbe_mode, + sgmii_mode, + operational_rate, + debug_link_timer_short, + force_isolate, + force_loopback, + force_unidir, + + rx_compensation_err, + ctc_drop_flag, + ctc_add_flag, + an_link_ok, + + // G/MII Interface +`ifdef SGMII_YES_SINGLE_CLOCK + tx_clock_enable_sink , + tx_clock_enable_source , + + rx_clock_enable_sink , + rx_clock_enable_source , +`else + tx_clk_mii , + rx_clk_mii , +`endif + tx_clk_125, + tx_d, + tx_en, + tx_er, + + rx_clk_125, + rx_d, + rx_dv, + rx_er, + col, + crs, + + // 8-bit Interface + tx_data, + tx_kcntl, + tx_disparity_cntl, + xmit_autoneg, + + serdes_recovered_clk, + rx_data, + rx_kcntl, + rx_even , + rx_disp_err , + rx_cv_err , + rx_err_decode_mode , + + // Managment Control Outputs + mr_an_complete, + mr_page_rx, + mr_lp_adv_ability, + + // Managment Control Inputs + mr_main_reset, + mr_an_enable, + mr_restart_an, + mr_adv_ability + ); + + + +// Control Interface +input rst_n ; +input signal_detect ; +input gbe_mode ; +input sgmii_mode ; +input [1:0] operational_rate ; +input debug_link_timer_short ; +input force_isolate ; +input force_loopback ; +input force_unidir ; + +output rx_compensation_err ; +output ctc_drop_flag ; +output ctc_add_flag ; +output an_link_ok ; + +// G/MII Interface +`ifdef SGMII_YES_SINGLE_CLOCK + input tx_clock_enable_sink; + output tx_clock_enable_source; + + input rx_clock_enable_sink; + output rx_clock_enable_source; +`else + input tx_clk_mii; + input rx_clk_mii; +`endif + +input tx_clk_125 ; +input [7:0] tx_d ; +input tx_en ; +input tx_er ; + +input rx_clk_125 ; +output [7:0] rx_d ; +output rx_dv ; +output rx_er ; +output col ; +output crs ; + +// 8-bit Interface +output [7:0] tx_data ; +output tx_kcntl; +output tx_disparity_cntl; +output xmit_autoneg; + +input serdes_recovered_clk ; +input [7:0] rx_data ; +input rx_even ; +input rx_kcntl; +input rx_disp_err ; // Displarity error on "rx_data". +input rx_cv_err ; // Code error on "rx_data". +input rx_err_decode_mode ; + +// Managment Control Outputs +output mr_an_complete; +output mr_page_rx; +output [15:0] mr_lp_adv_ability; + +// Managment Control Inputs +input mr_main_reset; +input mr_an_enable; +input mr_restart_an; +input [15:0] mr_adv_ability; + + +parameter STATIC_HI_THRESH = 32; +parameter STATIC_LO_THRESH = 16; +parameter LINK_TIMER_SH = 21'h1fff01; + + + +// SGMII PCS +sgmii_pcs_gda_001 # (.STATIC_HI_THRESH(STATIC_HI_THRESH), .STATIC_LO_THRESH(STATIC_LO_THRESH), .LINK_TIMER_SH(LINK_TIMER_SH)) sgmii_pcs_gda_001 ( + // Clock and Reset + .rst_n ( rst_n ) , + .signal_detect ( signal_detect ) , + .gbe_mode ( gbe_mode ) , + .sgmii_mode ( sgmii_mode ) , + .operational_rate ( operational_rate ) , + .debug_link_timer_short ( debug_link_timer_short ) , + .force_isolate ( force_isolate ) , + .force_loopback ( force_loopback ) , + .force_unidir ( force_unidir ) , + + .rx_compensation_err ( rx_compensation_err ) , + .ctc_drop_flag ( ctc_drop_flag ) , + .ctc_add_flag ( ctc_add_flag ) , + .an_link_ok ( an_link_ok ) , + +`ifdef SGMII_YES_SINGLE_CLOCK + .tx_clock_enable_sink ( tx_clock_enable_sink ), + .tx_clock_enable_source ( tx_clock_enable_source ), + + .rx_clock_enable_sink ( rx_clock_enable_sink ), + .rx_clock_enable_source ( rx_clock_enable_source ), +`else + .tx_clk_mii ( tx_clk_mii ), + .rx_clk_mii ( rx_clk_mii ), +`endif + + // GMII TX Inputs + .tx_clk_125 ( tx_clk_125 ) , + .tx_d ( tx_d) , + .tx_en ( tx_en) , + .tx_er ( tx_er) , + + // GMII RX Outputs + // To GMII/MAC interface + .rx_clk_125 ( rx_clk_125 ) , + .rx_d ( rx_d ) , + .rx_dv ( rx_dv ) , + .rx_er ( rx_er ) , + .col ( col ) , + .crs ( crs ) , + + // 8BI TX Outputs + .tx_data ( tx_data) , + .tx_kcntl ( tx_kcntl) , + .tx_disparity_cntl ( tx_disparity_cntl) , + .xmit_autoneg ( xmit_autoneg) , + + // 8BI RX Inputs + .serdes_recovered_clk ( serdes_recovered_clk ) , + .rx_data ( rx_data ) , + .rx_kcntl ( rx_kcntl ) , + .rx_even ( rx_even ) , + .rx_disp_err ( rx_disp_err ) , + .rx_cv_err ( rx_cv_err ) , + .rx_err_decode_mode ( rx_err_decode_mode ) , + + // Management Interface I/O + .mr_adv_ability (mr_adv_ability), + .mr_an_enable (mr_an_enable), + .mr_main_reset (mr_main_reset), + .mr_restart_an (mr_restart_an), + + .mr_an_complete (mr_an_complete), + .mr_lp_adv_ability (mr_lp_adv_ability), + .mr_page_rx (mr_page_rx) + ); + + +endmodule diff --git a/gbe_trb/media/ecp5/sgmii_channel_smi_core.v b/gbe_trb/media/ecp5/sgmii_channel_smi_core.v new file mode 100644 index 0000000..d26445c --- /dev/null +++ b/gbe_trb/media/ecp5/sgmii_channel_smi_core.v @@ -0,0 +1,230 @@ +//************************************************************************** +// ************************************************************************* +// * LATTICE SEMICONDUCTOR CONFIDENTIAL * +// * PROPRIETARY NOTE * +// * * +// * This software contains information confidential and proprietary * +// * to Lattice Semiconductor Corporation. It shall not be reproduced * +// * in whole or in part, or transferred to other documents, or disclosed * +// * to third parties, or used for any purpose other than that for which * +// * it was obtained, without the prior written consent of Lattice * +// * Semiconductor Corporation. All rights reserved. * +// * * +// ************************************************************************* +//************************************************************************** + +`define SGMII_YES_SINGLE_CLOCK + +module sgmii_channel_smi_core ( + + // Control Interface + rst_n, + signal_detect, + gbe_mode, + sgmii_mode, + operational_rate, + debug_link_timer_short, + force_isolate, + force_loopback, + force_unidir, + + rx_compensation_err, + ctc_drop_flag, + ctc_add_flag, + an_link_ok, + + // G/MII Interface +`ifdef SGMII_YES_SINGLE_CLOCK + tx_clock_enable_sink , + tx_clock_enable_source , + + rx_clock_enable_sink , + rx_clock_enable_source , +`else + tx_clk_mii , + rx_clk_mii , +`endif + tx_clk_125, + tx_d, + tx_en, + tx_er, + + rx_clk_125, + rx_d, + rx_dv, + rx_er, + col, + crs, + + // 8-bit Interface + tx_data, + tx_kcntl, + tx_disparity_cntl, + xmit_autoneg, + + serdes_recovered_clk, + rx_data, + rx_kcntl, + rx_even , + rx_disp_err , + rx_cv_err , + rx_err_decode_mode , + + // Managment Control Outputs + mr_an_complete, + mr_page_rx, + mr_lp_adv_ability, + + // Managment Control Inputs + mr_main_reset, + mr_an_enable, + mr_restart_an, + mr_adv_ability + ); + + + +// Control Interface +input rst_n ; +input signal_detect ; +input gbe_mode ; +input sgmii_mode ; +input [1:0] operational_rate ; +input debug_link_timer_short ; +input force_isolate ; +input force_loopback ; +input force_unidir ; + +output rx_compensation_err ; +output ctc_drop_flag ; +output ctc_add_flag ; +output an_link_ok ; + +// G/MII Interface +`ifdef SGMII_YES_SINGLE_CLOCK + input tx_clock_enable_sink; + output tx_clock_enable_source; + + input rx_clock_enable_sink; + output rx_clock_enable_source; +`else + input tx_clk_mii; + input rx_clk_mii; +`endif + +input tx_clk_125 ; +input [7:0] tx_d ; +input tx_en ; +input tx_er ; + +input rx_clk_125 ; +output [7:0] rx_d ; +output rx_dv ; +output rx_er ; +output col ; +output crs ; + +// 8-bit Interface +output [7:0] tx_data ; +output tx_kcntl; +output tx_disparity_cntl; +output xmit_autoneg; + +input serdes_recovered_clk ; +input [7:0] rx_data ; +input rx_even ; +input rx_kcntl; +input rx_disp_err ; // Displarity error on "rx_data". +input rx_cv_err ; // Code error on "rx_data". +input rx_err_decode_mode ; + +// Managment Control Outputs +output mr_an_complete; +output mr_page_rx; +output [15:0] mr_lp_adv_ability; + +// Managment Control Inputs +input mr_main_reset; +input mr_an_enable; +input mr_restart_an; +input [15:0] mr_adv_ability; + + +parameter STATIC_HI_THRESH = 32; +parameter STATIC_LO_THRESH = 16; +parameter LINK_TIMER_SH = 21'h1fff01; + + + +// SGMII PCS +sgmii_pcs_gda_001 # (.STATIC_HI_THRESH(STATIC_HI_THRESH), .STATIC_LO_THRESH(STATIC_LO_THRESH), .LINK_TIMER_SH(LINK_TIMER_SH)) sgmii_pcs_gda_001 ( + // Clock and Reset + .rst_n ( rst_n ) , + .signal_detect ( signal_detect ) , + .gbe_mode ( gbe_mode ) , + .sgmii_mode ( sgmii_mode ) , + .operational_rate ( operational_rate ) , + .debug_link_timer_short ( debug_link_timer_short ) , + .force_isolate ( force_isolate ) , + .force_loopback ( force_loopback ) , + .force_unidir ( force_unidir ) , + + .rx_compensation_err ( rx_compensation_err ) , + .ctc_drop_flag ( ctc_drop_flag ) , + .ctc_add_flag ( ctc_add_flag ) , + .an_link_ok ( an_link_ok ) , + +`ifdef SGMII_YES_SINGLE_CLOCK + .tx_clock_enable_sink ( tx_clock_enable_sink ), + .tx_clock_enable_source ( tx_clock_enable_source ), + + .rx_clock_enable_sink ( rx_clock_enable_sink ), + .rx_clock_enable_source ( rx_clock_enable_source ), +`else + .tx_clk_mii ( tx_clk_mii ), + .rx_clk_mii ( rx_clk_mii ), +`endif + + // GMII TX Inputs + .tx_clk_125 ( tx_clk_125 ) , + .tx_d ( tx_d) , + .tx_en ( tx_en) , + .tx_er ( tx_er) , + + // GMII RX Outputs + // To GMII/MAC interface + .rx_clk_125 ( rx_clk_125 ) , + .rx_d ( rx_d ) , + .rx_dv ( rx_dv ) , + .rx_er ( rx_er ) , + .col ( col ) , + .crs ( crs ) , + + // 8BI TX Outputs + .tx_data ( tx_data) , + .tx_kcntl ( tx_kcntl) , + .tx_disparity_cntl ( tx_disparity_cntl) , + .xmit_autoneg ( xmit_autoneg) , + + // 8BI RX Inputs + .serdes_recovered_clk ( serdes_recovered_clk ) , + .rx_data ( rx_data ) , + .rx_kcntl ( rx_kcntl ) , + .rx_even ( rx_even ) , + .rx_disp_err ( rx_disp_err ) , + .rx_cv_err ( rx_cv_err ) , + .rx_err_decode_mode ( rx_err_decode_mode ) , + + // Management Interface I/O + .mr_adv_ability (mr_adv_ability), + .mr_an_enable (mr_an_enable), + .mr_main_reset (mr_main_reset), + .mr_restart_an (mr_restart_an), + + .mr_an_complete (mr_an_complete), + .mr_lp_adv_ability (mr_lp_adv_ability), + .mr_page_rx (mr_page_rx) + ); + + +endmodule diff --git a/gbe_trb/media/ecp5/sgmii_defines.v b/gbe_trb/media/ecp5/sgmii_defines.v new file mode 100644 index 0000000..ef2ca4e --- /dev/null +++ b/gbe_trb/media/ecp5/sgmii_defines.v @@ -0,0 +1,4 @@ +`define SGMII_NO_ENC +`define SGMII_YES_CTC_DYNAMIC +`define SGMII_YES_SINGLE_CLOCK +`define SGMII_FIFO_FAMILY_ECP5 diff --git a/gbe_trb/media/ecp5/sgmii_ecp5.lpc b/gbe_trb/media/ecp5/sgmii_ecp5.lpc new file mode 100644 index 0000000..1f57fa4 --- /dev/null +++ b/gbe_trb/media/ecp5/sgmii_ecp5.lpc @@ -0,0 +1,97 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA756 +PartName=LFE5UM-85F-8BG756C +PartType=LFE5UM-85F +SpeedGrade=8 +Status=P +[IP] +CoreName=PCS +CoreRevision=8.2 +CoreStatus=Demo +CoreType=LPM +Date=05/07/2019 +ModuleName=sgmii_ecp5 +ParameterFileVersion=1.0 +SourceFormat=vhdl +Time=17:09:58 +VendorName=Lattice Semiconductor Corporation +[Parameters] +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +;RXMCAENABLE=Disabled +CDRLOLACTION=Full Recalibration +CDRLOLRANGE=0 +CDR_MAX_RATE=1.25 +CDR_MULT=10X +CDR_REF_RATE=125.0000 +CH_MODE=Rx and Tx +Destination=Synplicity +EDIF=1 +Expression=BusA(0 to 7) +IO=0 +IO_TYPE=GbE +LEQ=0 +LOOPBACK=Disabled +LOSPORT=Enabled +NUM_CHS=1 +Order=Big Endian [MSB:LSB] +PPORT_RX_RDY=Enabled +PPORT_TX_RDY=Enabled +PROTOCOL=GbE +PWAIT_RX_RDY=3000 +PWAIT_TX_RDY=3000 +RCSRC=Disabled +REFCLK_RATE=125.0000 +RSTSEQSEL=Enabled +RX8B10B=Enabled +RXCOMMAA=1010000011 +RXCOMMAB=0101111100 +RXCOMMAM=1111111111 +RXCOUPLING=AC +RXCTC=Enabled +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=1 BCH +RXCTCBYTEN3=0 50H +RXCTCMATCHPATTERN=M2-S2 +RXDIFFTERM=50 ohms +RXFIFO_ENABLE=Enabled +RXINVPOL=Non-invert +RXLDR=Off +RXLOSTHRESHOLD=2 +RXLSM=Enabled +RXSC=K28P5 +RXWA=Barrel Shift +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=125.0000 +RX_LINE_RATE=1.2500 +RX_RATE_DIV=Full Rate +SCIPORT=Enabled +SOFTLOL=Enabled +TX8B10B=Enabled +TXAMPLITUDE=1100 +TXDEPOST=Disabled +TXDEPRE=Disabled +TXDIFFTERM=50 ohms +TXFIFO_ENABLE=Enabled +TXINVPOL=Non-invert +TXLDR=Off +TXPLLLOLTHRESHOLD=0 +TXPLLMULT=10X +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=125.0000 +TX_LINE_RATE=1.2500 +TX_MAX_RATE=1.25 +TX_RATE_DIV=Full Rate +VHDL=1 +Verilog=0 +[FilesGenerated] +sgmii_ecp5.pp=pp +sgmii_ecp5.sym=sym +sgmii_ecp5.tft=tft +sgmii_ecp5.txt=pcs_module +[SYSTEMPNR] +LN0=DCU1_CH1 diff --git a/gbe_trb/media/ecp5/sgmii_ecp5.lpc_old b/gbe_trb/media/ecp5/sgmii_ecp5.lpc_old new file mode 100644 index 0000000..54f9b73 --- /dev/null +++ b/gbe_trb/media/ecp5/sgmii_ecp5.lpc_old @@ -0,0 +1,97 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA756 +PartName=LFE5UM-85F-8BG756C +PartType=LFE5UM-85F +SpeedGrade=8 +Status=P +[IP] +CoreName=PCS +CoreRevision=8.2 +CoreStatus=Demo +CoreType=LPM +Date=04/29/2019 +ModuleName=sgmii_ecp5 +ParameterFileVersion=1.0 +SourceFormat=vhdl +Time=16:13:12 +VendorName=Lattice Semiconductor Corporation +[Parameters] +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +;RXMCAENABLE=Disabled +CDRLOLACTION=Full Recalibration +CDRLOLRANGE=0 +CDR_MAX_RATE=1.25 +CDR_MULT=10X +CDR_REF_RATE=125.0000 +CH_MODE=Rx and Tx +Destination=Synplicity +EDIF=1 +Expression=BusA(0 to 7) +IO=0 +IO_TYPE=GbE +LEQ=0 +LOOPBACK=Disabled +LOSPORT=Enabled +NUM_CHS=1 +Order=Big Endian [MSB:LSB] +PPORT_RX_RDY=Disabled +PPORT_TX_RDY=Disabled +PROTOCOL=GbE +PWAIT_RX_RDY=3000 +PWAIT_TX_RDY=3000 +RCSRC=Disabled +REFCLK_RATE=125.0000 +RSTSEQSEL=Disabled +RX8B10B=Enabled +RXCOMMAA=1010000011 +RXCOMMAB=0101111100 +RXCOMMAM=1111111111 +RXCOUPLING=AC +RXCTC=Enabled +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=1 BCH +RXCTCBYTEN3=0 50H +RXCTCMATCHPATTERN=M2-S2 +RXDIFFTERM=50 ohms +RXFIFO_ENABLE=Enabled +RXINVPOL=Non-invert +RXLDR=Off +RXLOSTHRESHOLD=2 +RXLSM=Enabled +RXSC=K28P5 +RXWA=Barrel Shift +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=125.0000 +RX_LINE_RATE=1.2500 +RX_RATE_DIV=Full Rate +SCIPORT=Disabled +SOFTLOL=Enabled +TX8B10B=Enabled +TXAMPLITUDE=1100 +TXDEPOST=Disabled +TXDEPRE=Disabled +TXDIFFTERM=50 ohms +TXFIFO_ENABLE=Enabled +TXINVPOL=Non-invert +TXLDR=Off +TXPLLLOLTHRESHOLD=0 +TXPLLMULT=10X +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=125.0000 +TX_LINE_RATE=1.2500 +TX_MAX_RATE=1.25 +TX_RATE_DIV=Full Rate +VHDL=1 +Verilog=0 +[FilesGenerated] +sgmii_ecp5.pp=pp +sgmii_ecp5.sym=sym +sgmii_ecp5.tft=tft +sgmii_ecp5.txt=pcs_module +[SYSTEMPNR] +LN0=DCU1_CH1 diff --git a/gbe_trb/media/ecp5/sgmii_ecp5.ngd b/gbe_trb/media/ecp5/sgmii_ecp5.ngd new file mode 100644 index 0000000..77445df Binary files /dev/null and b/gbe_trb/media/ecp5/sgmii_ecp5.ngd differ diff --git a/gbe_trb/media/ecp5/sgmii_ecp5.ngo b/gbe_trb/media/ecp5/sgmii_ecp5.ngo new file mode 100644 index 0000000..19fca44 Binary files /dev/null and b/gbe_trb/media/ecp5/sgmii_ecp5.ngo differ diff --git a/gbe_trb/media/ecp5/sgmii_ecp5.ngo_old b/gbe_trb/media/ecp5/sgmii_ecp5.ngo_old new file mode 100644 index 0000000..7e95388 Binary files /dev/null and b/gbe_trb/media/ecp5/sgmii_ecp5.ngo_old differ diff --git a/gbe_trb/media/ecp5/sgmii_ecp5.vhd b/gbe_trb/media/ecp5/sgmii_ecp5.vhd new file mode 100644 index 0000000..5cb3267 --- /dev/null +++ b/gbe_trb/media/ecp5/sgmii_ecp5.vhd @@ -0,0 +1,433 @@ + +-- +-- Verific VHDL Description of module DCUA +-- + +-- DCUA is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module sgmii_ecp5rsl_core +-- + +-- sgmii_ecp5rsl_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module sgmii_ecp5sll_core +-- + +-- sgmii_ecp5sll_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module sgmii_ecp5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +library ecp5um ; +use ecp5um.components.all ; + +entity sgmii_ecp5 is + port (hdoutp: out std_logic; + hdoutn: out std_logic; + hdinp: in std_logic; + hdinn: in std_logic; + rxrefclk: in std_logic; + tx_pclk: out std_logic; + txi_clk: in std_logic; + txdata: in std_logic_vector(7 downto 0); + tx_k: in std_logic_vector(0 downto 0); + xmit: in std_logic_vector(0 downto 0); + tx_disp_correct: in std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_cv_err: out std_logic_vector(0 downto 0); + signal_detect_c: in std_logic; + rx_los_low_s: out std_logic; + lsm_status_s: out std_logic; + ctc_urun_s: out std_logic; + ctc_orun_s: out std_logic; + rx_cdr_lol_s: out std_logic; + ctc_ins_s: out std_logic; + ctc_del_s: out std_logic; + sli_rst: in std_logic; + tx_pwrup_c: in std_logic; + rx_pwrup_c: in std_logic; + sci_wrdata: in std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_en_dual: in std_logic; + sci_sel_dual: in std_logic; + sci_en: in std_logic; + sci_sel: in std_logic; + sci_rd: in std_logic; + sci_wrn: in std_logic; + sci_int: out std_logic; + cyawstn: in std_logic; + serdes_pdb: in std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + serdes_rst_dual_c: in std_logic; + rst_dual_c: in std_logic; + tx_serdes_rst_c: in std_logic; + tx_pcs_rst_c: in std_logic; + pll_lol: out std_logic; + rsl_tx_rdy: out std_logic; + rx_serdes_rst_c: in std_logic; + rx_pcs_rst_c: in std_logic; + rsl_rx_rdy: out std_logic + ); + +end entity sgmii_ecp5; + +architecture v1 of sgmii_ecp5 is + component sgmii_ecp5rsl_core is + generic (pnum_channels: integer := 1; + pprotocol: string := "GBE"; + pserdes_mode: string := "RX AND TX"; + pport_tx_rdy: string := "ENABLED"; + pwait_tx_rdy: integer := 3000; + pport_rx_rdy: string := "ENABLED"; + pwait_rx_rdy: integer := 3000); + port (rui_rst: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132) + rui_serdes_rst_dual_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133) + rui_rst_dual_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134) + rui_rsl_disable: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135) + rui_tx_ref_clk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137) + rui_tx_serdes_rst_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138) + rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139) + rdi_pll_lol: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140) + rui_rx_ref_clk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142) + rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143) + rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144) + rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145) + rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146) + rdo_serdes_rst_dual_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149) + rdo_rst_dual_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150) + ruo_tx_rdy: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152) + rdo_tx_serdes_rst_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153) + rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154) + ruo_rx_rdy: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156) + rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157) + rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158) + ); + + end component sgmii_ecp5rsl_core; -- syn_black_box=1 -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88) + component sgmii_ecp5sll_core is + generic (PPROTOCOL: string := "GBE"; + PLOL_SETTING: integer := 0; + PDYN_RATE_CTRL: string := "DISABLED"; + PPCIE_MAX_RATE: string := "2.5"; + PDIFF_VAL_LOCK: integer := 39; + PDIFF_VAL_UNLOCK: integer := 78; + PPCLK_TC: integer := 131072; + PDIFF_DIV11_VAL_LOCK: integer := 0; + PDIFF_DIV11_VAL_UNLOCK: integer := 0; + PPCLK_DIV11_TC: integer := 0); + port (sli_rst: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(125) + sli_refclk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(126) + sli_pclk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(127) + sli_div2_rate: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(128) + sli_div11_rate: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(129) + sli_gear_mode: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(130) + sli_cpri_mode: in std_logic_vector(2 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(131) + sli_pcie_mode: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(132) + slo_plol: out std_logic -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(135) + ); + + end component sgmii_ecp5sll_core; -- syn_black_box=1 -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(107) + signal n45,n44,n1,n2,n3,n4,tx_pclk_c,n5,n6,n7,n8,n9,n10,n11, + n12,n13,rx_los_low_s_c,n14,n15,rx_cdr_lol_s_c,rsl_tx_pcs_rst_c, + rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c,rsl_serdes_rst_dual_c, + rsl_tx_serdes_rst_c,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25, + n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39, + n40,n41,n42,n43,n46,n103,n102,n47,n48,n49,n50,n51,n52,n53, + n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67, + n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81, + n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95, + n96,n97,n98,n99,n100,n101,n112,n111,n110,pll_lol_c,n122,n121, + n113,n114,n115,n116,n117,n118,n119,n120,\_Z\,n124,n123,gnd, + pwr : std_logic; + attribute LOC : string; + attribute LOC of DCU1_inst : label is "DCU1"; + attribute CHAN : string; + attribute CHAN of DCU1_inst : label is "CH1"; +begin + tx_pclk <= tx_pclk_c; + rx_los_low_s <= rx_los_low_s_c; + rx_cdr_lol_s <= rx_cdr_lol_s_c; + pll_lol <= pll_lol_c; + DCU1_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", + D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", + D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", + D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b0",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", + CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", + CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0", + CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0", + CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0", + CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0", + CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b0", + CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b1", + CH1_MATCH_4_ENABLE=>"0b0",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x000", + CH1_CC_MATCH_2=>"0x000",CH1_CC_MATCH_3=>"0x1BC",CH1_CC_MATCH_4=>"0x050", + CH1_UDF_COMMA_MASK=>"0x3ff",CH1_UDF_COMMA_A=>"0x283",CH1_UDF_COMMA_B=>"0x17C", + CH1_RX_DCO_CK_DIV=>"0b010",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1", + CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00", + CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b01",CH1_TDRV_SLICE1_SEL=>"0b00", + CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01", + CH1_TDRV_SLICE5_SEL=>"0b01",CH1_TDRV_SLICE0_CUR=>"0b101",CH1_TDRV_SLICE1_CUR=>"0b000", + CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b11", + CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0", + CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0", + CH1_SEL_SD_RX_CLK=>"0b0",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0", + CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0", + CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00", + CH1_REQ_EN=>"0b1",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1", + CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000", + CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b010",CH1_RX_LOS_CEQ=>"0b11", + CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0", + CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"1.25",CH1_CDR_MAX_RATE=>"1.25", + CH1_TXAMPLITUDE=>"0d1100",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED", + CH1_PROTOCOL=>"GBE",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00", + D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000", + D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00", + CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00", + CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b001",CH1_DCOCTLGI=>"0b010", + CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b01",CH1_DCOFTNRG=>"0b110", + CH1_DCOIOSTUNE=>"0b000",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b111", + CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b101",CH1_DCOSCALEI=>"0b00", + CH1_DCOSTARTVAL=>"0b000",CH1_DCOSTEP=>"0b00",CH1_BAND_THRESHOLD=>"0d0", + CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0", + CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0", + CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00", + D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", + D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", + D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d8", + D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b010",D_PLL_LOL_SET=>"0b00", + D_RG_EN=>"0b0",D_RG_SET=>"0b00") + port map (CH0_HDINP=>n103,CH1_HDINP=>hdinp,CH0_HDINN=>n103,CH1_HDINN=>hdinn, + D_TXBIT_CLKP_FROM_ND=>n44,D_TXBIT_CLKN_FROM_ND=>n44,D_SYNC_ND=>n44,D_TXPLL_LOL_FROM_ND=>n44, + CH0_RX_REFCLK=>n103,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n102,CH1_FF_RXI_CLK=>tx_pclk_c, + CH0_FF_TXI_CLK=>n102,CH1_FF_TXI_CLK=>txi_clk,CH0_FF_EBRD_CLK=>n102,CH1_FF_EBRD_CLK=>tx_pclk_c, + CH0_FF_TX_D_0=>n103,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n103,CH1_FF_TX_D_1=>txdata(1), + CH0_FF_TX_D_2=>n103,CH1_FF_TX_D_2=>txdata(2),CH0_FF_TX_D_3=>n103,CH1_FF_TX_D_3=>txdata(3), + CH0_FF_TX_D_4=>n103,CH1_FF_TX_D_4=>txdata(4),CH0_FF_TX_D_5=>n103,CH1_FF_TX_D_5=>txdata(5), + CH0_FF_TX_D_6=>n103,CH1_FF_TX_D_6=>txdata(6),CH0_FF_TX_D_7=>n103,CH1_FF_TX_D_7=>txdata(7), + CH0_FF_TX_D_8=>n103,CH1_FF_TX_D_8=>tx_k(0),CH0_FF_TX_D_9=>n103,CH1_FF_TX_D_9=>n44, + CH0_FF_TX_D_10=>n103,CH1_FF_TX_D_10=>xmit(0),CH0_FF_TX_D_11=>n103,CH1_FF_TX_D_11=>tx_disp_correct(0), + CH0_FF_TX_D_12=>n103,CH1_FF_TX_D_12=>n103,CH0_FF_TX_D_13=>n103,CH1_FF_TX_D_13=>n103, + CH0_FF_TX_D_14=>n103,CH1_FF_TX_D_14=>n103,CH0_FF_TX_D_15=>n103,CH1_FF_TX_D_15=>n103, + CH0_FF_TX_D_16=>n103,CH1_FF_TX_D_16=>n103,CH0_FF_TX_D_17=>n103,CH1_FF_TX_D_17=>n103, + CH0_FF_TX_D_18=>n103,CH1_FF_TX_D_18=>n103,CH0_FF_TX_D_19=>n103,CH1_FF_TX_D_19=>n103, + CH0_FF_TX_D_20=>n103,CH1_FF_TX_D_20=>n103,CH0_FF_TX_D_21=>n103,CH1_FF_TX_D_21=>n44, + CH0_FF_TX_D_22=>n103,CH1_FF_TX_D_22=>n103,CH0_FF_TX_D_23=>n103,CH1_FF_TX_D_23=>n103, + CH0_FFC_EI_EN=>n103,CH1_FFC_EI_EN=>n44,CH0_FFC_PCIE_DET_EN=>n103,CH1_FFC_PCIE_DET_EN=>n44, + CH0_FFC_PCIE_CT=>n103,CH1_FFC_PCIE_CT=>n44,CH0_FFC_SB_INV_RX=>n103,CH1_FFC_SB_INV_RX=>n103, + CH0_FFC_ENABLE_CGALIGN=>n103,CH1_FFC_ENABLE_CGALIGN=>n103,CH0_FFC_SIGNAL_DETECT=>n103, + CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n103,CH1_FFC_FB_LOOPBACK=>n44, + CH0_FFC_SB_PFIFO_LP=>n103,CH1_FFC_SB_PFIFO_LP=>n44,CH0_FFC_PFIFO_CLR=>n103, + CH1_FFC_PFIFO_CLR=>n44,CH0_FFC_RATE_MODE_RX=>n103,CH1_FFC_RATE_MODE_RX=>n44, + CH0_FFC_RATE_MODE_TX=>n103,CH1_FFC_RATE_MODE_TX=>n44,CH0_FFC_DIV11_MODE_RX=>n103, + CH1_FFC_DIV11_MODE_RX=>n44,CH0_FFC_DIV11_MODE_TX=>n103,CH1_FFC_DIV11_MODE_TX=>n44, + CH0_FFC_RX_GEAR_MODE=>n103,CH1_FFC_RX_GEAR_MODE=>n44,CH0_FFC_TX_GEAR_MODE=>n103, + CH1_FFC_TX_GEAR_MODE=>n44,CH0_FFC_LDR_CORE2TX_EN=>n103,CH1_FFC_LDR_CORE2TX_EN=>n103, + CH0_FFC_LANE_TX_RST=>n103,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,CH0_FFC_LANE_RX_RST=>n103, + CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n103,CH1_FFC_RRST=>rsl_rx_serdes_rst_c, + CH0_FFC_TXPWDNB=>n103,CH1_FFC_TXPWDNB=>tx_pwrup_c,CH0_FFC_RXPWDNB=>n103, + CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n103,CH1_LDR_CORE2TX=>n103, + D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1),D_SCIWDATA2=>sci_wrdata(2), + D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4),D_SCIWDATA5=>sci_wrdata(5), + D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7),D_SCIADDR0=>sci_addr(0), + D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2),D_SCIADDR3=>sci_addr(3), + D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5),D_SCIENAUX=>sci_en_dual, + D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n103,CH1_SCIEN=>sci_en,CH0_SCISEL=>n103, + CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,D_CYAWSTN=>cyawstn, + D_FFC_SYNC_TOGGLE=>n103,D_FFC_DUAL_RST=>rsl_rst_dual_c,D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c, + D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n103, + CH1_FFC_CDR_EN_BITSLIP=>n44,D_SCAN_ENABLE=>n44,D_SCAN_IN_0=>n44,D_SCAN_IN_1=>n44, + D_SCAN_IN_2=>n44,D_SCAN_IN_3=>n44,D_SCAN_IN_4=>n44,D_SCAN_IN_5=>n44, + D_SCAN_IN_6=>n44,D_SCAN_IN_7=>n44,D_SCAN_MODE=>n44,D_SCAN_RESET=>n44, + D_CIN0=>n44,D_CIN1=>n44,D_CIN2=>n44,D_CIN3=>n44,D_CIN4=>n44,D_CIN5=>n44, + D_CIN6=>n44,D_CIN7=>n44,D_CIN8=>n44,D_CIN9=>n44,D_CIN10=>n44,D_CIN11=>n44, + CH0_HDOUTP=>n47,CH1_HDOUTP=>hdoutp,CH0_HDOUTN=>n48,CH1_HDOUTN=>hdoutn, + D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4, + CH0_FF_RX_F_CLK=>n49,CH1_FF_RX_F_CLK=>n5,CH0_FF_RX_H_CLK=>n50,CH1_FF_RX_H_CLK=>n6, + CH0_FF_TX_F_CLK=>n51,CH1_FF_TX_F_CLK=>n7,CH0_FF_TX_H_CLK=>n52,CH1_FF_TX_H_CLK=>n8, + CH0_FF_RX_PCLK=>n53,CH1_FF_RX_PCLK=>n9,CH0_FF_TX_PCLK=>n54,CH1_FF_TX_PCLK=>tx_pclk_c, + CH0_FF_RX_D_0=>n55,CH1_FF_RX_D_0=>rxdata(0),CH0_FF_RX_D_1=>n56,CH1_FF_RX_D_1=>rxdata(1), + CH0_FF_RX_D_2=>n57,CH1_FF_RX_D_2=>rxdata(2),CH0_FF_RX_D_3=>n58,CH1_FF_RX_D_3=>rxdata(3), + CH0_FF_RX_D_4=>n59,CH1_FF_RX_D_4=>rxdata(4),CH0_FF_RX_D_5=>n60,CH1_FF_RX_D_5=>rxdata(5), + CH0_FF_RX_D_6=>n61,CH1_FF_RX_D_6=>rxdata(6),CH0_FF_RX_D_7=>n62,CH1_FF_RX_D_7=>rxdata(7), + CH0_FF_RX_D_8=>n63,CH1_FF_RX_D_8=>rx_k(0),CH0_FF_RX_D_9=>n64,CH1_FF_RX_D_9=>rx_disp_err(0), + CH0_FF_RX_D_10=>n65,CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n66, + CH1_FF_RX_D_11=>n10,CH0_FF_RX_D_12=>n67,CH1_FF_RX_D_12=>n68,CH0_FF_RX_D_13=>n69, + CH1_FF_RX_D_13=>n70,CH0_FF_RX_D_14=>n71,CH1_FF_RX_D_14=>n72,CH0_FF_RX_D_15=>n73, + CH1_FF_RX_D_15=>n74,CH0_FF_RX_D_16=>n75,CH1_FF_RX_D_16=>n76,CH0_FF_RX_D_17=>n77, + CH1_FF_RX_D_17=>n78,CH0_FF_RX_D_18=>n79,CH1_FF_RX_D_18=>n80,CH0_FF_RX_D_19=>n81, + CH1_FF_RX_D_19=>n82,CH0_FF_RX_D_20=>n83,CH1_FF_RX_D_20=>n84,CH0_FF_RX_D_21=>n85, + CH1_FF_RX_D_21=>n86,CH0_FF_RX_D_22=>n87,CH1_FF_RX_D_22=>n88,CH0_FF_RX_D_23=>n89, + CH1_FF_RX_D_23=>n11,CH0_FFS_PCIE_DONE=>n90,CH1_FFS_PCIE_DONE=>n12,CH0_FFS_PCIE_CON=>n91, + CH1_FFS_PCIE_CON=>n13,CH0_FFS_RLOS=>n92,CH1_FFS_RLOS=>rx_los_low_s_c, + CH0_FFS_LS_SYNC_STATUS=>n93,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s,CH0_FFS_CC_UNDERRUN=>n94, + CH1_FFS_CC_UNDERRUN=>ctc_urun_s,CH0_FFS_CC_OVERRUN=>n95,CH1_FFS_CC_OVERRUN=>ctc_orun_s, + CH0_FFS_RXFBFIFO_ERROR=>n96,CH1_FFS_RXFBFIFO_ERROR=>n14,CH0_FFS_TXFBFIFO_ERROR=>n97, + CH1_FFS_TXFBFIFO_ERROR=>n15,CH0_FFS_RLOL=>n98,CH1_FFS_RLOL=>rx_cdr_lol_s_c, + CH0_FFS_SKP_ADDED=>n99,CH1_FFS_SKP_ADDED=>ctc_ins_s,CH0_FFS_SKP_DELETED=>n100, + CH1_FFS_SKP_DELETED=>ctc_del_s,CH0_LDR_RX2CORE=>n101,CH1_LDR_RX2CORE=>n112, + D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),D_SCIRDATA2=>sci_rddata(2), + D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),D_SCIRDATA5=>sci_rddata(5), + D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),D_SCIINT=>sci_int, + D_SCAN_OUT_0=>n16,D_SCAN_OUT_1=>n17,D_SCAN_OUT_2=>n18,D_SCAN_OUT_3=>n19, + D_SCAN_OUT_4=>n20,D_SCAN_OUT_5=>n21,D_SCAN_OUT_6=>n22,D_SCAN_OUT_7=>n23, + D_COUT0=>n24,D_COUT1=>n25,D_COUT2=>n26,D_COUT3=>n27,D_COUT4=>n28,D_COUT5=>n29, + D_COUT6=>n30,D_COUT7=>n31,D_COUT8=>n32,D_COUT9=>n33,D_COUT10=>n34,D_COUT11=>n35, + D_COUT12=>n36,D_COUT13=>n37,D_COUT14=>n38,D_COUT15=>n39,D_COUT16=>n40, + D_COUT17=>n41,D_COUT18=>n42,D_COUT19=>n43,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n46); + n45 <= '1' ; + n44 <= '0' ; + n1 <= 'Z' ; + n2 <= 'Z' ; + n3 <= 'Z' ; + n4 <= 'Z' ; + n5 <= 'Z' ; + n6 <= 'Z' ; + n7 <= 'Z' ; + n8 <= 'Z' ; + n9 <= 'Z' ; + n10 <= 'Z' ; + n11 <= 'Z' ; + n12 <= 'Z' ; + n13 <= 'Z' ; + n14 <= 'Z' ; + n15 <= 'Z' ; + n16 <= 'Z' ; + n17 <= 'Z' ; + n18 <= 'Z' ; + n19 <= 'Z' ; + n20 <= 'Z' ; + n21 <= 'Z' ; + n22 <= 'Z' ; + n23 <= 'Z' ; + n24 <= 'Z' ; + n25 <= 'Z' ; + n26 <= 'Z' ; + n27 <= 'Z' ; + n28 <= 'Z' ; + n29 <= 'Z' ; + n30 <= 'Z' ; + n31 <= 'Z' ; + n32 <= 'Z' ; + n33 <= 'Z' ; + n34 <= 'Z' ; + n35 <= 'Z' ; + n36 <= 'Z' ; + n37 <= 'Z' ; + n38 <= 'Z' ; + n39 <= 'Z' ; + n40 <= 'Z' ; + n41 <= 'Z' ; + n42 <= 'Z' ; + n43 <= 'Z' ; + n46 <= 'Z' ; + n103 <= '0' ; + n102 <= '1' ; + n47 <= 'Z' ; + n48 <= 'Z' ; + n49 <= 'Z' ; + n50 <= 'Z' ; + n51 <= 'Z' ; + n52 <= 'Z' ; + n53 <= 'Z' ; + n54 <= 'Z' ; + n55 <= 'Z' ; + n56 <= 'Z' ; + n57 <= 'Z' ; + n58 <= 'Z' ; + n59 <= 'Z' ; + n60 <= 'Z' ; + n61 <= 'Z' ; + n62 <= 'Z' ; + n63 <= 'Z' ; + n64 <= 'Z' ; + n65 <= 'Z' ; + n66 <= 'Z' ; + n67 <= 'Z' ; + n68 <= 'Z' ; + n69 <= 'Z' ; + n70 <= 'Z' ; + n71 <= 'Z' ; + n72 <= 'Z' ; + n73 <= 'Z' ; + n74 <= 'Z' ; + n75 <= 'Z' ; + n76 <= 'Z' ; + n77 <= 'Z' ; + n78 <= 'Z' ; + n79 <= 'Z' ; + n80 <= 'Z' ; + n81 <= 'Z' ; + n82 <= 'Z' ; + n83 <= 'Z' ; + n84 <= 'Z' ; + n85 <= 'Z' ; + n86 <= 'Z' ; + n87 <= 'Z' ; + n88 <= 'Z' ; + n89 <= 'Z' ; + n90 <= 'Z' ; + n91 <= 'Z' ; + n92 <= 'Z' ; + n93 <= 'Z' ; + n94 <= 'Z' ; + n95 <= 'Z' ; + n96 <= 'Z' ; + n97 <= 'Z' ; + n98 <= 'Z' ; + n99 <= 'Z' ; + n100 <= 'Z' ; + n101 <= 'Z' ; + n112 <= 'Z' ; + rsl_inst: component sgmii_ecp5rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c, + rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki, + rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n122, + rui_tx_pcs_rst_c(2)=>n122,rui_tx_pcs_rst_c(1)=>n122,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c, + rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n122, + rui_rx_serdes_rst_c(2)=>n122,rui_rx_serdes_rst_c(1)=>n122,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c, + rui_rx_pcs_rst_c(3)=>n122,rui_rx_pcs_rst_c(2)=>n122,rui_rx_pcs_rst_c(1)=>n122, + rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n122,rdi_rx_los_low_s(2)=>n122, + rdi_rx_los_low_s(1)=>n122,rdi_rx_los_low_s(0)=>rx_los_low_s_c, + rdi_rx_cdr_lol_s(3)=>n122,rdi_rx_cdr_lol_s(2)=>n122,rdi_rx_cdr_lol_s(1)=>n122, + rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c, + rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c, + rdo_tx_pcs_rst_c(3)=>n113,rdo_tx_pcs_rst_c(2)=>n114,rdo_tx_pcs_rst_c(1)=>n115, + rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n116, + rdo_rx_serdes_rst_c(2)=>n117,rdo_rx_serdes_rst_c(1)=>n118,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c, + rdo_rx_pcs_rst_c(3)=>n119,rdo_rx_pcs_rst_c(2)=>n120,rdo_rx_pcs_rst_c(1)=>\_Z\, + rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c); + n111 <= '1' ; + n110 <= '0' ; + n122 <= '0' ; + n121 <= '1' ; + n113 <= 'Z' ; + n114 <= 'Z' ; + n115 <= 'Z' ; + n116 <= 'Z' ; + n117 <= 'Z' ; + n118 <= 'Z' ; + n119 <= 'Z' ; + n120 <= 'Z' ; + \_Z\ <= 'Z' ; + sll_inst: component sgmii_ecp5sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki, + sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd, + sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd, + sli_pcie_mode=>gnd,slo_plol=>pll_lol_c); + n124 <= '1' ; + n123 <= '0' ; + gnd <= '0' ; + pwr <= '1' ; + +end architecture v1; + diff --git a/gbe_trb/media/ecp5/sgmii_ecp5.vhd_old b/gbe_trb/media/ecp5/sgmii_ecp5.vhd_old new file mode 100644 index 0000000..31195d1 --- /dev/null +++ b/gbe_trb/media/ecp5/sgmii_ecp5.vhd_old @@ -0,0 +1,351 @@ + +-- +-- Verific VHDL Description of module DCUA +-- + +-- DCUA is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module sgmii_ecp5sll_core +-- + +-- sgmii_ecp5sll_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module sgmii_ecp5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +library ecp5um ; +use ecp5um.components.all ; + +entity sgmii_ecp5 is + port (hdoutp: out std_logic; + hdoutn: out std_logic; + hdinp: in std_logic; + hdinn: in std_logic; + rxrefclk: in std_logic; + tx_pclk: out std_logic; + txi_clk: in std_logic; + txdata: in std_logic_vector(7 downto 0); + tx_k: in std_logic_vector(0 downto 0); + xmit: in std_logic_vector(0 downto 0); + tx_disp_correct: in std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_cv_err: out std_logic_vector(0 downto 0); + signal_detect_c: in std_logic; + rx_los_low_s: out std_logic; + lsm_status_s: out std_logic; + ctc_urun_s: out std_logic; + ctc_orun_s: out std_logic; + rx_cdr_lol_s: out std_logic; + ctc_ins_s: out std_logic; + ctc_del_s: out std_logic; + tx_pcs_rst_c: in std_logic; + rx_pcs_rst_c: in std_logic; + rx_serdes_rst_c: in std_logic; + tx_pwrup_c: in std_logic; + rx_pwrup_c: in std_logic; + rst_dual_c: in std_logic; + serdes_rst_dual_c: in std_logic; + serdes_pdb: in std_logic; + tx_serdes_rst_c: in std_logic; + pll_refclki: in std_logic; + sli_rst: in std_logic; + pll_lol: out std_logic + ); + +end entity sgmii_ecp5; + +architecture v1 of sgmii_ecp5 is + component sgmii_ecp5sll_core is + generic (PPROTOCOL: string := "GBE"; + PLOL_SETTING: integer := 0; + PDYN_RATE_CTRL: string := "DISABLED"; + PPCIE_MAX_RATE: string := "2.5"; + PDIFF_VAL_LOCK: integer := 39; + PDIFF_VAL_UNLOCK: integer := 78; + PPCLK_TC: integer := 131072; + PDIFF_DIV11_VAL_LOCK: integer := 0; + PDIFF_DIV11_VAL_UNLOCK: integer := 0; + PPCLK_DIV11_TC: integer := 0); + port (sli_rst: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(125) + sli_refclk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(126) + sli_pclk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(127) + sli_div2_rate: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(128) + sli_div11_rate: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(129) + sli_gear_mode: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(130) + sli_cpri_mode: in std_logic_vector(2 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(131) + sli_pcie_mode: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(132) + slo_plol: out std_logic -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(135) + ); + + end component sgmii_ecp5sll_core; -- syn_black_box=1 -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(107) + signal n45,n44,n1,n2,n3,n4,tx_pclk_c,n5,n6,n7,n8,n9,n10,n11, + n12,n13,n14,n15,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25, + n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39, + n40,n41,n42,n43,n46,n112,n111,n47,n48,n49,n50,n51,n52,n53, + n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67, + n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81, + n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95, + n96,n97,n98,n99,n100,n101,n102,n103,n104,n105,n106,n107, + n108,n109,n110,\_Z\,n114,n113,gnd,pwr : std_logic; + attribute LOC : string; + attribute LOC of DCU1_inst : label is "DCU1"; + attribute CHAN : string; + attribute CHAN of DCU1_inst : label is "CH1"; +begin + tx_pclk <= tx_pclk_c; + DCU1_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", + D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", + D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", + D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b0",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", + CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", + CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0", + CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0", + CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0", + CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0", + CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b0", + CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b1", + CH1_MATCH_4_ENABLE=>"0b0",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x000", + CH1_CC_MATCH_2=>"0x000",CH1_CC_MATCH_3=>"0x1BC",CH1_CC_MATCH_4=>"0x050", + CH1_UDF_COMMA_MASK=>"0x3ff",CH1_UDF_COMMA_A=>"0x283",CH1_UDF_COMMA_B=>"0x17C", + CH1_RX_DCO_CK_DIV=>"0b010",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1", + CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00", + CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b01",CH1_TDRV_SLICE1_SEL=>"0b00", + CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01", + CH1_TDRV_SLICE5_SEL=>"0b01",CH1_TDRV_SLICE0_CUR=>"0b101",CH1_TDRV_SLICE1_CUR=>"0b000", + CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b11", + CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0", + CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0", + CH1_SEL_SD_RX_CLK=>"0b0",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0", + CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0", + CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00", + CH1_REQ_EN=>"0b1",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1", + CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000", + CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b010",CH1_RX_LOS_CEQ=>"0b11", + CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0", + CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"1.25",CH1_CDR_MAX_RATE=>"1.25", + CH1_TXAMPLITUDE=>"0d1100",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED", + CH1_PROTOCOL=>"GBE",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00", + D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000", + D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00", + CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00", + CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b001",CH1_DCOCTLGI=>"0b010", + CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b01",CH1_DCOFTNRG=>"0b110", + CH1_DCOIOSTUNE=>"0b000",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b111", + CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b101",CH1_DCOSCALEI=>"0b00", + CH1_DCOSTARTVAL=>"0b000",CH1_DCOSTEP=>"0b00",CH1_BAND_THRESHOLD=>"0d0", + CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0", + CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0", + CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00", + D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", + D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", + D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d8", + D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b010",D_PLL_LOL_SET=>"0b00", + D_RG_EN=>"0b0",D_RG_SET=>"0b00") + port map (CH0_HDINP=>n112,CH1_HDINP=>hdinp,CH0_HDINN=>n112,CH1_HDINN=>hdinn, + D_TXBIT_CLKP_FROM_ND=>n44,D_TXBIT_CLKN_FROM_ND=>n44,D_SYNC_ND=>n44,D_TXPLL_LOL_FROM_ND=>n44, + CH0_RX_REFCLK=>n112,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n111,CH1_FF_RXI_CLK=>tx_pclk_c, + CH0_FF_TXI_CLK=>n111,CH1_FF_TXI_CLK=>txi_clk,CH0_FF_EBRD_CLK=>n111,CH1_FF_EBRD_CLK=>tx_pclk_c, + CH0_FF_TX_D_0=>n112,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n112,CH1_FF_TX_D_1=>txdata(1), + CH0_FF_TX_D_2=>n112,CH1_FF_TX_D_2=>txdata(2),CH0_FF_TX_D_3=>n112,CH1_FF_TX_D_3=>txdata(3), + CH0_FF_TX_D_4=>n112,CH1_FF_TX_D_4=>txdata(4),CH0_FF_TX_D_5=>n112,CH1_FF_TX_D_5=>txdata(5), + CH0_FF_TX_D_6=>n112,CH1_FF_TX_D_6=>txdata(6),CH0_FF_TX_D_7=>n112,CH1_FF_TX_D_7=>txdata(7), + CH0_FF_TX_D_8=>n112,CH1_FF_TX_D_8=>tx_k(0),CH0_FF_TX_D_9=>n112,CH1_FF_TX_D_9=>n44, + CH0_FF_TX_D_10=>n112,CH1_FF_TX_D_10=>xmit(0),CH0_FF_TX_D_11=>n112,CH1_FF_TX_D_11=>tx_disp_correct(0), + CH0_FF_TX_D_12=>n112,CH1_FF_TX_D_12=>n112,CH0_FF_TX_D_13=>n112,CH1_FF_TX_D_13=>n112, + CH0_FF_TX_D_14=>n112,CH1_FF_TX_D_14=>n112,CH0_FF_TX_D_15=>n112,CH1_FF_TX_D_15=>n112, + CH0_FF_TX_D_16=>n112,CH1_FF_TX_D_16=>n112,CH0_FF_TX_D_17=>n112,CH1_FF_TX_D_17=>n112, + CH0_FF_TX_D_18=>n112,CH1_FF_TX_D_18=>n112,CH0_FF_TX_D_19=>n112,CH1_FF_TX_D_19=>n112, + CH0_FF_TX_D_20=>n112,CH1_FF_TX_D_20=>n112,CH0_FF_TX_D_21=>n112,CH1_FF_TX_D_21=>n44, + CH0_FF_TX_D_22=>n112,CH1_FF_TX_D_22=>n112,CH0_FF_TX_D_23=>n112,CH1_FF_TX_D_23=>n112, + CH0_FFC_EI_EN=>n112,CH1_FFC_EI_EN=>n44,CH0_FFC_PCIE_DET_EN=>n112,CH1_FFC_PCIE_DET_EN=>n44, + CH0_FFC_PCIE_CT=>n112,CH1_FFC_PCIE_CT=>n44,CH0_FFC_SB_INV_RX=>n112,CH1_FFC_SB_INV_RX=>n112, + CH0_FFC_ENABLE_CGALIGN=>n112,CH1_FFC_ENABLE_CGALIGN=>n112,CH0_FFC_SIGNAL_DETECT=>n112, + CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n112,CH1_FFC_FB_LOOPBACK=>n44, + CH0_FFC_SB_PFIFO_LP=>n112,CH1_FFC_SB_PFIFO_LP=>n44,CH0_FFC_PFIFO_CLR=>n112, + CH1_FFC_PFIFO_CLR=>n44,CH0_FFC_RATE_MODE_RX=>n112,CH1_FFC_RATE_MODE_RX=>n44, + CH0_FFC_RATE_MODE_TX=>n112,CH1_FFC_RATE_MODE_TX=>n44,CH0_FFC_DIV11_MODE_RX=>n112, + CH1_FFC_DIV11_MODE_RX=>n44,CH0_FFC_DIV11_MODE_TX=>n112,CH1_FFC_DIV11_MODE_TX=>n44, + CH0_FFC_RX_GEAR_MODE=>n112,CH1_FFC_RX_GEAR_MODE=>n44,CH0_FFC_TX_GEAR_MODE=>n112, + CH1_FFC_TX_GEAR_MODE=>n44,CH0_FFC_LDR_CORE2TX_EN=>n112,CH1_FFC_LDR_CORE2TX_EN=>n112, + CH0_FFC_LANE_TX_RST=>n112,CH1_FFC_LANE_TX_RST=>tx_pcs_rst_c,CH0_FFC_LANE_RX_RST=>n112, + CH1_FFC_LANE_RX_RST=>rx_pcs_rst_c,CH0_FFC_RRST=>n112,CH1_FFC_RRST=>rx_serdes_rst_c, + CH0_FFC_TXPWDNB=>n112,CH1_FFC_TXPWDNB=>tx_pwrup_c,CH0_FFC_RXPWDNB=>n112, + CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n112,CH1_LDR_CORE2TX=>n112, + D_SCIWDATA0=>n112,D_SCIWDATA1=>n112,D_SCIWDATA2=>n112,D_SCIWDATA3=>n112, + D_SCIWDATA4=>n112,D_SCIWDATA5=>n112,D_SCIWDATA6=>n112,D_SCIWDATA7=>n112, + D_SCIADDR0=>n112,D_SCIADDR1=>n112,D_SCIADDR2=>n112,D_SCIADDR3=>n112, + D_SCIADDR4=>n112,D_SCIADDR5=>n112,D_SCIENAUX=>n112,D_SCISELAUX=>n112, + CH0_SCIEN=>n112,CH1_SCIEN=>n112,CH0_SCISEL=>n112,CH1_SCISEL=>n112,D_SCIRD=>n112, + D_SCIWSTN=>n112,D_CYAWSTN=>n112,D_FFC_SYNC_TOGGLE=>n112,D_FFC_DUAL_RST=>rst_dual_c, + D_FFC_MACRO_RST=>serdes_rst_dual_c,D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>tx_serdes_rst_c, + CH0_FFC_CDR_EN_BITSLIP=>n112,CH1_FFC_CDR_EN_BITSLIP=>n44,D_SCAN_ENABLE=>n44, + D_SCAN_IN_0=>n44,D_SCAN_IN_1=>n44,D_SCAN_IN_2=>n44,D_SCAN_IN_3=>n44, + D_SCAN_IN_4=>n44,D_SCAN_IN_5=>n44,D_SCAN_IN_6=>n44,D_SCAN_IN_7=>n44, + D_SCAN_MODE=>n44,D_SCAN_RESET=>n44,D_CIN0=>n44,D_CIN1=>n44,D_CIN2=>n44, + D_CIN3=>n44,D_CIN4=>n44,D_CIN5=>n44,D_CIN6=>n44,D_CIN7=>n44,D_CIN8=>n44, + D_CIN9=>n44,D_CIN10=>n44,D_CIN11=>n44,CH0_HDOUTP=>n47,CH1_HDOUTP=>hdoutp, + CH0_HDOUTN=>n48,CH1_HDOUTN=>hdoutn,D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2, + D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,CH0_FF_RX_F_CLK=>n49,CH1_FF_RX_F_CLK=>n5, + CH0_FF_RX_H_CLK=>n50,CH1_FF_RX_H_CLK=>n6,CH0_FF_TX_F_CLK=>n51,CH1_FF_TX_F_CLK=>n7, + CH0_FF_TX_H_CLK=>n52,CH1_FF_TX_H_CLK=>n8,CH0_FF_RX_PCLK=>n53,CH1_FF_RX_PCLK=>n9, + CH0_FF_TX_PCLK=>n54,CH1_FF_TX_PCLK=>tx_pclk_c,CH0_FF_RX_D_0=>n55,CH1_FF_RX_D_0=>rxdata(0), + CH0_FF_RX_D_1=>n56,CH1_FF_RX_D_1=>rxdata(1),CH0_FF_RX_D_2=>n57,CH1_FF_RX_D_2=>rxdata(2), + CH0_FF_RX_D_3=>n58,CH1_FF_RX_D_3=>rxdata(3),CH0_FF_RX_D_4=>n59,CH1_FF_RX_D_4=>rxdata(4), + CH0_FF_RX_D_5=>n60,CH1_FF_RX_D_5=>rxdata(5),CH0_FF_RX_D_6=>n61,CH1_FF_RX_D_6=>rxdata(6), + CH0_FF_RX_D_7=>n62,CH1_FF_RX_D_7=>rxdata(7),CH0_FF_RX_D_8=>n63,CH1_FF_RX_D_8=>rx_k(0), + CH0_FF_RX_D_9=>n64,CH1_FF_RX_D_9=>rx_disp_err(0),CH0_FF_RX_D_10=>n65, + CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n66,CH1_FF_RX_D_11=>n10, + CH0_FF_RX_D_12=>n67,CH1_FF_RX_D_12=>n68,CH0_FF_RX_D_13=>n69,CH1_FF_RX_D_13=>n70, + CH0_FF_RX_D_14=>n71,CH1_FF_RX_D_14=>n72,CH0_FF_RX_D_15=>n73,CH1_FF_RX_D_15=>n74, + CH0_FF_RX_D_16=>n75,CH1_FF_RX_D_16=>n76,CH0_FF_RX_D_17=>n77,CH1_FF_RX_D_17=>n78, + CH0_FF_RX_D_18=>n79,CH1_FF_RX_D_18=>n80,CH0_FF_RX_D_19=>n81,CH1_FF_RX_D_19=>n82, + CH0_FF_RX_D_20=>n83,CH1_FF_RX_D_20=>n84,CH0_FF_RX_D_21=>n85,CH1_FF_RX_D_21=>n86, + CH0_FF_RX_D_22=>n87,CH1_FF_RX_D_22=>n88,CH0_FF_RX_D_23=>n89,CH1_FF_RX_D_23=>n11, + CH0_FFS_PCIE_DONE=>n90,CH1_FFS_PCIE_DONE=>n12,CH0_FFS_PCIE_CON=>n91,CH1_FFS_PCIE_CON=>n13, + CH0_FFS_RLOS=>n92,CH1_FFS_RLOS=>rx_los_low_s,CH0_FFS_LS_SYNC_STATUS=>n93, + CH1_FFS_LS_SYNC_STATUS=>lsm_status_s,CH0_FFS_CC_UNDERRUN=>n94,CH1_FFS_CC_UNDERRUN=>ctc_urun_s, + CH0_FFS_CC_OVERRUN=>n95,CH1_FFS_CC_OVERRUN=>ctc_orun_s,CH0_FFS_RXFBFIFO_ERROR=>n96, + CH1_FFS_RXFBFIFO_ERROR=>n14,CH0_FFS_TXFBFIFO_ERROR=>n97,CH1_FFS_TXFBFIFO_ERROR=>n15, + CH0_FFS_RLOL=>n98,CH1_FFS_RLOL=>rx_cdr_lol_s,CH0_FFS_SKP_ADDED=>n99,CH1_FFS_SKP_ADDED=>ctc_ins_s, + CH0_FFS_SKP_DELETED=>n100,CH1_FFS_SKP_DELETED=>ctc_del_s,CH0_LDR_RX2CORE=>n101, + CH1_LDR_RX2CORE=>n102,D_SCIRDATA0=>n103,D_SCIRDATA1=>n104,D_SCIRDATA2=>n105, + D_SCIRDATA3=>n106,D_SCIRDATA4=>n107,D_SCIRDATA5=>n108,D_SCIRDATA6=>n109, + D_SCIRDATA7=>n110,D_SCIINT=>\_Z\,D_SCAN_OUT_0=>n16,D_SCAN_OUT_1=>n17, + D_SCAN_OUT_2=>n18,D_SCAN_OUT_3=>n19,D_SCAN_OUT_4=>n20,D_SCAN_OUT_5=>n21, + D_SCAN_OUT_6=>n22,D_SCAN_OUT_7=>n23,D_COUT0=>n24,D_COUT1=>n25,D_COUT2=>n26, + D_COUT3=>n27,D_COUT4=>n28,D_COUT5=>n29,D_COUT6=>n30,D_COUT7=>n31,D_COUT8=>n32, + D_COUT9=>n33,D_COUT10=>n34,D_COUT11=>n35,D_COUT12=>n36,D_COUT13=>n37, + D_COUT14=>n38,D_COUT15=>n39,D_COUT16=>n40,D_COUT17=>n41,D_COUT18=>n42, + D_COUT19=>n43,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n46); + n45 <= '1' ; + n44 <= '0' ; + n1 <= 'Z' ; + n2 <= 'Z' ; + n3 <= 'Z' ; + n4 <= 'Z' ; + n5 <= 'Z' ; + n6 <= 'Z' ; + n7 <= 'Z' ; + n8 <= 'Z' ; + n9 <= 'Z' ; + n10 <= 'Z' ; + n11 <= 'Z' ; + n12 <= 'Z' ; + n13 <= 'Z' ; + n14 <= 'Z' ; + n15 <= 'Z' ; + n16 <= 'Z' ; + n17 <= 'Z' ; + n18 <= 'Z' ; + n19 <= 'Z' ; + n20 <= 'Z' ; + n21 <= 'Z' ; + n22 <= 'Z' ; + n23 <= 'Z' ; + n24 <= 'Z' ; + n25 <= 'Z' ; + n26 <= 'Z' ; + n27 <= 'Z' ; + n28 <= 'Z' ; + n29 <= 'Z' ; + n30 <= 'Z' ; + n31 <= 'Z' ; + n32 <= 'Z' ; + n33 <= 'Z' ; + n34 <= 'Z' ; + n35 <= 'Z' ; + n36 <= 'Z' ; + n37 <= 'Z' ; + n38 <= 'Z' ; + n39 <= 'Z' ; + n40 <= 'Z' ; + n41 <= 'Z' ; + n42 <= 'Z' ; + n43 <= 'Z' ; + n46 <= 'Z' ; + n112 <= '0' ; + n111 <= '1' ; + n47 <= 'Z' ; + n48 <= 'Z' ; + n49 <= 'Z' ; + n50 <= 'Z' ; + n51 <= 'Z' ; + n52 <= 'Z' ; + n53 <= 'Z' ; + n54 <= 'Z' ; + n55 <= 'Z' ; + n56 <= 'Z' ; + n57 <= 'Z' ; + n58 <= 'Z' ; + n59 <= 'Z' ; + n60 <= 'Z' ; + n61 <= 'Z' ; + n62 <= 'Z' ; + n63 <= 'Z' ; + n64 <= 'Z' ; + n65 <= 'Z' ; + n66 <= 'Z' ; + n67 <= 'Z' ; + n68 <= 'Z' ; + n69 <= 'Z' ; + n70 <= 'Z' ; + n71 <= 'Z' ; + n72 <= 'Z' ; + n73 <= 'Z' ; + n74 <= 'Z' ; + n75 <= 'Z' ; + n76 <= 'Z' ; + n77 <= 'Z' ; + n78 <= 'Z' ; + n79 <= 'Z' ; + n80 <= 'Z' ; + n81 <= 'Z' ; + n82 <= 'Z' ; + n83 <= 'Z' ; + n84 <= 'Z' ; + n85 <= 'Z' ; + n86 <= 'Z' ; + n87 <= 'Z' ; + n88 <= 'Z' ; + n89 <= 'Z' ; + n90 <= 'Z' ; + n91 <= 'Z' ; + n92 <= 'Z' ; + n93 <= 'Z' ; + n94 <= 'Z' ; + n95 <= 'Z' ; + n96 <= 'Z' ; + n97 <= 'Z' ; + n98 <= 'Z' ; + n99 <= 'Z' ; + n100 <= 'Z' ; + n101 <= 'Z' ; + n102 <= 'Z' ; + n103 <= 'Z' ; + n104 <= 'Z' ; + n105 <= 'Z' ; + n106 <= 'Z' ; + n107 <= 'Z' ; + n108 <= 'Z' ; + n109 <= 'Z' ; + n110 <= 'Z' ; + \_Z\ <= 'Z' ; + sll_inst: component sgmii_ecp5sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki, + sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd, + sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd, + sli_pcie_mode=>gnd,slo_plol=>pll_lol); + n114 <= '1' ; + n113 <= '0' ; + gnd <= '0' ; + pwr <= '1' ; + +end architecture v1; + diff --git a/gbe_trb/media/ecp5/sgmii_ecp5_softlogic.v b/gbe_trb/media/ecp5/sgmii_ecp5_softlogic.v new file mode 100644 index 0000000..69a023d --- /dev/null +++ b/gbe_trb/media/ecp5/sgmii_ecp5_softlogic.v @@ -0,0 +1,2003 @@ + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2016 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : RSL- Reset Sequence Logic +// File : rsl_core.v +// Title : Top-level file for RSL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : BM +// Mod. Date : October 28, 2013 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : BM +// Mod. Date : November 06, 2013 +// Changes Made : Tx/Rx separation, ready port code exclusion +// ----------------------------------------------------------------------------- +// Version : 1.2 +// Author(s) : BM +// Mod. Date : June 13, 2014 +// Changes Made : Updated Rx PCS reset method +// ----------------------------------------------------------------------------- +// ----------------------------------------------------------------------------- +// Version : 1.3 +// Author(s) : UA +// Mod. Date : Dec 19, 2014 +// Changes Made : Added new parameter fro PCIE +// ----------------------------------------------------------------------------- +// Version : 1.31 +// Author(s) : BM/UM +// Mod. Date : Feb 23, 2016 +// Changes Made : Behavior of rx_rdy output modified. The output rx_rdy +// and the rx_rdy wait counter are reset to zero on +// LOL or LOS. Reverted back the counter value change for PCIE. +// ----------------------------------------------------------------------------- +// Version : 1.4 +// Author(s) : EB +// Mod. Date: : March 21, 2017 +// Changes Made : +// ----------------------------------------------------------------------------- +// Version : 1.5 +// Author(s) : ES +// Mod. Date: : May 8, 2017 +// Changes Made : Implemented common RSL behaviour as proposed by BM. +// ============================================================================= + +`timescale 1ns/10ps + +module sgmii_ecp5rsl_core ( + // ------------ Inputs + // Common + rui_rst, // Active high reset for the RSL module + rui_serdes_rst_dual_c, // SERDES macro reset user command + rui_rst_dual_c, // PCS dual reset user command + rui_rsl_disable, // Active high signal that disables all reset outputs of RSL + // Tx + rui_tx_ref_clk, // Tx reference clock + rui_tx_serdes_rst_c, // Tx SERDES reset user command + rui_tx_pcs_rst_c, // Tx lane reset user command + rdi_pll_lol, // Tx PLL Loss of Lock status input from the SERDES + // Rx + rui_rx_ref_clk, // Rx reference clock + rui_rx_serdes_rst_c, // SERDES Receive channel reset user command + rui_rx_pcs_rst_c, // Rx lane reset user command + rdi_rx_los_low_s, // Receive loss of signal status input from SERDES + rdi_rx_cdr_lol_s, // Receive CDR loss of lock status input from SERDES + + // ------------ Outputs + // Common + rdo_serdes_rst_dual_c, // SERDES macro reset command output + rdo_rst_dual_c, // PCS dual reset command output + // Tx + ruo_tx_rdy, // Tx lane ready status output + rdo_tx_serdes_rst_c, // SERDES Tx reset command output + rdo_tx_pcs_rst_c, // PCS Tx lane reset command output + // Rx + ruo_rx_rdy, // Rx lane ready status output + rdo_rx_serdes_rst_c, // SERDES Rx channel reset command output + rdo_rx_pcs_rst_c // PCS Rx lane reset command output + ); + +// ------------ Module parameters +`ifdef NUM_CHANNELS + parameter pnum_channels = `NUM_CHANNELS; // 1,2,4 +`else + parameter pnum_channels = 1; +`endif + +`ifdef PCIE + parameter pprotocol = "PCIE"; +`else + parameter pprotocol = ""; +`endif + +`ifdef RX_ONLY + parameter pserdes_mode = "RX ONLY"; +`else + `ifdef TX_ONLY + parameter pserdes_mode = "TX ONLY"; + `else + parameter pserdes_mode = "RX AND TX"; + `endif +`endif + +`ifdef PORT_TX_RDY + parameter pport_tx_rdy = "ENABLED"; +`else + parameter pport_tx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_TX_RDY + parameter pwait_tx_rdy = `WAIT_TX_RDY; +`else + parameter pwait_tx_rdy = 3000; +`endif + +`ifdef PORT_RX_RDY + parameter pport_rx_rdy = "ENABLED"; +`else + parameter pport_rx_rdy = "DISABLED"; +`endif + +`ifdef WAIT_RX_RDY + parameter pwait_rx_rdy = `WAIT_RX_RDY; +`else + parameter pwait_rx_rdy = 3000; +`endif + +// ------------ Local parameters + localparam wa_num_cycles = 1024; + localparam dac_num_cycles = 3; + localparam lreset_pwidth = 3; // reset pulse width-1, default=4-1=3 + localparam lwait_b4_trst = 781250; // 5ms wait with worst-case Fmax=156 MHz + localparam lwait_b4_trst_s = 781; // for simulation + localparam lplol_cnt_width = 20; // width for lwait_b4_trst + localparam lwait_after_plol0 = 4; + localparam lwait_b4_rrst = 180224; // total calibration time + localparam lrrst_wait_width = 20; + localparam lwait_after_rrst = 800000; // For CPRI- unused + localparam lwait_b4_rrst_s = 460; // wait cycles provided by design team + localparam lrlol_cnt_width = 19; // width for lwait_b4_rrst + localparam lwait_after_lols = (16384 * dac_num_cycles) + wa_num_cycles; // 16384 cycles * dac_num_cycles + 1024 cycles + localparam lwait_after_lols_s = 150; // wait cycles provided by design team + localparam llols_cnt_width = 18; // lols count width + localparam lrdb_max = 15; // maximum debounce count + localparam ltxr_wait_width = 12; // width of tx ready wait counter + localparam lrxr_wait_width = 12; // width of tx ready wait counter + +// ------------ input ports + input rui_rst; + input rui_serdes_rst_dual_c; + input rui_rst_dual_c; + input rui_rsl_disable; + + input rui_tx_ref_clk; + input rui_tx_serdes_rst_c; + input [3:0] rui_tx_pcs_rst_c; + input rdi_pll_lol; + + input rui_rx_ref_clk; + input [3:0] rui_rx_serdes_rst_c; + input [3:0] rui_rx_pcs_rst_c; + input [3:0] rdi_rx_los_low_s; + input [3:0] rdi_rx_cdr_lol_s; + +// ------------ output ports + output rdo_serdes_rst_dual_c; + output rdo_rst_dual_c; + + output ruo_tx_rdy; + output rdo_tx_serdes_rst_c; + output [3:0] rdo_tx_pcs_rst_c; + + output ruo_rx_rdy; + output [3:0] rdo_rx_serdes_rst_c; + output [3:0] rdo_rx_pcs_rst_c; + +// ------------ Internal registers and wires + // inputs + wire rui_rst; + wire rui_serdes_rst_dual_c; + wire rui_rst_dual_c; + wire rui_rsl_disable; + wire rui_tx_ref_clk; + wire rui_tx_serdes_rst_c; + wire [3:0] rui_tx_pcs_rst_c; + wire rdi_pll_lol; + wire rui_rx_ref_clk; + wire [3:0] rui_rx_serdes_rst_c; + wire [3:0] rui_rx_pcs_rst_c; + wire [3:0] rdi_rx_los_low_s; + wire [3:0] rdi_rx_cdr_lol_s; + + // outputs + wire rdo_serdes_rst_dual_c; + wire rdo_rst_dual_c; + wire ruo_tx_rdy; + wire rdo_tx_serdes_rst_c; + wire [3:0] rdo_tx_pcs_rst_c; + wire ruo_rx_rdy; + wire [3:0] rdo_rx_serdes_rst_c; + wire [3:0] rdo_rx_pcs_rst_c; + + // internal signals + // common + wire rsl_enable; + wire [lplol_cnt_width-1:0] wait_b4_trst; + wire [lrlol_cnt_width-1:0] wait_b4_rrst; + wire [llols_cnt_width-1:0] wait_after_lols; + reg pll_lol_p1; + reg pll_lol_p2; + reg pll_lol_p3; + // ------------ Tx + // rdo_tx_serdes_rst_c + reg [lplol_cnt_width-1:0] plol_cnt; + wire plol_cnt_tc; + + reg [2:0] txs_cnt; + reg txs_rst; + wire txs_cnt_tc; + // rdo_tx_pcs_rst_c + wire plol_fedge; + wire plol_redge; + reg waita_plol0; + reg [2:0] plol0_cnt; + wire plol0_cnt_tc; + reg [2:0] txp_cnt; + reg txp_rst; + wire txp_cnt_tc; + // ruo_tx_rdy + wire dual_or_serd_rst; + wire tx_any_pcs_rst; + wire tx_any_rst; + reg txsr_appd /* synthesis syn_keep=1 */; + reg txdpr_appd; + reg [pnum_channels-1:0] txpr_appd; + reg txr_wt_en; + reg [ltxr_wait_width-1:0] txr_wt_cnt; + wire txr_wt_tc; + reg ruo_tx_rdyr; + + // ------------ Rx + wire comb_rlos; + wire comb_rlol; + //wire rlols; + wire rx_all_well; + + //reg rlols_p1; + //reg rlols_p2; + //reg rlols_p3; + + reg rlol_p1; + reg rlol_p2; + reg rlol_p3; + reg rlos_p1; + reg rlos_p2; + reg rlos_p3; + + //reg [3:0] rdb_cnt; + //wire rdb_cnt_max; + //wire rdb_cnt_zero; + //reg rlols_db; + //reg rlols_db_p1; + + reg [3:0] rlol_db_cnt; + wire rlol_db_cnt_max; + wire rlol_db_cnt_zero; + reg rlol_db; + reg rlol_db_p1; + + reg [3:0] rlos_db_cnt; + wire rlos_db_cnt_max; + wire rlos_db_cnt_zero; + reg rlos_db; + reg rlos_db_p1; + + // rdo_rx_serdes_rst_c + reg [lrlol_cnt_width-1:0] rlol1_cnt; + wire rlol1_cnt_tc; + reg [2:0] rxs_cnt; + reg rxs_rst; + wire rxs_cnt_tc; + reg [lrrst_wait_width-1:0] rrst_cnt; + wire rrst_cnt_tc; + reg rrst_wait; + // rdo_rx_pcs_rst_c + //wire rlols_fedge; + //wire rlols_redge; + wire rlol_fedge; + wire rlol_redge; + wire rlos_fedge; + wire rlos_redge; + + reg wait_calib; + reg waita_rlols0; + reg [llols_cnt_width-1:0] rlols0_cnt; + wire rlols0_cnt_tc; + reg [2:0] rxp_cnt; + reg rxp_rst; + wire rxp_cnt_tc; + + wire rx_any_serd_rst; + reg [llols_cnt_width-1:0] rlolsz_cnt; + wire rlolsz_cnt_tc; + reg [2:0] rxp_cnt2; + reg rxp_rst2; + wire rxp_cnt2_tc; + reg [15:0] data_loop_b_cnt; + reg data_loop_b; + wire data_loop_b_tc; + + // ruo_rx_rdy + reg [pnum_channels-1:0] rxsr_appd; + reg [pnum_channels-1:0] rxpr_appd; + reg rxsdr_appd /* synthesis syn_keep=1 */; + reg rxdpr_appd; + wire rxsdr_or_sr_appd; + wire dual_or_rserd_rst; + wire rx_any_pcs_rst; + wire rx_any_rst; + reg rxr_wt_en; + reg [lrxr_wait_width-1:0] rxr_wt_cnt; + wire rxr_wt_tc; + reg ruo_rx_rdyr; + +// ================================================================== +// Start of code +// ================================================================== + assign rsl_enable = ~rui_rsl_disable; + +// ------------ rdo_serdes_rst_dual_c + assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c; + +// ------------ rdo_rst_dual_c + assign rdo_rst_dual_c = rui_rst_dual_c; + +// ------------ Setting counter values for RSL_SIM_MODE + `ifdef RSL_SIM_MODE + assign wait_b4_trst = lwait_b4_trst_s; + assign wait_b4_rrst = lwait_b4_rrst_s; + assign wait_after_lols = lwait_after_lols_s; + `else + assign wait_b4_trst = lwait_b4_trst; + assign wait_b4_rrst = lwait_b4_rrst; + assign wait_after_lols = lwait_after_lols; + `endif + +// ================================================================== +// Tx +// ================================================================== + generate + if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin + +// ------------ Synchronizing pll_lol to the tx clock + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + pll_lol_p1 <= 1'd0; + pll_lol_p2 <= 1'd0; + pll_lol_p3 <= 1'd0; + end + else begin + pll_lol_p1 <= rdi_pll_lol; + pll_lol_p2 <= pll_lol_p1; + pll_lol_p3 <= pll_lol_p2; + end + end + +// ------------ rdo_tx_serdes_rst_c + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol_cnt <= 'd0; + else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1)) + plol_cnt <= 'd0; + else + plol_cnt <= plol_cnt+1; + end + assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txs_cnt <= 'd0; // tx serdes reset pulse count + txs_rst <= 1'b0; // tx serdes reset + end + else if(plol_cnt_tc==1) + txs_rst <= 1'b1; + else if(txs_cnt_tc==1) begin + txs_cnt <= 'd0; + txs_rst <= 1'b0; + end + else if(txs_rst==1) + txs_cnt <= txs_cnt+1; + end + assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0; + + assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c; + +// ------------ rdo_tx_pcs_rst_c + assign plol_fedge = ~pll_lol_p2 & pll_lol_p3; + assign plol_redge = pll_lol_p2 & ~pll_lol_p3; + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + waita_plol0 <= 1'd0; + else if(plol_fedge==1'b1) + waita_plol0 <= 1'b1; + else if((plol0_cnt_tc==1)||(plol_redge==1)) + waita_plol0 <= 1'd0; + end + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) + plol0_cnt <= 'd0; + else if((pll_lol_p2==1)||(plol0_cnt_tc==1)) + plol0_cnt <= 'd0; + else if(waita_plol0==1'b1) + plol0_cnt <= plol0_cnt+1; + end + assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0; + + always @(posedge rui_tx_ref_clk or posedge rui_rst) begin + if(rui_rst==1'b1) begin + txp_cnt <= 'd0; // tx serdes reset pulse count + txp_rst <= 1'b0; // tx serdes reset + end + else if(plol0_cnt_tc==1) + txp_rst <= 1'b1; + else if(txp_cnt_tc==1) begin + txp_cnt <= 'd0; + txp_rst <= 1'b0; + end + else if(txp_rst==1) + txp_cnt <= txp_cnt+1; + end + assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0; + + genvar i; + for(i=0;i>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : SLL - Soft Loss Of Lock(LOL) Logic +// File : sll_core.v +// Title : Top-level file for SLL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : March 2, 2015 +// Changes Made : Initial Creation +// ============================================================================= +// REVISION HISTORY +// Version : 1.1 +// Author(s) : AV +// Mod. Date : June 8, 2015 +// Changes Made : Following updates were made +// : 1. Changed all the PLOL status logic and FSM to run +// : on sli_refclk. +// : 2. Added the HB logic for presence of tx_pclk +// : 3. Changed the lparam assignment scheme for +// : simulation purposes. +// ============================================================================= +// REVISION HISTORY +// Version : 1.2 +// Author(s) : AV +// Mod. Date : June 24, 2015 +// Changes Made : Updated the gearing logic for SDI dynamic rate change +// ============================================================================= +// REVISION HISTORY +// Version : 1.3 +// Author(s) : AV +// Mod. Date : July 14, 2015 +// Changes Made : Added the logic for dynamic rate change in CPRI +// ============================================================================= +// REVISION HISTORY +// Version : 1.4 +// Author(s) : AV +// Mod. Date : August 21, 2015 +// Changes Made : Added the logic for dynamic rate change of 5G CPRI & +// PCIe. +// ============================================================================= +// REVISION HISTORY +// Version : 1.5 +// Author(s) : ES/EB +// Mod. Date : March 21, 2017 +// Changes Made : 1. Added pdiff_sync signal to syncrhonize pcount_diff +// : to sli_refclk. +// : 2. Updated terminal count logic for PCIe 5G +// : 3. Modified checking of pcount_diff in SLL state +// : machine to cover actual count +// : (from 16-bits to 22-bits) +// ============================================================================= +// REVISION HISTORY +// Version : 1.6 +// Author(s) : ES +// Mod. Date : April 19, 2017 +// Changes Made : 1. Added registered lock and unlock signal from +// pdiff_sync to totally decouple pcount_diff from +// SLL state machine. +// : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI +// is operating @ 4.9125Gbps data rate. +// ============================================================================= +`timescale 1ns/10ps + +module sgmii_ecp5sll_core ( + //Reset and Clock inputs + sli_rst, //Active high asynchronous reset input + sli_refclk, //Refclk input to the Tx PLL + sli_pclk, //Tx pclk output from the PCS + + //Control inputs + sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate + sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11 + sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20 + sli_cpri_mode, //Mode of operation specific to CPRI protocol + sli_pcie_mode, //Mode of operation specific to PCIe mode (2.5G or 5G) + + //LOL Output + slo_plol //Tx PLL Loss of Lock output to the user logic + ); + +// Inputs +input sli_rst; +input sli_refclk; +input sli_pclk; +input sli_div2_rate; +input sli_div11_rate; +input sli_gear_mode; +input [2:0] sli_cpri_mode; +input sli_pcie_mode; + +// Outputs +output slo_plol; + + +// Parameters +parameter PPROTOCOL = "PCIE"; //Protocol selected by the User +parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3 +parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control +parameter PPCIE_MAX_RATE = "2.5"; //PCIe max data rate +parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock +parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock +parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk +parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11 +parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11 +parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk + + +// Local Parameters +localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state +localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state +localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state +localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state +`ifdef RSL_SIM_MODE +localparam [15:0] LRCLK_TC = 16'd63; //Terminal count value for counter running on sli_refclk +`else +localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk +`endif +localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse +localparam [7:0] LHB_WAIT_CNT = 8'd255; //Wait count for the Heartbeat signal + +// Local Parameters related to the CPRI dynamic modes +// Terminal count values for the four CPRI modes +localparam LPCLK_TC_0 = 32768; +localparam LPCLK_TC_1 = 65536; +localparam LPCLK_TC_2 = 131072; +localparam LPCLK_TC_3 = 163840; +localparam LPCLK_TC_4 = 65536; + +// Lock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_LOCK_00 = 9; localparam LPDIFF_LOCK_10 = 19; localparam LPDIFF_LOCK_20 = 39; localparam LPDIFF_LOCK_30 = 49; localparam LPDIFF_LOCK_40 = 19; +localparam LPDIFF_LOCK_01 = 9; localparam LPDIFF_LOCK_11 = 19; localparam LPDIFF_LOCK_21 = 39; localparam LPDIFF_LOCK_31 = 49; localparam LPDIFF_LOCK_41 = 19; +localparam LPDIFF_LOCK_02 = 49; localparam LPDIFF_LOCK_12 = 98; localparam LPDIFF_LOCK_22 = 196; localparam LPDIFF_LOCK_32 = 245; localparam LPDIFF_LOCK_42 = 98; +localparam LPDIFF_LOCK_03 = 131; localparam LPDIFF_LOCK_13 = 262; localparam LPDIFF_LOCK_23 = 524; localparam LPDIFF_LOCK_33 = 655; localparam LPDIFF_LOCK_43 = 262; + +// Unlock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_UNLOCK_00 = 19; localparam LPDIFF_UNLOCK_10 = 39; localparam LPDIFF_UNLOCK_20 = 78; localparam LPDIFF_UNLOCK_30 = 98; localparam LPDIFF_UNLOCK_40 = 39; +localparam LPDIFF_UNLOCK_01 = 65; localparam LPDIFF_UNLOCK_11 = 131; localparam LPDIFF_UNLOCK_21 = 262; localparam LPDIFF_UNLOCK_31 = 327; localparam LPDIFF_UNLOCK_41 = 131; +localparam LPDIFF_UNLOCK_02 = 72; localparam LPDIFF_UNLOCK_12 = 144; localparam LPDIFF_UNLOCK_22 = 288; localparam LPDIFF_UNLOCK_32 = 360; localparam LPDIFF_UNLOCK_42 = 144; +localparam LPDIFF_UNLOCK_03 = 196; localparam LPDIFF_UNLOCK_13 = 393; localparam LPDIFF_UNLOCK_23 = 786; localparam LPDIFF_UNLOCK_33 = 983; localparam LPDIFF_UNLOCK_43 = 393; + +// Input and Output reg and wire declarations +wire sli_rst; +wire sli_refclk; +wire sli_pclk; +wire sli_div2_rate; +wire sli_div11_rate; +wire sli_gear_mode; +wire [2:0] sli_cpri_mode; +wire sli_pcie_mode; +wire slo_plol; + +//-------------- Internal signals reg and wire declarations -------------------- + +//Signals running on sli_refclk +reg [15:0] rcount; //16-bit Counter +reg rtc_pul; //Terminal count pulse +reg rtc_pul_p1; //Terminal count pulse pipeline +reg rtc_ctrl; //Terminal count pulse control + +reg [7:0] rhb_wait_cnt; //Heartbeat wait counter + +//Heatbeat synchronization and pipeline registers +wire rhb_sync; +reg rhb_sync_p2; +reg rhb_sync_p1; + +//Pipeling registers for dynamic control mode +wire rgear; +wire rdiv2; +wire rdiv11; +reg rgear_p1; +reg rdiv2_p1; +reg rdiv11_p1; + +reg rstat_pclk; //Pclk presence/absence status + +reg [21:0] rcount_tc; //Tx_pclk terminal count register +reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock +reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock + +wire rpcie_mode; //PCIe mode signal synchronized to refclk +reg rpcie_mode_p1; //PCIe mode pipeline register + +wire rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk +reg rcpri_mod_ch_p1; //CPRI mode change pipeline register +reg rcpri_mod_ch_p2; //CPRI mode change pipeline register +reg rcpri_mod_ch_st; //CPRI mode change status + +reg [1:0] sll_state; //Current-state register for LOL FSM + +reg pll_lock; //PLL Lock signal + +//Signals running on sli_pclk +//Synchronization and pipeline registers +wire ppul_sync; +reg ppul_sync_p1; +reg ppul_sync_p2; +reg ppul_sync_p3; + +wire pdiff_sync; +reg pdiff_sync_p1; + +reg [21:0] pcount; //22-bit counter +reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value + +//Heartbeat counter and heartbeat signal running on pclk +reg [2:0] phb_cnt; +reg phb; + +//CPRI dynamic mode releated signals +reg [2:0] pcpri_mode; +reg pcpri_mod_ch; + +//Assignment scheme changed mainly for simulation purpose +wire [15:0] LRCLK_TC_w; +assign LRCLK_TC_w = LRCLK_TC; + +reg unlock; +reg lock; + +//Heartbeat synchronization +sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (phb), + .data_out(rhb_sync) + ); + + +//Terminal count pulse synchronization +sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( + .clk (sli_pclk), + .rst (sli_rst), + .data_in (rtc_pul), + .data_out(ppul_sync) + ); + +//Differential value logic update synchronization +sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (ppul_sync), + .data_out(pdiff_sync) + ); + +//Gear mode synchronization +sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_gear_mode), + .data_out(rgear) + ); + +//Div2 synchronization +sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div2_rate), + .data_out(rdiv2) + ); + +//Div11 synchronization +sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div11_rate), + .data_out(rdiv11) + ); + +//CPRI mode change synchronization +sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (pcpri_mod_ch), + .data_out(rcpri_mod_ch_sync) + ); + +//PCIe mode change synchronization +sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_pcie_mode), + .data_out(rpcie_mode) + ); + +// ============================================================================= +// Synchronized Lock/Unlock signals +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + unlock <= 1'b0; + lock <= 1'b0; + pdiff_sync_p1 <= 1'b0; + end + else begin + pdiff_sync_p1 <= pdiff_sync; + if (unlock) begin + unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock; + end + else begin + unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0; + end + if (lock) begin + lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock; + end + else begin + lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0; + end + end +end + +// ============================================================================= +// Refclk Counter, pulse generation logic and Heartbeat monitor logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount <= 16'd0; + rtc_pul <= 1'b0; + rtc_ctrl <= 1'b0; + rtc_pul_p1 <= 1'b0; + end + else begin + //Counter logic + if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + if (rtc_ctrl == 1'b1) begin + rcount <= LRCLK_TC_PUL_WIDTH; + end + end + else begin + if (rcount != LRCLK_TC_w) begin + rcount <= rcount + 1; + end + else begin + rcount <= 16'd0; + end + end + + //Pulse control logic + if (rcount == LRCLK_TC_w - 1) begin + rtc_ctrl <= 1'b1; + end + + //Pulse Generation logic + if (rtc_ctrl == 1'b1) begin + if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin + rtc_pul <= 1'b1; + end + else begin + rtc_pul <= 1'b0; + end + end + + rtc_pul_p1 <= rtc_pul; + end +end + + +// ============================================================================= +// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rhb_sync_p1 <= 1'b0; + rhb_sync_p2 <= 1'b0; + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + rgear_p1 <= 1'b0; + rdiv2_p1 <= 1'b0; + rdiv11_p1 <= 1'b0; + rcpri_mod_ch_p1 <= 1'b0; + rcpri_mod_ch_p2 <= 1'b0; + rcpri_mod_ch_st <= 1'b0; + rpcie_mode_p1 <= 1'b0; + + end + else begin + //Pipeline stages for the Heartbeat + rhb_sync_p1 <= rhb_sync; + rhb_sync_p2 <= rhb_sync_p1; + + //Pipeline stages of the Dynamic rate control signals + rgear_p1 <= rgear; + rdiv2_p1 <= rdiv2; + rdiv11_p1 <= rdiv11; + + //Pipeline stage for PCIe mode + rpcie_mode_p1 <= rpcie_mode; + + //Pipeline stage for CPRI mode change + rcpri_mod_ch_p1 <= rcpri_mod_ch_sync; + rcpri_mod_ch_p2 <= rcpri_mod_ch_p1; + + //CPRI mode change status logic + if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin + rcpri_mod_ch_st <= 1'b1; + end + + //Heartbeat wait counter and monitor logic + if (rtc_ctrl == 1'b1) begin + if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b1; + end + else if (rhb_wait_cnt == LHB_WAIT_CNT) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + end + else begin + rhb_wait_cnt <= rhb_wait_cnt + 1; + end + end + end +end + + +// ============================================================================= +// Pipleline registers for the TC pulse and CPRI mode change logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + ppul_sync_p1 <= 1'b0; + ppul_sync_p2 <= 1'b0; + ppul_sync_p3 <= 1'b0; + pcpri_mode <= 3'b0; + pcpri_mod_ch <= 1'b0; + end + else begin + ppul_sync_p1 <= ppul_sync; + ppul_sync_p2 <= ppul_sync_p1; + ppul_sync_p3 <= ppul_sync_p2; + + //CPRI mode change logic + pcpri_mode <= sli_cpri_mode; + + if (pcpri_mode != sli_cpri_mode) begin + pcpri_mod_ch <= ~pcpri_mod_ch; + end + end +end + + +// ============================================================================= +// Terminal count logic +// ============================================================================= + +//For SDI protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 11 is enabled + if (rdiv11 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_DIV11_TC; + rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0}; + rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0}; + rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0}; + end + end + //Div by 2 is enabled + else if (rdiv2 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end + //Both div by 11 and div by 2 are disabled + else begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_TC[20:0],1'b0}; + rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0}; + rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0}; + end + end + end +end +end +endgenerate + +//For G8B10B protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 2 is enabled + if (rdiv2 == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + + +//For CPRI protocol with Dynamic rate control is disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for CPRI protocol + //Only if there is a change in the rate mode from the default + if (rcpri_mod_ch_st == 1'b1) begin + if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin + case(sli_cpri_mode) + 3'd0 : begin //For 0.6Gbps + rcount_tc <= LPCLK_TC_0; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_01; + rdiff_comp_unlock <= LPDIFF_UNLOCK_01; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_02; + rdiff_comp_unlock <= LPDIFF_UNLOCK_02; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_03; + rdiff_comp_unlock <= LPDIFF_UNLOCK_03; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + + 3'd1 : begin //For 1.2Gbps + rcount_tc <= LPCLK_TC_1; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_11; + rdiff_comp_unlock <= LPDIFF_UNLOCK_11; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_12; + rdiff_comp_unlock <= LPDIFF_UNLOCK_12; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_13; + rdiff_comp_unlock <= LPDIFF_UNLOCK_13; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + endcase + end + + 3'd2 : begin //For 2.4Gbps + rcount_tc <= LPCLK_TC_2; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_21; + rdiff_comp_unlock <= LPDIFF_UNLOCK_21; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_22; + rdiff_comp_unlock <= LPDIFF_UNLOCK_22; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_23; + rdiff_comp_unlock <= LPDIFF_UNLOCK_23; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + endcase + end + + 3'd3 : begin //For 3.07Gbps + rcount_tc <= LPCLK_TC_3; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_30; + rdiff_comp_unlock <= LPDIFF_UNLOCK_30; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_31; + rdiff_comp_unlock <= LPDIFF_UNLOCK_31; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_32; + rdiff_comp_unlock <= LPDIFF_UNLOCK_32; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_33; + rdiff_comp_unlock <= LPDIFF_UNLOCK_33; + end + endcase + end + + 3'd4 : begin //For 4.9125bps + rcount_tc <= LPCLK_TC_4; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_41; + rdiff_comp_unlock <= LPDIFF_UNLOCK_41; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_42; + rdiff_comp_unlock <= LPDIFF_UNLOCK_42; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_43; + rdiff_comp_unlock <= LPDIFF_UNLOCK_43; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + endcase + end + + default : begin + rcount_tc <= LPCLK_TC_0; + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + end + else begin + //If there is no change in the CPRI rate mode from default + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + +//For PCIe protocol with Dynamic rate control disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + if (PPCIE_MAX_RATE == "2.5") begin + //2.5G mode is enabled + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //5G mode is enabled + if (rpcie_mode == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //2.5G mode is enabled + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + end + end +end +end +endgenerate + +//For all protocols other than CPRI & PCIe +generate +if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for all protocols other than CPRI & PCIe + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end +end +end +endgenerate + + +// ============================================================================= +// Tx_pclk counter, Heartbeat and Differential value logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pcount <= 22'd0; + pcount_diff <= 22'd65535; + phb_cnt <= 3'd0; + phb <= 1'b0; + end + else begin + //Counter logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount <= 22'd0; + end + else begin + pcount <= pcount + 1; + end + + //Heartbeat logic + phb_cnt <= phb_cnt + 1; + + if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin + phb <= 1'b1; + end + else begin + phb <= 1'b0; + end + + //Differential value logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount_diff <= rcount_tc + ~(pcount) + 1; + end + else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin + if (pcount_diff[21] == 1'b1) begin + pcount_diff <= ~(pcount_diff) + 1; + end + end + end +end + + +// ============================================================================= +// State transition logic for SLL FSM +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI + if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || + (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_LOSS_ST; + end + else if (lock) begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_PRELOCK_ST; + end + else begin + sll_state <= LPLL_LOCK_ST; + end + end + end + end + + LPLL_LOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + end + + LPLL_PRELOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + + LPLL_PRELOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_PRELOSS_ST; + end + else if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + end + end + + default: begin + sll_state <= LPLL_LOSS_ST; + end + endcase + end + end +end + + +// ============================================================================= +// Logic for Tx PLL Lock +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pll_lock <= 1'b0; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + pll_lock <= 1'b0; + end + + LPLL_LOCK_ST : begin + pll_lock <= 1'b1; + end + + LPLL_PRELOSS_ST : begin + pll_lock <= 1'b0; + end + + default: begin + pll_lock <= 1'b0; + end + endcase + end +end + +assign slo_plol = ~(pll_lock); + +endmodule + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : Synchronizer Logic +// File : sync.v +// Title : Synchronizer module +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : July 7, 2015 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : EB +// Mod. Date : March 21, 2017 +// Changes Made : +// ============================================================================= + +`ifndef PCS_SYNC_MODULE +`define PCS_SYNC_MODULE +module sync ( + clk, + rst, + data_in, + data_out + ); + +input clk; //Clock in which the async data needs to be synchronized to +input rst; //Active high reset +input data_in; //Asynchronous data +output data_out; //Synchronized data + +parameter PDATA_RST_VAL = 0; //Reset value for the registers + +reg data_p1; +reg data_p2; + +// ============================================================================= +// Synchronization logic +// ============================================================================= +always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + data_p1 <= PDATA_RST_VAL; + data_p2 <= PDATA_RST_VAL; + end + else begin + data_p1 <= data_in; + data_p2 <= data_p1; + end +end + +assign data_out = data_p2; + +endmodule +`endif + diff --git a/gbe_trb/media/ecp5/sgmii_ecp5_softlogic.v_old b/gbe_trb/media/ecp5/sgmii_ecp5_softlogic.v_old new file mode 100644 index 0000000..f730049 --- /dev/null +++ b/gbe_trb/media/ecp5/sgmii_ecp5_softlogic.v_old @@ -0,0 +1,1060 @@ + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : SLL - Soft Loss Of Lock(LOL) Logic +// File : sll_core.v +// Title : Top-level file for SLL +// Dependencies : 1. +// : 2. +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : March 2, 2015 +// Changes Made : Initial Creation +// ============================================================================= +// REVISION HISTORY +// Version : 1.1 +// Author(s) : AV +// Mod. Date : June 8, 2015 +// Changes Made : Following updates were made +// : 1. Changed all the PLOL status logic and FSM to run +// : on sli_refclk. +// : 2. Added the HB logic for presence of tx_pclk +// : 3. Changed the lparam assignment scheme for +// : simulation purposes. +// ============================================================================= +// REVISION HISTORY +// Version : 1.2 +// Author(s) : AV +// Mod. Date : June 24, 2015 +// Changes Made : Updated the gearing logic for SDI dynamic rate change +// ============================================================================= +// REVISION HISTORY +// Version : 1.3 +// Author(s) : AV +// Mod. Date : July 14, 2015 +// Changes Made : Added the logic for dynamic rate change in CPRI +// ============================================================================= +// REVISION HISTORY +// Version : 1.4 +// Author(s) : AV +// Mod. Date : August 21, 2015 +// Changes Made : Added the logic for dynamic rate change of 5G CPRI & +// PCIe. +// ============================================================================= +// REVISION HISTORY +// Version : 1.5 +// Author(s) : ES/EB +// Mod. Date : March 21, 2017 +// Changes Made : 1. Added pdiff_sync signal to syncrhonize pcount_diff +// : to sli_refclk. +// : 2. Updated terminal count logic for PCIe 5G +// : 3. Modified checking of pcount_diff in SLL state +// : machine to cover actual count +// : (from 16-bits to 22-bits) +// ============================================================================= +// REVISION HISTORY +// Version : 1.6 +// Author(s) : ES +// Mod. Date : April 19, 2017 +// Changes Made : 1. Added registered lock and unlock signal from +// pdiff_sync to totally decouple pcount_diff from +// SLL state machine. +// : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI +// is operating @ 4.9125Gbps data rate. +// ============================================================================= +`timescale 1ns/10ps + +module sgmii_ecp5sll_core ( + //Reset and Clock inputs + sli_rst, //Active high asynchronous reset input + sli_refclk, //Refclk input to the Tx PLL + sli_pclk, //Tx pclk output from the PCS + + //Control inputs + sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate + sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11 + sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20 + sli_cpri_mode, //Mode of operation specific to CPRI protocol + sli_pcie_mode, //Mode of operation specific to PCIe mode (2.5G or 5G) + + //LOL Output + slo_plol //Tx PLL Loss of Lock output to the user logic + ); + +// Inputs +input sli_rst; +input sli_refclk; +input sli_pclk; +input sli_div2_rate; +input sli_div11_rate; +input sli_gear_mode; +input [2:0] sli_cpri_mode; +input sli_pcie_mode; + +// Outputs +output slo_plol; + + +// Parameters +parameter PPROTOCOL = "PCIE"; //Protocol selected by the User +parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3 +parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control +parameter PPCIE_MAX_RATE = "2.5"; //PCIe max data rate +parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock +parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock +parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk +parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11 +parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11 +parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk + + +// Local Parameters +localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state +localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state +localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state +localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state +`ifdef RSL_SIM_MODE +localparam [15:0] LRCLK_TC = 16'd63; //Terminal count value for counter running on sli_refclk +`else +localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk +`endif +localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse +localparam [7:0] LHB_WAIT_CNT = 8'd255; //Wait count for the Heartbeat signal + +// Local Parameters related to the CPRI dynamic modes +// Terminal count values for the four CPRI modes +localparam LPCLK_TC_0 = 32768; +localparam LPCLK_TC_1 = 65536; +localparam LPCLK_TC_2 = 131072; +localparam LPCLK_TC_3 = 163840; +localparam LPCLK_TC_4 = 65536; + +// Lock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_LOCK_00 = 9; localparam LPDIFF_LOCK_10 = 19; localparam LPDIFF_LOCK_20 = 39; localparam LPDIFF_LOCK_30 = 49; localparam LPDIFF_LOCK_40 = 19; +localparam LPDIFF_LOCK_01 = 9; localparam LPDIFF_LOCK_11 = 19; localparam LPDIFF_LOCK_21 = 39; localparam LPDIFF_LOCK_31 = 49; localparam LPDIFF_LOCK_41 = 19; +localparam LPDIFF_LOCK_02 = 49; localparam LPDIFF_LOCK_12 = 98; localparam LPDIFF_LOCK_22 = 196; localparam LPDIFF_LOCK_32 = 245; localparam LPDIFF_LOCK_42 = 98; +localparam LPDIFF_LOCK_03 = 131; localparam LPDIFF_LOCK_13 = 262; localparam LPDIFF_LOCK_23 = 524; localparam LPDIFF_LOCK_33 = 655; localparam LPDIFF_LOCK_43 = 262; + +// Unlock values count values for the four CPRI modes and four PLOL settings (4x5) +// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4 +localparam LPDIFF_UNLOCK_00 = 19; localparam LPDIFF_UNLOCK_10 = 39; localparam LPDIFF_UNLOCK_20 = 78; localparam LPDIFF_UNLOCK_30 = 98; localparam LPDIFF_UNLOCK_40 = 39; +localparam LPDIFF_UNLOCK_01 = 65; localparam LPDIFF_UNLOCK_11 = 131; localparam LPDIFF_UNLOCK_21 = 262; localparam LPDIFF_UNLOCK_31 = 327; localparam LPDIFF_UNLOCK_41 = 131; +localparam LPDIFF_UNLOCK_02 = 72; localparam LPDIFF_UNLOCK_12 = 144; localparam LPDIFF_UNLOCK_22 = 288; localparam LPDIFF_UNLOCK_32 = 360; localparam LPDIFF_UNLOCK_42 = 144; +localparam LPDIFF_UNLOCK_03 = 196; localparam LPDIFF_UNLOCK_13 = 393; localparam LPDIFF_UNLOCK_23 = 786; localparam LPDIFF_UNLOCK_33 = 983; localparam LPDIFF_UNLOCK_43 = 393; + +// Input and Output reg and wire declarations +wire sli_rst; +wire sli_refclk; +wire sli_pclk; +wire sli_div2_rate; +wire sli_div11_rate; +wire sli_gear_mode; +wire [2:0] sli_cpri_mode; +wire sli_pcie_mode; +wire slo_plol; + +//-------------- Internal signals reg and wire declarations -------------------- + +//Signals running on sli_refclk +reg [15:0] rcount; //16-bit Counter +reg rtc_pul; //Terminal count pulse +reg rtc_pul_p1; //Terminal count pulse pipeline +reg rtc_ctrl; //Terminal count pulse control + +reg [7:0] rhb_wait_cnt; //Heartbeat wait counter + +//Heatbeat synchronization and pipeline registers +wire rhb_sync; +reg rhb_sync_p2; +reg rhb_sync_p1; + +//Pipeling registers for dynamic control mode +wire rgear; +wire rdiv2; +wire rdiv11; +reg rgear_p1; +reg rdiv2_p1; +reg rdiv11_p1; + +reg rstat_pclk; //Pclk presence/absence status + +reg [21:0] rcount_tc; //Tx_pclk terminal count register +reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock +reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock + +wire rpcie_mode; //PCIe mode signal synchronized to refclk +reg rpcie_mode_p1; //PCIe mode pipeline register + +wire rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk +reg rcpri_mod_ch_p1; //CPRI mode change pipeline register +reg rcpri_mod_ch_p2; //CPRI mode change pipeline register +reg rcpri_mod_ch_st; //CPRI mode change status + +reg [1:0] sll_state; //Current-state register for LOL FSM + +reg pll_lock; //PLL Lock signal + +//Signals running on sli_pclk +//Synchronization and pipeline registers +wire ppul_sync; +reg ppul_sync_p1; +reg ppul_sync_p2; +reg ppul_sync_p3; + +wire pdiff_sync; +reg pdiff_sync_p1; + +reg [21:0] pcount; //22-bit counter +reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value + +//Heartbeat counter and heartbeat signal running on pclk +reg [2:0] phb_cnt; +reg phb; + +//CPRI dynamic mode releated signals +reg [2:0] pcpri_mode; +reg pcpri_mod_ch; + +//Assignment scheme changed mainly for simulation purpose +wire [15:0] LRCLK_TC_w; +assign LRCLK_TC_w = LRCLK_TC; + +reg unlock; +reg lock; + +//Heartbeat synchronization +sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (phb), + .data_out(rhb_sync) + ); + + +//Terminal count pulse synchronization +sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( + .clk (sli_pclk), + .rst (sli_rst), + .data_in (rtc_pul), + .data_out(ppul_sync) + ); + +//Differential value logic update synchronization +sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (ppul_sync), + .data_out(pdiff_sync) + ); + +//Gear mode synchronization +sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_gear_mode), + .data_out(rgear) + ); + +//Div2 synchronization +sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div2_rate), + .data_out(rdiv2) + ); + +//Div11 synchronization +sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_div11_rate), + .data_out(rdiv11) + ); + +//CPRI mode change synchronization +sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (pcpri_mod_ch), + .data_out(rcpri_mod_ch_sync) + ); + +//PCIe mode change synchronization +sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( + .clk (sli_refclk), + .rst (sli_rst), + .data_in (sli_pcie_mode), + .data_out(rpcie_mode) + ); + +// ============================================================================= +// Synchronized Lock/Unlock signals +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + unlock <= 1'b0; + lock <= 1'b0; + pdiff_sync_p1 <= 1'b0; + end + else begin + pdiff_sync_p1 <= pdiff_sync; + if (unlock) begin + unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock; + end + else begin + unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0; + end + if (lock) begin + lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock; + end + else begin + lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0; + end + end +end + +// ============================================================================= +// Refclk Counter, pulse generation logic and Heartbeat monitor logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount <= 16'd0; + rtc_pul <= 1'b0; + rtc_ctrl <= 1'b0; + rtc_pul_p1 <= 1'b0; + end + else begin + //Counter logic + if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + if (rtc_ctrl == 1'b1) begin + rcount <= LRCLK_TC_PUL_WIDTH; + end + end + else begin + if (rcount != LRCLK_TC_w) begin + rcount <= rcount + 1; + end + else begin + rcount <= 16'd0; + end + end + + //Pulse control logic + if (rcount == LRCLK_TC_w - 1) begin + rtc_ctrl <= 1'b1; + end + + //Pulse Generation logic + if (rtc_ctrl == 1'b1) begin + if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin + rtc_pul <= 1'b1; + end + else begin + rtc_pul <= 1'b0; + end + end + + rtc_pul_p1 <= rtc_pul; + end +end + + +// ============================================================================= +// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rhb_sync_p1 <= 1'b0; + rhb_sync_p2 <= 1'b0; + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + rgear_p1 <= 1'b0; + rdiv2_p1 <= 1'b0; + rdiv11_p1 <= 1'b0; + rcpri_mod_ch_p1 <= 1'b0; + rcpri_mod_ch_p2 <= 1'b0; + rcpri_mod_ch_st <= 1'b0; + rpcie_mode_p1 <= 1'b0; + + end + else begin + //Pipeline stages for the Heartbeat + rhb_sync_p1 <= rhb_sync; + rhb_sync_p2 <= rhb_sync_p1; + + //Pipeline stages of the Dynamic rate control signals + rgear_p1 <= rgear; + rdiv2_p1 <= rdiv2; + rdiv11_p1 <= rdiv11; + + //Pipeline stage for PCIe mode + rpcie_mode_p1 <= rpcie_mode; + + //Pipeline stage for CPRI mode change + rcpri_mod_ch_p1 <= rcpri_mod_ch_sync; + rcpri_mod_ch_p2 <= rcpri_mod_ch_p1; + + //CPRI mode change status logic + if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin + rcpri_mod_ch_st <= 1'b1; + end + + //Heartbeat wait counter and monitor logic + if (rtc_ctrl == 1'b1) begin + if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b1; + end + else if (rhb_wait_cnt == LHB_WAIT_CNT) begin + rhb_wait_cnt <= 8'd0; + rstat_pclk <= 1'b0; + end + else begin + rhb_wait_cnt <= rhb_wait_cnt + 1; + end + end + end +end + + +// ============================================================================= +// Pipleline registers for the TC pulse and CPRI mode change logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + ppul_sync_p1 <= 1'b0; + ppul_sync_p2 <= 1'b0; + ppul_sync_p3 <= 1'b0; + pcpri_mode <= 3'b0; + pcpri_mod_ch <= 1'b0; + end + else begin + ppul_sync_p1 <= ppul_sync; + ppul_sync_p2 <= ppul_sync_p1; + ppul_sync_p3 <= ppul_sync_p2; + + //CPRI mode change logic + pcpri_mode <= sli_cpri_mode; + + if (pcpri_mode != sli_cpri_mode) begin + pcpri_mod_ch <= ~pcpri_mod_ch; + end + end +end + + +// ============================================================================= +// Terminal count logic +// ============================================================================= + +//For SDI protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 11 is enabled + if (rdiv11 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_DIV11_TC; + rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0}; + rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0}; + rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0}; + end + end + //Div by 2 is enabled + else if (rdiv2 == 1'b1) begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end + //Both div by 11 and div by 2 are disabled + else begin + //Gear mode is 16/20 + if (rgear == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + rcount_tc <= {PPCLK_TC[20:0],1'b0}; + rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0}; + rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0}; + end + end + end +end +end +endgenerate + +//For G8B10B protocol with Dynamic rate control enabled +generate +if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + //Div by 2 is enabled + if (rdiv2 == 1'b1) begin + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + else begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + + +//For CPRI protocol with Dynamic rate control is disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for CPRI protocol + //Only if there is a change in the rate mode from the default + if (rcpri_mod_ch_st == 1'b1) begin + if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin + case(sli_cpri_mode) + 3'd0 : begin //For 0.6Gbps + rcount_tc <= LPCLK_TC_0; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_01; + rdiff_comp_unlock <= LPDIFF_UNLOCK_01; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_02; + rdiff_comp_unlock <= LPDIFF_UNLOCK_02; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_03; + rdiff_comp_unlock <= LPDIFF_UNLOCK_03; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + + 3'd1 : begin //For 1.2Gbps + rcount_tc <= LPCLK_TC_1; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_11; + rdiff_comp_unlock <= LPDIFF_UNLOCK_11; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_12; + rdiff_comp_unlock <= LPDIFF_UNLOCK_12; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_13; + rdiff_comp_unlock <= LPDIFF_UNLOCK_13; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_10; + rdiff_comp_unlock <= LPDIFF_UNLOCK_10; + end + endcase + end + + 3'd2 : begin //For 2.4Gbps + rcount_tc <= LPCLK_TC_2; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_21; + rdiff_comp_unlock <= LPDIFF_UNLOCK_21; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_22; + rdiff_comp_unlock <= LPDIFF_UNLOCK_22; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_23; + rdiff_comp_unlock <= LPDIFF_UNLOCK_23; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_20; + rdiff_comp_unlock <= LPDIFF_UNLOCK_20; + end + endcase + end + + 3'd3 : begin //For 3.07Gbps + rcount_tc <= LPCLK_TC_3; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_30; + rdiff_comp_unlock <= LPDIFF_UNLOCK_30; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_31; + rdiff_comp_unlock <= LPDIFF_UNLOCK_31; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_32; + rdiff_comp_unlock <= LPDIFF_UNLOCK_32; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_33; + rdiff_comp_unlock <= LPDIFF_UNLOCK_33; + end + endcase + end + + 3'd4 : begin //For 4.9125bps + rcount_tc <= LPCLK_TC_4; + case(PLOL_SETTING) + 'd0 : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + + 'd1 : begin + rdiff_comp_lock <= LPDIFF_LOCK_41; + rdiff_comp_unlock <= LPDIFF_UNLOCK_41; + end + + 'd2 : begin + rdiff_comp_lock <= LPDIFF_LOCK_42; + rdiff_comp_unlock <= LPDIFF_UNLOCK_42; + end + + 'd3 : begin + rdiff_comp_lock <= LPDIFF_LOCK_43; + rdiff_comp_unlock <= LPDIFF_UNLOCK_43; + end + + default : begin + rdiff_comp_lock <= LPDIFF_LOCK_40; + rdiff_comp_unlock <= LPDIFF_UNLOCK_40; + end + endcase + end + + default : begin + rcount_tc <= LPCLK_TC_0; + rdiff_comp_lock <= LPDIFF_LOCK_00; + rdiff_comp_unlock <= LPDIFF_UNLOCK_00; + end + endcase + end + end + else begin + //If there is no change in the CPRI rate mode from default + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + end +end +end +endgenerate + +//For PCIe protocol with Dynamic rate control disabled +generate +if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic + if (PPCIE_MAX_RATE == "2.5") begin + //2.5G mode is enabled + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //5G mode is enabled + if (rpcie_mode == 1'b1) begin + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end + else begin + //2.5G mode is enabled + rcount_tc <= {1'b0,PPCLK_TC[21:1]}; + rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]}; + rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]}; + end + end + end +end +end +endgenerate + +//For all protocols other than CPRI & PCIe +generate +if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + rcount_tc <= 22'd0; + rdiff_comp_lock <= 16'd0; + rdiff_comp_unlock <= 16'd0; + end + else begin + //Terminal count logic for all protocols other than CPRI & PCIe + rcount_tc <= PPCLK_TC; + rdiff_comp_lock <= PDIFF_VAL_LOCK; + rdiff_comp_unlock <= PDIFF_VAL_UNLOCK; + end +end +end +endgenerate + + +// ============================================================================= +// Tx_pclk counter, Heartbeat and Differential value logic +// ============================================================================= +always @(posedge sli_pclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pcount <= 22'd0; + pcount_diff <= 22'd65535; + phb_cnt <= 3'd0; + phb <= 1'b0; + end + else begin + //Counter logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount <= 22'd0; + end + else begin + pcount <= pcount + 1; + end + + //Heartbeat logic + phb_cnt <= phb_cnt + 1; + + if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin + phb <= 1'b1; + end + else begin + phb <= 1'b0; + end + + //Differential value logic + if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin + pcount_diff <= rcount_tc + ~(pcount) + 1; + end + else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin + if (pcount_diff[21] == 1'b1) begin + pcount_diff <= ~(pcount_diff) + 1; + end + end + end +end + + +// ============================================================================= +// State transition logic for SLL FSM +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI + if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || + (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_LOSS_ST; + end + else if (lock) begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_PRELOCK_ST; + end + else begin + sll_state <= LPLL_LOCK_ST; + end + end + end + end + + LPLL_LOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + if (PLOL_SETTING == 2'd0) begin + sll_state <= LPLL_LOSS_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + end + + LPLL_PRELOCK_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + else begin + sll_state <= LPLL_PRELOSS_ST; + end + end + end + + LPLL_PRELOSS_ST : begin + if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin + if (unlock) begin + sll_state <= LPLL_PRELOSS_ST; + end + else if (lock) begin + sll_state <= LPLL_LOCK_ST; + end + end + end + + default: begin + sll_state <= LPLL_LOSS_ST; + end + endcase + end + end +end + + +// ============================================================================= +// Logic for Tx PLL Lock +// ============================================================================= +always @(posedge sli_refclk or posedge sli_rst) begin + if (sli_rst == 1'b1) begin + pll_lock <= 1'b0; + end + else begin + case(sll_state) + LPLL_LOSS_ST : begin + pll_lock <= 1'b0; + end + + LPLL_LOCK_ST : begin + pll_lock <= 1'b1; + end + + LPLL_PRELOSS_ST : begin + pll_lock <= 1'b0; + end + + default: begin + pll_lock <= 1'b0; + end + endcase + end +end + +assign slo_plol = ~(pll_lock); + +endmodule + + +// =========================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< +// --------------------------------------------------------------------------- +// Copyright (c) 2015 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code +// pursuant to the terms of the Lattice Reference Design License Agreement. +// +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// --------------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// --------------------------------------------------------------------------- +// +// ============================================================================= +// FILE DETAILS +// Project : Synchronizer Logic +// File : sync.v +// Title : Synchronizer module +// Description : +// ============================================================================= +// REVISION HISTORY +// Version : 1.0 +// Author(s) : AV +// Mod. Date : July 7, 2015 +// Changes Made : Initial Creation +// ----------------------------------------------------------------------------- +// Version : 1.1 +// Author(s) : EB +// Mod. Date : March 21, 2017 +// Changes Made : +// ============================================================================= + +`ifndef PCS_SYNC_MODULE +`define PCS_SYNC_MODULE +module sync ( + clk, + rst, + data_in, + data_out + ); + +input clk; //Clock in which the async data needs to be synchronized to +input rst; //Active high reset +input data_in; //Asynchronous data +output data_out; //Synchronized data + +parameter PDATA_RST_VAL = 0; //Reset value for the registers + +reg data_p1; +reg data_p2; + +// ============================================================================= +// Synchronization logic +// ============================================================================= +always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + data_p1 <= PDATA_RST_VAL; + data_p2 <= PDATA_RST_VAL; + end + else begin + data_p1 <= data_in; + data_p2 <= data_p1; + end +end + +assign data_out = data_p2; + +endmodule +`endif + diff --git a/gbe_trb/media/ecp5/sgmii_ecp5_txpllLoLdeleted.vhd b/gbe_trb/media/ecp5/sgmii_ecp5_txpllLoLdeleted.vhd new file mode 100644 index 0000000..d4b7e6e --- /dev/null +++ b/gbe_trb/media/ecp5/sgmii_ecp5_txpllLoLdeleted.vhd @@ -0,0 +1,433 @@ + +-- +-- Verific VHDL Description of module DCUA +-- + +-- DCUA is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module sgmii_ecp5rsl_core +-- + +-- sgmii_ecp5rsl_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module sgmii_ecp5sll_core +-- + +-- sgmii_ecp5sll_core is a black-box. Cannot print a valid VHDL entity description for it + +-- +-- Verific VHDL Description of module sgmii_ecp5 +-- + +library ieee ; +use ieee.std_logic_1164.all ; + +library ecp5um ; +use ecp5um.components.all ; + +entity sgmii_ecp5 is + port (hdoutp: out std_logic; + hdoutn: out std_logic; + hdinp: in std_logic; + hdinn: in std_logic; + rxrefclk: in std_logic; + tx_pclk: out std_logic; + txi_clk: in std_logic; + txdata: in std_logic_vector(7 downto 0); + tx_k: in std_logic_vector(0 downto 0); + xmit: in std_logic_vector(0 downto 0); + tx_disp_correct: in std_logic_vector(0 downto 0); + rxdata: out std_logic_vector(7 downto 0); + rx_k: out std_logic_vector(0 downto 0); + rx_disp_err: out std_logic_vector(0 downto 0); + rx_cv_err: out std_logic_vector(0 downto 0); + signal_detect_c: in std_logic; + rx_los_low_s: out std_logic; + lsm_status_s: out std_logic; + ctc_urun_s: out std_logic; + ctc_orun_s: out std_logic; + rx_cdr_lol_s: out std_logic; + ctc_ins_s: out std_logic; + ctc_del_s: out std_logic; + sli_rst: in std_logic; + tx_pwrup_c: in std_logic; + rx_pwrup_c: in std_logic; + sci_wrdata: in std_logic_vector(7 downto 0); + sci_addr: in std_logic_vector(5 downto 0); + sci_rddata: out std_logic_vector(7 downto 0); + sci_en_dual: in std_logic; + sci_sel_dual: in std_logic; + sci_en: in std_logic; + sci_sel: in std_logic; + sci_rd: in std_logic; + sci_wrn: in std_logic; + sci_int: out std_logic; + cyawstn: in std_logic; + serdes_pdb: in std_logic; + pll_refclki: in std_logic; + rsl_disable: in std_logic; + rsl_rst: in std_logic; + serdes_rst_dual_c: in std_logic; + rst_dual_c: in std_logic; + tx_serdes_rst_c: in std_logic; + tx_pcs_rst_c: in std_logic; + pll_lol: out std_logic; + rsl_tx_rdy: out std_logic; + rx_serdes_rst_c: in std_logic; + rx_pcs_rst_c: in std_logic; + rsl_rx_rdy: out std_logic + ); + +end entity sgmii_ecp5; + +architecture v1 of sgmii_ecp5 is + component sgmii_ecp5rsl_core is + generic (pnum_channels: integer := 1; + pprotocol: string := "GBE"; + pserdes_mode: string := "RX AND TX"; + pport_tx_rdy: string := "ENABLED"; + pwait_tx_rdy: integer := 3000; + pport_rx_rdy: string := "ENABLED"; + pwait_rx_rdy: integer := 3000); + port (rui_rst: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132) + rui_serdes_rst_dual_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133) + rui_rst_dual_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134) + rui_rsl_disable: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135) + rui_tx_ref_clk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137) + rui_tx_serdes_rst_c: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138) + rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139) + rdi_pll_lol: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140) + rui_rx_ref_clk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142) + rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143) + rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144) + rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145) + rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146) + rdo_serdes_rst_dual_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149) + rdo_rst_dual_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150) + ruo_tx_rdy: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152) + rdo_tx_serdes_rst_c: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153) + rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154) + ruo_rx_rdy: out std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156) + rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157) + rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158) + ); + + end component sgmii_ecp5rsl_core; -- syn_black_box=1 -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88) + component sgmii_ecp5sll_core is + generic (PPROTOCOL: string := "GBE"; + PLOL_SETTING: integer := 0; + PDYN_RATE_CTRL: string := "DISABLED"; + PPCIE_MAX_RATE: string := "2.5"; + PDIFF_VAL_LOCK: integer := 39; + PDIFF_VAL_UNLOCK: integer := 78; + PPCLK_TC: integer := 131072; + PDIFF_DIV11_VAL_LOCK: integer := 0; + PDIFF_DIV11_VAL_UNLOCK: integer := 0; + PPCLK_DIV11_TC: integer := 0); + port (sli_rst: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(125) + sli_refclk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(126) + sli_pclk: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(127) + sli_div2_rate: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(128) + sli_div11_rate: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(129) + sli_gear_mode: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(130) + sli_cpri_mode: in std_logic_vector(2 downto 0); -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(131) + sli_pcie_mode: in std_logic; -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(132) + slo_plol: out std_logic -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(135) + ); + + end component sgmii_ecp5sll_core; -- syn_black_box=1 -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(107) + signal n45,n44,n1,n2,n3,n4,tx_pclk_c,n5,n6,n7,n8,n9,n10,n11, + n12,n13,rx_los_low_s_c,n14,n15,rx_cdr_lol_s_c,rsl_tx_pcs_rst_c, + rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c,rsl_serdes_rst_dual_c, + rsl_tx_serdes_rst_c,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25, + n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39, + n40,n41,n42,n43,n46,n103,n102,n47,n48,n49,n50,n51,n52,n53, + n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67, + n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81, + n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95, + n96,n97,n98,n99,n100,n101,n112,n111,n110,pll_lol_c,n122,n121, + n113,n114,n115,n116,n117,n118,n119,n120,\_Z\,n124,n123,gnd, + pwr : std_logic; + attribute LOC : string; + attribute LOC of DCU1_inst : label is "DCU1"; + attribute CHAN : string; + attribute CHAN of DCU1_inst : label is "CH1"; +begin + tx_pclk <= tx_pclk_c; + rx_los_low_s <= rx_los_low_s_c; + rx_cdr_lol_s <= rx_cdr_lol_s_c; + pll_lol <= pll_lol_c; + DCU1_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", + D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", + D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", + D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b0",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", + CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", + CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0", + CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0", + CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0", + CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0", + CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b0", + CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b1", + CH1_MATCH_4_ENABLE=>"0b0",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x000", + CH1_CC_MATCH_2=>"0x000",CH1_CC_MATCH_3=>"0x1BC",CH1_CC_MATCH_4=>"0x050", + CH1_UDF_COMMA_MASK=>"0x3ff",CH1_UDF_COMMA_A=>"0x283",CH1_UDF_COMMA_B=>"0x17C", + CH1_RX_DCO_CK_DIV=>"0b010",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1", + CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00", + CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b01",CH1_TDRV_SLICE1_SEL=>"0b00", + CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01", + CH1_TDRV_SLICE5_SEL=>"0b01",CH1_TDRV_SLICE0_CUR=>"0b101",CH1_TDRV_SLICE1_CUR=>"0b000", + CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b11", + CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0", + CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0", + CH1_SEL_SD_RX_CLK=>"0b0",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0", + CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0", + CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00", + CH1_REQ_EN=>"0b1",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1", + CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000", + CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b010",CH1_RX_LOS_CEQ=>"0b11", + CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0", + CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"1.25",CH1_CDR_MAX_RATE=>"1.25", + CH1_TXAMPLITUDE=>"0d1100",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED", + CH1_PROTOCOL=>"GBE",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00", + D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000", + D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00", + CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00", + CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b001",CH1_DCOCTLGI=>"0b010", + CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b01",CH1_DCOFTNRG=>"0b110", + CH1_DCOIOSTUNE=>"0b000",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b111", + CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b101",CH1_DCOSCALEI=>"0b00", + CH1_DCOSTARTVAL=>"0b000",CH1_DCOSTEP=>"0b00",CH1_BAND_THRESHOLD=>"0d0", + CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0", + CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0", + CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00", + D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", + D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", + D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d8", + D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b010",D_PLL_LOL_SET=>"0b00", + D_RG_EN=>"0b0",D_RG_SET=>"0b00") + port map (CH0_HDINP=>n103,CH1_HDINP=>hdinp,CH0_HDINN=>n103,CH1_HDINN=>hdinn, + D_TXBIT_CLKP_FROM_ND=>n44,D_TXBIT_CLKN_FROM_ND=>n44,D_SYNC_ND=>n44,D_TXPLL_LOL_FROM_ND=>n44, + CH0_RX_REFCLK=>n103,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n102,CH1_FF_RXI_CLK=>tx_pclk_c, + CH0_FF_TXI_CLK=>n102,CH1_FF_TXI_CLK=>txi_clk,CH0_FF_EBRD_CLK=>n102,CH1_FF_EBRD_CLK=>tx_pclk_c, + CH0_FF_TX_D_0=>n103,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n103,CH1_FF_TX_D_1=>txdata(1), + CH0_FF_TX_D_2=>n103,CH1_FF_TX_D_2=>txdata(2),CH0_FF_TX_D_3=>n103,CH1_FF_TX_D_3=>txdata(3), + CH0_FF_TX_D_4=>n103,CH1_FF_TX_D_4=>txdata(4),CH0_FF_TX_D_5=>n103,CH1_FF_TX_D_5=>txdata(5), + CH0_FF_TX_D_6=>n103,CH1_FF_TX_D_6=>txdata(6),CH0_FF_TX_D_7=>n103,CH1_FF_TX_D_7=>txdata(7), + CH0_FF_TX_D_8=>n103,CH1_FF_TX_D_8=>tx_k(0),CH0_FF_TX_D_9=>n103,CH1_FF_TX_D_9=>n44, + CH0_FF_TX_D_10=>n103,CH1_FF_TX_D_10=>xmit(0),CH0_FF_TX_D_11=>n103,CH1_FF_TX_D_11=>tx_disp_correct(0), + CH0_FF_TX_D_12=>n103,CH1_FF_TX_D_12=>n103,CH0_FF_TX_D_13=>n103,CH1_FF_TX_D_13=>n103, + CH0_FF_TX_D_14=>n103,CH1_FF_TX_D_14=>n103,CH0_FF_TX_D_15=>n103,CH1_FF_TX_D_15=>n103, + CH0_FF_TX_D_16=>n103,CH1_FF_TX_D_16=>n103,CH0_FF_TX_D_17=>n103,CH1_FF_TX_D_17=>n103, + CH0_FF_TX_D_18=>n103,CH1_FF_TX_D_18=>n103,CH0_FF_TX_D_19=>n103,CH1_FF_TX_D_19=>n103, + CH0_FF_TX_D_20=>n103,CH1_FF_TX_D_20=>n103,CH0_FF_TX_D_21=>n103,CH1_FF_TX_D_21=>n44, + CH0_FF_TX_D_22=>n103,CH1_FF_TX_D_22=>n103,CH0_FF_TX_D_23=>n103,CH1_FF_TX_D_23=>n103, + CH0_FFC_EI_EN=>n103,CH1_FFC_EI_EN=>n44,CH0_FFC_PCIE_DET_EN=>n103,CH1_FFC_PCIE_DET_EN=>n44, + CH0_FFC_PCIE_CT=>n103,CH1_FFC_PCIE_CT=>n44,CH0_FFC_SB_INV_RX=>n103,CH1_FFC_SB_INV_RX=>n103, + CH0_FFC_ENABLE_CGALIGN=>n103,CH1_FFC_ENABLE_CGALIGN=>n103,CH0_FFC_SIGNAL_DETECT=>n103, + CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n103,CH1_FFC_FB_LOOPBACK=>n44, + CH0_FFC_SB_PFIFO_LP=>n103,CH1_FFC_SB_PFIFO_LP=>n44,CH0_FFC_PFIFO_CLR=>n103, + CH1_FFC_PFIFO_CLR=>n44,CH0_FFC_RATE_MODE_RX=>n103,CH1_FFC_RATE_MODE_RX=>n44, + CH0_FFC_RATE_MODE_TX=>n103,CH1_FFC_RATE_MODE_TX=>n44,CH0_FFC_DIV11_MODE_RX=>n103, + CH1_FFC_DIV11_MODE_RX=>n44,CH0_FFC_DIV11_MODE_TX=>n103,CH1_FFC_DIV11_MODE_TX=>n44, + CH0_FFC_RX_GEAR_MODE=>n103,CH1_FFC_RX_GEAR_MODE=>n44,CH0_FFC_TX_GEAR_MODE=>n103, + CH1_FFC_TX_GEAR_MODE=>n44,CH0_FFC_LDR_CORE2TX_EN=>n103,CH1_FFC_LDR_CORE2TX_EN=>n103, + CH0_FFC_LANE_TX_RST=>n103,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,CH0_FFC_LANE_RX_RST=>n103, + CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n103,CH1_FFC_RRST=>rsl_rx_serdes_rst_c, + CH0_FFC_TXPWDNB=>n103,CH1_FFC_TXPWDNB=>tx_pwrup_c,CH0_FFC_RXPWDNB=>n103, + CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n103,CH1_LDR_CORE2TX=>n103, + D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1),D_SCIWDATA2=>sci_wrdata(2), + D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4),D_SCIWDATA5=>sci_wrdata(5), + D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7),D_SCIADDR0=>sci_addr(0), + D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2),D_SCIADDR3=>sci_addr(3), + D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5),D_SCIENAUX=>sci_en_dual, + D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n103,CH1_SCIEN=>sci_en,CH0_SCISEL=>n103, + CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,D_CYAWSTN=>cyawstn, + D_FFC_SYNC_TOGGLE=>n103,D_FFC_DUAL_RST=>rsl_rst_dual_c,D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c, + D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n103, + CH1_FFC_CDR_EN_BITSLIP=>n44,D_SCAN_ENABLE=>n44,D_SCAN_IN_0=>n44,D_SCAN_IN_1=>n44, + D_SCAN_IN_2=>n44,D_SCAN_IN_3=>n44,D_SCAN_IN_4=>n44,D_SCAN_IN_5=>n44, + D_SCAN_IN_6=>n44,D_SCAN_IN_7=>n44,D_SCAN_MODE=>n44,D_SCAN_RESET=>n44, + D_CIN0=>n44,D_CIN1=>n44,D_CIN2=>n44,D_CIN3=>n44,D_CIN4=>n44,D_CIN5=>n44, + D_CIN6=>n44,D_CIN7=>n44,D_CIN8=>n44,D_CIN9=>n44,D_CIN10=>n44,D_CIN11=>n44, + CH0_HDOUTP=>n47,CH1_HDOUTP=>hdoutp,CH0_HDOUTN=>n48,CH1_HDOUTN=>hdoutn, + D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4, + CH0_FF_RX_F_CLK=>n49,CH1_FF_RX_F_CLK=>n5,CH0_FF_RX_H_CLK=>n50,CH1_FF_RX_H_CLK=>n6, + CH0_FF_TX_F_CLK=>n51,CH1_FF_TX_F_CLK=>n7,CH0_FF_TX_H_CLK=>n52,CH1_FF_TX_H_CLK=>n8, + CH0_FF_RX_PCLK=>n53,CH1_FF_RX_PCLK=>n9,CH0_FF_TX_PCLK=>n54,CH1_FF_TX_PCLK=>tx_pclk_c, + CH0_FF_RX_D_0=>n55,CH1_FF_RX_D_0=>rxdata(0),CH0_FF_RX_D_1=>n56,CH1_FF_RX_D_1=>rxdata(1), + CH0_FF_RX_D_2=>n57,CH1_FF_RX_D_2=>rxdata(2),CH0_FF_RX_D_3=>n58,CH1_FF_RX_D_3=>rxdata(3), + CH0_FF_RX_D_4=>n59,CH1_FF_RX_D_4=>rxdata(4),CH0_FF_RX_D_5=>n60,CH1_FF_RX_D_5=>rxdata(5), + CH0_FF_RX_D_6=>n61,CH1_FF_RX_D_6=>rxdata(6),CH0_FF_RX_D_7=>n62,CH1_FF_RX_D_7=>rxdata(7), + CH0_FF_RX_D_8=>n63,CH1_FF_RX_D_8=>rx_k(0),CH0_FF_RX_D_9=>n64,CH1_FF_RX_D_9=>rx_disp_err(0), + CH0_FF_RX_D_10=>n65,CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n66, + CH1_FF_RX_D_11=>n10,CH0_FF_RX_D_12=>n67,CH1_FF_RX_D_12=>n68,CH0_FF_RX_D_13=>n69, + CH1_FF_RX_D_13=>n70,CH0_FF_RX_D_14=>n71,CH1_FF_RX_D_14=>n72,CH0_FF_RX_D_15=>n73, + CH1_FF_RX_D_15=>n74,CH0_FF_RX_D_16=>n75,CH1_FF_RX_D_16=>n76,CH0_FF_RX_D_17=>n77, + CH1_FF_RX_D_17=>n78,CH0_FF_RX_D_18=>n79,CH1_FF_RX_D_18=>n80,CH0_FF_RX_D_19=>n81, + CH1_FF_RX_D_19=>n82,CH0_FF_RX_D_20=>n83,CH1_FF_RX_D_20=>n84,CH0_FF_RX_D_21=>n85, + CH1_FF_RX_D_21=>n86,CH0_FF_RX_D_22=>n87,CH1_FF_RX_D_22=>n88,CH0_FF_RX_D_23=>n89, + CH1_FF_RX_D_23=>n11,CH0_FFS_PCIE_DONE=>n90,CH1_FFS_PCIE_DONE=>n12,CH0_FFS_PCIE_CON=>n91, + CH1_FFS_PCIE_CON=>n13,CH0_FFS_RLOS=>n92,CH1_FFS_RLOS=>rx_los_low_s_c, + CH0_FFS_LS_SYNC_STATUS=>n93,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s,CH0_FFS_CC_UNDERRUN=>n94, + CH1_FFS_CC_UNDERRUN=>ctc_urun_s,CH0_FFS_CC_OVERRUN=>n95,CH1_FFS_CC_OVERRUN=>ctc_orun_s, + CH0_FFS_RXFBFIFO_ERROR=>n96,CH1_FFS_RXFBFIFO_ERROR=>n14,CH0_FFS_TXFBFIFO_ERROR=>n97, + CH1_FFS_TXFBFIFO_ERROR=>n15,CH0_FFS_RLOL=>n98,CH1_FFS_RLOL=>rx_cdr_lol_s_c, + CH0_FFS_SKP_ADDED=>n99,CH1_FFS_SKP_ADDED=>ctc_ins_s,CH0_FFS_SKP_DELETED=>n100, + CH1_FFS_SKP_DELETED=>ctc_del_s,CH0_LDR_RX2CORE=>n101,CH1_LDR_RX2CORE=>n112, + D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),D_SCIRDATA2=>sci_rddata(2), + D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),D_SCIRDATA5=>sci_rddata(5), + D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),D_SCIINT=>sci_int, + D_SCAN_OUT_0=>n16,D_SCAN_OUT_1=>n17,D_SCAN_OUT_2=>n18,D_SCAN_OUT_3=>n19, + D_SCAN_OUT_4=>n20,D_SCAN_OUT_5=>n21,D_SCAN_OUT_6=>n22,D_SCAN_OUT_7=>n23, + D_COUT0=>n24,D_COUT1=>n25,D_COUT2=>n26,D_COUT3=>n27,D_COUT4=>n28,D_COUT5=>n29, + D_COUT6=>n30,D_COUT7=>n31,D_COUT8=>n32,D_COUT9=>n33,D_COUT10=>n34,D_COUT11=>n35, + D_COUT12=>n36,D_COUT13=>n37,D_COUT14=>n38,D_COUT15=>n39,D_COUT16=>n40, + D_COUT17=>n41,D_COUT18=>n42,D_COUT19=>n43,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n46); + n45 <= '1' ; + n44 <= '0' ; + n1 <= 'Z' ; + n2 <= 'Z' ; + n3 <= 'Z' ; + n4 <= 'Z' ; + n5 <= 'Z' ; + n6 <= 'Z' ; + n7 <= 'Z' ; + n8 <= 'Z' ; + n9 <= 'Z' ; + n10 <= 'Z' ; + n11 <= 'Z' ; + n12 <= 'Z' ; + n13 <= 'Z' ; + n14 <= 'Z' ; + n15 <= 'Z' ; + n16 <= 'Z' ; + n17 <= 'Z' ; + n18 <= 'Z' ; + n19 <= 'Z' ; + n20 <= 'Z' ; + n21 <= 'Z' ; + n22 <= 'Z' ; + n23 <= 'Z' ; + n24 <= 'Z' ; + n25 <= 'Z' ; + n26 <= 'Z' ; + n27 <= 'Z' ; + n28 <= 'Z' ; + n29 <= 'Z' ; + n30 <= 'Z' ; + n31 <= 'Z' ; + n32 <= 'Z' ; + n33 <= 'Z' ; + n34 <= 'Z' ; + n35 <= 'Z' ; + n36 <= 'Z' ; + n37 <= 'Z' ; + n38 <= 'Z' ; + n39 <= 'Z' ; + n40 <= 'Z' ; + n41 <= 'Z' ; + n42 <= 'Z' ; + n43 <= 'Z' ; + n46 <= 'Z' ; + n103 <= '0' ; + n102 <= '1' ; + n47 <= 'Z' ; + n48 <= 'Z' ; + n49 <= 'Z' ; + n50 <= 'Z' ; + n51 <= 'Z' ; + n52 <= 'Z' ; + n53 <= 'Z' ; + n54 <= 'Z' ; + n55 <= 'Z' ; + n56 <= 'Z' ; + n57 <= 'Z' ; + n58 <= 'Z' ; + n59 <= 'Z' ; + n60 <= 'Z' ; + n61 <= 'Z' ; + n62 <= 'Z' ; + n63 <= 'Z' ; + n64 <= 'Z' ; + n65 <= 'Z' ; + n66 <= 'Z' ; + n67 <= 'Z' ; + n68 <= 'Z' ; + n69 <= 'Z' ; + n70 <= 'Z' ; + n71 <= 'Z' ; + n72 <= 'Z' ; + n73 <= 'Z' ; + n74 <= 'Z' ; + n75 <= 'Z' ; + n76 <= 'Z' ; + n77 <= 'Z' ; + n78 <= 'Z' ; + n79 <= 'Z' ; + n80 <= 'Z' ; + n81 <= 'Z' ; + n82 <= 'Z' ; + n83 <= 'Z' ; + n84 <= 'Z' ; + n85 <= 'Z' ; + n86 <= 'Z' ; + n87 <= 'Z' ; + n88 <= 'Z' ; + n89 <= 'Z' ; + n90 <= 'Z' ; + n91 <= 'Z' ; + n92 <= 'Z' ; + n93 <= 'Z' ; + n94 <= 'Z' ; + n95 <= 'Z' ; + n96 <= 'Z' ; + n97 <= 'Z' ; + n98 <= 'Z' ; + n99 <= 'Z' ; + n100 <= 'Z' ; + n101 <= 'Z' ; + n112 <= 'Z' ; + rsl_inst: component sgmii_ecp5rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c, + rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki, + rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n122, + rui_tx_pcs_rst_c(2)=>n122,rui_tx_pcs_rst_c(1)=>n122,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c, + rdi_pll_lol=>'0',rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n122, + rui_rx_serdes_rst_c(2)=>n122,rui_rx_serdes_rst_c(1)=>n122,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c, + rui_rx_pcs_rst_c(3)=>n122,rui_rx_pcs_rst_c(2)=>n122,rui_rx_pcs_rst_c(1)=>n122, + rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n122,rdi_rx_los_low_s(2)=>n122, + rdi_rx_los_low_s(1)=>n122,rdi_rx_los_low_s(0)=>rx_los_low_s_c, + rdi_rx_cdr_lol_s(3)=>n122,rdi_rx_cdr_lol_s(2)=>n122,rdi_rx_cdr_lol_s(1)=>n122, + rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c, + rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c, + rdo_tx_pcs_rst_c(3)=>n113,rdo_tx_pcs_rst_c(2)=>n114,rdo_tx_pcs_rst_c(1)=>n115, + rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n116, + rdo_rx_serdes_rst_c(2)=>n117,rdo_rx_serdes_rst_c(1)=>n118,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c, + rdo_rx_pcs_rst_c(3)=>n119,rdo_rx_pcs_rst_c(2)=>n120,rdo_rx_pcs_rst_c(1)=>\_Z\, + rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c); + n111 <= '1' ; + n110 <= '0' ; + n122 <= '0' ; + n121 <= '1' ; + n113 <= 'Z' ; + n114 <= 'Z' ; + n115 <= 'Z' ; + n116 <= 'Z' ; + n117 <= 'Z' ; + n118 <= 'Z' ; + n119 <= 'Z' ; + n120 <= 'Z' ; + \_Z\ <= 'Z' ; + sll_inst: component sgmii_ecp5sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki, + sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd, + sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd, + sli_pcie_mode=>gnd,slo_plol=>pll_lol_c); + n124 <= '1' ; + n123 <= '0' ; + gnd <= '0' ; + pwr <= '1' ; + +end architecture v1; + diff --git a/gbe_trb/media/ecp5/sgmii_gbe_pcs35.vhd b/gbe_trb/media/ecp5/sgmii_gbe_pcs35.vhd new file mode 100644 index 0000000..d4ecee8 --- /dev/null +++ b/gbe_trb/media/ecp5/sgmii_gbe_pcs35.vhd @@ -0,0 +1,191 @@ +--************************************************************************** +-- ************************************************************************* +-- * LATTICE SEMICONDUCTOR CONFIDENTIAL * +-- * PROPRIETARY NOTE * +-- * * +-- * This software contains information confidential and proprietary * +-- * to Lattice Semiconductor Corporation. It shall not be reproduced * +-- * in whole or in part, or transferred to other documents, or disclosed * +-- * to third parties, or used for any purpose other than that for which * +-- * it was obtained, without the prior written consent of Lattice * +-- * Semiconductor Corporation. All rights reserved. * +-- * * +-- ************************************************************************* +--************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +entity sgmii_gbe_pcs35 is port ( + rst_n : in std_logic; + signal_detect : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + force_isolate : in std_logic; + force_loopback : in std_logic; + force_unidir : in std_logic; + operational_rate : in std_logic_vector(1 downto 0); + debug_link_timer_short : in std_logic; + rx_compensation_err : out std_logic; + ctc_drop_flag : out std_logic; + ctc_add_flag : out std_logic; + an_link_ok : out std_logic; + + tx_clock_enable_sink : in std_logic; + tx_clock_enable_source : out std_logic; + + rx_clock_enable_sink : in std_logic; + rx_clock_enable_source : out std_logic; + + tx_clk_125 : in std_logic; + tx_d : in std_logic_vector(7 downto 0); + tx_en : in std_logic; + tx_er : in std_logic; + rx_clk_125 : in std_logic; + rx_d : out std_logic_vector(7 downto 0); + rx_dv : out std_logic; + rx_er : out std_logic; + col : out std_logic; + crs : out std_logic; + tx_data : out std_logic_vector(7 downto 0); + tx_kcntl : out std_logic; + tx_disparity_cntl : out std_logic; + xmit_autoneg : out std_logic; + serdes_recovered_clk : in std_logic; + rx_data : in std_logic_vector(7 downto 0); + rx_even : in std_logic; + rx_kcntl : in std_logic; + rx_disp_err : in std_logic; + rx_cv_err : in std_logic; + rx_err_decode_mode : in std_logic; + mr_an_complete : out std_logic; + mr_page_rx : out std_logic; + mr_lp_adv_ability : out std_logic_vector(15 downto 0); + mr_main_reset : in std_logic; + mr_an_enable : in std_logic; + mr_restart_an : in std_logic; + mr_adv_ability : in std_logic_vector(15 downto 0) + ); +end entity; + +architecture arch of sgmii_gbe_pcs35 is +component sgmii_channel_smi_core port ( + rst_n : in std_logic; + signal_detect : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + force_isolate : in std_logic; + force_loopback : in std_logic; + force_unidir : in std_logic; + operational_rate : in std_logic_vector(1 downto 0); + debug_link_timer_short : in std_logic; + rx_compensation_err : out std_logic; + ctc_drop_flag : out std_logic; + ctc_add_flag : out std_logic; + an_link_ok : out std_logic; + + tx_clock_enable_sink : in std_logic; + tx_clock_enable_source : out std_logic; + + rx_clock_enable_sink : in std_logic; + rx_clock_enable_source : out std_logic; + + tx_clk_125 : in std_logic; + tx_d : in std_logic_vector(7 downto 0); + tx_en : in std_logic; + tx_er : in std_logic; + rx_clk_125 : in std_logic; + rx_d : out std_logic_vector(7 downto 0); + rx_dv : out std_logic; + rx_er : out std_logic; + col : out std_logic; + crs : out std_logic; + tx_data : out std_logic_vector(7 downto 0); + tx_kcntl : out std_logic; + tx_disparity_cntl : out std_logic; + xmit_autoneg : out std_logic; + serdes_recovered_clk : in std_logic; + rx_data : in std_logic_vector(7 downto 0); + rx_even : in std_logic; + rx_kcntl : in std_logic; + rx_disp_err : in std_logic; + rx_cv_err : in std_logic; + rx_err_decode_mode : in std_logic; + mr_an_complete : out std_logic; + mr_page_rx : out std_logic; + mr_lp_adv_ability : out std_logic_vector(15 downto 0); + mr_main_reset : in std_logic; + mr_an_enable : in std_logic; + mr_restart_an : in std_logic; + mr_adv_ability : in std_logic_vector(15 downto 0) + ); +end component; + + +begin + +-- Instantiate SGMII IP Core +u_sgmii_core : sgmii_channel_smi_core port map( + -- Clock and Reset + rst_n => rst_n , + signal_detect => signal_detect , + gbe_mode => gbe_mode , + sgmii_mode => sgmii_mode , + operational_rate => operational_rate , + debug_link_timer_short => debug_link_timer_short , + force_isolate => force_isolate , + force_loopback => force_loopback , + force_unidir => force_unidir , + + rx_compensation_err => rx_compensation_err , + ctc_drop_flag => ctc_drop_flag , + ctc_add_flag => ctc_add_flag , + an_link_ok => an_link_ok , + + tx_clock_enable_sink => tx_clock_enable_sink , + tx_clock_enable_source => tx_clock_enable_source , + + rx_clock_enable_sink => rx_clock_enable_sink , + rx_clock_enable_source => rx_clock_enable_source , + tx_clk_125 => tx_clk_125 , + rx_clk_125 => rx_clk_125 , + -- GMII TX Inputs + tx_d => tx_d, + tx_en => tx_en, + tx_er => tx_er, + -- GMII RX Outputs + -- To GMII/MAC interface + rx_d => rx_d , + rx_dv => rx_dv , + rx_er => rx_er , + col => col , + crs => crs , + + -- 8BI TX Outputs + tx_data => tx_data, + tx_kcntl => tx_kcntl, + tx_disparity_cntl => tx_disparity_cntl, + xmit_autoneg => xmit_autoneg, + + -- 8BI RX Inputs + serdes_recovered_clk => serdes_recovered_clk , + rx_data => rx_data , + rx_kcntl => rx_kcntl , + rx_even => rx_even , + rx_disp_err => rx_disp_err , + rx_cv_err => rx_cv_err , + rx_err_decode_mode => rx_err_decode_mode , + + -- Management Interface I/O + mr_adv_ability => mr_adv_ability, + mr_an_enable => mr_an_enable, + mr_main_reset => mr_main_reset, + mr_restart_an => mr_restart_an, + + mr_an_complete => mr_an_complete, + mr_lp_adv_ability => mr_lp_adv_ability, + mr_page_rx => mr_page_rx + ); + +end architecture; + diff --git a/gbe_trb/media/ecp5/sgmii_gbe_pcs35_core.ngo b/gbe_trb/media/ecp5/sgmii_gbe_pcs35_core.ngo new file mode 100644 index 0000000..aeab23d Binary files /dev/null and b/gbe_trb/media/ecp5/sgmii_gbe_pcs35_core.ngo differ diff --git a/gbe_trb/media/ecp5/test/sgmii_channel_smi_core.ngo b/gbe_trb/media/ecp5/test/sgmii_channel_smi_core.ngo new file mode 100644 index 0000000..924439e Binary files /dev/null and b/gbe_trb/media/ecp5/test/sgmii_channel_smi_core.ngo differ diff --git a/gbe_trb/media/ecp5/test/sgmii_channel_smi_core.vhd b/gbe_trb/media/ecp5/test/sgmii_channel_smi_core.vhd new file mode 100644 index 0000000..53bfdd5 --- /dev/null +++ b/gbe_trb/media/ecp5/test/sgmii_channel_smi_core.vhd @@ -0,0 +1,359 @@ +--************************************************************************** +-- ************************************************************************* +-- * LATTICE SEMICONDUCTOR CONFIDENTIAL * +-- * PROPRIETARY NOTE * +-- * * +-- * This software contains information confidential and proprietary * +-- * to Lattice Semiconductor Corporation. It shall not be reproduced * +-- * in whole or in part, or transferred to other documents, or disclosed * +-- * to third parties, or used for any purpose other than that for which * +-- * it was obtained, without the prior written consent of Lattice * +-- * Semiconductor Corporation. All rights reserved. * +-- * * +-- ************************************************************************* +--************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +entity sgmii_channel_smi_core is port ( + rst_n : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + operational_rate : in std_logic_vector(1 downto 0); + debug_link_timer_short : in std_logic; + force_isolate : in std_logic; + force_loopback : in std_logic; + force_unidir : in std_logic; + --rx_compensation_err : out std_logic; + --ctc_drop_flag : out std_logic; + --ctc_add_flag : out std_logic; + an_link_ok : out std_logic; + tx_clock_enable_sink : in std_logic; + tx_clock_enable_source : out std_logic; + + rx_clock_enable_sink : in std_logic; + rx_clock_enable_source : out std_logic; + tx_clk_125 : in std_logic; + rx_clk_125 : in std_logic; + tx_d : in std_logic_vector(7 downto 0); + tx_en : in std_logic; + tx_er : in std_logic; + rx_d : out std_logic_vector(7 downto 0); + rx_dv : out std_logic; + rx_er : out std_logic; + col : out std_logic; + crs : out std_logic; + mr_an_complete : out std_logic; + mr_page_rx : out std_logic; + mr_lp_adv_ability : out std_logic_vector(15 downto 0); + mr_main_reset : in std_logic; + mr_an_enable : in std_logic; + mr_restart_an : in std_logic; + mr_adv_ability : in std_logic_vector(15 downto 0); + + hdoutp: out std_logic; + hdoutn: out std_logic; + hdinp: in std_logic; + hdinn: in std_logic; + + sli_rst : in std_logic; + serdes_rst_dual_c : out std_logic; + tx_serdes_rst_c : out std_logic; + serdes_pdb : out std_logic; + tx_pwrup_c : out std_logic; + + pll_refclki : in std_logic; + rxrefclk : in std_logic; + + sci_wrdata : in std_logic_vector(7 downto 0); + sci_addr : in std_logic_vector(5 downto 0); + sci_rddata : out std_logic_vector(7 downto 0); + sci_en_dual : in std_logic; + sci_sel_dual: in std_logic; + sci_en: in std_logic; + sci_sel: in std_logic; + sci_rd: in std_logic; + sci_wrn: in std_logic; + sci_int: out std_logic; + cyawstn: in std_logic; + + rx_cdr_lol_s: out std_logic; + + tx_pcs_rst_c: in std_logic; + rx_pcs_rst_c: in std_logic; + rx_serdes_rst_c: in std_logic; + + rst_dual_c: in std_logic; + pll_lol: out std_logic; + + + mr_power_down: in std_logic + ); +end entity; + +architecture arch of sgmii_channel_smi_core is +component sgmii_channel_smi_core_core port ( + rst_n : in std_logic; + signal_detect : in std_logic; + gbe_mode : in std_logic; + sgmii_mode : in std_logic; + force_isolate : in std_logic; + force_loopback : in std_logic; + force_unidir : in std_logic; + operational_rate : in std_logic_vector(1 downto 0); + debug_link_timer_short : in std_logic; + rx_compensation_err : out std_logic; + ctc_drop_flag : out std_logic; + ctc_add_flag : out std_logic; + an_link_ok : out std_logic; + + tx_clock_enable_sink : in std_logic; + tx_clock_enable_source : out std_logic; + + rx_clock_enable_sink : in std_logic; + rx_clock_enable_source : out std_logic; + + tx_clk_125 : in std_logic; + tx_d : in std_logic_vector(7 downto 0); + tx_en : in std_logic; + tx_er : in std_logic; + rx_clk_125 : in std_logic; + rx_d : out std_logic_vector(7 downto 0); + rx_dv : out std_logic; + rx_er : out std_logic; + col : out std_logic; + crs : out std_logic; + tx_data : out std_logic_vector(7 downto 0); + tx_kcntl : out std_logic; + tx_disparity_cntl : out std_logic; + xmit_autoneg : out std_logic; + serdes_recovered_clk : in std_logic; + rx_data : in std_logic_vector(7 downto 0); + rx_even : in std_logic; + rx_kcntl : in std_logic; + rx_disp_err : in std_logic; + rx_cv_err : in std_logic; + rx_err_decode_mode : in std_logic; + mr_an_complete : out std_logic; + mr_page_rx : out std_logic; + mr_lp_adv_ability : out std_logic_vector(15 downto 0); + mr_main_reset : in std_logic; + mr_an_enable : in std_logic; + mr_restart_an : in std_logic; + mr_adv_ability : in std_logic_vector(15 downto 0) + ); +end component; + +component sgmii_channel_smi_core_pcs port ( + hdoutp : out std_logic; + hdoutn : out std_logic; + hdinp : in std_logic; + hdinn : in std_logic; + rxrefclk : in std_logic; + txi_clk : in std_logic; + sli_rst : in std_logic; + rx_pclk : out std_logic; + tx_pclk : out std_logic; + txdata : in std_logic_vector(7 downto 0); + tx_k : in std_logic_vector(0 downto 0); + xmit : in std_logic_vector(0 downto 0); + tx_disp_correct : in std_logic_vector(0 downto 0); + rxdata : out std_logic_vector(7 downto 0); + rx_k : out std_logic_vector(0 downto 0); + rx_disp_err : out std_logic_vector(0 downto 0); + rx_cv_err : out std_logic_vector(0 downto 0); + sci_wrdata : in std_logic_vector(7 downto 0); + signal_detect_c : in std_logic; + sci_addr : in std_logic_vector(5 downto 0); + sci_rddata : out std_logic_vector(7 downto 0); + sci_en_dual : in std_logic; + sci_sel_dual: in std_logic; + sci_en: in std_logic; + sci_sel: in std_logic; + sci_rd: in std_logic; + sci_wrn: in std_logic; + sci_int: out std_logic; + cyawstn: in std_logic; + lsm_status_s : out std_logic; + rx_cdr_lol_s : out std_logic; + tx_pcs_rst_c : in std_logic; + rx_pcs_rst_c : in std_logic; + rx_serdes_rst_c : in std_logic; + rsl_disable : in std_logic; + rsl_rst : in std_logic; + tx_pwrup_c : in std_logic; + rx_pwrup_c : in std_logic; + rst_dual_c : in std_logic; + serdes_rst_dual_c : in std_logic; + serdes_pdb : in std_logic; + tx_serdes_rst_c : in std_logic; + pll_refclki : in std_logic; + pll_lol : out std_logic + ); +end component; + +-- 8-bit Interface Signals from SGMII channel to QuadPCS/SERDES +signal data_chan2quad : std_logic_vector(7 downto 0); +signal kcntl_chan2quad : std_logic_vector(0 downto 0); +signal disparity_cntl_chan2quad: std_logic_vector(0 downto 0); + +-- 8-bit Interface Signals from QuadPCS/SERDES to SGMII channel +signal data_quad2chan : std_logic_vector(7 downto 0); +signal kcntl_quad2chan : std_logic_vector(0 downto 0); +signal disp_err_quad2chan : std_logic_vector(0 downto 0); +signal cv_err_quad2chan : std_logic_vector(0 downto 0); +signal link_status : std_logic; +signal serdes_recovered_clk : std_logic; +signal xmit_autoneg : std_logic_vector(0 downto 0); +signal reset : std_logic; +signal mr_power_down_inv : std_logic; + +begin + +reset <= not rst_n; +mr_power_down_inv <= not(mr_power_down); +-- Instantiate SGMII IP Core +u_sgmii_core : sgmii_channel_smi_core_core port map( + -- Clock and Reset + rst_n => rst_n , + signal_detect => link_status , + gbe_mode => gbe_mode , + sgmii_mode => sgmii_mode , + operational_rate => operational_rate , + debug_link_timer_short => debug_link_timer_short , + force_isolate => force_isolate , + force_loopback => force_loopback , + force_unidir => force_unidir , + + rx_compensation_err => open , + ctc_drop_flag => open , + ctc_add_flag => open , + an_link_ok => an_link_ok , + + tx_clock_enable_sink => tx_clock_enable_sink , + tx_clock_enable_source => tx_clock_enable_source , + + rx_clock_enable_sink => rx_clock_enable_sink , + rx_clock_enable_source => rx_clock_enable_source , + tx_clk_125 => tx_clk_125 , + rx_clk_125 => rx_clk_125 , + -- GMII TX Inputs + tx_d => tx_d, + tx_en => tx_en, + tx_er => tx_er, + -- GMII RX Outputs + -- To GMII/MAC interface + rx_d => rx_d , + rx_dv => rx_dv , + rx_er => rx_er , + col => col , + crs => crs , + + -- 8BI TX Outputs + tx_data => data_chan2quad, + tx_kcntl => kcntl_chan2quad(0), + tx_disparity_cntl => disparity_cntl_chan2quad(0), + xmit_autoneg => xmit_autoneg(0), + + -- 8BI RX Inputs + serdes_recovered_clk => serdes_recovered_clk , + rx_data => data_quad2chan , + rx_kcntl => kcntl_quad2chan(0) , + rx_even => '0' , + rx_disp_err => disp_err_quad2chan(0) , + rx_cv_err => cv_err_quad2chan(0) , + rx_err_decode_mode => '0' , + + -- Management Interface I/O + mr_adv_ability => mr_adv_ability, + mr_an_enable => mr_an_enable, + mr_main_reset => mr_main_reset, + mr_restart_an => mr_restart_an, + + mr_an_complete => mr_an_complete, + mr_lp_adv_ability => mr_lp_adv_ability, + mr_page_rx => mr_page_rx + ); + + + serdes_rst_dual_c <= reset; + tx_serdes_rst_c <= reset; + serdes_pdb <= '1'; + tx_pwrup_c <= mr_power_down_inv; + +u_sgmii_pcs : sgmii_channel_smi_core_pcs port map( +-- Global Clocks and Resets + -- inputs + rst_dual_c => rst_dual_c, + serdes_rst_dual_c => reset, + pll_refclki => pll_refclki, + rxrefclk => rxrefclk, + + txi_clk => tx_clk_125, + + sli_rst => sli_rst, + +-- fpga tx datapath signals + -- inputs + tx_pcs_rst_c => tx_pcs_rst_c, + txdata => data_chan2quad, + tx_k => kcntl_chan2quad, + tx_disp_correct => disparity_cntl_chan2quad, + + -- outputs + tx_pclk => open , + +-- fpga rx datapath signals + -- inputs + rx_pcs_rst_c => rx_pcs_rst_c, + xmit => xmit_autoneg, + + -- outputs + rx_pclk => serdes_recovered_clk, + rxdata => data_quad2chan, + rx_k => kcntl_quad2chan, + rx_disp_err => disp_err_quad2chan, + rx_cv_err => cv_err_quad2chan, + lsm_status_s => link_status, + rx_cdr_lol_s => rx_cdr_lol_s, + +-- serdes signals + -- inputs + rx_serdes_rst_c => rx_serdes_rst_c, + tx_serdes_rst_c => reset, + + hdinp => hdinp, + hdinn => hdinn, + + -- outputs + hdoutp => hdoutp, + hdoutn => hdoutn, + signal_detect_c => '1', + + cyawstn => cyawstn, + sci_en => sci_en, + sci_en_dual => sci_en_dual, + sci_sel_dual => sci_sel_dual, + sci_sel => sci_sel, + sci_wrdata => sci_wrdata, + sci_addr => sci_addr, + sci_rddata => sci_rddata, + sci_rd => sci_rd, + sci_wrn => sci_wrn, + sci_int => sci_int, + +-- misc control signals + -- inputs + rsl_disable => '0', + rsl_rst => reset, + tx_pwrup_c => mr_power_down_inv, -- powerup tx channel + rx_pwrup_c => mr_power_down_inv, -- power up rx channel + serdes_pdb => '1', + + -- outputs + pll_lol => pll_lol +); + +end architecture; + diff --git a/gbe_trb/media/ecp5/test/sgmii_channel_smi_core_core.ngo b/gbe_trb/media/ecp5/test/sgmii_channel_smi_core_core.ngo new file mode 100644 index 0000000..1cc0f0d Binary files /dev/null and b/gbe_trb/media/ecp5/test/sgmii_channel_smi_core_core.ngo differ diff --git a/gbe_trb/media/ecp5/test/sgmii_channel_smi_core_pcs.v b/gbe_trb/media/ecp5/test/sgmii_channel_smi_core_pcs.v new file mode 100644 index 0000000..c60589f --- /dev/null +++ b/gbe_trb/media/ecp5/test/sgmii_channel_smi_core_pcs.v @@ -0,0 +1,476 @@ +// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70 +// Netlist written on Mon May 6 11:24:40 2019 +// +// Verilog Description of module sgmii_channel_smi_core_pcs +// + +`timescale 1ns/1ps +module sgmii_channel_smi_core_pcs (hdoutp, hdoutn, hdinp, + hdinn, rxrefclk, rx_pclk, txi_clk, tx_pclk, txdata, + tx_k, xmit, tx_disp_correct, rxdata, rx_k, rx_disp_err, + rx_cv_err, signal_detect_c, lsm_status_s, rx_cdr_lol_s, + sli_rst, tx_pwrup_c, rx_pwrup_c, sci_wrdata, sci_addr, + sci_rddata, sci_en_dual, sci_sel_dual, sci_en, sci_sel, + sci_rd, sci_wrn, sci_int, cyawstn, serdes_pdb, pll_refclki, + rsl_disable, rsl_rst, serdes_rst_dual_c, rst_dual_c, tx_serdes_rst_c, + tx_pcs_rst_c, pll_lol, rx_serdes_rst_c, rx_pcs_rst_c); + output hdoutp; + output hdoutn; + input hdinp; + input hdinn; + input rxrefclk; + output rx_pclk; + input txi_clk; + output tx_pclk; + input [7:0]txdata; + input [0:0]tx_k; + input [0:0]xmit; + input [0:0]tx_disp_correct; + output [7:0]rxdata; + output [0:0]rx_k; + output [0:0]rx_disp_err; + output [0:0]rx_cv_err; + input signal_detect_c; + output lsm_status_s; + output rx_cdr_lol_s; + input sli_rst; + input tx_pwrup_c; + input rx_pwrup_c; + input [7:0]sci_wrdata; + input [5:0]sci_addr; + output [7:0]sci_rddata; + input sci_en_dual; + input sci_sel_dual; + input sci_en; + input sci_sel; + input sci_rd; + input sci_wrn; + output sci_int; + input cyawstn; + input serdes_pdb; + input pll_refclki; + input rsl_disable; + input rsl_rst; + input serdes_rst_dual_c; + input rst_dual_c; + input tx_serdes_rst_c; + input tx_pcs_rst_c; + output pll_lol; + input rx_serdes_rst_c; + input rx_pcs_rst_c; + + + wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, + n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, + n22, n23, n24, n25, n26, n27, n28, n29, rsl_tx_pcs_rst_c, + rsl_rx_pcs_rst_c, rsl_rx_serdes_rst_c, rsl_rst_dual_c, rsl_serdes_rst_dual_c, + rsl_tx_serdes_rst_c, n30, n31, n32, n33, n34, n35, n36, + n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, + n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, + n57, n60, n61, n62, n63, n64, n65, n66, n67, n68, + n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, + n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, + n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, + n99, n100, n101, n102, n103, n104, n105, n116, n117, + n118, n119, n120, n121, n122, n123, n124, n125, n126, + _Z; + + DCUA DCU1_inst (.CH0_HDINP(1'b0), .CH1_HDINP(hdinp), .CH0_HDINN(1'b0), + .CH1_HDINN(hdinn), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0), + .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(1'b0), + .CH1_RX_REFCLK(rxrefclk), .CH0_FF_RXI_CLK(1'b1), .CH1_FF_RXI_CLK(rx_pclk), + .CH0_FF_TXI_CLK(1'b1), .CH1_FF_TXI_CLK(txi_clk), .CH0_FF_EBRD_CLK(1'b1), + .CH1_FF_EBRD_CLK(1'b1), .CH0_FF_TX_D_0(1'b0), .CH1_FF_TX_D_0(txdata[0]), + .CH0_FF_TX_D_1(1'b0), .CH1_FF_TX_D_1(txdata[1]), .CH0_FF_TX_D_2(1'b0), + .CH1_FF_TX_D_2(txdata[2]), .CH0_FF_TX_D_3(1'b0), .CH1_FF_TX_D_3(txdata[3]), + .CH0_FF_TX_D_4(1'b0), .CH1_FF_TX_D_4(txdata[4]), .CH0_FF_TX_D_5(1'b0), + .CH1_FF_TX_D_5(txdata[5]), .CH0_FF_TX_D_6(1'b0), .CH1_FF_TX_D_6(txdata[6]), + .CH0_FF_TX_D_7(1'b0), .CH1_FF_TX_D_7(txdata[7]), .CH0_FF_TX_D_8(1'b0), + .CH1_FF_TX_D_8(tx_k[0]), .CH0_FF_TX_D_9(1'b0), .CH1_FF_TX_D_9(1'b0), + .CH0_FF_TX_D_10(1'b0), .CH1_FF_TX_D_10(xmit[0]), .CH0_FF_TX_D_11(1'b0), + .CH1_FF_TX_D_11(tx_disp_correct[0]), .CH0_FF_TX_D_12(1'b0), .CH1_FF_TX_D_12(1'b0), + .CH0_FF_TX_D_13(1'b0), .CH1_FF_TX_D_13(1'b0), .CH0_FF_TX_D_14(1'b0), + .CH1_FF_TX_D_14(1'b0), .CH0_FF_TX_D_15(1'b0), .CH1_FF_TX_D_15(1'b0), + .CH0_FF_TX_D_16(1'b0), .CH1_FF_TX_D_16(1'b0), .CH0_FF_TX_D_17(1'b0), + .CH1_FF_TX_D_17(1'b0), .CH0_FF_TX_D_18(1'b0), .CH1_FF_TX_D_18(1'b0), + .CH0_FF_TX_D_19(1'b0), .CH1_FF_TX_D_19(1'b0), .CH0_FF_TX_D_20(1'b0), + .CH1_FF_TX_D_20(1'b0), .CH0_FF_TX_D_21(1'b0), .CH1_FF_TX_D_21(1'b0), + .CH0_FF_TX_D_22(1'b0), .CH1_FF_TX_D_22(1'b0), .CH0_FF_TX_D_23(1'b0), + .CH1_FF_TX_D_23(1'b0), .CH0_FFC_EI_EN(1'b0), .CH1_FFC_EI_EN(1'b0), + .CH0_FFC_PCIE_DET_EN(1'b0), .CH1_FFC_PCIE_DET_EN(1'b0), .CH0_FFC_PCIE_CT(1'b0), + .CH1_FFC_PCIE_CT(1'b0), .CH0_FFC_SB_INV_RX(1'b0), .CH1_FFC_SB_INV_RX(1'b0), + .CH0_FFC_ENABLE_CGALIGN(1'b0), .CH1_FFC_ENABLE_CGALIGN(1'b0), .CH0_FFC_SIGNAL_DETECT(1'b0), + .CH1_FFC_SIGNAL_DETECT(signal_detect_c), .CH0_FFC_FB_LOOPBACK(1'b0), + .CH1_FFC_FB_LOOPBACK(1'b0), .CH0_FFC_SB_PFIFO_LP(1'b0), .CH1_FFC_SB_PFIFO_LP(1'b0), + .CH0_FFC_PFIFO_CLR(1'b0), .CH1_FFC_PFIFO_CLR(1'b0), .CH0_FFC_RATE_MODE_RX(1'b0), + .CH1_FFC_RATE_MODE_RX(1'b0), .CH0_FFC_RATE_MODE_TX(1'b0), .CH1_FFC_RATE_MODE_TX(1'b0), + .CH0_FFC_DIV11_MODE_RX(1'b0), .CH1_FFC_DIV11_MODE_RX(1'b0), .CH0_FFC_DIV11_MODE_TX(1'b0), + .CH1_FFC_DIV11_MODE_TX(1'b0), .CH0_FFC_RX_GEAR_MODE(1'b0), .CH1_FFC_RX_GEAR_MODE(1'b0), + .CH0_FFC_TX_GEAR_MODE(1'b0), .CH1_FFC_TX_GEAR_MODE(1'b0), .CH0_FFC_LDR_CORE2TX_EN(1'b0), + .CH1_FFC_LDR_CORE2TX_EN(1'b0), .CH0_FFC_LANE_TX_RST(1'b0), .CH1_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c), + .CH0_FFC_LANE_RX_RST(1'b0), .CH1_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c), + .CH0_FFC_RRST(1'b0), .CH1_FFC_RRST(rsl_rx_serdes_rst_c), .CH0_FFC_TXPWDNB(1'b0), + .CH1_FFC_TXPWDNB(tx_pwrup_c), .CH0_FFC_RXPWDNB(1'b0), .CH1_FFC_RXPWDNB(rx_pwrup_c), + .CH0_LDR_CORE2TX(1'b0), .CH1_LDR_CORE2TX(1'b0), .D_SCIWDATA0(sci_wrdata[0]), + .D_SCIWDATA1(sci_wrdata[1]), .D_SCIWDATA2(sci_wrdata[2]), .D_SCIWDATA3(sci_wrdata[3]), + .D_SCIWDATA4(sci_wrdata[4]), .D_SCIWDATA5(sci_wrdata[5]), .D_SCIWDATA6(sci_wrdata[6]), + .D_SCIWDATA7(sci_wrdata[7]), .D_SCIADDR0(sci_addr[0]), .D_SCIADDR1(sci_addr[1]), + .D_SCIADDR2(sci_addr[2]), .D_SCIADDR3(sci_addr[3]), .D_SCIADDR4(sci_addr[4]), + .D_SCIADDR5(sci_addr[5]), .D_SCIENAUX(sci_en_dual), .D_SCISELAUX(sci_sel_dual), + .CH0_SCIEN(1'b0), .CH1_SCIEN(sci_en), .CH0_SCISEL(1'b0), .CH1_SCISEL(sci_sel), + .D_SCIRD(sci_rd), .D_SCIWSTN(sci_wrn), .D_CYAWSTN(cyawstn), .D_FFC_SYNC_TOGGLE(1'b0), + .D_FFC_DUAL_RST(rsl_rst_dual_c), .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c), + .D_FFC_MACROPDB(serdes_pdb), .D_FFC_TRST(rsl_tx_serdes_rst_c), + .CH0_FFC_CDR_EN_BITSLIP(1'b0), .CH1_FFC_CDR_EN_BITSLIP(1'b0), .D_SCAN_ENABLE(1'b0), + .D_SCAN_IN_0(1'b0), .D_SCAN_IN_1(1'b0), .D_SCAN_IN_2(1'b0), .D_SCAN_IN_3(1'b0), + .D_SCAN_IN_4(1'b0), .D_SCAN_IN_5(1'b0), .D_SCAN_IN_6(1'b0), .D_SCAN_IN_7(1'b0), + .D_SCAN_MODE(1'b0), .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), + .D_CIN2(1'b0), .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), + .D_CIN6(1'b0), .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), + .D_CIN10(1'b0), .D_CIN11(1'b0), .CH0_HDOUTP(n61), .CH1_HDOUTP(hdoutp), + .CH0_HDOUTN(n62), .CH1_HDOUTN(hdoutn), .D_TXBIT_CLKP_TO_ND(n1), + .D_TXBIT_CLKN_TO_ND(n2), .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), + .CH0_FF_RX_F_CLK(n63), .CH1_FF_RX_F_CLK(n5), .CH0_FF_RX_H_CLK(n64), + .CH1_FF_RX_H_CLK(n6), .CH0_FF_TX_F_CLK(n65), .CH1_FF_TX_F_CLK(n7), + .CH0_FF_TX_H_CLK(n66), .CH1_FF_TX_H_CLK(n8), .CH0_FF_RX_PCLK(n67), + .CH1_FF_RX_PCLK(rx_pclk), .CH0_FF_TX_PCLK(n68), .CH1_FF_TX_PCLK(tx_pclk), + .CH0_FF_RX_D_0(n69), .CH1_FF_RX_D_0(rxdata[0]), .CH0_FF_RX_D_1(n70), + .CH1_FF_RX_D_1(rxdata[1]), .CH0_FF_RX_D_2(n71), .CH1_FF_RX_D_2(rxdata[2]), + .CH0_FF_RX_D_3(n72), .CH1_FF_RX_D_3(rxdata[3]), .CH0_FF_RX_D_4(n73), + .CH1_FF_RX_D_4(rxdata[4]), .CH0_FF_RX_D_5(n74), .CH1_FF_RX_D_5(rxdata[5]), + .CH0_FF_RX_D_6(n75), .CH1_FF_RX_D_6(rxdata[6]), .CH0_FF_RX_D_7(n76), + .CH1_FF_RX_D_7(rxdata[7]), .CH0_FF_RX_D_8(n77), .CH1_FF_RX_D_8(rx_k[0]), + .CH0_FF_RX_D_9(n78), .CH1_FF_RX_D_9(rx_disp_err[0]), .CH0_FF_RX_D_10(n79), + .CH1_FF_RX_D_10(rx_cv_err[0]), .CH0_FF_RX_D_11(n80), .CH1_FF_RX_D_11(n9), + .CH0_FF_RX_D_12(n81), .CH1_FF_RX_D_12(n10), .CH0_FF_RX_D_13(n82), + .CH1_FF_RX_D_13(n11), .CH0_FF_RX_D_14(n83), .CH1_FF_RX_D_14(n12), + .CH0_FF_RX_D_15(n84), .CH1_FF_RX_D_15(n13), .CH0_FF_RX_D_16(n85), + .CH1_FF_RX_D_16(n14), .CH0_FF_RX_D_17(n86), .CH1_FF_RX_D_17(n15), + .CH0_FF_RX_D_18(n87), .CH1_FF_RX_D_18(n16), .CH0_FF_RX_D_19(n88), + .CH1_FF_RX_D_19(n17), .CH0_FF_RX_D_20(n89), .CH1_FF_RX_D_20(n18), + .CH0_FF_RX_D_21(n90), .CH1_FF_RX_D_21(n19), .CH0_FF_RX_D_22(n91), + .CH1_FF_RX_D_22(n20), .CH0_FF_RX_D_23(n92), .CH1_FF_RX_D_23(n21), + .CH0_FFS_PCIE_DONE(n93), .CH1_FFS_PCIE_DONE(n22), .CH0_FFS_PCIE_CON(n94), + .CH1_FFS_PCIE_CON(n23), .CH0_FFS_RLOS(n95), .CH1_FFS_RLOS(n96), + .CH0_FFS_LS_SYNC_STATUS(n97), .CH1_FFS_LS_SYNC_STATUS(lsm_status_s), + .CH0_FFS_CC_UNDERRUN(n98), .CH1_FFS_CC_UNDERRUN(n24), .CH0_FFS_CC_OVERRUN(n99), + .CH1_FFS_CC_OVERRUN(n25), .CH0_FFS_RXFBFIFO_ERROR(n100), .CH1_FFS_RXFBFIFO_ERROR(n26), + .CH0_FFS_TXFBFIFO_ERROR(n101), .CH1_FFS_TXFBFIFO_ERROR(n27), .CH0_FFS_RLOL(n102), + .CH1_FFS_RLOL(rx_cdr_lol_s), .CH0_FFS_SKP_ADDED(n103), .CH1_FFS_SKP_ADDED(n28), + .CH0_FFS_SKP_DELETED(n104), .CH1_FFS_SKP_DELETED(n29), .CH0_LDR_RX2CORE(n105), + .CH1_LDR_RX2CORE(n116), .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), + .D_SCIRDATA2(sci_rddata[2]), .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), + .D_SCIRDATA5(sci_rddata[5]), .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), + .D_SCIINT(sci_int), .D_SCAN_OUT_0(n30), .D_SCAN_OUT_1(n31), .D_SCAN_OUT_2(n32), + .D_SCAN_OUT_3(n33), .D_SCAN_OUT_4(n34), .D_SCAN_OUT_5(n35), .D_SCAN_OUT_6(n36), + .D_SCAN_OUT_7(n37), .D_COUT0(n38), .D_COUT1(n39), .D_COUT2(n40), + .D_COUT3(n41), .D_COUT4(n42), .D_COUT5(n43), .D_COUT6(n44), + .D_COUT7(n45), .D_COUT8(n46), .D_COUT9(n47), .D_COUT10(n48), + .D_COUT11(n49), .D_COUT12(n50), .D_COUT13(n51), .D_COUT14(n52), + .D_COUT15(n53), .D_COUT16(n54), .D_COUT17(n55), .D_COUT18(n56), + .D_COUT19(n57), .D_REFCLKI(pll_refclki), .D_FFS_PLOL(n60)) /* synthesis LOC=DCU1 CHAN=CH1 */ ; + defparam DCU1_inst.D_MACROPDB = "0b1"; + defparam DCU1_inst.D_IB_PWDNB = "0b1"; + defparam DCU1_inst.D_XGE_MODE = "0b0"; + defparam DCU1_inst.D_LOW_MARK = "0d4"; + defparam DCU1_inst.D_HIGH_MARK = "0d12"; + defparam DCU1_inst.D_BUS8BIT_SEL = "0b0"; + defparam DCU1_inst.D_CDR_LOL_SET = "0b00"; + defparam DCU1_inst.D_TXPLL_PWDNB = "0b1"; + defparam DCU1_inst.D_BITCLK_LOCAL_EN = "0b1"; + defparam DCU1_inst.D_BITCLK_ND_EN = "0b0"; + defparam DCU1_inst.D_BITCLK_FROM_ND_EN = "0b0"; + defparam DCU1_inst.D_SYNC_LOCAL_EN = "0b1"; + defparam DCU1_inst.D_SYNC_ND_EN = "0b0"; + defparam DCU1_inst.CH1_UC_MODE = "0b0"; + defparam DCU1_inst.CH1_PCIE_MODE = "0b0"; + defparam DCU1_inst.CH1_RIO_MODE = "0b0"; + defparam DCU1_inst.CH1_WA_MODE = "0b0"; + defparam DCU1_inst.CH1_INVERT_RX = "0b0"; + defparam DCU1_inst.CH1_INVERT_TX = "0b0"; + defparam DCU1_inst.CH1_PRBS_SELECTION = "0b0"; + defparam DCU1_inst.CH1_GE_AN_ENABLE = "0b1"; + defparam DCU1_inst.CH1_PRBS_LOCK = "0b0"; + defparam DCU1_inst.CH1_PRBS_ENABLE = "0b0"; + defparam DCU1_inst.CH1_ENABLE_CG_ALIGN = "0b1"; + defparam DCU1_inst.CH1_TX_GEAR_MODE = "0b0"; + defparam DCU1_inst.CH1_RX_GEAR_MODE = "0b0"; + defparam DCU1_inst.CH1_PCS_DET_TIME_SEL = "0b00"; + defparam DCU1_inst.CH1_PCIE_EI_EN = "0b0"; + defparam DCU1_inst.CH1_TX_GEAR_BYPASS = "0b0"; + defparam DCU1_inst.CH1_ENC_BYPASS = "0b0"; + defparam DCU1_inst.CH1_SB_BYPASS = "0b0"; + defparam DCU1_inst.CH1_RX_SB_BYPASS = "0b0"; + defparam DCU1_inst.CH1_WA_BYPASS = "0b0"; + defparam DCU1_inst.CH1_DEC_BYPASS = "0b0"; + defparam DCU1_inst.CH1_CTC_BYPASS = "0b1"; + defparam DCU1_inst.CH1_RX_GEAR_BYPASS = "0b0"; + defparam DCU1_inst.CH1_LSM_DISABLE = "0b0"; + defparam DCU1_inst.CH1_MATCH_2_ENABLE = "0b0"; + defparam DCU1_inst.CH1_MATCH_4_ENABLE = "0b0"; + defparam DCU1_inst.CH1_MIN_IPG_CNT = "0b11"; + defparam DCU1_inst.CH1_CC_MATCH_1 = "0x000"; + defparam DCU1_inst.CH1_CC_MATCH_2 = "0x000"; + defparam DCU1_inst.CH1_CC_MATCH_3 = "0x000"; + defparam DCU1_inst.CH1_CC_MATCH_4 = "0x000"; + defparam DCU1_inst.CH1_UDF_COMMA_MASK = "0x3ff"; + defparam DCU1_inst.CH1_UDF_COMMA_A = "0x283"; + defparam DCU1_inst.CH1_UDF_COMMA_B = "0x17C"; + defparam DCU1_inst.CH1_RX_DCO_CK_DIV = "0b000"; + defparam DCU1_inst.CH1_RCV_DCC_EN = "0b0"; + defparam DCU1_inst.CH1_TPWDNB = "0b1"; + defparam DCU1_inst.CH1_RATE_MODE_TX = "0b1"; + defparam DCU1_inst.CH1_RTERM_TX = "0d19"; + defparam DCU1_inst.CH1_TX_CM_SEL = "0b00"; + defparam DCU1_inst.CH1_TDRV_PRE_EN = "0b0"; + defparam DCU1_inst.CH1_TDRV_SLICE0_SEL = "0b01"; + defparam DCU1_inst.CH1_TDRV_SLICE1_SEL = "0b00"; + defparam DCU1_inst.CH1_TDRV_SLICE2_SEL = "0b01"; + defparam DCU1_inst.CH1_TDRV_SLICE3_SEL = "0b01"; + defparam DCU1_inst.CH1_TDRV_SLICE4_SEL = "0b01"; + defparam DCU1_inst.CH1_TDRV_SLICE5_SEL = "0b00"; + defparam DCU1_inst.CH1_TDRV_SLICE0_CUR = "0b011"; + defparam DCU1_inst.CH1_TDRV_SLICE1_CUR = "0b000"; + defparam DCU1_inst.CH1_TDRV_SLICE2_CUR = "0b11"; + defparam DCU1_inst.CH1_TDRV_SLICE3_CUR = "0b11"; + defparam DCU1_inst.CH1_TDRV_SLICE4_CUR = "0b11"; + defparam DCU1_inst.CH1_TDRV_SLICE5_CUR = "0b00"; + defparam DCU1_inst.CH1_TDRV_DAT_SEL = "0b00"; + defparam DCU1_inst.CH1_TX_DIV11_SEL = "0b0"; + defparam DCU1_inst.CH1_RPWDNB = "0b1"; + defparam DCU1_inst.CH1_RATE_MODE_RX = "0b1"; + defparam DCU1_inst.CH1_RX_DIV11_SEL = "0b0"; + defparam DCU1_inst.CH1_SEL_SD_RX_CLK = "0b1"; + defparam DCU1_inst.CH1_FF_RX_H_CLK_EN = "0b0"; + defparam DCU1_inst.CH1_FF_RX_F_CLK_DIS = "0b0"; + defparam DCU1_inst.CH1_FF_TX_H_CLK_EN = "0b0"; + defparam DCU1_inst.CH1_FF_TX_F_CLK_DIS = "0b0"; + defparam DCU1_inst.CH1_TDRV_POST_EN = "0b0"; + defparam DCU1_inst.CH1_TX_POST_SIGN = "0b0"; + defparam DCU1_inst.CH1_TX_PRE_SIGN = "0b0"; + defparam DCU1_inst.CH1_REQ_LVL_SET = "0b01"; + defparam DCU1_inst.CH1_REQ_EN = "0b1"; + defparam DCU1_inst.CH1_RTERM_RX = "0d22"; + defparam DCU1_inst.CH1_RXTERM_CM = "0b11"; + defparam DCU1_inst.CH1_PDEN_SEL = "0b1"; + defparam DCU1_inst.CH1_RXIN_CM = "0b11"; + defparam DCU1_inst.CH1_LEQ_OFFSET_SEL = "0b0"; + defparam DCU1_inst.CH1_LEQ_OFFSET_TRIM = "0b000"; + defparam DCU1_inst.CH1_RLOS_SEL = "0b1"; + defparam DCU1_inst.CH1_RX_LOS_LVL = "0b010"; + defparam DCU1_inst.CH1_RX_LOS_CEQ = "0b11"; + defparam DCU1_inst.CH1_RX_LOS_HYST_EN = "0b0"; + defparam DCU1_inst.CH1_RX_LOS_EN = "0b0"; + defparam DCU1_inst.CH1_LDR_RX2CORE_SEL = "0b0"; + defparam DCU1_inst.CH1_LDR_CORE2TX_SEL = "0b0"; + defparam DCU1_inst.D_TX_MAX_RATE = "2.5"; + defparam DCU1_inst.CH1_CDR_MAX_RATE = "2.5"; + defparam DCU1_inst.CH1_TXAMPLITUDE = "0d6"; + defparam DCU1_inst.CH1_TXDEPRE = "DISABLED"; + defparam DCU1_inst.CH1_TXDEPOST = "DISABLED"; + defparam DCU1_inst.CH1_PROTOCOL = "SGMII"; + defparam DCU1_inst.D_ISETLOS = "0d0"; + defparam DCU1_inst.D_SETIRPOLY_AUX = "0b00"; + defparam DCU1_inst.D_SETICONST_AUX = "0b00"; + defparam DCU1_inst.D_SETIRPOLY_CH = "0b00"; + defparam DCU1_inst.D_SETICONST_CH = "0b00"; + defparam DCU1_inst.D_REQ_ISET = "0b000"; + defparam DCU1_inst.D_PD_ISET = "0b00"; + defparam DCU1_inst.D_DCO_CALIB_TIME_SEL = "0b00"; + defparam DCU1_inst.CH1_CDR_CNT4SEL = "0b00"; + defparam DCU1_inst.CH1_CDR_CNT8SEL = "0b00"; + defparam DCU1_inst.CH1_DCOATDCFG = "0b00"; + defparam DCU1_inst.CH1_DCOATDDLY = "0b00"; + defparam DCU1_inst.CH1_DCOBYPSATD = "0b1"; + defparam DCU1_inst.CH1_DCOCALDIV = "0b001"; + defparam DCU1_inst.CH1_DCOCTLGI = "0b010"; + defparam DCU1_inst.CH1_DCODISBDAVOID = "0b0"; + defparam DCU1_inst.CH1_DCOFLTDAC = "0b01"; + defparam DCU1_inst.CH1_DCOFTNRG = "0b110"; + defparam DCU1_inst.CH1_DCOIOSTUNE = "0b000"; + defparam DCU1_inst.CH1_DCOITUNE = "0b00"; + defparam DCU1_inst.CH1_DCOITUNE4LSB = "0b111"; + defparam DCU1_inst.CH1_DCOIUPDNX2 = "0b1"; + defparam DCU1_inst.CH1_DCONUOFLSB = "0b101"; + defparam DCU1_inst.CH1_DCOSCALEI = "0b00"; + defparam DCU1_inst.CH1_DCOSTARTVAL = "0b000"; + defparam DCU1_inst.CH1_DCOSTEP = "0b00"; + defparam DCU1_inst.CH1_BAND_THRESHOLD = "0d0"; + defparam DCU1_inst.CH1_AUTO_FACQ_EN = "0b1"; + defparam DCU1_inst.CH1_AUTO_CALIB_EN = "0b1"; + defparam DCU1_inst.CH1_CALIB_CK_MODE = "0b0"; + defparam DCU1_inst.CH1_REG_BAND_OFFSET = "0d0"; + defparam DCU1_inst.CH1_REG_BAND_SEL = "0d0"; + defparam DCU1_inst.CH1_REG_IDAC_SEL = "0d0"; + defparam DCU1_inst.CH1_REG_IDAC_EN = "0b0"; + defparam DCU1_inst.D_CMUSETISCL4VCO = "0b000"; + defparam DCU1_inst.D_CMUSETI4VCO = "0b00"; + defparam DCU1_inst.D_CMUSETINITVCT = "0b00"; + defparam DCU1_inst.D_CMUSETZGM = "0b000"; + defparam DCU1_inst.D_CMUSETP2AGM = "0b000"; + defparam DCU1_inst.D_CMUSETP1GM = "0b000"; + defparam DCU1_inst.D_CMUSETI4CPZ = "0d3"; + defparam DCU1_inst.D_CMUSETI4CPP = "0d3"; + defparam DCU1_inst.D_CMUSETICP4Z = "0b101"; + defparam DCU1_inst.D_CMUSETICP4P = "0b01"; + defparam DCU1_inst.D_CMUSETBIASI = "0b00"; + defparam DCU1_inst.D_SETPLLRC = "0d1"; + defparam DCU1_inst.CH1_RX_RATE_SEL = "0d8"; + defparam DCU1_inst.D_REFCK_MODE = "0b000"; + defparam DCU1_inst.D_TX_VCO_CK_DIV = "0b000"; + defparam DCU1_inst.D_PLL_LOL_SET = "0b00"; + defparam DCU1_inst.D_RG_EN = "0b0"; + defparam DCU1_inst.D_RG_SET = "0b00"; + assign n1 = 1'bz; + assign n2 = 1'bz; + assign n3 = 1'bz; + assign n4 = 1'bz; + assign n5 = 1'bz; + assign n6 = 1'bz; + assign n7 = 1'bz; + assign n8 = 1'bz; + assign n9 = 1'bz; + assign n10 = 1'bz; + assign n11 = 1'bz; + assign n12 = 1'bz; + assign n13 = 1'bz; + assign n14 = 1'bz; + assign n15 = 1'bz; + assign n16 = 1'bz; + assign n17 = 1'bz; + assign n18 = 1'bz; + assign n19 = 1'bz; + assign n20 = 1'bz; + assign n21 = 1'bz; + assign n22 = 1'bz; + assign n23 = 1'bz; + assign n24 = 1'bz; + assign n25 = 1'bz; + assign n26 = 1'bz; + assign n27 = 1'bz; + assign n28 = 1'bz; + assign n29 = 1'bz; + assign n30 = 1'bz; + assign n31 = 1'bz; + assign n32 = 1'bz; + assign n33 = 1'bz; + assign n34 = 1'bz; + assign n35 = 1'bz; + assign n36 = 1'bz; + assign n37 = 1'bz; + assign n38 = 1'bz; + assign n39 = 1'bz; + assign n40 = 1'bz; + assign n41 = 1'bz; + assign n42 = 1'bz; + assign n43 = 1'bz; + assign n44 = 1'bz; + assign n45 = 1'bz; + assign n46 = 1'bz; + assign n47 = 1'bz; + assign n48 = 1'bz; + assign n49 = 1'bz; + assign n50 = 1'bz; + assign n51 = 1'bz; + assign n52 = 1'bz; + assign n53 = 1'bz; + assign n54 = 1'bz; + assign n55 = 1'bz; + assign n56 = 1'bz; + assign n57 = 1'bz; + assign n60 = 1'bz; + assign n61 = 1'bz; + assign n62 = 1'bz; + assign n63 = 1'bz; + assign n64 = 1'bz; + assign n65 = 1'bz; + assign n66 = 1'bz; + assign n67 = 1'bz; + assign n68 = 1'bz; + assign n69 = 1'bz; + assign n70 = 1'bz; + assign n71 = 1'bz; + assign n72 = 1'bz; + assign n73 = 1'bz; + assign n74 = 1'bz; + assign n75 = 1'bz; + assign n76 = 1'bz; + assign n77 = 1'bz; + assign n78 = 1'bz; + assign n79 = 1'bz; + assign n80 = 1'bz; + assign n81 = 1'bz; + assign n82 = 1'bz; + assign n83 = 1'bz; + assign n84 = 1'bz; + assign n85 = 1'bz; + assign n86 = 1'bz; + assign n87 = 1'bz; + assign n88 = 1'bz; + assign n89 = 1'bz; + assign n90 = 1'bz; + assign n91 = 1'bz; + assign n92 = 1'bz; + assign n93 = 1'bz; + assign n94 = 1'bz; + assign n95 = 1'bz; + assign n96 = 1'bz; + assign n97 = 1'bz; + assign n98 = 1'bz; + assign n99 = 1'bz; + assign n100 = 1'bz; + assign n101 = 1'bz; + assign n102 = 1'bz; + assign n103 = 1'bz; + assign n104 = 1'bz; + assign n105 = 1'bz; + assign n116 = 1'bz; + sgmii_channel_smi_core_pcsrsl_core rsl_inst (.rui_rst(rsl_rst), .rui_serdes_rst_dual_c(serdes_rst_dual_c), + .rui_rst_dual_c(rst_dual_c), .rui_rsl_disable(rsl_disable), + .rui_tx_ref_clk(pll_refclki), .rui_tx_serdes_rst_c(tx_serdes_rst_c), + .rui_tx_pcs_rst_c({3'b000, tx_pcs_rst_c}), .rdi_pll_lol(pll_lol), + .rui_rx_ref_clk(rxrefclk), .rui_rx_serdes_rst_c({3'b000, rx_serdes_rst_c}), + .rui_rx_pcs_rst_c({3'b000, rx_pcs_rst_c}), .rdi_rx_los_low_s({4'b0000}), + .rdi_rx_cdr_lol_s({3'b000, rx_cdr_lol_s}), .rdo_serdes_rst_dual_c(rsl_serdes_rst_dual_c), + .rdo_rst_dual_c(rsl_rst_dual_c), .ruo_tx_rdy(n117), .rdo_tx_serdes_rst_c(rsl_tx_serdes_rst_c), + .rdo_tx_pcs_rst_c({n118, n119, n120, rsl_tx_pcs_rst_c}), + .ruo_rx_rdy(n121), .rdo_rx_serdes_rst_c({n122, n123, n124, + rsl_rx_serdes_rst_c}), .rdo_rx_pcs_rst_c({n125, n126, _Z, + rsl_rx_pcs_rst_c})); + defparam rsl_inst.pnum_channels = 1; + defparam rsl_inst.pprotocol = "SGMII"; + defparam rsl_inst.pserdes_mode = "RX AND TX"; + defparam rsl_inst.pport_tx_rdy = "DISABLED"; + defparam rsl_inst.pwait_tx_rdy = 3000; + defparam rsl_inst.pport_rx_rdy = "DISABLED"; + defparam rsl_inst.pwait_rx_rdy = 3000; + assign n117 = 1'bz; + assign n118 = 1'bz; + assign n119 = 1'bz; + assign n120 = 1'bz; + assign n121 = 1'bz; + assign n122 = 1'bz; + assign n123 = 1'bz; + assign n124 = 1'bz; + assign n125 = 1'bz; + assign n126 = 1'bz; + assign _Z = 1'bz; + sgmii_channel_smi_core_pcssll_core sll_inst (.sli_rst(sli_rst), .sli_refclk(pll_refclki), + .sli_pclk(tx_pclk), .sli_div2_rate(1'b0), .sli_div11_rate(1'b0), + .sli_gear_mode(1'b0), .sli_cpri_mode({3'b000}), .sli_pcie_mode(1'b0), + .slo_plol(pll_lol)); + defparam sll_inst.PPROTOCOL = "SGMII"; + defparam sll_inst.PLOL_SETTING = 0; + defparam sll_inst.PDYN_RATE_CTRL = "DISABLED"; + defparam sll_inst.PPCIE_MAX_RATE = "2.5"; + defparam sll_inst.PDIFF_VAL_LOCK = 19; + defparam sll_inst.PDIFF_VAL_UNLOCK = 39; + defparam sll_inst.PPCLK_TC = 65536; + defparam sll_inst.PDIFF_DIV11_VAL_LOCK = 0; + defparam sll_inst.PDIFF_DIV11_VAL_UNLOCK = 0; + defparam sll_inst.PPCLK_DIV11_TC = 0; + +endmodule + + + diff --git a/gbe_trb/media/ecp5/tsmac.lpc b/gbe_trb/media/ecp5/tsmac.lpc new file mode 100644 index 0000000..5c8ae17 --- /dev/null +++ b/gbe_trb/media/ecp5/tsmac.lpc @@ -0,0 +1,37 @@ +[Device] +Family=sa5p00m +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=IPCFG +CoreStatus=Demo +CoreName=Tri-Speed Ethernet MAC +CoreRevision=4.1 +ModuleName=tsmac +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=04/29/2019 +Time=13:44:50 + +[Parameters] +MIIM=No +MODE=SGMII easy connect +MODS_TOOL=1 +ALDC_TOOL=0 +MULT_WB=NO +LOOPBACK=NO +STAT_REGS=NO +CORE_SYNP=1 + +[Files] +Synthesis= +Simulation= +Logical= +Physical= +Misc= diff --git a/gbe_trb/media/ecp5/tsmac.ngd b/gbe_trb/media/ecp5/tsmac.ngd new file mode 100644 index 0000000..3fe1735 Binary files /dev/null and b/gbe_trb/media/ecp5/tsmac.ngd differ diff --git a/gbe_trb/media/ecp5/tsmac.ngo b/gbe_trb/media/ecp5/tsmac.ngo new file mode 100644 index 0000000..50ccd6f Binary files /dev/null and b/gbe_trb/media/ecp5/tsmac.ngo differ diff --git a/gbe_trb/media/ecp5/tsmac.v b/gbe_trb/media/ecp5/tsmac.v new file mode 100644 index 0000000..569c933 --- /dev/null +++ b/gbe_trb/media/ecp5/tsmac.v @@ -0,0 +1,212 @@ +//============================================================================= +// Verilog module generated by IPExpress +// Filename: USERNAME.v +// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. +//============================================================================= + +/* WARNING - Changes to this file should be performed by re-running IPexpress +or modifying the .LPC file and regenerating the core. Other changes may lead +to inconsistent simulation and/or implemenation results */ +`timescale 1 ns/ 1ns +module tsmac ( + // clock and reset + hclk, + txmac_clk, + rxmac_clk, + reset_n, + txmac_clk_en, + rxmac_clk_en, + + // Input signals to the GMII + rxd, + rx_dv, + rx_er, + col, + crs, + // Input signals to the CPU Interface + haddr, + hdatain, + hcs_n, + hwrite_n, + hread_n, + + // Input signals to the MII Management Interface + + // Input signals to the Tx MAC FIFO Interface + tx_fifodata, + tx_fifoavail, + tx_fifoeof, + tx_fifoempty, + tx_sndpaustim, + tx_sndpausreq, + tx_fifoctrl, + + // Input signals to the Rx MAC FIFO Interface + rx_fifo_full, + ignore_pkt, + + // Output signals from the GMII + txd, + tx_en, + tx_er, + + // Output signals from the CPU Interface + hdataout, + hdataout_en_n, + hready_n, + cpu_if_gbit_en, + + // Output signals from the MII Management Interface + + // Output signals from the Tx MAC FIFO Interface + tx_macread, + tx_discfrm, + tx_staten, + tx_statvec, + tx_done, + + // Output signals from the Rx MAC FIFO Interface + rx_fifo_error, + rx_stat_vector, + rx_dbout, + rx_write, + rx_stat_en, + rx_eof, + rx_error + ); + + // ------------------------- clock and reset inputs --------------------- + input hclk; // clock to the CPU I/F + input txmac_clk; // clock to the Tx MAC + input rxmac_clk; // clock to the RX MAC + input reset_n; // Global reset + input txmac_clk_en; // clock enable to the Tx MAC + input rxmac_clk_en; // clock enable to the RX MAC + + // ----------------------- Input signals to the GMII ------------------- + input [7:0] rxd; // Receive data + input rx_dv; // Receive data valid + input rx_er; // Receive data error + input col; // Collision detect + input crs; // Carrier Sense + // -------------------- Input signals to the CPU I/F ------------------- + input [7:0] haddr; // Address Bus + input [7:0] hdatain; // Input data Bus + input hcs_n; // Chip select + input hwrite_n; // Register write + input hread_n; // Register read + + // -------------------- Input signals to the MII I/F ------------------- + + + // ---------------- Input signals to the Tx MAC FIFO I/F --------------- + input [7:0] tx_fifodata; // Data Input from FIFO + input tx_fifoavail; // Data Available in FIFO + input tx_fifoeof; // End of Frame + input tx_fifoempty; // FIFO Empty + input [15:0] tx_sndpaustim; // Pause frame parameter + input tx_sndpausreq; // Transmit PAUSE frame + input tx_fifoctrl; // Control frame or Not + + // ---------------- Input signals to the Rx MAC FIFO I/F --------------- + input rx_fifo_full; // Receive FIFO Full + input ignore_pkt; // Ignore the frame + + // -------------------- Output signals from the GMII ----------------------- + output [7:0] txd; // Transmit data + output tx_en; // Transmit Enable + output tx_er; // Transmit Error + + // -------------------- Output signals from the CPU I/F ------------------- + output [7:0] hdataout; // Output data Bus + output hdataout_en_n; // Data Out Enable + output hready_n; // Ready signal + output cpu_if_gbit_en; // Gig or 10/100 mode + + // -------------------- Output signals from the MII I/F ------------------- + + + // ---------------- Output signals from the Tx MAC FIFO I/F --------------- + output tx_macread; // Read FIFO + output tx_discfrm; // Discard Frame + output tx_staten; // Status Vector Valid + output tx_done; // Transmit of Frame done + output [30:0] tx_statvec; // Tx Status Vector + + // ---------------- Output signals from the Rx MAC FIFO I/F --------------- + output rx_fifo_error; // FIFO full detected + output [31:0] rx_stat_vector; // Rx Status Vector + output [7:0] rx_dbout; // Data Output to FIFO + output rx_write; // Write FIFO + output rx_stat_en; // Status Vector Valid + output rx_eof; // Entire frame written + output rx_error; // Erroneous frame + + tsmac_core U1_LSC_ts_mac_core ( + + // clock and reset + .hclk(hclk), + .txmac_clk(txmac_clk), + .rxmac_clk(rxmac_clk), + .reset_n(reset_n), + .txmac_clk_en(txmac_clk_en), + .rxmac_clk_en(rxmac_clk_en), + + // Input signals to the GMII + .rxd(rxd), + .rx_dv(rx_dv), + .rx_er(rx_er), + .col(col), + .crs(crs), + // Input signals to the CPU Interface + .haddr(haddr), + .hdatain(hdatain), + .hcs_n(hcs_n), + .hwrite_n(hwrite_n), + .hread_n(hread_n), + + // Input signals to the MII Management Interface + + // Input signals to the Tx MAC FIFO Interface + .tx_fifodata(tx_fifodata), + .tx_fifoavail(tx_fifoavail), + .tx_fifoeof(tx_fifoeof), + .tx_fifoempty(tx_fifoempty), + .tx_sndpaustim(tx_sndpaustim), + .tx_sndpausreq(tx_sndpausreq), + .tx_fifoctrl(tx_fifoctrl), + + // Input signals to the Rx MAC FIFO Interface + .rx_fifo_full(rx_fifo_full), + .ignore_pkt(ignore_pkt), + + // Output signals from the GMII + .txd(txd), + .tx_en(tx_en), + .tx_er(tx_er), + + // Output signals from the CPU Interface + .hdataout(hdataout), + .hdataout_en_n(hdataout_en_n), + .hready_n(hready_n), + .cpu_if_gbit_en(cpu_if_gbit_en), + + // Output signals from the MII Management Interface + + // Output signals from the Tx MAC FIFO Interface + .tx_macread(tx_macread), + .tx_discfrm(tx_discfrm), + .tx_staten(tx_staten), + .tx_statvec(tx_statvec), + .tx_done(tx_done), + + // Output signals from the Rx MAC FIFO Interface + .rx_fifo_error(rx_fifo_error), + .rx_stat_vector(rx_stat_vector), + .rx_dbout(rx_dbout), + .rx_write(rx_write), + .rx_stat_en(rx_stat_en), + .rx_eof(rx_eof), + .rx_error(rx_error) + ); +endmodule diff --git a/gbe_trb/media/ecp5/tsmac35.lpc b/gbe_trb/media/ecp5/tsmac35.lpc new file mode 100644 index 0000000..a9703a3 --- /dev/null +++ b/gbe_trb/media/ecp5/tsmac35.lpc @@ -0,0 +1,37 @@ +[Device] +Family=sa5p00m +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=IPCFG +CoreStatus=Demo +CoreName=Tri-Speed Ethernet MAC +CoreRevision=4.1 +ModuleName=tsmac35 +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=04/30/2019 +Time=13:54:14 + +[Parameters] +MIIM=No +MODE=SGMII easy connect +MODS_TOOL=1 +ALDC_TOOL=0 +MULT_WB=NO +LOOPBACK=NO +STAT_REGS=NO +CORE_SYNP=1 + +[Files] +Synthesis= +Simulation= +Logical= +Physical= +Misc= diff --git a/gbe_trb/media/ecp5/tsmac35.ngo b/gbe_trb/media/ecp5/tsmac35.ngo new file mode 100644 index 0000000..da48365 Binary files /dev/null and b/gbe_trb/media/ecp5/tsmac35.ngo differ diff --git a/gbe_trb/media/ecp5/tsmac35.v b/gbe_trb/media/ecp5/tsmac35.v new file mode 100644 index 0000000..9359be2 --- /dev/null +++ b/gbe_trb/media/ecp5/tsmac35.v @@ -0,0 +1,212 @@ +//============================================================================= +// Verilog module generated by IPExpress +// Filename: USERNAME.v +// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved. +//============================================================================= + +/* WARNING - Changes to this file should be performed by re-running IPexpress +or modifying the .LPC file and regenerating the core. Other changes may lead +to inconsistent simulation and/or implemenation results */ +`timescale 1 ns/ 1ns +module tsmac35 ( + // clock and reset + hclk, + txmac_clk, + rxmac_clk, + reset_n, + txmac_clk_en, + rxmac_clk_en, + + // Input signals to the GMII + rxd, + rx_dv, + rx_er, + col, + crs, + // Input signals to the CPU Interface + haddr, + hdatain, + hcs_n, + hwrite_n, + hread_n, + + // Input signals to the MII Management Interface + + // Input signals to the Tx MAC FIFO Interface + tx_fifodata, + tx_fifoavail, + tx_fifoeof, + tx_fifoempty, + tx_sndpaustim, + tx_sndpausreq, + tx_fifoctrl, + + // Input signals to the Rx MAC FIFO Interface + rx_fifo_full, + ignore_pkt, + + // Output signals from the GMII + txd, + tx_en, + tx_er, + + // Output signals from the CPU Interface + hdataout, + hdataout_en_n, + hready_n, + cpu_if_gbit_en, + + // Output signals from the MII Management Interface + + // Output signals from the Tx MAC FIFO Interface + tx_macread, + tx_discfrm, + tx_staten, + tx_statvec, + tx_done, + + // Output signals from the Rx MAC FIFO Interface + rx_fifo_error, + rx_stat_vector, + rx_dbout, + rx_write, + rx_stat_en, + rx_eof, + rx_error + ); + + // ------------------------- clock and reset inputs --------------------- + input hclk; // clock to the CPU I/F + input txmac_clk; // clock to the Tx MAC + input rxmac_clk; // clock to the RX MAC + input reset_n; // Global reset + input txmac_clk_en; // clock enable to the Tx MAC + input rxmac_clk_en; // clock enable to the RX MAC + + // ----------------------- Input signals to the GMII ------------------- + input [7:0] rxd; // Receive data + input rx_dv; // Receive data valid + input rx_er; // Receive data error + input col; // Collision detect + input crs; // Carrier Sense + // -------------------- Input signals to the CPU I/F ------------------- + input [7:0] haddr; // Address Bus + input [7:0] hdatain; // Input data Bus + input hcs_n; // Chip select + input hwrite_n; // Register write + input hread_n; // Register read + + // -------------------- Input signals to the MII I/F ------------------- + + + // ---------------- Input signals to the Tx MAC FIFO I/F --------------- + input [7:0] tx_fifodata; // Data Input from FIFO + input tx_fifoavail; // Data Available in FIFO + input tx_fifoeof; // End of Frame + input tx_fifoempty; // FIFO Empty + input [15:0] tx_sndpaustim; // Pause frame parameter + input tx_sndpausreq; // Transmit PAUSE frame + input tx_fifoctrl; // Control frame or Not + + // ---------------- Input signals to the Rx MAC FIFO I/F --------------- + input rx_fifo_full; // Receive FIFO Full + input ignore_pkt; // Ignore the frame + + // -------------------- Output signals from the GMII ----------------------- + output [7:0] txd; // Transmit data + output tx_en; // Transmit Enable + output tx_er; // Transmit Error + + // -------------------- Output signals from the CPU I/F ------------------- + output [7:0] hdataout; // Output data Bus + output hdataout_en_n; // Data Out Enable + output hready_n; // Ready signal + output cpu_if_gbit_en; // Gig or 10/100 mode + + // -------------------- Output signals from the MII I/F ------------------- + + + // ---------------- Output signals from the Tx MAC FIFO I/F --------------- + output tx_macread; // Read FIFO + output tx_discfrm; // Discard Frame + output tx_staten; // Status Vector Valid + output tx_done; // Transmit of Frame done + output [30:0] tx_statvec; // Tx Status Vector + + // ---------------- Output signals from the Rx MAC FIFO I/F --------------- + output rx_fifo_error; // FIFO full detected + output [31:0] rx_stat_vector; // Rx Status Vector + output [7:0] rx_dbout; // Data Output to FIFO + output rx_write; // Write FIFO + output rx_stat_en; // Status Vector Valid + output rx_eof; // Entire frame written + output rx_error; // Erroneous frame + + tsmac_core U1_LSC_ts_mac_core ( + + // clock and reset + .hclk(hclk), + .txmac_clk(txmac_clk), + .rxmac_clk(rxmac_clk), + .reset_n(reset_n), + .txmac_clk_en(txmac_clk_en), + .rxmac_clk_en(rxmac_clk_en), + + // Input signals to the GMII + .rxd(rxd), + .rx_dv(rx_dv), + .rx_er(rx_er), + .col(col), + .crs(crs), + // Input signals to the CPU Interface + .haddr(haddr), + .hdatain(hdatain), + .hcs_n(hcs_n), + .hwrite_n(hwrite_n), + .hread_n(hread_n), + + // Input signals to the MII Management Interface + + // Input signals to the Tx MAC FIFO Interface + .tx_fifodata(tx_fifodata), + .tx_fifoavail(tx_fifoavail), + .tx_fifoeof(tx_fifoeof), + .tx_fifoempty(tx_fifoempty), + .tx_sndpaustim(tx_sndpaustim), + .tx_sndpausreq(tx_sndpausreq), + .tx_fifoctrl(tx_fifoctrl), + + // Input signals to the Rx MAC FIFO Interface + .rx_fifo_full(rx_fifo_full), + .ignore_pkt(ignore_pkt), + + // Output signals from the GMII + .txd(txd), + .tx_en(tx_en), + .tx_er(tx_er), + + // Output signals from the CPU Interface + .hdataout(hdataout), + .hdataout_en_n(hdataout_en_n), + .hready_n(hready_n), + .cpu_if_gbit_en(cpu_if_gbit_en), + + // Output signals from the MII Management Interface + + // Output signals from the Tx MAC FIFO Interface + .tx_macread(tx_macread), + .tx_discfrm(tx_discfrm), + .tx_staten(tx_staten), + .tx_statvec(tx_statvec), + .tx_done(tx_done), + + // Output signals from the Rx MAC FIFO Interface + .rx_fifo_error(rx_fifo_error), + .rx_stat_vector(rx_stat_vector), + .rx_dbout(rx_dbout), + .rx_write(rx_write), + .rx_stat_en(rx_stat_en), + .rx_eof(rx_eof), + .rx_error(rx_error) + ); +endmodule