From: hadaq Date: Sun, 8 Apr 2012 17:48:59 +0000 (+0000) Subject: bugs fixed X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b421137635293e02676c4defd2df55b854761f23;p=ctsaddon.git bugs fixed --- diff --git a/cts_beam_structure.vhd b/cts_beam_structure.vhd index d69336f..fafd96f 100644 --- a/cts_beam_structure.vhd +++ b/cts_beam_structure.vhd @@ -15,13 +15,13 @@ entity cts_beam_structure is ); port ( RESET : in std_logic; - TRIGGER_CLK : in std_logic; --200MHz - LOCAL_CLK : in std_logic; --100MHz - START_TIME_OFFSET_IN : in std_logic_vector(31 downto 0); - START_TIME_SAMPLE_IN : in std_logic_vector(31 downto 0); - START_BEAM_IN : in std_logic; - BEAM_INHIBIT_LENGTH_IN : in std_logic_vector(31 downto 0); - BEAM_INHIBIT_OUT : out std_logic; + TRIGGER_CLK : in std_logic; --200MHz + LOCAL_CLK : in std_logic; --100MHz + START_TIME_OFFSET_IN : in std_logic_vector(31 downto 0); + START_TIME_SAMPLE_IN : in std_logic_vector(31 downto 0); + START_BEAM_IN : in std_logic; + BEAM_INHIBIT_LENGTH_IN : in std_logic_vector(31 downto 0); + BEAM_INHIBIT_OUT : out std_logic; BEAM_STRUCTURE_SIGNAL_IN : in std_logic_vector(1 downto 0); BEAM_START_VETO_STRUCKTURE_IN : in std_logic_vector(25 downto 0); STRUCTURE_DATA_OUT : out std_logic_vector(31 downto 0); diff --git a/cts_components.vhd b/cts_components.vhd index 0c6d380..c9bea05 100644 --- a/cts_components.vhd +++ b/cts_components.vhd @@ -59,6 +59,7 @@ package cts_components is LVDS_TIMING_OUT : out std_logic_vector(12 downto 0); PECL_TIMING_OUT : out std_logic_vector(2 downto 0); START_VETO_STRUCTURE_OUT : out std_logic_vector(23 downto 0); + HIST_DISABLE_IN : in std_logic_vector(39 downto 0); TRIG_CNTRL_IN : in std_logic_vector(7 downto 0); TRIG_STAT_OUT : out std_logic_vector(7 downto 0) ); diff --git a/cts_delay_large.vhd b/cts_delay_large.vhd index 08b4e5b..b93112f 100644 --- a/cts_delay_large.vhd +++ b/cts_delay_large.vhd @@ -111,11 +111,17 @@ begin if rising_edge(CLK) then if RESET = '1' or reset_fifo = '1' then rden <= '0'; - elsif (wcnt < DELAY_IN -1) and DELAY_IN > 0 then +-- elsif (wcnt < DELAY_IN -1) and DELAY_IN > 0 then +-- rden <= '0'; +-- else +-- rden <= '1'; +-- end if; + elsif (wcnt < DELAY_IN) then rden <= '0'; else rden <= '1'; end if; + end if; end process COUNT_FOR_DELAY; diff --git a/cts_fpga1.vhd b/cts_fpga1.vhd index a05ff4f..5445784 100644 --- a/cts_fpga1.vhd +++ b/cts_fpga1.vhd @@ -483,17 +483,17 @@ begin RS2 <= (others => 'Z'); - TEST_LINE(31) <= clk_100; - TEST_LINE(30) <= lvl2_trbnet_busy_in_i; - TEST_LINE(29) <= lvl1_trbnet_busy_in_i; - TEST_LINE(28) <= ipu_data_out_i(31); - TEST_LINE(27) <= ipu_dataready_out_i; - TEST_LINE(26) <= lvl1_trigger_out_i; - TEST_LINE(25) <= lvl1_triggbox_busy_in_i; - TEST_LINE(24) <= lvl1_triggbox_busy_out_i; - TEST_LINE(23 downto 20) <= lvl1_triggbox_code_out_i; - TEST_LINE(19 downto 16) <= r_register_i(0)(23 downto 20); - TEST_LINE(15) <= reset_i_100; +-- TEST_LINE(31) <= clk_100; +-- TEST_LINE(30) <= lvl2_trbnet_busy_in_i; +-- TEST_LINE(29) <= lvl1_trbnet_busy_in_i; +-- TEST_LINE(28) <= ipu_data_out_i(31); +-- TEST_LINE(27) <= ipu_dataready_out_i; +-- TEST_LINE(26) <= lvl1_trigger_out_i; +-- TEST_LINE(25) <= lvl1_triggbox_busy_in_i; +-- TEST_LINE(24) <= lvl1_triggbox_busy_out_i; +-- TEST_LINE(23 downto 20) <= lvl1_triggbox_code_out_i; +-- TEST_LINE(19 downto 16) <= r_register_i(0)(23 downto 20); +-- TEST_LINE(15) <= reset_i_100; ------------------------------------------------------------------------------- @@ -558,6 +558,8 @@ begin LVDS_TIMING_OUT(12 downto 12) => RICH_TIMING_OUT, PECL_TIMING_OUT => PECL_OUT, START_VETO_STRUCTURE_OUT => start_veto_beam_structure_buf, + HIST_DISABLE_IN(31 downto 0) => rw_register_i(23), + HIST_DISABLE_IN(39 downto 32) => rw_register_i(24)(7 downto 0), TRIG_CNTRL_IN => rw_register_i(26)(7 downto 0), TRIG_STAT_OUT => r_register_i(2)(31 downto 24) ); @@ -947,7 +949,7 @@ begin rw_register_i(i-1) <= rw_register_vector(32*i-1 downto 32*(i-1)); end generate REWRITE_RW_REGISTER; - LED_GREEN <= '1'; + LED_GREEN <= '0'; LED_ORANGE <= '0'; LED_RED <= '1'; LED_YELLOW <= '0'; @@ -963,7 +965,7 @@ begin THE_CTS_BEAM_STRUCTURE: cts_beam_structure generic map ( START_SAMPLE_NUMBER => 500, - HOW_MANY_HISTOGRAMS => 25) + HOW_MANY_HISTOGRAMS => 26) port map ( RESET => reset_i_100, TRIGGER_CLK => clk_200,--CLK_200_IN, diff --git a/cts_fpga1_tb.vhd b/cts_fpga1_tb.vhd index cc6c2a1..06b47fc 100644 --- a/cts_fpga1_tb.vhd +++ b/cts_fpga1_tb.vhd @@ -427,7 +427,10 @@ BEGIN DIS1 => DIS1, DIS2 => DIS2, TEST_LINE => TEST_LINE); - + + RS1 <= (others => '1'); + RS2 <= (others => '1'); + cts_fpga2_1: cts_fpga2 port map ( CLK_100_IN => FPGA2_CLK_100_IN, diff --git a/cts_fpga2_reg_interface.vhd b/cts_fpga2_reg_interface.vhd index 6e75a30..08cb628 100644 --- a/cts_fpga2_reg_interface.vhd +++ b/cts_fpga2_reg_interface.vhd @@ -351,6 +351,12 @@ begin when x"B" => mem_saved_address(15 downto 12) <= x"1"; mem_saved_address(11 downto 0) <= saved_address(11 downto 0); + when x"C" => + mem_saved_address(15 downto 12) <= x"2"; + mem_saved_address(11 downto 0) <= saved_address(11 downto 0); + when x"D" => + mem_saved_address(15 downto 12) <= x"3"; + mem_saved_address(11 downto 0) <= saved_address(11 downto 0); when others => mem_saved_address(15 downto 12) <= x"0"; mem_saved_address(11 downto 0) <= saved_address(11 downto 0); diff --git a/cts_set_width_large.vhd b/cts_set_width_large.vhd index f6f6f75..b1a19fc 100644 --- a/cts_set_width_large.vhd +++ b/cts_set_width_large.vhd @@ -39,22 +39,35 @@ begin -- cts_set_width end if; end process SAVE_OLD_PULSE; - CHECK_FALLING_EDGE : process (CLK, RESET) +-- CHECK_FALLING_EDGE : process (CLK, RESET) +-- begin +-- if rising_edge(CLK) then +-- if RESET = '1' then +-- detected_falling_edge <= '0'; +-- elsif +-- (SIGNAL_IN(0) = '0' and there_was_signal = '1') or +-- (SIGNAL_IN(1) = '0' and SIGNAL_IN(0) = '1') or +-- (SIGNAL_IN(2) = '0' and SIGNAL_IN(1) = '1') or +-- (SIGNAL_IN(3) = '0' and SIGNAL_IN(2) = '1') then +-- detected_falling_edge <= '1'; +-- else +-- detected_falling_edge <= '0'; +-- end if; +-- end if; +-- end process CHECK_FALLING_EDGE; + + CHECK_PULSE : process (CLK, RESET) begin if rising_edge(CLK) then if RESET = '1' then detected_falling_edge <= '0'; - elsif - (SIGNAL_IN(0) = '0' and there_was_signal = '1') or - (SIGNAL_IN(1) = '0' and SIGNAL_IN(0) = '1') or - (SIGNAL_IN(2) = '0' and SIGNAL_IN(1) = '1') or - (SIGNAL_IN(3) = '0' and SIGNAL_IN(2) = '1') then + elsif SIGNAL_IN > 0 then detected_falling_edge <= '1'; else detected_falling_edge <= '0'; - end if; + end if; end if; - end process CHECK_FALLING_EDGE; + end process CHECK_PULSE; VECTOR_IN_WIDTH4 : if VECTOR_WIDTH = 4 generate CREATE_EDGES : process (CLK, RESET) @@ -62,9 +75,9 @@ begin -- cts_set_width if rising_edge(CLK) then if detected_falling_edge = '1' then case signal_in_sync_a(3 downto 0) is - when x"0" => --falling edge in previous word - leading_edge <= x"8"; - trailing_edge <= x"f"; +-- when x"0" => --falling edge in previous word +-- leading_edge <= x"8"; +-- trailing_edge <= x"f"; --first bit when x"1" => @@ -77,23 +90,23 @@ begin -- cts_set_width leading_edge <= x"e"; trailing_edge <= x"3"; - when x"3" => - leading_edge <= x"f"; - trailing_edge <= x"3"; +-- when x"3" => +-- leading_edge <= x"f"; +-- trailing_edge <= x"3"; - --3rd bit +-- --3rd bit when x"4" => leading_edge <= x"c"; trailing_edge <= x"7"; - when x"6" => - leading_edge <= x"e"; - trailing_edge <= x"7"; +-- when x"6" => +-- leading_edge <= x"e"; +-- trailing_edge <= x"7"; - when x"7" => - leading_edge <= x"f"; - trailing_edge <= x"7"; +-- when x"7" => +-- leading_edge <= x"f"; +-- trailing_edge <= x"7"; --4th @@ -101,17 +114,17 @@ begin -- cts_set_width leading_edge <= x"8"; trailing_edge <= x"f"; - when x"c" => - leading_edge <= x"c"; - trailing_edge <= x"f"; +-- when x"c" => +-- leading_edge <= x"c"; +-- trailing_edge <= x"f"; - when x"e" => - leading_edge <= x"e"; - trailing_edge <= x"f"; +-- when x"e" => +-- leading_edge <= x"e"; +-- trailing_edge <= x"f"; - when x"f" => - leading_edge <= x"f"; - trailing_edge <= x"f"; +-- when x"f" => +-- leading_edge <= x"f"; +-- trailing_edge <= x"f"; when others => leading_edge <= x"f"; diff --git a/cts_simulation_tb.mpf b/cts_simulation_tb.mpf index 79004bf..2c673a2 100644 --- a/cts_simulation_tb.mpf +++ b/cts_simulation_tb.mpf @@ -583,7 +583,7 @@ Resolution = ns UserTimeUnit = default ; Default run length -RunLength = 330 us +RunLength = 400 us ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 @@ -1548,26 +1548,26 @@ Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 144 -Project_File_0 = /home/marek/trbnet/basics/ram.vhd -Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 58 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_0 = /home/marek/trbv2/up_down_counter.vhd +Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249045055 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 116 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_1 = /home/marek/trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1228404858 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 74 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_2 = /home/marek/trbv2/up_down_counter.vhd -Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249045055 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 116 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_3 = /home/marek/ctsaddon/simulation/cts_readout_data_buff.vhd -Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_4 = /home/marek/ctsaddon/simulation/cts_simple_data_transport.vhd -Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 39 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_5 = /home/marek/trbnet/basics/ram_16x8_dp.vhd -Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 59 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_6 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd -Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277134650 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 80 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_7 = /home/marek/ctsaddon/simulation/cts_cal_screset_gen.vhd -Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_2 = /home/marek/trbnet/basics/ram.vhd +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 58 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_3 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277134650 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 80 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_4 = /home/marek/trbnet/basics/ram_16x8_dp.vhd +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 59 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_5 = /home/marek/ctsaddon/simulation/cts_simple_data_transport.vhd +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 39 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_6 = /home/marek/ctsaddon/simulation/cts_readout_data_buff.vhd +Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_7 = /home/marek/trbnet/special/spi_master.vhd +Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1286546951 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 112 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_8 = /home/marek/trbnet/trb_net_priority_arbiter.vhd Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 94 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_9 = /home/marek/trbnet/special/spi_master.vhd -Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1286546951 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 112 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_9 = /home/marek/ctsaddon/simulation/cts_cal_screset_gen.vhd +Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_10 = /home/marek/ctsaddon/simulation/ram_register.vhd Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_11 = /home/marek/trbnet/lattice/ecp2m/trb_net_clock_generator.vhd @@ -1579,7 +1579,7 @@ Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 Project_File_14 = /home/marek/trbnet/trb_net_sbuf6.vhd Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 97 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_15 = /home/marek/ctsaddon/simulation/cts_fpga2_reg_interface.vhd -Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331894152 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 35 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332007582 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 35 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_16 = /home/marek/ctsaddon/simulation/delay.vhd Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331907215 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 138 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_17 = /home/marek/trbnet/special/handler_trigger_and_data.vhd @@ -1619,7 +1619,7 @@ Project_File_P_33 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 Project_File_34 = /home/marek/ctsaddon/simulation/cts_fpga2_to_fpga1.vhd Project_File_P_34 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 36 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_35 = /home/marek/ctsaddon/simulation/cts_fpga2.vhd -Project_File_P_35 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 123 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_35 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 123 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_36 = /home/marek/ctsaddon/simulation/cts_eb_ip_switch.vhd Project_File_P_36 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 31 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_37 = /home/marek/ctsaddon/simulation/cts_witdh_rom_simulation.vhd @@ -1639,203 +1639,203 @@ Project_File_P_43 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 Project_File_44 = /home/marek/trbnet/trb_net16_ibuf.vhd Project_File_P_44 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 101 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_45 = /home/marek/ctsaddon/simulation/trb_net16_med_ecp_sfp_gbe.vhd -Project_File_P_45 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 117 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_45 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 117 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_46 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x256_oreg.vhd Project_File_P_46 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 78 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_47 = /home/marek/ctsaddon/simulation/cts_beam_structure.vhd Project_File_P_47 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325766507 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 134 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_48 = /home/marek/ctsaddon/simulation/cts_fpga2_trig_gen.vhd -Project_File_P_48 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 37 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_49 = /home/marek/trbnet/trb_net16_ipudata.vhd -Project_File_P_49 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760358 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 52 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_50 = /home/marek/ctsaddon/simulation/ddr2_busses.vhd -Project_File_P_50 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 133 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_51 = /home/marek/trbnet/trb_net_CRC.vhd -Project_File_P_51 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1235046634 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 91 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_48 = /home/marek/trbnet/trb_net16_ipudata.vhd +Project_File_P_48 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760358 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 52 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_49 = /home/marek/ctsaddon/simulation/cts_fpga2_trig_gen.vhd +Project_File_P_49 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 37 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_50 = /home/marek/trbnet/trb_net_CRC.vhd +Project_File_P_50 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1235046634 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 91 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_51 = /home/marek/ctsaddon/simulation/ddr2_busses.vhd +Project_File_P_51 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 133 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_52 = /home/marek/trbnet/trb_net16_io_multiplexer.vhd Project_File_P_52 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285861828 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 102 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_53 = /home/marek/ctsaddon/simulation/cts_delay_large.vhd -Project_File_P_53 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 25 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_54 = /home/marek/ctsaddon/simulation/cts_polarity_check.vhd -Project_File_P_54 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 38 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_53 = /home/marek/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd +Project_File_P_53 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 71 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_54 = /home/marek/ctsaddon/simulation/delay_fifo.vhd +Project_File_P_54 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_55 = /home/marek/ctsaddon/simulation/ddr2_3out_clkdiv.vhd Project_File_P_55 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_56 = /home/marek/ctsaddon/simulation/delay_fifo.vhd -Project_File_P_56 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_57 = /home/marek/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd -Project_File_P_57 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 71 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_58 = /home/marek/ctsaddon/simulation/pll_in200_out400.vhd -Project_File_P_58 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672874 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_56 = /home/marek/ctsaddon/simulation/cts_polarity_check.vhd +Project_File_P_56 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 38 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_57 = /home/marek/ctsaddon/simulation/cts_delay_large.vhd +Project_File_P_57 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332007582 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 25 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_58 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd +Project_File_P_58 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1275387240 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 77 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_59 = /home/marek/trbnet/trb_net16_api_base.vhd Project_File_P_59 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 98 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_60 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd -Project_File_P_60 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1275387240 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 77 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_60 = /home/marek/ctsaddon/simulation/pll_in200_out400.vhd +Project_File_P_60 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672874 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_61 = /home/marek/ctsaddon/simulation/cts_fpga2_reg_mem.vhd Project_File_P_61 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 40 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_62 = /home/marek/ctsaddon/simulation/cts_readout.vhd -Project_File_P_62 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331894152 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_62 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd +Project_File_P_62 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 75 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_63 = /home/marek/trbnet/trb_net16_endpoint_hades_cts.vhd Project_File_P_63 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321875836 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 130 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_64 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd -Project_File_P_64 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 75 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_65 = /home/marek/ctsaddon/simulation/cts_set_width_large.vhd -Project_File_P_65 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 27 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_66 = /home/marek/trbnet/trb_net_onewire_listener.vhd -Project_File_P_66 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872784 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 126 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_67 = /home/marek/trbnet/trb_net16_dummy_fifo.vhd -Project_File_P_67 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600670 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 51 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_68 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd -Project_File_P_68 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248958666 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 122 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_69 = /home/marek/ctsaddon/simulation/cts_components.vhd -Project_File_P_69 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672874 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_70 = /home/marek/ctsaddon/simulation/dll_in400_out200.vhd -Project_File_P_70 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672874 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_71 = /home/marek/ctsaddon/simulation/ecp2m_lvl2_trigger_buffer_fifo_1kW.vhd -Project_File_P_71 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 41 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_72 = /home/marek/trbnet/trb_net_pattern_gen.vhd -Project_File_P_72 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1214858855 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 93 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_73 = /home/marek/ctsaddon/simulation/beam_structure_fifo.vhd -Project_File_P_73 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_74 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl2.vhd -Project_File_P_74 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 34 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_64 = /home/marek/ctsaddon/simulation/cts_readout.vhd +Project_File_P_64 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332007582 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_65 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd +Project_File_P_65 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248958666 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 122 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_66 = /home/marek/trbnet/trb_net16_dummy_fifo.vhd +Project_File_P_66 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600670 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 51 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_67 = /home/marek/trbnet/trb_net_onewire_listener.vhd +Project_File_P_67 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872784 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 126 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_68 = /home/marek/ctsaddon/simulation/cts_set_width_large.vhd +Project_File_P_68 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 27 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_69 = /home/marek/trbnet/trb_net_pattern_gen.vhd +Project_File_P_69 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1214858855 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 93 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_70 = /home/marek/ctsaddon/simulation/ecp2m_lvl2_trigger_buffer_fifo_1kW.vhd +Project_File_P_70 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 41 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_71 = /home/marek/ctsaddon/simulation/dll_in400_out200.vhd +Project_File_P_71 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672874 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_72 = /home/marek/ctsaddon/simulation/cts_components.vhd +Project_File_P_72 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672874 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_73 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd +Project_File_P_73 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760376 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 83 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_74 = /home/marek/trbnet/special/trb_net_reset_handler.vhd +Project_File_P_74 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280937906 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 65 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_75 = /home/marek/ctsaddon/simulation/fifo_1bit_to_32bit.vhd Project_File_P_75 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 42 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_76 = /home/marek/trbnet/special/trb_net_reset_handler.vhd -Project_File_P_76 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280937906 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 65 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_77 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd -Project_File_P_77 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760376 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 83 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_78 = /home/marek/ctsaddon/simulation/fifo_2bit_to_32bit.vhd -Project_File_P_78 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 43 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_76 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl2.vhd +Project_File_P_76 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 34 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_77 = /home/marek/ctsaddon/simulation/beam_structure_fifo.vhd +Project_File_P_77 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_78 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd +Project_File_P_78 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 70 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_79 = /home/marek/trbnet/trb_net_onewire.vhd Project_File_P_79 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872769 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 125 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_80 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd -Project_File_P_80 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 70 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_81 = /home/marek/ctsaddon/simulation/scm_fifo_1bit_to_32bit.vhd -Project_File_P_81 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_80 = /home/marek/ctsaddon/simulation/fifo_2bit_to_32bit.vhd +Project_File_P_80 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 43 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_81 = /home/marek/trbv2/etrax_write_read_tb.vhd +Project_File_P_81 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321461742 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 118 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_82 = /home/marek/trbnet/basics/ram_dp.vhd Project_File_P_82 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 61 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_83 = /home/marek/trbv2/etrax_write_read_tb.vhd -Project_File_P_83 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321461742 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 118 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_84 = /home/marek/ctsaddon/simulation/ddr_lvl1_trigger.vhd -Project_File_P_84 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331894152 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 28 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_85 = /home/marek/ctsaddon/simulation/fifo_4bit_to_32bit.vhd -Project_File_P_85 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 44 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_83 = /home/marek/ctsaddon/simulation/scm_fifo_1bit_to_32bit.vhd +Project_File_P_83 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_84 = /home/marek/ctsaddon/cts_fpga1_test.vhd +Project_File_P_84 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672862 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 136 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_85 = /home/marek/trbnet/trb_net16_regio_bus_handler.vhd +Project_File_P_85 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 106 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_86 = /home/marek/ctsaddon/simulation/scm_fifo_2bit_to_32bit.vhd Project_File_P_86 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 20 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_87 = /home/marek/trbnet/trb_net16_regio_bus_handler.vhd -Project_File_P_87 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 106 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_88 = /home/marek/ctsaddon/cts_fpga1_test.vhd -Project_File_P_88 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672862 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 136 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_87 = /home/marek/ctsaddon/simulation/fifo_4bit_to_32bit.vhd +Project_File_P_87 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 44 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_88 = /home/marek/ctsaddon/simulation/ddr_lvl1_trigger.vhd +Project_File_P_88 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331894152 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 28 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_89 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x8k_oreg.vhd Project_File_P_89 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760377 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 84 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_90 = /home/marek/ctsaddon/simulation/scm_fifo_4bit_to_32bit.vhd -Project_File_P_90 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_91 = /home/marek/trbnet/trb_net_sbuf5.vhd -Project_File_P_91 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 48 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_92 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd -Project_File_P_92 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1282206842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 68 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_93 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd -Project_File_P_93 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249891632 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 121 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_94 = /home/marek/ctsaddon/simulation/fifo16bit_synch.vhd -Project_File_P_94 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_95 = /home/marek/ctsaddon/simulation/version.vhd -Project_File_P_95 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331921178 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_90 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd +Project_File_P_90 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249891632 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 121 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_91 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd +Project_File_P_91 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1282206842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 68 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_92 = /home/marek/trbnet/trb_net_sbuf5.vhd +Project_File_P_92 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 48 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_93 = /home/marek/ctsaddon/simulation/scm_fifo_4bit_to_32bit.vhd +Project_File_P_93 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_94 = /home/marek/trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd +Project_File_P_94 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1267800223 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 114 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_95 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd +Project_File_P_95 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 87 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_96 = /home/marek/trbnet/special/handler_ipu.vhd Project_File_P_96 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304089906 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 108 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_97 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd -Project_File_P_97 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 87 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_98 = /home/marek/trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd -Project_File_P_98 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1267800223 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 114 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_99 = /home/marek/ctsaddon/simulation/fifo_8bit_to_32bit.vhd -Project_File_P_99 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 45 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_100 = /home/marek/ctsaddon/ddr2_13out_clkdiv.vhd -Project_File_P_100 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329503926 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 140 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_97 = /home/marek/ctsaddon/simulation/version.vhd +Project_File_P_97 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332007582 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_98 = /home/marek/ctsaddon/simulation/fifo16bit_synch.vhd +Project_File_P_98 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_99 = /home/marek/ctsaddon/ddr2_13out_clkdiv.vhd +Project_File_P_99 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329503926 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 140 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_100 = /home/marek/ctsaddon/simulation/fifo_8bit_to_32bit.vhd +Project_File_P_100 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 45 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_101 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_8b_16b_dualport.vhd Project_File_P_101 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1278661530 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 69 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_102 = /home/marek/ctsaddon/simulation/cts_downscale.vhd -Project_File_P_102 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 30 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_103 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_lvl2_fifo.vhd -Project_File_P_103 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 47 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_104 = /home/marek/ctsaddon/simulation/scm_fifo_8bit_to_32bit.vhd -Project_File_P_104 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_105 = /home/marek/trbnet/trb_net_priority_encoder.vhd -Project_File_P_105 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1203091968 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 95 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_106 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd -Project_File_P_106 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760373 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 86 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_107 = /home/marek/ctsaddon/simulation/cts_fpga1_test_set_width.vhd -Project_File_P_107 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 124 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_102 = /home/marek/ctsaddon/simulation/cts_fpga1_test_set_width.vhd +Project_File_P_102 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 124 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_103 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd +Project_File_P_103 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760373 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 86 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_104 = /home/marek/trbnet/trb_net_priority_encoder.vhd +Project_File_P_104 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1203091968 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 95 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_105 = /home/marek/ctsaddon/simulation/scm_fifo_8bit_to_32bit.vhd +Project_File_P_105 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_106 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_lvl2_fifo.vhd +Project_File_P_106 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 47 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_107 = /home/marek/ctsaddon/simulation/cts_downscale.vhd +Project_File_P_107 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 30 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_108 = /home/marek/trbnet/trb_net16_obuf.vhd Project_File_P_108 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1302529528 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 104 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_109 = /home/marek/ctsaddon/simulation/cts_align_signals.vhd -Project_File_P_109 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 29 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_110 = /home/marek/trbnet/trb_net16_term_ibuf.vhd -Project_File_P_110 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 56 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_111 = /home/marek/ctsaddon/simulation/cts_fpga1_tb.vhd -Project_File_P_111 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689502 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 135 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_112 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd -Project_File_P_112 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 81 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_109 = /home/marek/trbnet/trb_net16_term_ibuf.vhd +Project_File_P_109 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 56 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_110 = /home/marek/ctsaddon/simulation/cts_align_signals.vhd +Project_File_P_110 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 29 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_111 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd +Project_File_P_111 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 81 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_112 = /home/marek/ctsaddon/simulation/cts_fpga1_tb.vhd +Project_File_P_112 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689502 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 135 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_113 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd Project_File_P_113 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 76 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_114 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_data_downscale.vhd -Project_File_P_114 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 33 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_114 = /home/marek/trbnet/basics/ram_16x16_dp.vhd +Project_File_P_114 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1291756328 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 60 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_115 = /home/marek/ctsaddon/simulation/etrax_reg_mem.vhd Project_File_P_115 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_116 = /home/marek/trbnet/basics/ram_16x16_dp.vhd -Project_File_P_116 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1291756328 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 60 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_117 = /home/marek/ctsaddon/simulation/cts_fpga1.vhd -Project_File_P_117 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 137 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_116 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_data_downscale.vhd +Project_File_P_116 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 33 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_117 = /home/marek/ctsaddon/simulation/trb_net16_lsm_sfp.vhd +Project_File_P_117 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 89 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_118 = /home/marek/ctsaddon/simulation/dll_edge.vhd Project_File_P_118 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_119 = /home/marek/ctsaddon/simulation/trb_net16_lsm_sfp.vhd -Project_File_P_119 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 89 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_120 = /home/marek/ctsaddon/simulation/multiplicity.vhd -Project_File_P_120 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331919062 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 143 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_121 = /home/marek/trbnet/basics/signal_sync.vhd -Project_File_P_121 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1253527273 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 64 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_122 = /home/marek/ctsaddon/simulation/cts_trigger_logic.vhd -Project_File_P_122 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923063 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_119 = /home/marek/ctsaddon/simulation/cts_fpga1.vhd +Project_File_P_119 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 137 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_120 = /home/marek/trbnet/basics/signal_sync.vhd +Project_File_P_120 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1253527273 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 64 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_121 = /home/marek/ctsaddon/simulation/multiplicity.vhd +Project_File_P_121 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 143 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_122 = /home/marek/trbnet/basics/ram_dp_rw.vhd +Project_File_P_122 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 62 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_123 = /home/marek/ctsaddon/simulation/ddr2_12out_clkdiv.vhd Project_File_P_123 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_124 = /home/marek/trbnet/basics/ram_dp_rw.vhd -Project_File_P_124 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 62 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_125 = /home/marek/ctsaddon/simulation/trb_net_components.vhd -Project_File_P_125 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 90 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_124 = /home/marek/ctsaddon/simulation/cts_trigger_logic.vhd +Project_File_P_124 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008208 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_125 = /home/marek/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd +Project_File_P_125 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 72 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_126 = /home/marek/trbnet/trb_net16_trigger.vhd Project_File_P_126 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 57 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_127 = /home/marek/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd -Project_File_P_127 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 72 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_127 = /home/marek/ctsaddon/simulation/trb_net_components.vhd +Project_File_P_127 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 90 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_128 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd Project_File_P_128 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600671 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 120 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_129 = /home/marek/trbnet/lattice/ecp2m/pll_in100_out100.vhd Project_File_P_129 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292102 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 119 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_130 = /home/marek/ctsaddon/simulation/cts_one_clock.vhd -Project_File_P_130 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 26 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_131 = /home/marek/trbnet/trb_net16_endpoint_hades_full.vhd -Project_File_P_131 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 99 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_130 = /home/marek/trbnet/trb_net16_endpoint_hades_full.vhd +Project_File_P_130 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 99 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_131 = /home/marek/ctsaddon/simulation/cts_one_clock.vhd +Project_File_P_131 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 26 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_132 = /home/marek/ctsaddon/simulation/cts_delay.vhd Project_File_P_132 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 24 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_133 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd -Project_File_P_133 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 79 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_134 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd -Project_File_P_134 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1271868444 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 113 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_133 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd +Project_File_P_133 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1271868444 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 113 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_134 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd +Project_File_P_134 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 79 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_135 = /home/marek/trbnet/special/handler_data.vhd Project_File_P_135 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304328663 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 128 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_136 = /home/marek/trbnet/trb_net_std.vhd -Project_File_P_136 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 49 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_136 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd +Project_File_P_136 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760366 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 85 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_137 = /home/marek/trbnet/basics/rom_16x8.vhd Project_File_P_137 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 63 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_138 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd -Project_File_P_138 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760366 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 85 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_138 = /home/marek/trbnet/trb_net_std.vhd +Project_File_P_138 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 49 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_139 = /home/marek/ctsaddon/simulation/cts_set_width.vhd -Project_File_P_139 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331923078 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 132 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_139 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 132 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_140 = /home/marek/trbnet/trb_net16_addresses.vhd Project_File_P_140 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1266500256 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 50 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_141 = /home/marek/ctsaddon/simulation/fifo_16bit_to_32bit.vhd -Project_File_P_141 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 46 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_141 = /home/marek/ctsaddon/cts_polarity_check.vhd +Project_File_P_141 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453598 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 139 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_142 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd Project_File_P_142 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 82 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_143 = /home/marek/ctsaddon/cts_polarity_check.vhd -Project_File_P_143 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453598 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 139 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_143 = /home/marek/ctsaddon/simulation/fifo_16bit_to_32bit.vhd +Project_File_P_143 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 46 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 diff --git a/cts_trigger_logic.vhd b/cts_trigger_logic.vhd index e7494b8..039a079 100755 --- a/cts_trigger_logic.vhd +++ b/cts_trigger_logic.vhd @@ -497,7 +497,8 @@ architecture cts_trigger_logic of cts_trigger_logic is signal lvl1_busy_end_fsm : std_logic; signal lvl1_trigger_debug_fsm : std_logic_vector(3 downto 0); signal lvl1_trigger,lvl1_trigger_pulse : std_logic; - signal lvl1_busy : std_logic; + signal lvl1_busy : std_logic; + signal not_lvl1_busy, lvl1_busy_finished, disable_accepetd_triggers : std_logic; signal data_valid : std_logic; signal data_out_i : std_logic_vector(31 downto 0); signal lvl1_busy_end : std_logic; @@ -1012,6 +1013,7 @@ begin ENABLE_IN => '1', ONE_CLOCK_VECTOR_IN => tof_rpc_or, ONE_CLOCK_VECTOR_OUT => multiplicity_out_array); + mult_array_signal_delay <= x"0" & TRIGGER_LOGIC_CTRL_IN_1(3 downto 0); SET_DELAY_FOR_MULT_ARRAY : process (CLK, RESET) @@ -1020,7 +1022,7 @@ begin if RESET = '1' then mult_array_signal_delay_conv <= x"01"; else - mult_array_signal_delay_conv <= mult_array_signal_delay + 5; + mult_array_signal_delay_conv <= mult_array_signal_delay + 4; end if; end if; end process SET_DELAY_FOR_MULT_ARRAY; @@ -1287,9 +1289,11 @@ begin ANTICOINCIDENCE_SIGNALS_CLOCK : process (CLK, RESET) begin if rising_edge(CLK) then - if TRIGGER_LOGIC_CTRL_IN_0(16) = '0' then - -- start_veto_anticoincidence_array <= start_downscaled_in_delayed and (not veto_width_out_delayed); - start_veto_anticoincidence_array <= pti_downscaled_in_array(0) and (not veto_width_out_delayed); + if TRIGGER_LOGIC_CTRL_IN_0(17 downto 16) = 0 then + start_veto_anticoincidence_array <= pti_downscaled_in_array(0); +-- start_veto_anticoincidence_array <= start_downscaled_in_delayed and (not veto_width_out_delayed); + elsif TRIGGER_LOGIC_CTRL_IN_0(17 downto 16) = 1 then + start_veto_anticoincidence_array <= pti_downscaled_in_array(0) and (not veto_width_out_delayed); else start_veto_anticoincidence_array <= multiplicity_out_array; end if; @@ -1439,6 +1443,39 @@ begin ----------------------------------------------------------------------------- -- scalers after accepting 19 ----------------------------------------------------------------------------- + SYNCH_NOT_BUSY : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + not_lvl1_busy <= '0'; + else + not_lvl1_busy <= not lvl1_busy; + end if; + end if; + end process SYNCH_NOT_BUSY; + + + MAKE_BUSY_END_PULSE : edge_to_pulse + port map ( + clock => CLK, + en_clk => '1', + signal_in => not_lvl1_busy,-- scalers_out_save_signal, + pulse => lvl1_busy_finished); + + SET_DISABLE_ACCEPTED_SCALERS : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' or lvl1_busy_finished = '1' then + disable_accepetd_triggers <= '0'; + elsif internal_trigger = '1' and out_inhibit = '0' and phys_trigger_out_local_busy= '0' then + disable_accepetd_triggers <= '1'; + else + disable_accepetd_triggers <= disable_accepetd_triggers; + end if; + end if; + end process SET_DISABLE_ACCEPTED_SCALERS; + + MAKE_OUT_SCALERS_SAVE_PULSE : edge_to_pulse port map ( clock => CLK, @@ -1452,10 +1489,11 @@ begin FAST_UPDATE_UP_SIGNAL_FOR_OUT_SCALERS : process (CLK) begin if rising_edge(CLK) then - if RESET = '1' or TRIGGER_LOGIC_CTRL_IN_2(27 downto 0) > 0 then +-- if RESET = '1' or TRIGGER_LOGIC_CTRL_IN_2(27 downto 0) > 0 then + if RESET = '1' or disable_accepetd_triggers = '1' then scalers_out_up(i) <= '0'; else - scalers_out_up(i) <= ( pti_and_gts_out_saved(i) and scalers_out_save_pulse and (not(internal_trigger)) ); + scalers_out_up(i) <= ( pti_and_gts_out_saved(i) and scalers_out_save_pulse ); end if; end if; end process FAST_UPDATE_UP_SIGNAL_FOR_OUT_SCALERS; @@ -1712,7 +1750,7 @@ begin if rising_edge(CLK) then multiplexer_address_a <= conv_integer(MULTIPLEXER_SELECT_IN(7 downto 0)); multiplexer_address_b <= conv_integer(MULTIPLEXER_SELECT_IN(15 downto 8)); - multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER) <= start_downscaled_in_delayed; + multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER) <= pti_downscaled_in_array(0);--start_downscaled_in_delayed; multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+1) <= veto_width_out_delayed; multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+2) <= start_veto_anticoincidence_array; multiplexer_array_out_a <= multiplexer_in_array_a(multiplexer_address_a); diff --git a/ddr2_busses.vhd b/ddr2_busses.vhd index 3b4d4fc..d75ca14 100644 --- a/ddr2_busses.vhd +++ b/ddr2_busses.vhd @@ -24,6 +24,7 @@ entity ddr2_busses is LVDS_TIMING_OUT : out std_logic_vector(12 downto 0); PECL_TIMING_OUT : out std_logic_vector(2 downto 0); START_VETO_STRUCTURE_OUT : out std_logic_vector(23 downto 0); + HIST_DISABLE_IN : in std_logic_vector(39 downto 0); TRIG_CNTRL_IN : in std_logic_vector(7 downto 0); TRIG_STAT_OUT : out std_logic_vector(7 downto 0) ); @@ -186,9 +187,22 @@ architecture ddr2_busses of ddr2_busses is signal pecl_trigger_tmp : std_logic_vector(11 downto 0); signal start_veto_beam_struct_signals : std_logic_vector(63 downto 0); + + signal hist_disable_in_i : std_logic_vector(39 downto 0); begin + + SYNCH_DISABLE_SIGNAL : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + hist_disable_in_i <= (others => '0'); + else + hist_disable_in_i <= HIST_DISABLE_IN; + end if; + end if; + end process SYNCH_DISABLE_SIGNAL; -- DDR2_32INPUTS_INST_FIRST: ddr2_32inputs --bank 2 and 3 of the FPGA -- port map ( -- Data => TRIG_IN(31 downto 0), @@ -257,19 +271,58 @@ begin -- 44:37 Physical triggers - --start in 16 out 3 x 8 (beam shifting by 4 due to the start detector damage) for triggering + --start in 16 out 3 x 8 (beam shifting by 4 due to the start detector damage) for triggering + + + +--start cable is mixed: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +-- 1 3 5 7 9 11 13 15 16 14 12 10 8 6 4 2 + + SELECT_START_SIGNALS_FOR_TRIGGER : process (CLK, RESET) --connector 1 and 2 begin if rising_edge(CLK) then case TRIG_CNTRL_IN(7 downto 6) is when b"00" => - TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(8*4-1 downto 0); +-- TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(8*4-1 downto 0); + TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(13*4-1 downto 12*4) & + output_from_fifo_sunch_a(4*4-1 downto 3*4) & + output_from_fifo_sunch_a(14*4-1 downto 13*4) & + output_from_fifo_sunch_a(3*4-1 downto 2*4) & + output_from_fifo_sunch_a(15*4-1 downto 14*4) & + output_from_fifo_sunch_a(2*4-1 downto 1*4) & + output_from_fifo_sunch_a(16*4-1 downto 15*4) & + output_from_fifo_sunch_a(1*4-1 downto 0); when b"01" => - TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(12*4-1 downto 4*4); +-- TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(12*4-1 downto 4*4); + TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(11*4-1 downto 10*4) & + output_from_fifo_sunch_a(6*4-1 downto 5*4) & + output_from_fifo_sunch_a(12*4-1 downto 11*4) & + output_from_fifo_sunch_a(5*4-1 downto 4*4) & + output_from_fifo_sunch_a(13*4-1 downto 12*4) & + output_from_fifo_sunch_a(4*4-1 downto 3*4) & + output_from_fifo_sunch_a(14*4-1 downto 13*4) & + output_from_fifo_sunch_a(3*4-1 downto 2*4); when b"10" => - TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(16*4-1 downto 8*4); +-- TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(16*4-1 downto 8*4); + TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(9*4-1 downto 8*4) & + output_from_fifo_sunch_a(8*4-1 downto 7*4) & + output_from_fifo_sunch_a(10*4-1 downto 9*4) & + output_from_fifo_sunch_a(7*4-1 downto 6*4) & + output_from_fifo_sunch_a(11*4-1 downto 10*4) & + output_from_fifo_sunch_a(6*4-1 downto 5*4) & + output_from_fifo_sunch_a(12*4-1 downto 11*4) & + output_from_fifo_sunch_a(5*4-1 downto 4*4); when others => - TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(8*4-1 downto 0); +-- TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(8*4-1 downto 0); + TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(13*4-1 downto 12*4) & + output_from_fifo_sunch_a(4*4-1 downto 3*4) & + output_from_fifo_sunch_a(14*4-1 downto 13*4) & + output_from_fifo_sunch_a(3*4-1 downto 2*4) & + output_from_fifo_sunch_a(15*4-1 downto 14*4) & + output_from_fifo_sunch_a(2*4-1 downto 1*4) & + output_from_fifo_sunch_a(16*4-1 downto 15*4) & + output_from_fifo_sunch_a(1*4-1 downto 0); end case; end if; end process SELECT_START_SIGNALS_FOR_TRIGGER; @@ -293,37 +346,119 @@ begin -- beam structure (pulses on rising edge made in the beam structure component) ----------------------------------------------------------------------------- SET_START_VETO_STRUCT_SIGNALS: for i in 0 to 39 generate - SET_HISTOGRAM_SIGNALS_PROC : process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - start_veto_beam_struct_signals(i) <= '0'; - elsif output_from_fifo_sunch_a((i+1)*4-1 downto i*4) /= x"f" then + START_IN: if i < 32 generate + SET_HISTOGRAM_SIGNALS_PROC_A : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' or hist_disable_in_i(i) = '1' then + start_veto_beam_struct_signals(i) <= '0'; + elsif output_from_fifo_sunch_a((i+1)*4-1 downto i*4) /= x"f" then --inverted start and veto inputs start_veto_beam_struct_signals(i) <= '1'; - else - start_veto_beam_struct_signals(i) <= '0'; + else + start_veto_beam_struct_signals(i) <= '0'; + end if; end if; - end if; - end process SET_HISTOGRAM_SIGNALS_PROC; + end process SET_HISTOGRAM_SIGNALS_PROC_A; + end generate START_IN; + + VETO_IN: if i > 31 generate + SET_HISTOGRAM_SIGNALS_PROC_A : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' or hist_disable_in_i(i) = '1' then + start_veto_beam_struct_signals(i) <= '0'; + elsif output_from_fifo_sunch_a((i+8+1)*4-1 downto (i+8)*4) /= x"f" then +--inverted start and veto inputs + start_veto_beam_struct_signals(i) <= '1'; + else + start_veto_beam_struct_signals(i) <= '0'; + end if; + end if; + end process SET_HISTOGRAM_SIGNALS_PROC_A; + end generate VETO_IN; + end generate SET_START_VETO_STRUCT_SIGNALS; + + + + SELECT_START_SIGNALS_A : process (CLK, RESET) begin if rising_edge(CLK) then case TRIG_CNTRL_IN(1 downto 0) is when b"00" => - START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(7 downto 0); +-- START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(7 downto 0); + START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(12) & + start_veto_beam_struct_signals(3) & + start_veto_beam_struct_signals(13) & + start_veto_beam_struct_signals(2) & + start_veto_beam_struct_signals(14) & + start_veto_beam_struct_signals(1) & + start_veto_beam_struct_signals(15) & + start_veto_beam_struct_signals(0); when b"01" => - START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(11 downto 4); +-- START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(11 downto 4); + START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(10) & + start_veto_beam_struct_signals(5) & + start_veto_beam_struct_signals(11) & + start_veto_beam_struct_signals(4) & + start_veto_beam_struct_signals(12) & + start_veto_beam_struct_signals(3) & + start_veto_beam_struct_signals(13) & + start_veto_beam_struct_signals(2); when b"10" => - START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(15 downto 8); +-- START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(15 downto 8); + START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(8) & + start_veto_beam_struct_signals(7) & + start_veto_beam_struct_signals(9) & + start_veto_beam_struct_signals(6) & + start_veto_beam_struct_signals(10) & + start_veto_beam_struct_signals(5) & + start_veto_beam_struct_signals(11) & + start_veto_beam_struct_signals(4); when others => - START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(7 downto 0); +-- START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(7 downto 0); + START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(12) & + start_veto_beam_struct_signals(3) & + start_veto_beam_struct_signals(13) & + start_veto_beam_struct_signals(2) & + start_veto_beam_struct_signals(14) & + start_veto_beam_struct_signals(1) & + start_veto_beam_struct_signals(15) & + start_veto_beam_struct_signals(0); end case; end if; end process SELECT_START_SIGNALS_A; +-- START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals((13+16)*4-1 downto (12+16)*4) & +-- start_veto_beam_struct_signals((4+16)*4-1 downto (3+16)*4) & +-- start_veto_beam_struct_signals((14+16)*4-1 downto (13+16)*4) & +-- start_veto_beam_struct_signals((3+16)*4-1 downto (2+16)*4) & +-- start_veto_beam_struct_signals((15+16)*4-1 downto (14+16)*4) & +-- start_veto_beam_struct_signals((2+16)*4-1 downto (1+16)*4) & +-- start_veto_beam_struct_signals((16+16)*4-1 downto (15+16)*4) & +-- start_veto_beam_struct_signals((1+16)*4-1 downto 16*4); + +-- START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals((11+16)*4-1 downto (10+16)*4) & +-- start_veto_beam_struct_signals((6+16)*4-1 downto (5+16)*4) & +-- start_veto_beam_struct_signals((12+16)*4-1 downto (11+16)*4) & +-- start_veto_beam_struct_signals((5+16)*4-1 downto (4+16)*4) & +-- start_veto_beam_struct_signals((13+16)*4-1 downto (12+16)*4) & +-- start_veto_beam_struct_signals((4+16)*4-1 downto (3+16)*4) & +-- start_veto_beam_struct_signals((14+16)*4-1 downto (13+16)*4) & +-- start_veto_beam_struct_signals((3+16)*4-1 downto (2+16)*4); + +-- START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals((9+16)*4-1 downto (8+16)*4) & +-- start_veto_beam_struct_signals((8+16)*4-1 downto (7+16)*4) & +-- start_veto_beam_struct_signals((10+16)*4-1 downto (9+16)*4) & +-- start_veto_beam_struct_signals((7+16)*4-1 downto (6+16)*4) & +-- start_veto_beam_struct_signals((11+16)*4-1 downto (10+16)*4) & +-- start_veto_beam_struct_signals((6+16)*4-1 downto (5+16)*4) & +-- start_veto_beam_struct_signals((12+16)*4-1 downto (11+16)*4) & +-- start_veto_beam_struct_signals((5+16)*4-1 downto (4+16)*4); + --this part is for histograming only - perpendicular stripes of the Start --detector. first 16 used for triggering and histograming next only histograming SELECT_START_SIGNALS_B : process (CLK, RESET) @@ -331,13 +466,45 @@ begin if rising_edge(CLK) then case TRIG_CNTRL_IN(3 downto 2) is when b"00" => - START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals(23 downto 16); + -- START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals(23 downto 16); + START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals(12+16) & + start_veto_beam_struct_signals((3+16)) & + start_veto_beam_struct_signals((13+16)) & + start_veto_beam_struct_signals((2+16)) & + start_veto_beam_struct_signals((14+16)) & + start_veto_beam_struct_signals((1+16)) & + start_veto_beam_struct_signals((15+16)) & + start_veto_beam_struct_signals(16); when b"01" => - START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals(27 downto 20); + -- START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals(27 downto 20); + START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals((10+16)) & + start_veto_beam_struct_signals((5+16)) & + start_veto_beam_struct_signals((11+16)) & + start_veto_beam_struct_signals((4+16)) & + start_veto_beam_struct_signals((12+16)) & + start_veto_beam_struct_signals((3+16)) & + start_veto_beam_struct_signals((13+16)) & + start_veto_beam_struct_signals((2+16)); when b"10" => - START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals(31 downto 24); + -- START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals(31 downto 24); + START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals((8+16)) & + start_veto_beam_struct_signals((7+16)) & + start_veto_beam_struct_signals((9+16)) & + start_veto_beam_struct_signals((6+16)) & + start_veto_beam_struct_signals((10+16)) & + start_veto_beam_struct_signals((5+16)) & + start_veto_beam_struct_signals((11+16)) & + start_veto_beam_struct_signals((4+16)); when others => - START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals(23 downto 16); + -- START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals(23 downto 16); + START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals(12+16) & + start_veto_beam_struct_signals((3+16)) & + start_veto_beam_struct_signals((13+16)) & + start_veto_beam_struct_signals((2+16)) & + start_veto_beam_struct_signals((14+16)) & + start_veto_beam_struct_signals((1+16)) & + start_veto_beam_struct_signals((15+16)) & + start_veto_beam_struct_signals(16); end case; end if; end process SELECT_START_SIGNALS_B; diff --git a/multiplicity.vhd b/multiplicity.vhd index 0e91003..cf6e3bc 100644 --- a/multiplicity.vhd +++ b/multiplicity.vhd @@ -69,8 +69,21 @@ begin pulse => sample_mult_signal_pulse(0) --20 ns after input has --changed(mult.is settled after 20ns) ); - - sample_delay_value <= x"0" & SAMPLE_DELAY_IN; +-- SET_CORR_DELAY : process (CLK, RESET) +-- begin +-- if rising_edge(CLK) then +-- if RESET = '1' then +-- sample_delay_value <= x"00"; +-- elsif SAMPLE_DELAY_IN > 0 then +-- sample_delay_value <= (x"0"&SAMPLE_DELAY_IN) + 1; +-- else +-- sample_delay_value <= x"00"; +-- end if; +-- end if; +-- end process SET_CORR_DELAY; + + sample_delay_value <= x"0" & SAMPLE_DELAY_IN; + MULT_ARRAY_DELAY: cts_delay_large generic map ( VECTOR_WIDTH => 1) diff --git a/version.vhd b/version.vhd index 6b295d6..1f57c8b 100644 --- a/version.vhd +++ b/version.vhd @@ -8,6 +8,6 @@ use ieee.numeric_std.all; package version is - constant VERSION_NUMBER_TIME : integer := 1332000868; + constant VERSION_NUMBER_TIME : integer := 1333366798; end package version;