From: Jan Michel <j.michel@gsi.de>
Date: Mon, 8 Apr 2019 13:29:13 +0000 (+0200)
Subject: Update sed check with simple edge counter for errors
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b43feee4835bcfe2c17baeec100fa9df3e8b24e6;p=trb3.git

Update sed check with simple edge counter for errors
---

diff --git a/base/code/sedcheck.vhd b/base/code/sedcheck.vhd
index 5162216..47702f3 100644
--- a/base/code/sedcheck.vhd
+++ b/base/code/sedcheck.vhd
@@ -43,6 +43,7 @@ architecture sed_arch of sedcheck is
   signal state_bits     : std_logic_vector(3 downto 0);
 
   signal sed_edge       : std_logic;
+  signal sed_edge_last  : std_logic;
   signal sed_clock_last : std_logic;
 
   signal sed_clock      : std_logic;
@@ -55,25 +56,32 @@ architecture sed_arch of sedcheck is
   signal sed_clock_q      : std_logic;
   signal sed_done_q       : std_logic;
   signal sed_error_q      : std_logic;
+  signal sed_error_qq     : std_logic;
   signal sed_inprogress_q : std_logic;
+  signal sed_start_q      : std_logic;
+  signal sed_enable_q     : std_logic;
 
   signal control_i      : std_logic_vector(31 downto 0) := (others => '0');
   signal status_i       : std_logic_vector(31 downto 0);
+  signal status2_i      : std_logic_vector(31 downto 0);
+  
   
   signal run_counter    : unsigned(7 downto 0) := (others => '0');
   signal error_counter  : unsigned(7 downto 0) := (others => '0');
+  signal edge_counter   : unsigned(7 downto 0) := (others => '0');
   signal timer          : unsigned(5 downto 0);
   
 begin
 
 sed_clock_last <= sed_clock_q when rising_edge(CLK);
 sed_edge       <= sed_clock_q and not sed_clock_last when rising_edge(CLK);
+sed_edge_last  <= sed_edge when rising_edge(CLK);
 
 sed_clock_q      <= sed_clock when rising_edge(CLK);
 sed_done_q       <= sed_done when rising_edge(CLK);
 sed_inprogress_q <= sed_inprogress when rising_edge(CLK);
 sed_error_q      <= sed_error when rising_edge(CLK);
-
+sed_error_qq     <= sed_error_q when rising_edge(CLK);
 
 ---------------------------------------------------------------------------
 -- Status / Control Register for internal data bus
@@ -95,6 +103,7 @@ proc_reg : process begin
     case BUS_RX.addr(1 downto 0) is
       when "00"   => BUS_TX.data <= control_i;
       when "01"   => BUS_TX.data <= status_i;
+      when "10"   => BUS_TX.data <= status2_i;
       when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
     end case;
   end if;
@@ -123,7 +132,7 @@ proc_ctrl : process begin
     when INIT_2 =>
       sed_enable   <= '1';
       sed_start    <= '0';
-      if timer = 0 then
+      if sed_edge = '1' then
         state      <= INIT_3;
       end if;
     when INIT_3 =>
@@ -167,6 +176,16 @@ proc_ctrl : process begin
     state      <= IDLE;
   end if;
   
+  if(sed_error_q = '1' and sed_error_qq = '0') then
+    edge_counter <= edge_counter + 1;
+  end if;  
+  
+  if sed_edge_last = '1' then
+    sed_start_q <= sed_start;
+  end if;
+  if sed_edge_last = '1' or sed_enable_q = '0' then
+    sed_enable_q <= sed_enable;
+  end if;
 end process;
 
 ---------------------------------------------------------------------------
@@ -194,7 +213,10 @@ status_i(10)         <= sed_edge;
 status_i(15 downto 11) <= (others => '0');
 status_i(23 downto 16) <= std_logic_vector(run_counter);
 status_i(31 downto 24) <= std_logic_vector(error_counter);
-              
+
+status2_i(31 downto 8) <= (others => '0');
+status2_i(7 downto 0)  <= std_logic_vector(edge_counter);
+
 ERROR_OUT <= sed_error;              
 DEBUG     <= status_i when rising_edge(CLK);
 
@@ -210,8 +232,8 @@ THE_SED : SEDCA
       DEV_DENSITY  => "150K" 
       )
   port map(
-    SEDENABLE => sed_enable,
-    SEDSTART  => sed_start,
+    SEDENABLE => sed_enable_q,
+    SEDSTART  => sed_start_q,
     SEDFRCERR => '0',
     SEDERR    => sed_error,
     SEDDONE   => sed_done,