From: Tobias Weber Date: Mon, 7 Aug 2017 11:34:42 +0000 (+0200) Subject: Getting back to working compilation after latest pull from master branch. X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b4b2a849a60f83ae28e4271d8d0323eab029ab32;p=trb3.git Getting back to working compilation after latest pull from master branch. --- diff --git a/mupix/trb3_periph.prj b/mupix/trb3_periph.prj index f82fd15..a46de10 100644 --- a/mupix/trb3_periph.prj +++ b/mupix/trb3_periph.prj @@ -50,7 +50,7 @@ impl -active "workdir" #add_file options - +add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "version.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" @@ -75,6 +75,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" @@ -100,7 +101,9 @@ add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" @@ -125,7 +128,7 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dual add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" - +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" @@ -160,4 +163,5 @@ add_file -vhdl -lib "work" "sources/ResetHandler.vhd" add_file -vhdl -lib "work" "cores/fifo_4k32_async.vhd" add_file -vhdl -lib "work" "sources/TimeWalk.vhd" add_file -vhdl -lib "work" "sources/TimeWalkWithFiFo.vhd" -add_file -vhdl -lib "work" "sources/SignalDelay.vhd" \ No newline at end of file +add_file -vhdl -lib "work" "sources/SignalDelay.vhd" +add_file -vhdl -lib "work" "sources/StdTypes.vhd" \ No newline at end of file diff --git a/mupix/trb3_periph.vhd b/mupix/trb3_periph.vhd index d9610f5..a45515c 100644 --- a/mupix/trb3_periph.vhd +++ b/mupix/trb3_periph.vhd @@ -346,6 +346,7 @@ begin THE_MAIN_PLL : pll_in200_out100 port map( CLK => CLK_GPLL_RIGHT, + RESET => '0', CLKOP => clk_100_i, CLKOK => clk_200_i, LOCK => pll_lock