From: Andreas Neiser Date: Tue, 17 Feb 2015 12:54:17 +0000 (+0100) Subject: Testbenching the AD9219 entity X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b4d2e0e51b8387f50faa02d3539f3ccf71d5f566;p=trb3.git Testbenching the AD9219 entity --- diff --git a/ADC/sim/adc_serializer.vhd b/ADC/sim/adc_serializer.vhd new file mode 100644 index 0000000..50ef1f1 --- /dev/null +++ b/ADC/sim/adc_serializer.vhd @@ -0,0 +1,37 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.config.all; + +entity adc_serializer is + port ( + ADC_DCO : out std_logic; + ADC_DATA : out std_logic_vector(4 downto 0) + ); +end entity adc_serializer; + +architecture arch of adc_serializer is + signal ddr_clock : std_logic := '1'; + +begin + gen_40MHz : if ADC_SAMPLING_RATE = 40 generate + ddr_clock <= not ddr_clock after 2.5 ns; -- 200 MHz => 40x10=400Mbit DDR + end generate; + + gen_80MHz : if ADC_SAMPLING_RATE = 80 generate + ddr_clock <= not ddr_clock after 1.25 ns; + end generate; + + ADC_DCO <= ddr_clock; + + output : process is + begin + wait until rising_edge(ddr_clock); + ADC_DATA <= (others => '1'); + + wait until falling_edge(ddr_clock); + ADC_DATA <= (others => '0'); + end process output; + +end architecture arch; diff --git a/ADC/sim/tb_adcprocessor.vhd b/ADC/sim/tb_adcprocessor.vhd index bfdcc8d..a6c2a90 100644 --- a/ADC/sim/tb_adcprocessor.vhd +++ b/ADC/sim/tb_adcprocessor.vhd @@ -13,16 +13,24 @@ end entity; architecture tb_arch of tb is -component dummyADC is - generic( - stim_file: string :="adcsim.dat" - ); - port( - CLK : in std_logic; - DATA : out std_logic_vector(39 downto 0); - VALID : out std_logic - ); -end component; +component adc_ad9219 + generic(NUM_DEVICES : integer := 5); + port(CLK : in std_logic; + CLK_ADCRAW : in std_logic; + RESTART_IN : in std_logic; + ADCCLK_OUT : out std_logic; + ADC_DATA : in std_logic_vector(NUM_DEVICES * (CHANNELS + 1) - 1 downto 0); + ADC_DCO : in std_logic_vector(NUM_DEVICES downto 1); + DATA_OUT : out std_logic_vector(NUM_DEVICES * CHANNELS * RESOLUTION - 1 downto 0); + FCO_OUT : out std_logic_vector(NUM_DEVICES * RESOLUTION - 1 downto 0); + DATA_VALID_OUT : out std_logic_vector(NUM_DEVICES - 1 downto 0); + DEBUG : out std_logic_vector(NUM_DEVICES * 32 - 1 downto 0)); +end component adc_ad9219; + +component adc_serializer + port(ADC_DCO : out std_logic; + ADC_DATA : out std_logic_vector(4 downto 0)); +end component adc_serializer; component adc_processor is generic( @@ -54,8 +62,11 @@ component adc_processor is ); end component; -signal clock : std_logic := '1'; +signal clock100 : std_logic := '1'; +signal clock200 : std_logic := '1'; signal adc_data : std_logic_vector(39 downto 0) := (others => '0'); +signal adc_data_ser : std_logic_vector(4 downto 0); +signal adc_dco : std_logic; signal adc_valid : std_logic := '0'; signal stop_in : std_logic := '0'; signal trigger_out: std_logic := '0'; @@ -70,7 +81,11 @@ signal psa_addr : std_logic_vector(7 downto 0) := (others => '0'); begin -clock <= not clock after 5 ns; +clock100 <= not clock100 after 5 ns; + +clock200 <= not clock200 after 2.5 ns; + + -- -- config.buffer_depth <= to_unsigned(100 ,11); -- config.samples_after <= to_unsigned(20 ,11); @@ -145,20 +160,20 @@ control <= (others => '0'), (8 => '1',others => '0') after 1 us, (others => '0') proc_write_psa : process begin wait for 1 us; - wait until rising_edge(clock); wait for 0.5 ns; + wait until rising_edge(clock100); wait for 0.5 ns; psa_write <= '1'; psa_addr <= x"00"; psa_data <= "0"&x"01"; - wait until rising_edge(clock); wait for 0.5 ns; + wait until rising_edge(clock100); wait for 0.5 ns; psa_addr <= x"01"; psa_data <= "0"&x"02"; - wait until rising_edge(clock); wait for 0.5 ns; + wait until rising_edge(clock100); wait for 0.5 ns; psa_addr <= x"02"; psa_data <= "0"&x"03"; - wait until rising_edge(clock); wait for 0.5 ns; + wait until rising_edge(clock100); wait for 0.5 ns; psa_addr <= x"03"; psa_data <= "1"&x"ff"; - wait until rising_edge(clock); wait for 0.5 ns; + wait until rising_edge(clock100); wait for 0.5 ns; psa_write <= '0'; wait; end process; @@ -167,30 +182,43 @@ end process; proc_rdo : process begin readout_rx.data_valid <= '0'; readout_rx.valid_timing_trg <= '0'; - wait for 15 us; wait until rising_edge(clock); wait for 0.5 ns; + wait for 15 us; wait until rising_edge(clock100); wait for 0.5 ns; readout_rx.valid_timing_trg <= '1'; - wait until rising_edge(clock); wait for 0.5 ns; + wait until rising_edge(clock100); wait for 0.5 ns; readout_rx.valid_timing_trg <= '0'; - wait for 250 ns; wait until rising_edge(clock); wait for 0.5 ns; + wait for 250 ns; wait until rising_edge(clock100); wait for 0.5 ns; readout_rx.data_valid <= '1'; wait until readout_tx.busy_release = '1'; - wait for 10 ns; wait until rising_edge(clock); wait for 0.5 ns; + wait for 10 ns; wait until rising_edge(clock100); wait for 0.5 ns; readout_rx.data_valid <= '0'; end process; -THE_ADC : dummyADC - port map( - CLK => clock, - DATA => adc_data, - VALID => adc_valid - ); +THE_ADC_SER : adc_serializer + port map(ADC_DCO => ADC_DCO, + ADC_DATA => ADC_DATA_ser); + +THE_ADC : adc_ad9219 + generic map(NUM_DEVICES => 5) + port map(CLK => clock100, + CLK_ADCRAW => clock200, + RESTART_IN => '0', + --ADCCLK_OUT => open, + ADC_DATA(4 downto 0) => adc_data_ser, + --ADC_DATA(24 downto 5) => open, + ADC_DCO(1) => adc_dco, + --ADC_DCO(5 downto 2) => open, + DATA_OUT(39 downto 0) => adc_data, + --FCO_OUT => open, + DATA_VALID_OUT(0) => adc_valid--, + --DEBUG => open + ); UUT: adc_processor generic map( DEVICE => 0 ) port map( - CLK => clock, + CLK => clock100, ADC_DATA => adc_data, ADC_VALID => adc_valid, STOP_IN => stop_in, @@ -215,7 +243,7 @@ UUT: adc_processor PROC_ADC : process begin - wait until rising_edge(clock); wait for 0.5 ns; + wait until rising_edge(clock100); wait for 0.5 ns; end process;