From: Jan Michel Date: Tue, 10 Jul 2018 12:18:14 +0000 (+0200) Subject: change ring buffer almost full handling - now single words are discarded X-Git-Tag: v2.3~6 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b526739dc28225b64df4907893506954b33b58eb;p=tdc.git change ring buffer almost full handling - now single words are discarded --- diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.edn b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.edn index 3dfc2e6..d0faa0c 100644 --- a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.edn +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.edn @@ -4,9 +4,9 @@ (keywordMap (keywordLevel 0)) (status (written - (timestamp 2015 4 9 9 22 22) - (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) - (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -rdata_width 36 -regout -no_enable -pe -1 -pf 0 ") + (timestamp 2018 7 6 11 51 36) + (program "SCUBA" (version "Diamond (64-bit) 3.9.1.119")))) + (comment "/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -rdata_width 36 -regout -no_enable -pe 0 -pf -1 ") (library ORCLIB (edifLevel 0) (technology @@ -458,7 +458,7 @@ (direction INPUT)) (port RPReset (direction INPUT)) - (port (array (rename AmFullThresh "AmFullThresh(6:0)") 7) + (port (array (rename AmEmptyThresh "AmEmptyThresh(6:0)") 7) (direction INPUT)) (port (array (rename Q "Q(35:0)") 36) (direction OUTPUT)) @@ -466,25 +466,31 @@ (direction OUTPUT)) (port Full (direction OUTPUT)) - (port AlmostFull + (port AlmostEmpty (direction OUTPUT))) (property NGD_DRC_MASK (integer 1)) (contents - (instance AND2_t17 + (instance AND2_t19 (viewRef view1 (cellRef AND2))) - (instance INV_1 + (instance INV_2 (viewRef view1 (cellRef INV))) - (instance AND2_t16 + (instance AND2_t18 (viewRef view1 (cellRef AND2))) - (instance INV_0 + (instance INV_1 (viewRef view1 (cellRef INV))) - (instance OR2_t15 + (instance OR2_t17 (viewRef view1 (cellRef OR2))) + (instance XOR2_t16 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t15 + (viewRef view1 + (cellRef XOR2))) (instance XOR2_t14 (viewRef view1 (cellRef XOR2))) @@ -521,12 +527,6 @@ (instance XOR2_t3 (viewRef view1 (cellRef XOR2))) - (instance XOR2_t2 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t1 - (viewRef view1 - (cellRef XOR2))) (instance LUT4_19 (viewRef view1 (cellRef ROM16X1A)) @@ -607,7 +607,7 @@ (cellRef ROM16X1A)) (property initval (string "0x6996"))) - (instance XOR2_t0 + (instance XOR2_t2 (viewRef view1 (cellRef XOR2))) (instance LUT4_3 @@ -630,6 +630,15 @@ (cellRef ROM16X1A)) (property initval (string "0x4001"))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance AND2_t1 + (viewRef view1 + (cellRef AND2))) + (instance AND2_t0 + (viewRef view1 + (cellRef AND2))) (instance pdp_ram_0_0_0 (viewRef view1 (cellRef PDPW16KC)) @@ -1103,7 +1112,7 @@ (string "ENABLED"))) (instance FF_0 (viewRef view1 - (cellRef FD1S3DX)) + (cellRef FD1S3BX)) (property GSR (string "ENABLED"))) (instance w_gctr_cia @@ -1142,19 +1151,19 @@ (instance scuba_vhi_inst (viewRef view1 (cellRef VHI))) - (instance wcnt_0 + (instance rcnt_0 (viewRef view1 (cellRef FSUB2B))) - (instance wcnt_1 + (instance rcnt_1 (viewRef view1 (cellRef FSUB2B))) - (instance wcnt_2 + (instance rcnt_2 (viewRef view1 (cellRef FSUB2B))) - (instance wcnt_3 + (instance rcnt_3 (viewRef view1 (cellRef FSUB2B))) - (instance wcnt_4 + (instance rcnt_4 (viewRef view1 (cellRef FSUB2B))) (instance empty_cmp_ci_a @@ -1193,19 +1202,19 @@ (instance a1 (viewRef view1 (cellRef FADD2B))) - (instance af_d_cmp_ci_a + (instance ae_cmp_ci_a (viewRef view1 (cellRef FADD2B))) - (instance af_d_cmp_0 + (instance ae_cmp_0 (viewRef view1 (cellRef AGEB2))) - (instance af_d_cmp_1 + (instance ae_cmp_1 (viewRef view1 (cellRef AGEB2))) - (instance af_d_cmp_2 + (instance ae_cmp_2 (viewRef view1 (cellRef AGEB2))) - (instance af_d_cmp_3 + (instance ae_cmp_3 (viewRef view1 (cellRef AGEB2))) (instance scuba_vlo_inst @@ -1216,12 +1225,12 @@ (cellRef FADD2B))) (net invout_1 (joined - (portRef Z (instanceRef INV_1)) - (portRef B (instanceRef AND2_t17)))) + (portRef Z (instanceRef INV_2)) + (portRef B (instanceRef AND2_t19)))) (net invout_0 (joined - (portRef Z (instanceRef INV_0)) - (portRef B (instanceRef AND2_t16)))) + (portRef Z (instanceRef INV_1)) + (portRef B (instanceRef AND2_t18)))) (net w_g2b_xor_cluster_1 (joined (portRef AD2 (instanceRef LUT4_12)) @@ -1230,34 +1239,38 @@ (joined (portRef AD2 (instanceRef LUT4_4)) (portRef DO0 (instanceRef LUT4_10)))) + (net rcnt_reg_6_inv + (joined + (portRef B (instanceRef AND2_t1)) + (portRef Z (instanceRef INV_0)))) (net w_gdata_0 (joined (portRef D (instanceRef FF_82)) - (portRef Z (instanceRef XOR2_t14)))) + (portRef Z (instanceRef XOR2_t16)))) (net w_gdata_1 (joined (portRef D (instanceRef FF_81)) - (portRef Z (instanceRef XOR2_t13)))) + (portRef Z (instanceRef XOR2_t15)))) (net w_gdata_2 (joined (portRef D (instanceRef FF_80)) - (portRef Z (instanceRef XOR2_t12)))) + (portRef Z (instanceRef XOR2_t14)))) (net w_gdata_3 (joined (portRef D (instanceRef FF_79)) - (portRef Z (instanceRef XOR2_t11)))) + (portRef Z (instanceRef XOR2_t13)))) (net w_gdata_4 (joined (portRef D (instanceRef FF_78)) - (portRef Z (instanceRef XOR2_t10)))) + (portRef Z (instanceRef XOR2_t12)))) (net w_gdata_5 (joined (portRef D (instanceRef FF_77)) - (portRef Z (instanceRef XOR2_t9)))) + (portRef Z (instanceRef XOR2_t11)))) (net w_gdata_6 (joined (portRef D (instanceRef FF_76)) - (portRef Z (instanceRef XOR2_t8)))) + (portRef Z (instanceRef XOR2_t10)))) (net wptr_0 (joined (portRef Q (instanceRef FF_74)) @@ -1294,31 +1307,31 @@ (net r_gdata_0 (joined (portRef D (instanceRef FF_58)) - (portRef Z (instanceRef XOR2_t7)))) + (portRef Z (instanceRef XOR2_t9)))) (net r_gdata_1 (joined (portRef D (instanceRef FF_57)) - (portRef Z (instanceRef XOR2_t6)))) + (portRef Z (instanceRef XOR2_t8)))) (net r_gdata_2 (joined (portRef D (instanceRef FF_56)) - (portRef Z (instanceRef XOR2_t5)))) + (portRef Z (instanceRef XOR2_t7)))) (net r_gdata_3 (joined (portRef D (instanceRef FF_55)) - (portRef Z (instanceRef XOR2_t4)))) + (portRef Z (instanceRef XOR2_t6)))) (net r_gdata_4 (joined (portRef D (instanceRef FF_54)) - (portRef Z (instanceRef XOR2_t3)))) + (portRef Z (instanceRef XOR2_t5)))) (net r_gdata_5 (joined (portRef D (instanceRef FF_53)) - (portRef Z (instanceRef XOR2_t2)))) + (portRef Z (instanceRef XOR2_t4)))) (net r_gdata_6 (joined (portRef D (instanceRef FF_52)) - (portRef Z (instanceRef XOR2_t1)))) + (portRef Z (instanceRef XOR2_t3)))) (net rptr_0 (joined (portRef Q (instanceRef FF_50)) @@ -1490,6 +1503,7 @@ (portRef AD0 (instanceRef LUT4_19)) (portRef AD2 (instanceRef LUT4_17)) (portRef AD1 (instanceRef LUT4_16)) + (portRef A (instanceRef XOR2_t2)) (portRef AD1 (instanceRef LUT4_3)) (portRef AD1 (instanceRef LUT4_2)))) (net w_gcount_r7 @@ -1570,17 +1584,21 @@ (portRef AD0 (instanceRef LUT4_11)) (portRef AD2 (instanceRef LUT4_9)) (portRef AD1 (instanceRef LUT4_8)) - (portRef B (instanceRef XOR2_t0)) (portRef AD1 (instanceRef LUT4_1)) (portRef AD1 (instanceRef LUT4_0)))) (net r_gcount_w7 (joined (portRef D (instanceRef FF_11)) (portRef Q (instanceRef FF_27)))) + (net rcnt_reg_7 + (joined + (portRef Q (instanceRef FF_3)) + (portRef A (instanceRef AND2_t1)) + (portRef A (instanceRef AND2_t0)))) (net rRst (joined - (portRef PD (instanceRef FF_2)) - (portRef Z (instanceRef OR2_t15)) + (portRef PD (instanceRef FF_0)) + (portRef Z (instanceRef OR2_t17)) (portRef PD (instanceRef FF_66)) (portRef CD (instanceRef FF_65)) (portRef CD (instanceRef FF_64)) @@ -1620,7 +1638,16 @@ (portRef CD (instanceRef FF_14)) (portRef CD (instanceRef FF_13)) (portRef CD (instanceRef FF_12)) - (portRef CD (instanceRef FF_11)))) + (portRef CD (instanceRef FF_11)) + (portRef CD (instanceRef FF_10)) + (portRef CD (instanceRef FF_9)) + (portRef CD (instanceRef FF_8)) + (portRef CD (instanceRef FF_7)) + (portRef CD (instanceRef FF_6)) + (portRef CD (instanceRef FF_5)) + (portRef CD (instanceRef FF_4)) + (portRef CD (instanceRef FF_3)) + (portRef PD (instanceRef FF_2)))) (net iwcount_0 (joined (portRef NC0 (instanceRef w_gctr_0)) @@ -1675,8 +1702,7 @@ (net wcount_7 (joined (portRef PC1 (instanceRef w_gctr_3)) - (portRef B (instanceRef XOR2_t8)) - (portRef A (instanceRef XOR2_t0)) + (portRef B (instanceRef XOR2_t10)) (portRef AD2 (instanceRef LUT4_1)) (portRef AD2 (instanceRef LUT4_0)) (portRef Q (instanceRef FF_83)) @@ -1736,19 +1762,20 @@ (net rcount_7 (joined (portRef PC1 (instanceRef r_gctr_3)) - (portRef B (instanceRef XOR2_t1)) + (portRef B (instanceRef XOR2_t3)) + (portRef B (instanceRef XOR2_t2)) (portRef AD2 (instanceRef LUT4_3)) (portRef AD2 (instanceRef LUT4_2)) (portRef Q (instanceRef FF_59)) (portRef D (instanceRef FF_51)) (portRef D (instanceRef FF_43)))) - (net wcnt_sub_0 + (net rcnt_sub_0 (joined - (portRef S1 (instanceRef wcnt_0)) + (portRef S1 (instanceRef rcnt_0)) (portRef D (instanceRef FF_10)))) (net precin (joined - (portRef BI (instanceRef wcnt_0)) + (portRef BI (instanceRef rcnt_0)) (portRef COUT (instanceRef precin_inst284)))) (net scuba_vhi (joined @@ -1763,85 +1790,55 @@ (portRef A1 (instanceRef w_gctr_cia)) (portRef B1 (instanceRef r_gctr_cia)) (portRef A1 (instanceRef r_gctr_cia)) - (portRef A0 (instanceRef wcnt_0)))) - (net wcnt_sub_1 + (portRef A0 (instanceRef rcnt_0)))) + (net rcnt_sub_1 (joined - (portRef S0 (instanceRef wcnt_1)) + (portRef S0 (instanceRef rcnt_1)) (portRef D (instanceRef FF_9)))) - (net wcnt_sub_2 + (net rcnt_sub_2 (joined - (portRef S1 (instanceRef wcnt_1)) + (portRef S1 (instanceRef rcnt_1)) (portRef D (instanceRef FF_8)))) (net co0_2 (joined - (portRef BI (instanceRef wcnt_1)) - (portRef BOUT (instanceRef wcnt_0)))) - (net wcnt_sub_3 + (portRef BI (instanceRef rcnt_1)) + (portRef BOUT (instanceRef rcnt_0)))) + (net rcnt_sub_3 (joined - (portRef S0 (instanceRef wcnt_2)) + (portRef S0 (instanceRef rcnt_2)) (portRef D (instanceRef FF_7)))) - (net wcnt_sub_4 + (net rcnt_sub_4 (joined - (portRef S1 (instanceRef wcnt_2)) + (portRef S1 (instanceRef rcnt_2)) (portRef D (instanceRef FF_6)))) (net co1_2 (joined - (portRef BI (instanceRef wcnt_2)) - (portRef BOUT (instanceRef wcnt_1)))) - (net wcnt_sub_5 + (portRef BI (instanceRef rcnt_2)) + (portRef BOUT (instanceRef rcnt_1)))) + (net rcnt_sub_5 (joined - (portRef S0 (instanceRef wcnt_3)) + (portRef S0 (instanceRef rcnt_3)) (portRef D (instanceRef FF_5)))) - (net wcnt_sub_6 + (net rcnt_sub_6 (joined - (portRef S1 (instanceRef wcnt_3)) + (portRef S1 (instanceRef rcnt_3)) (portRef D (instanceRef FF_4)))) (net co2_2 (joined - (portRef BI (instanceRef wcnt_3)) - (portRef BOUT (instanceRef wcnt_2)))) - (net wcnt_sub_7 + (portRef BI (instanceRef rcnt_3)) + (portRef BOUT (instanceRef rcnt_2)))) + (net rcnt_sub_7 (joined - (portRef S0 (instanceRef wcnt_4)) + (portRef S0 (instanceRef rcnt_4)) (portRef D (instanceRef FF_3)))) (net co3_2 (joined - (portRef BI (instanceRef wcnt_4)) - (portRef BOUT (instanceRef wcnt_3)))) - (net wcnt_sub_msb - (joined - (portRef A0 (instanceRef wcnt_4)) - (portRef Z (instanceRef XOR2_t0)))) - (net rden_i + (portRef BI (instanceRef rcnt_4)) + (portRef BOUT (instanceRef rcnt_3)))) + (net rcnt_sub_msb (joined - (portRef A1 (instanceRef empty_cmp_ci_a)) - (portRef Z (instanceRef AND2_t16)) - (portRef CSR0 (instanceRef pdp_ram_0_0_0)) - (portRef SP (instanceRef FF_66)) - (portRef SP (instanceRef FF_65)) - (portRef SP (instanceRef FF_64)) - (portRef SP (instanceRef FF_63)) - (portRef SP (instanceRef FF_62)) - (portRef SP (instanceRef FF_61)) - (portRef SP (instanceRef FF_60)) - (portRef SP (instanceRef FF_59)) - (portRef SP (instanceRef FF_58)) - (portRef SP (instanceRef FF_57)) - (portRef SP (instanceRef FF_56)) - (portRef SP (instanceRef FF_55)) - (portRef SP (instanceRef FF_54)) - (portRef SP (instanceRef FF_53)) - (portRef SP (instanceRef FF_52)) - (portRef SP (instanceRef FF_51)) - (portRef SP (instanceRef FF_50)) - (portRef SP (instanceRef FF_49)) - (portRef SP (instanceRef FF_48)) - (portRef SP (instanceRef FF_47)) - (portRef SP (instanceRef FF_46)) - (portRef SP (instanceRef FF_45)) - (portRef SP (instanceRef FF_44)) - (portRef SP (instanceRef FF_43)) - (portRef B1 (instanceRef empty_cmp_ci_a)))) + (portRef A0 (instanceRef rcnt_4)) + (portRef Z (instanceRef XOR2_t2)))) (net cmp_ci (joined (portRef CI (instanceRef empty_cmp_0)) @@ -1849,26 +1846,30 @@ (net wcount_r0 (joined (portRef B0 (instanceRef empty_cmp_0)) - (portRef DO0 (instanceRef LUT4_12)))) + (portRef DO0 (instanceRef LUT4_12)) + (portRef A1 (instanceRef rcnt_0)))) (net wcount_r1 (joined (portRef B1 (instanceRef empty_cmp_0)) - (portRef DO0 (instanceRef LUT4_13)))) + (portRef DO0 (instanceRef LUT4_13)) + (portRef A0 (instanceRef rcnt_1)))) (net rcount_0 (joined (portRef A0 (instanceRef empty_cmp_0)) - (portRef A (instanceRef XOR2_t7)) + (portRef A (instanceRef XOR2_t9)) (portRef Q (instanceRef FF_66)) (portRef D (instanceRef FF_50)) - (portRef PC0 (instanceRef r_gctr_0)))) + (portRef PC0 (instanceRef r_gctr_0)) + (portRef B1 (instanceRef rcnt_0)))) (net rcount_1 (joined (portRef A1 (instanceRef empty_cmp_0)) - (portRef B (instanceRef XOR2_t7)) - (portRef A (instanceRef XOR2_t6)) + (portRef B (instanceRef XOR2_t9)) + (portRef A (instanceRef XOR2_t8)) (portRef Q (instanceRef FF_65)) (portRef D (instanceRef FF_49)) - (portRef PC1 (instanceRef r_gctr_0)))) + (portRef PC1 (instanceRef r_gctr_0)) + (portRef B0 (instanceRef rcnt_1)))) (net co0_3 (joined (portRef CI (instanceRef empty_cmp_1)) @@ -1876,27 +1877,31 @@ (net wcount_r2 (joined (portRef B0 (instanceRef empty_cmp_1)) - (portRef DO0 (instanceRef LUT4_14)))) + (portRef DO0 (instanceRef LUT4_14)) + (portRef A1 (instanceRef rcnt_1)))) (net wcount_r3 (joined (portRef B1 (instanceRef empty_cmp_1)) - (portRef DO0 (instanceRef LUT4_15)))) + (portRef DO0 (instanceRef LUT4_15)) + (portRef A0 (instanceRef rcnt_2)))) (net rcount_2 (joined (portRef A0 (instanceRef empty_cmp_1)) - (portRef B (instanceRef XOR2_t6)) - (portRef A (instanceRef XOR2_t5)) + (portRef B (instanceRef XOR2_t8)) + (portRef A (instanceRef XOR2_t7)) (portRef Q (instanceRef FF_64)) (portRef D (instanceRef FF_48)) - (portRef PC0 (instanceRef r_gctr_1)))) + (portRef PC0 (instanceRef r_gctr_1)) + (portRef B1 (instanceRef rcnt_1)))) (net rcount_3 (joined (portRef A1 (instanceRef empty_cmp_1)) - (portRef B (instanceRef XOR2_t5)) - (portRef A (instanceRef XOR2_t4)) + (portRef B (instanceRef XOR2_t7)) + (portRef A (instanceRef XOR2_t6)) (portRef Q (instanceRef FF_63)) (portRef D (instanceRef FF_47)) - (portRef PC1 (instanceRef r_gctr_1)))) + (portRef PC1 (instanceRef r_gctr_1)) + (portRef B0 (instanceRef rcnt_2)))) (net co1_3 (joined (portRef CI (instanceRef empty_cmp_2)) @@ -1906,28 +1911,32 @@ (portRef B0 (instanceRef empty_cmp_2)) (portRef DO0 (instanceRef LUT4_19)) (portRef AD0 (instanceRef LUT4_13)) - (portRef AD3 (instanceRef LUT4_12)))) + (portRef AD3 (instanceRef LUT4_12)) + (portRef A1 (instanceRef rcnt_2)))) (net wcount_r5 (joined (portRef B1 (instanceRef empty_cmp_2)) (portRef DO0 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_14)))) + (portRef AD0 (instanceRef LUT4_14)) + (portRef A0 (instanceRef rcnt_3)))) (net rcount_4 (joined (portRef A0 (instanceRef empty_cmp_2)) - (portRef B (instanceRef XOR2_t4)) - (portRef A (instanceRef XOR2_t3)) + (portRef B (instanceRef XOR2_t6)) + (portRef A (instanceRef XOR2_t5)) (portRef Q (instanceRef FF_62)) (portRef D (instanceRef FF_46)) - (portRef PC0 (instanceRef r_gctr_2)))) + (portRef PC0 (instanceRef r_gctr_2)) + (portRef B1 (instanceRef rcnt_2)))) (net rcount_5 (joined (portRef A1 (instanceRef empty_cmp_2)) - (portRef B (instanceRef XOR2_t3)) - (portRef A (instanceRef XOR2_t2)) + (portRef B (instanceRef XOR2_t5)) + (portRef A (instanceRef XOR2_t4)) (portRef Q (instanceRef FF_61)) (portRef D (instanceRef FF_45)) - (portRef PC1 (instanceRef r_gctr_2)))) + (portRef PC1 (instanceRef r_gctr_2)) + (portRef B0 (instanceRef rcnt_3)))) (net co2_3 (joined (portRef CI (instanceRef empty_cmp_3)) @@ -1936,7 +1945,8 @@ (joined (portRef B0 (instanceRef empty_cmp_3)) (portRef DO0 (instanceRef LUT4_17)) - (portRef AD0 (instanceRef LUT4_15)))) + (portRef AD0 (instanceRef LUT4_15)) + (portRef A1 (instanceRef rcnt_3)))) (net empty_cmp_clr (joined (portRef B1 (instanceRef empty_cmp_3)) @@ -1944,11 +1954,12 @@ (net rcount_6 (joined (portRef A0 (instanceRef empty_cmp_3)) - (portRef B (instanceRef XOR2_t2)) - (portRef A (instanceRef XOR2_t1)) + (portRef B (instanceRef XOR2_t4)) + (portRef A (instanceRef XOR2_t3)) (portRef Q (instanceRef FF_60)) (portRef D (instanceRef FF_44)) - (portRef PC0 (instanceRef r_gctr_3)))) + (portRef PC0 (instanceRef r_gctr_3)) + (portRef B1 (instanceRef rcnt_3)))) (net empty_cmp_set (joined (portRef A1 (instanceRef empty_cmp_3)) @@ -1961,6 +1972,36 @@ (joined (portRef CI (instanceRef a0)) (portRef GE (instanceRef empty_cmp_3)))) + (net wren_i + (joined + (portRef A1 (instanceRef full_cmp_ci_a)) + (portRef Z (instanceRef AND2_t19)) + (portRef CEW (instanceRef pdp_ram_0_0_0)) + (portRef SP (instanceRef FF_90)) + (portRef SP (instanceRef FF_89)) + (portRef SP (instanceRef FF_88)) + (portRef SP (instanceRef FF_87)) + (portRef SP (instanceRef FF_86)) + (portRef SP (instanceRef FF_85)) + (portRef SP (instanceRef FF_84)) + (portRef SP (instanceRef FF_83)) + (portRef SP (instanceRef FF_82)) + (portRef SP (instanceRef FF_81)) + (portRef SP (instanceRef FF_80)) + (portRef SP (instanceRef FF_79)) + (portRef SP (instanceRef FF_78)) + (portRef SP (instanceRef FF_77)) + (portRef SP (instanceRef FF_76)) + (portRef SP (instanceRef FF_75)) + (portRef SP (instanceRef FF_74)) + (portRef SP (instanceRef FF_73)) + (portRef SP (instanceRef FF_72)) + (portRef SP (instanceRef FF_71)) + (portRef SP (instanceRef FF_70)) + (portRef SP (instanceRef FF_69)) + (portRef SP (instanceRef FF_68)) + (portRef SP (instanceRef FF_67)) + (portRef B1 (instanceRef full_cmp_ci_a)))) (net cmp_ci_1 (joined (portRef CI (instanceRef full_cmp_0)) @@ -1968,30 +2009,26 @@ (net rcount_w0 (joined (portRef B0 (instanceRef full_cmp_0)) - (portRef DO0 (instanceRef LUT4_4)) - (portRef B1 (instanceRef wcnt_0)))) + (portRef DO0 (instanceRef LUT4_4)))) (net rcount_w1 (joined (portRef B1 (instanceRef full_cmp_0)) - (portRef DO0 (instanceRef LUT4_5)) - (portRef B0 (instanceRef wcnt_1)))) + (portRef DO0 (instanceRef LUT4_5)))) (net wcount_0 (joined (portRef A0 (instanceRef full_cmp_0)) - (portRef A (instanceRef XOR2_t14)) + (portRef A (instanceRef XOR2_t16)) (portRef Q (instanceRef FF_90)) (portRef D (instanceRef FF_74)) - (portRef PC0 (instanceRef w_gctr_0)) - (portRef A1 (instanceRef wcnt_0)))) + (portRef PC0 (instanceRef w_gctr_0)))) (net wcount_1 (joined (portRef A1 (instanceRef full_cmp_0)) - (portRef B (instanceRef XOR2_t14)) - (portRef A (instanceRef XOR2_t13)) + (portRef B (instanceRef XOR2_t16)) + (portRef A (instanceRef XOR2_t15)) (portRef Q (instanceRef FF_89)) (portRef D (instanceRef FF_73)) - (portRef PC1 (instanceRef w_gctr_0)) - (portRef A0 (instanceRef wcnt_1)))) + (portRef PC1 (instanceRef w_gctr_0)))) (net co0_4 (joined (portRef CI (instanceRef full_cmp_1)) @@ -1999,31 +2036,27 @@ (net rcount_w2 (joined (portRef B0 (instanceRef full_cmp_1)) - (portRef DO0 (instanceRef LUT4_6)) - (portRef B1 (instanceRef wcnt_1)))) + (portRef DO0 (instanceRef LUT4_6)))) (net rcount_w3 (joined (portRef B1 (instanceRef full_cmp_1)) - (portRef DO0 (instanceRef LUT4_7)) - (portRef B0 (instanceRef wcnt_2)))) + (portRef DO0 (instanceRef LUT4_7)))) (net wcount_2 (joined (portRef A0 (instanceRef full_cmp_1)) - (portRef B (instanceRef XOR2_t13)) - (portRef A (instanceRef XOR2_t12)) + (portRef B (instanceRef XOR2_t15)) + (portRef A (instanceRef XOR2_t14)) (portRef Q (instanceRef FF_88)) (portRef D (instanceRef FF_72)) - (portRef PC0 (instanceRef w_gctr_1)) - (portRef A1 (instanceRef wcnt_1)))) + (portRef PC0 (instanceRef w_gctr_1)))) (net wcount_3 (joined (portRef A1 (instanceRef full_cmp_1)) - (portRef B (instanceRef XOR2_t12)) - (portRef A (instanceRef XOR2_t11)) + (portRef B (instanceRef XOR2_t14)) + (portRef A (instanceRef XOR2_t13)) (portRef Q (instanceRef FF_87)) (portRef D (instanceRef FF_71)) - (portRef PC1 (instanceRef w_gctr_1)) - (portRef A0 (instanceRef wcnt_2)))) + (portRef PC1 (instanceRef w_gctr_1)))) (net co1_4 (joined (portRef CI (instanceRef full_cmp_2)) @@ -2033,32 +2066,28 @@ (portRef B0 (instanceRef full_cmp_2)) (portRef DO0 (instanceRef LUT4_11)) (portRef AD0 (instanceRef LUT4_5)) - (portRef AD3 (instanceRef LUT4_4)) - (portRef B1 (instanceRef wcnt_2)))) + (portRef AD3 (instanceRef LUT4_4)))) (net rcount_w5 (joined (portRef B1 (instanceRef full_cmp_2)) (portRef DO0 (instanceRef LUT4_8)) - (portRef AD0 (instanceRef LUT4_6)) - (portRef B0 (instanceRef wcnt_3)))) + (portRef AD0 (instanceRef LUT4_6)))) (net wcount_4 (joined (portRef A0 (instanceRef full_cmp_2)) - (portRef B (instanceRef XOR2_t11)) - (portRef A (instanceRef XOR2_t10)) + (portRef B (instanceRef XOR2_t13)) + (portRef A (instanceRef XOR2_t12)) (portRef Q (instanceRef FF_86)) (portRef D (instanceRef FF_70)) - (portRef PC0 (instanceRef w_gctr_2)) - (portRef A1 (instanceRef wcnt_2)))) + (portRef PC0 (instanceRef w_gctr_2)))) (net wcount_5 (joined (portRef A1 (instanceRef full_cmp_2)) - (portRef B (instanceRef XOR2_t10)) - (portRef A (instanceRef XOR2_t9)) + (portRef B (instanceRef XOR2_t12)) + (portRef A (instanceRef XOR2_t11)) (portRef Q (instanceRef FF_85)) (portRef D (instanceRef FF_69)) - (portRef PC1 (instanceRef w_gctr_2)) - (portRef A0 (instanceRef wcnt_3)))) + (portRef PC1 (instanceRef w_gctr_2)))) (net co2_4 (joined (portRef CI (instanceRef full_cmp_3)) @@ -2067,8 +2096,7 @@ (joined (portRef B0 (instanceRef full_cmp_3)) (portRef DO0 (instanceRef LUT4_9)) - (portRef AD0 (instanceRef LUT4_7)) - (portRef B1 (instanceRef wcnt_3)))) + (portRef AD0 (instanceRef LUT4_7)))) (net full_cmp_clr (joined (portRef B1 (instanceRef full_cmp_3)) @@ -2076,12 +2104,11 @@ (net wcount_6 (joined (portRef A0 (instanceRef full_cmp_3)) - (portRef B (instanceRef XOR2_t9)) - (portRef A (instanceRef XOR2_t8)) + (portRef B (instanceRef XOR2_t11)) + (portRef A (instanceRef XOR2_t10)) (portRef Q (instanceRef FF_84)) (portRef D (instanceRef FF_68)) - (portRef PC0 (instanceRef w_gctr_3)) - (portRef A1 (instanceRef wcnt_3)))) + (portRef PC0 (instanceRef w_gctr_3)))) (net full_cmp_set (joined (portRef A1 (instanceRef full_cmp_3)) @@ -2094,94 +2121,100 @@ (joined (portRef CI (instanceRef a1)) (portRef GE (instanceRef full_cmp_3)))) - (net wren_i + (net rden_i (joined - (portRef A1 (instanceRef af_d_cmp_ci_a)) - (portRef Z (instanceRef AND2_t17)) - (portRef CEW (instanceRef pdp_ram_0_0_0)) - (portRef SP (instanceRef FF_90)) - (portRef SP (instanceRef FF_89)) - (portRef SP (instanceRef FF_88)) - (portRef SP (instanceRef FF_87)) - (portRef SP (instanceRef FF_86)) - (portRef SP (instanceRef FF_85)) - (portRef SP (instanceRef FF_84)) - (portRef SP (instanceRef FF_83)) - (portRef SP (instanceRef FF_82)) - (portRef SP (instanceRef FF_81)) - (portRef SP (instanceRef FF_80)) - (portRef SP (instanceRef FF_79)) - (portRef SP (instanceRef FF_78)) - (portRef SP (instanceRef FF_77)) - (portRef SP (instanceRef FF_76)) - (portRef SP (instanceRef FF_75)) - (portRef SP (instanceRef FF_74)) - (portRef SP (instanceRef FF_73)) - (portRef SP (instanceRef FF_72)) - (portRef SP (instanceRef FF_71)) - (portRef SP (instanceRef FF_70)) - (portRef SP (instanceRef FF_69)) - (portRef SP (instanceRef FF_68)) - (portRef SP (instanceRef FF_67)) - (portRef B1 (instanceRef full_cmp_ci_a)) - (portRef A1 (instanceRef full_cmp_ci_a)) - (portRef B1 (instanceRef af_d_cmp_ci_a)))) + (portRef A1 (instanceRef ae_cmp_ci_a)) + (portRef Z (instanceRef AND2_t18)) + (portRef CSR0 (instanceRef pdp_ram_0_0_0)) + (portRef SP (instanceRef FF_66)) + (portRef SP (instanceRef FF_65)) + (portRef SP (instanceRef FF_64)) + (portRef SP (instanceRef FF_63)) + (portRef SP (instanceRef FF_62)) + (portRef SP (instanceRef FF_61)) + (portRef SP (instanceRef FF_60)) + (portRef SP (instanceRef FF_59)) + (portRef SP (instanceRef FF_58)) + (portRef SP (instanceRef FF_57)) + (portRef SP (instanceRef FF_56)) + (portRef SP (instanceRef FF_55)) + (portRef SP (instanceRef FF_54)) + (portRef SP (instanceRef FF_53)) + (portRef SP (instanceRef FF_52)) + (portRef SP (instanceRef FF_51)) + (portRef SP (instanceRef FF_50)) + (portRef SP (instanceRef FF_49)) + (portRef SP (instanceRef FF_48)) + (portRef SP (instanceRef FF_47)) + (portRef SP (instanceRef FF_46)) + (portRef SP (instanceRef FF_45)) + (portRef SP (instanceRef FF_44)) + (portRef SP (instanceRef FF_43)) + (portRef B1 (instanceRef empty_cmp_ci_a)) + (portRef A1 (instanceRef empty_cmp_ci_a)) + (portRef B1 (instanceRef ae_cmp_ci_a)))) (net cmp_ci_2 (joined - (portRef CI (instanceRef af_d_cmp_0)) - (portRef COUT (instanceRef af_d_cmp_ci_a)))) - (net wcnt_reg_0 + (portRef CI (instanceRef ae_cmp_0)) + (portRef COUT (instanceRef ae_cmp_ci_a)))) + (net rcnt_reg_0 (joined - (portRef A0 (instanceRef af_d_cmp_0)) + (portRef B0 (instanceRef ae_cmp_0)) (portRef Q (instanceRef FF_10)))) - (net wcnt_reg_1 + (net rcnt_reg_1 (joined - (portRef A1 (instanceRef af_d_cmp_0)) + (portRef B1 (instanceRef ae_cmp_0)) (portRef Q (instanceRef FF_9)))) (net co0_5 (joined - (portRef CI (instanceRef af_d_cmp_1)) - (portRef GE (instanceRef af_d_cmp_0)))) - (net wcnt_reg_2 + (portRef CI (instanceRef ae_cmp_1)) + (portRef GE (instanceRef ae_cmp_0)))) + (net rcnt_reg_2 (joined - (portRef A0 (instanceRef af_d_cmp_1)) + (portRef B0 (instanceRef ae_cmp_1)) (portRef Q (instanceRef FF_8)))) - (net wcnt_reg_3 + (net rcnt_reg_3 (joined - (portRef A1 (instanceRef af_d_cmp_1)) + (portRef B1 (instanceRef ae_cmp_1)) (portRef Q (instanceRef FF_7)))) (net co1_5 (joined - (portRef CI (instanceRef af_d_cmp_2)) - (portRef GE (instanceRef af_d_cmp_1)))) - (net wcnt_reg_4 + (portRef CI (instanceRef ae_cmp_2)) + (portRef GE (instanceRef ae_cmp_1)))) + (net rcnt_reg_4 (joined - (portRef A0 (instanceRef af_d_cmp_2)) + (portRef B0 (instanceRef ae_cmp_2)) (portRef Q (instanceRef FF_6)))) - (net wcnt_reg_5 + (net rcnt_reg_5 (joined - (portRef A1 (instanceRef af_d_cmp_2)) + (portRef B1 (instanceRef ae_cmp_2)) (portRef Q (instanceRef FF_5)))) (net co2_5 (joined - (portRef CI (instanceRef af_d_cmp_3)) - (portRef GE (instanceRef af_d_cmp_2)))) - (net wcnt_reg_6 + (portRef CI (instanceRef ae_cmp_3)) + (portRef GE (instanceRef ae_cmp_2)))) + (net rcnt_reg_6 (joined - (portRef A0 (instanceRef af_d_cmp_3)) + (portRef B0 (instanceRef ae_cmp_3)) + (portRef A (instanceRef INV_0)) + (portRef B (instanceRef AND2_t0)) (portRef Q (instanceRef FF_4)))) - (net wcnt_reg_7 + (net ae_clrsig (joined - (portRef A1 (instanceRef af_d_cmp_3)) - (portRef Q (instanceRef FF_3)))) - (net af_d + (portRef B1 (instanceRef ae_cmp_3)) + (portRef Z (instanceRef AND2_t1)))) + (net ae_setsig + (joined + (portRef A1 (instanceRef ae_cmp_3)) + (portRef Z (instanceRef AND2_t0)))) + (net ae_d (joined (portRef S0 (instanceRef a2)) (portRef D (instanceRef FF_0)))) - (net af_d_c + (net ae_d_c (joined (portRef CI (instanceRef a2)) - (portRef GE (instanceRef af_d_cmp_3)))) + (portRef GE (instanceRef ae_cmp_3)))) (net scuba_vlo (joined (portRef Z (instanceRef scuba_vlo_inst)) @@ -2223,10 +2256,10 @@ (portRef B1 (instanceRef precin_inst284)) (portRef A0 (instanceRef precin_inst284)) (portRef A1 (instanceRef precin_inst284)) - (portRef B0 (instanceRef wcnt_0)) - (portRef B0 (instanceRef wcnt_4)) - (portRef B1 (instanceRef wcnt_4)) - (portRef A1 (instanceRef wcnt_4)) + (portRef B0 (instanceRef rcnt_0)) + (portRef B0 (instanceRef rcnt_4)) + (portRef B1 (instanceRef rcnt_4)) + (portRef A1 (instanceRef rcnt_4)) (portRef CI (instanceRef empty_cmp_ci_a)) (portRef B0 (instanceRef empty_cmp_ci_a)) (portRef A0 (instanceRef empty_cmp_ci_a)) @@ -2241,28 +2274,27 @@ (portRef B1 (instanceRef a1)) (portRef A0 (instanceRef a1)) (portRef A1 (instanceRef a1)) - (portRef CI (instanceRef af_d_cmp_ci_a)) - (portRef B0 (instanceRef af_d_cmp_ci_a)) - (portRef A0 (instanceRef af_d_cmp_ci_a)) - (portRef B1 (instanceRef af_d_cmp_3)) + (portRef CI (instanceRef ae_cmp_ci_a)) + (portRef B0 (instanceRef ae_cmp_ci_a)) + (portRef A0 (instanceRef ae_cmp_ci_a)) (portRef B0 (instanceRef a2)) (portRef B1 (instanceRef a2)) (portRef A0 (instanceRef a2)) (portRef A1 (instanceRef a2)))) - (net partial_full + (net partial_empty (joined - (portRef AlmostFull) + (portRef AlmostEmpty) (portRef Q (instanceRef FF_0)))) (net Full (joined (portRef Full) (portRef Q (instanceRef FF_1)) - (portRef A (instanceRef INV_1)))) + (portRef A (instanceRef INV_2)))) (net Empty (joined (portRef Empty) (portRef Q (instanceRef FF_2)) - (portRef A (instanceRef INV_0)))) + (portRef A (instanceRef INV_1)))) (net dataout35 (joined (portRef (member Q 0)) @@ -2407,42 +2439,42 @@ (joined (portRef (member Q 35)) (portRef DO18 (instanceRef pdp_ram_0_0_0)))) - (net AmFullThresh6 + (net AmEmptyThresh6 (joined - (portRef (member AmFullThresh 0)) - (portRef B0 (instanceRef af_d_cmp_3)))) - (net AmFullThresh5 + (portRef (member AmEmptyThresh 0)) + (portRef A0 (instanceRef ae_cmp_3)))) + (net AmEmptyThresh5 (joined - (portRef (member AmFullThresh 1)) - (portRef B1 (instanceRef af_d_cmp_2)))) - (net AmFullThresh4 + (portRef (member AmEmptyThresh 1)) + (portRef A1 (instanceRef ae_cmp_2)))) + (net AmEmptyThresh4 (joined - (portRef (member AmFullThresh 2)) - (portRef B0 (instanceRef af_d_cmp_2)))) - (net AmFullThresh3 + (portRef (member AmEmptyThresh 2)) + (portRef A0 (instanceRef ae_cmp_2)))) + (net AmEmptyThresh3 (joined - (portRef (member AmFullThresh 3)) - (portRef B1 (instanceRef af_d_cmp_1)))) - (net AmFullThresh2 + (portRef (member AmEmptyThresh 3)) + (portRef A1 (instanceRef ae_cmp_1)))) + (net AmEmptyThresh2 (joined - (portRef (member AmFullThresh 4)) - (portRef B0 (instanceRef af_d_cmp_1)))) - (net AmFullThresh1 + (portRef (member AmEmptyThresh 4)) + (portRef A0 (instanceRef ae_cmp_1)))) + (net AmEmptyThresh1 (joined - (portRef (member AmFullThresh 5)) - (portRef B1 (instanceRef af_d_cmp_0)))) - (net AmFullThresh0 + (portRef (member AmEmptyThresh 5)) + (portRef A1 (instanceRef ae_cmp_0)))) + (net AmEmptyThresh0 (joined - (portRef (member AmFullThresh 6)) - (portRef B0 (instanceRef af_d_cmp_0)))) + (portRef (member AmEmptyThresh 6)) + (portRef A0 (instanceRef ae_cmp_0)))) (net RPRst (joined (portRef RPReset) - (portRef B (instanceRef OR2_t15)))) + (portRef B (instanceRef OR2_t17)))) (net reset (joined (portRef Reset) - (portRef A (instanceRef OR2_t15)) + (portRef A (instanceRef OR2_t17)) (portRef RST (instanceRef pdp_ram_0_0_0)) (portRef PD (instanceRef FF_90)) (portRef CD (instanceRef FF_89)) @@ -2484,24 +2516,15 @@ (portRef CD (instanceRef FF_21)) (portRef CD (instanceRef FF_20)) (portRef CD (instanceRef FF_19)) - (portRef CD (instanceRef FF_10)) - (portRef CD (instanceRef FF_9)) - (portRef CD (instanceRef FF_8)) - (portRef CD (instanceRef FF_7)) - (portRef CD (instanceRef FF_6)) - (portRef CD (instanceRef FF_5)) - (portRef CD (instanceRef FF_4)) - (portRef CD (instanceRef FF_3)) - (portRef CD (instanceRef FF_1)) - (portRef CD (instanceRef FF_0)))) + (portRef CD (instanceRef FF_1)))) (net rden (joined (portRef RdEn) - (portRef A (instanceRef AND2_t16)))) + (portRef A (instanceRef AND2_t18)))) (net wren (joined (portRef WrEn) - (portRef A (instanceRef AND2_t17)))) + (portRef A (instanceRef AND2_t19)))) (net rclk (joined (portRef RdClock) @@ -2546,7 +2569,16 @@ (portRef CK (instanceRef FF_21)) (portRef CK (instanceRef FF_20)) (portRef CK (instanceRef FF_19)) - (portRef CK (instanceRef FF_2)))) + (portRef CK (instanceRef FF_10)) + (portRef CK (instanceRef FF_9)) + (portRef CK (instanceRef FF_8)) + (portRef CK (instanceRef FF_7)) + (portRef CK (instanceRef FF_6)) + (portRef CK (instanceRef FF_5)) + (portRef CK (instanceRef FF_4)) + (portRef CK (instanceRef FF_3)) + (portRef CK (instanceRef FF_2)) + (portRef CK (instanceRef FF_0)))) (net wclk (joined (portRef WrClock) @@ -2591,16 +2623,7 @@ (portRef CK (instanceRef FF_13)) (portRef CK (instanceRef FF_12)) (portRef CK (instanceRef FF_11)) - (portRef CK (instanceRef FF_10)) - (portRef CK (instanceRef FF_9)) - (portRef CK (instanceRef FF_8)) - (portRef CK (instanceRef FF_7)) - (portRef CK (instanceRef FF_6)) - (portRef CK (instanceRef FF_5)) - (portRef CK (instanceRef FF_4)) - (portRef CK (instanceRef FF_3)) - (portRef CK (instanceRef FF_1)) - (portRef CK (instanceRef FF_0)))) + (portRef CK (instanceRef FF_1)))) (net datain35 (joined (portRef (member Data 0)) diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.ipx b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.ipx index d554bb6..04cb07b 100644 --- a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.ipx +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.ipx @@ -1,9 +1,9 @@ - + - - - - + + + + diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.jhd b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.jhd index e69de29..f513696 100644 --- a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.jhd +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.jhd @@ -0,0 +1,343 @@ +MODULE FIFO_DC_36x128_DynThr_OutReg DEFIN FIFO_DC_36x128_DynThr_OutReg.vhd + SUBMODULE FADD2B + INSTANCE a2 + SUBMODULE VLO + INSTANCE scuba_vlo_inst + SUBMODULE AGEB2 + INSTANCE ae_cmp_3 + SUBMODULE AGEB2 + INSTANCE ae_cmp_2 + SUBMODULE AGEB2 + INSTANCE ae_cmp_1 + SUBMODULE AGEB2 + INSTANCE ae_cmp_0 + SUBMODULE FADD2B + INSTANCE ae_cmp_ci_a + SUBMODULE FADD2B + INSTANCE a1 + SUBMODULE AGEB2 + INSTANCE full_cmp_3 + SUBMODULE AGEB2 + INSTANCE full_cmp_2 + SUBMODULE AGEB2 + INSTANCE full_cmp_1 + SUBMODULE AGEB2 + INSTANCE full_cmp_0 + SUBMODULE FADD2B + INSTANCE full_cmp_ci_a + SUBMODULE FADD2B + INSTANCE a0 + SUBMODULE AGEB2 + INSTANCE empty_cmp_3 + SUBMODULE AGEB2 + INSTANCE empty_cmp_2 + SUBMODULE AGEB2 + INSTANCE empty_cmp_1 + SUBMODULE AGEB2 + INSTANCE empty_cmp_0 + SUBMODULE FADD2B + INSTANCE empty_cmp_ci_a + SUBMODULE FSUB2B + INSTANCE rcnt_4 + SUBMODULE FSUB2B + INSTANCE rcnt_3 + SUBMODULE FSUB2B + INSTANCE rcnt_2 + SUBMODULE FSUB2B + INSTANCE rcnt_1 + SUBMODULE FSUB2B + INSTANCE rcnt_0 + SUBMODULE VHI + INSTANCE scuba_vhi_inst + SUBMODULE FADD2B + INSTANCE precin_inst284 + SUBMODULE CU2 + INSTANCE r_gctr_3 + SUBMODULE CU2 + INSTANCE r_gctr_2 + SUBMODULE CU2 + INSTANCE r_gctr_1 + SUBMODULE CU2 + INSTANCE r_gctr_0 + SUBMODULE FADD2B + INSTANCE r_gctr_cia + SUBMODULE CU2 + INSTANCE w_gctr_3 + SUBMODULE CU2 + INSTANCE w_gctr_2 + SUBMODULE CU2 + INSTANCE w_gctr_1 + SUBMODULE CU2 + INSTANCE w_gctr_0 + SUBMODULE FADD2B + INSTANCE w_gctr_cia + SUBMODULE FD1S3BX + INSTANCE FF_0 + SUBMODULE FD1S3DX + INSTANCE FF_1 + SUBMODULE FD1S3BX + INSTANCE FF_2 + SUBMODULE FD1S3DX + INSTANCE FF_3 + SUBMODULE FD1S3DX + INSTANCE FF_4 + SUBMODULE FD1S3DX + INSTANCE FF_5 + SUBMODULE FD1S3DX + INSTANCE FF_6 + SUBMODULE FD1S3DX + INSTANCE FF_7 + SUBMODULE FD1S3DX + INSTANCE FF_8 + SUBMODULE FD1S3DX + INSTANCE FF_9 + SUBMODULE FD1S3DX + INSTANCE FF_10 + SUBMODULE FD1S3DX + INSTANCE FF_11 + SUBMODULE FD1S3DX + INSTANCE FF_12 + SUBMODULE FD1S3DX + INSTANCE FF_13 + SUBMODULE FD1S3DX + INSTANCE FF_14 + SUBMODULE FD1S3DX + INSTANCE FF_15 + SUBMODULE FD1S3DX + INSTANCE FF_16 + SUBMODULE FD1S3DX + INSTANCE FF_17 + SUBMODULE FD1S3DX + INSTANCE FF_18 + SUBMODULE FD1S3DX + INSTANCE FF_19 + SUBMODULE FD1S3DX + INSTANCE FF_20 + SUBMODULE FD1S3DX + INSTANCE FF_21 + SUBMODULE FD1S3DX + INSTANCE FF_22 + SUBMODULE FD1S3DX + INSTANCE FF_23 + SUBMODULE FD1S3DX + INSTANCE FF_24 + SUBMODULE FD1S3DX + INSTANCE FF_25 + SUBMODULE FD1S3DX + INSTANCE FF_26 + SUBMODULE FD1S3DX + INSTANCE FF_27 + SUBMODULE FD1S3DX + INSTANCE FF_28 + SUBMODULE FD1S3DX + INSTANCE FF_29 + SUBMODULE FD1S3DX + INSTANCE FF_30 + SUBMODULE FD1S3DX + INSTANCE FF_31 + SUBMODULE FD1S3DX + INSTANCE FF_32 + SUBMODULE FD1S3DX + INSTANCE FF_33 + SUBMODULE FD1S3DX + INSTANCE FF_34 + SUBMODULE FD1S3DX + INSTANCE FF_35 + SUBMODULE FD1S3DX + INSTANCE FF_36 + SUBMODULE FD1S3DX + INSTANCE FF_37 + SUBMODULE FD1S3DX + INSTANCE FF_38 + SUBMODULE FD1S3DX + INSTANCE FF_39 + SUBMODULE FD1S3DX + INSTANCE FF_40 + SUBMODULE FD1S3DX + INSTANCE FF_41 + SUBMODULE FD1S3DX + INSTANCE FF_42 + SUBMODULE FD1P3DX + INSTANCE FF_43 + SUBMODULE FD1P3DX + INSTANCE FF_44 + SUBMODULE FD1P3DX + INSTANCE FF_45 + SUBMODULE FD1P3DX + INSTANCE FF_46 + SUBMODULE FD1P3DX + INSTANCE FF_47 + SUBMODULE FD1P3DX + INSTANCE FF_48 + SUBMODULE FD1P3DX + INSTANCE FF_49 + SUBMODULE FD1P3DX + INSTANCE FF_50 + SUBMODULE FD1P3DX + INSTANCE FF_51 + SUBMODULE FD1P3DX + INSTANCE FF_52 + SUBMODULE FD1P3DX + INSTANCE FF_53 + SUBMODULE FD1P3DX + INSTANCE FF_54 + SUBMODULE FD1P3DX + INSTANCE FF_55 + SUBMODULE FD1P3DX + INSTANCE FF_56 + SUBMODULE FD1P3DX + INSTANCE FF_57 + SUBMODULE FD1P3DX + INSTANCE FF_58 + SUBMODULE FD1P3DX + INSTANCE FF_59 + SUBMODULE FD1P3DX + INSTANCE FF_60 + SUBMODULE FD1P3DX + INSTANCE FF_61 + SUBMODULE FD1P3DX + INSTANCE FF_62 + SUBMODULE FD1P3DX + INSTANCE FF_63 + SUBMODULE FD1P3DX + INSTANCE FF_64 + SUBMODULE FD1P3DX + INSTANCE FF_65 + SUBMODULE FD1P3BX + INSTANCE FF_66 + SUBMODULE FD1P3DX + INSTANCE FF_67 + SUBMODULE FD1P3DX + INSTANCE FF_68 + SUBMODULE FD1P3DX + INSTANCE FF_69 + SUBMODULE FD1P3DX + INSTANCE FF_70 + SUBMODULE FD1P3DX + INSTANCE FF_71 + SUBMODULE FD1P3DX + INSTANCE FF_72 + SUBMODULE FD1P3DX + INSTANCE FF_73 + SUBMODULE FD1P3DX + INSTANCE FF_74 + SUBMODULE FD1P3DX + INSTANCE FF_75 + SUBMODULE FD1P3DX + INSTANCE FF_76 + SUBMODULE FD1P3DX + INSTANCE FF_77 + SUBMODULE FD1P3DX + INSTANCE FF_78 + SUBMODULE FD1P3DX + INSTANCE FF_79 + SUBMODULE FD1P3DX + INSTANCE FF_80 + SUBMODULE FD1P3DX + INSTANCE FF_81 + SUBMODULE FD1P3DX + INSTANCE FF_82 + SUBMODULE FD1P3DX + INSTANCE FF_83 + SUBMODULE FD1P3DX + INSTANCE FF_84 + SUBMODULE FD1P3DX + INSTANCE FF_85 + SUBMODULE FD1P3DX + INSTANCE FF_86 + SUBMODULE FD1P3DX + INSTANCE FF_87 + SUBMODULE FD1P3DX + INSTANCE FF_88 + SUBMODULE FD1P3DX + INSTANCE FF_89 + SUBMODULE FD1P3BX + INSTANCE FF_90 + SUBMODULE PDPW16KC + INSTANCE pdp_ram_0_0_0 + SUBMODULE AND2 + INSTANCE AND2_t0 + SUBMODULE AND2 + INSTANCE AND2_t1 + SUBMODULE INV + INSTANCE INV_0 + SUBMODULE ROM16X1A + INSTANCE LUT4_0 + SUBMODULE ROM16X1A + INSTANCE LUT4_1 + SUBMODULE ROM16X1A + INSTANCE LUT4_2 + SUBMODULE ROM16X1A + INSTANCE LUT4_3 + SUBMODULE XOR2 + INSTANCE XOR2_t2 + SUBMODULE ROM16X1A + INSTANCE LUT4_4 + SUBMODULE ROM16X1A + INSTANCE LUT4_5 + SUBMODULE ROM16X1A + INSTANCE LUT4_6 + SUBMODULE ROM16X1A + INSTANCE LUT4_7 + SUBMODULE ROM16X1A + INSTANCE LUT4_8 + SUBMODULE ROM16X1A + INSTANCE LUT4_9 + SUBMODULE ROM16X1A + INSTANCE LUT4_10 + SUBMODULE ROM16X1A + INSTANCE LUT4_11 + SUBMODULE ROM16X1A + INSTANCE LUT4_12 + SUBMODULE ROM16X1A + INSTANCE LUT4_13 + SUBMODULE ROM16X1A + INSTANCE LUT4_14 + SUBMODULE ROM16X1A + INSTANCE LUT4_15 + SUBMODULE ROM16X1A + INSTANCE LUT4_16 + SUBMODULE ROM16X1A + INSTANCE LUT4_17 + SUBMODULE ROM16X1A + INSTANCE LUT4_18 + SUBMODULE ROM16X1A + INSTANCE LUT4_19 + SUBMODULE XOR2 + INSTANCE XOR2_t3 + SUBMODULE XOR2 + INSTANCE XOR2_t4 + SUBMODULE XOR2 + INSTANCE XOR2_t5 + SUBMODULE XOR2 + INSTANCE XOR2_t6 + SUBMODULE XOR2 + INSTANCE XOR2_t7 + SUBMODULE XOR2 + INSTANCE XOR2_t8 + SUBMODULE XOR2 + INSTANCE XOR2_t9 + SUBMODULE XOR2 + INSTANCE XOR2_t10 + SUBMODULE XOR2 + INSTANCE XOR2_t11 + SUBMODULE XOR2 + INSTANCE XOR2_t12 + SUBMODULE XOR2 + INSTANCE XOR2_t13 + SUBMODULE XOR2 + INSTANCE XOR2_t14 + SUBMODULE XOR2 + INSTANCE XOR2_t15 + SUBMODULE XOR2 + INSTANCE XOR2_t16 + SUBMODULE OR2 + INSTANCE OR2_t17 + SUBMODULE INV + INSTANCE INV_1 + SUBMODULE AND2 + INSTANCE AND2_t18 + SUBMODULE INV + INSTANCE INV_2 + SUBMODULE AND2 + INSTANCE AND2_t19 diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.lpc b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.lpc index e2c0325..353174b 100644 --- a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.lpc +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=FIFO_DC -CoreRevision=5.7 +CoreRevision=5.8 ModuleName=FIFO_DC_36x128_DynThr_OutReg SourceFormat=VHDL ParameterFileVersion=1.0 -Date=04/09/2015 -Time=09:22:22 +Date=07/06/2018 +Time=11:51:35 [Parameters] Verilog=0 @@ -34,11 +34,11 @@ RDepth=128 RWidth=36 regout=1 CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold +EmpFlg=1 +PeMode=Dynamic - Single Threshold PeAssert=10 PeDeassert=12 -FullFlg=1 +FullFlg=0 PfMode=Dynamic - Single Threshold PfAssert=508 PfDeassert=506 @@ -47,4 +47,4 @@ WDataCount=0 EnECC=0 [Command] -cmd_line= -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 7 -data_width 36 -num_words 128 -rdata_width 36 -outdata REGISTERED -no_enable -pe -1 -pf 0 +cmd_line= -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 7 -data_width 36 -num_words 128 -rdata_width 36 -outdata REGISTERED -no_enable -pe 0 -pf -1 diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.srp b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.srp index e214ba0..2c2ea91 100644 --- a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.srp +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.srp @@ -1,19 +1,19 @@ -SCUBA, Version Diamond (64-bit) 3.4.0.80 -Thu Apr 9 09:22:22 2015 +SCUBA, Version Diamond (64-bit) 3.9.1.119 +Fri Jul 6 11:51:36 2018 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. +Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. - Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 7 -data_width 36 -num_words 128 -rdata_width 36 -outdata REGISTERED -no_enable -pe -1 -pf 0 + Issued command : /d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 7 -data_width 36 -num_words 128 -rdata_width 36 -outdata REGISTERED -no_enable -pe 0 -pf -1 Circuit name : FIFO_DC_36x128_DynThr_OutReg Module type : ebfifo - Module Version : 5.7 + Module Version : 5.8 Ports : - Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmFullThresh[6:0] - Outputs : Q[35:0], Empty, Full, AlmostFull + Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[6:0] + Outputs : Q[35:0], Empty, Full, AlmostEmpty I/O buffer : not inserted EDIF output : FIFO_DC_36x128_DynThr_OutReg.edn VHDL output : FIFO_DC_36x128_DynThr_OutReg.vhd @@ -24,20 +24,20 @@ Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. Report output : FIFO_DC_36x128_DynThr_OutReg.srp Element Usage : AGEB2 : 12 - AND2 : 2 + AND2 : 4 CU2 : 8 FADD2B : 9 FSUB2B : 5 FD1P3BX : 2 FD1P3DX : 46 - FD1S3BX : 1 - FD1S3DX : 42 - INV : 2 + FD1S3BX : 2 + FD1S3DX : 41 + INV : 3 OR2 : 1 ROM16X1A : 20 XOR2 : 15 PDPW16KC : 1 Estimated Resource Usage: - LUT : 106 + LUT : 108 EBR : 1 Reg : 91 diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd index 5df39e9..8eb7a66 100644 --- a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 --- Module Version: 5.7 ---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -rdata_width 36 -regout -no_enable -pe -1 -pf 0 +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.1.119 +-- Module Version: 5.8 +--/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 128 -width 36 -depth 128 -rdata_width 36 -regout -no_enable -pe 0 -pf -1 --- Thu Apr 9 09:22:22 2015 +-- Fri Jul 6 11:51:36 2018 library IEEE; use IEEE.std_logic_1164.all; @@ -20,11 +20,11 @@ entity FIFO_DC_36x128_DynThr_OutReg is RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - AmFullThresh: in std_logic_vector(6 downto 0); + AmEmptyThresh: in std_logic_vector(6 downto 0); Q: out std_logic_vector(35 downto 0); Empty: out std_logic; Full: out std_logic; - AlmostFull: out std_logic); + AlmostEmpty: out std_logic); end FIFO_DC_36x128_DynThr_OutReg; architecture Structure of FIFO_DC_36x128_DynThr_OutReg is @@ -34,6 +34,7 @@ architecture Structure of FIFO_DC_36x128_DynThr_OutReg is signal invout_0: std_logic; signal w_g2b_xor_cluster_1: std_logic; signal r_g2b_xor_cluster_1: std_logic; + signal rcnt_reg_6_inv: std_logic; signal w_gdata_0: std_logic; signal w_gdata_1: std_logic; signal w_gdata_2: std_logic; @@ -112,9 +113,10 @@ architecture Structure of FIFO_DC_36x128_DynThr_OutReg is signal r_gcount_w6: std_logic; signal r_gcount_w27: std_logic; signal r_gcount_w7: std_logic; + signal rcnt_reg_7: std_logic; signal empty_i: std_logic; - signal rRst: std_logic; signal full_i: std_logic; + signal rRst: std_logic; signal iwcount_0: std_logic; signal iwcount_1: std_logic; signal w_gctr_ci: std_logic; @@ -143,22 +145,21 @@ architecture Structure of FIFO_DC_36x128_DynThr_OutReg is signal co3_1: std_logic; signal co2_1: std_logic; signal rcount_7: std_logic; - signal wcnt_sub_0: std_logic; + signal rcnt_sub_0: std_logic; signal precin: std_logic; signal scuba_vhi: std_logic; - signal wcnt_sub_1: std_logic; - signal wcnt_sub_2: std_logic; + signal rcnt_sub_1: std_logic; + signal rcnt_sub_2: std_logic; signal co0_2: std_logic; - signal wcnt_sub_3: std_logic; - signal wcnt_sub_4: std_logic; + signal rcnt_sub_3: std_logic; + signal rcnt_sub_4: std_logic; signal co1_2: std_logic; - signal wcnt_sub_5: std_logic; - signal wcnt_sub_6: std_logic; + signal rcnt_sub_5: std_logic; + signal rcnt_sub_6: std_logic; signal co2_2: std_logic; - signal wcnt_sub_7: std_logic; + signal rcnt_sub_7: std_logic; signal co3_2: std_logic; - signal wcnt_sub_msb: std_logic; - signal rden_i: std_logic; + signal rcnt_sub_msb: std_logic; signal cmp_ci: std_logic; signal wcount_r0: std_logic; signal wcount_r1: std_logic; @@ -181,6 +182,7 @@ architecture Structure of FIFO_DC_36x128_DynThr_OutReg is signal empty_cmp_set: std_logic; signal empty_d: std_logic; signal empty_d_c: std_logic; + signal wren_i: std_logic; signal cmp_ci_1: std_logic; signal rcount_w0: std_logic; signal rcount_w1: std_logic; @@ -203,21 +205,22 @@ architecture Structure of FIFO_DC_36x128_DynThr_OutReg is signal full_cmp_set: std_logic; signal full_d: std_logic; signal full_d_c: std_logic; - signal wren_i: std_logic; + signal rden_i: std_logic; signal cmp_ci_2: std_logic; - signal wcnt_reg_0: std_logic; - signal wcnt_reg_1: std_logic; + signal rcnt_reg_0: std_logic; + signal rcnt_reg_1: std_logic; signal co0_5: std_logic; - signal wcnt_reg_2: std_logic; - signal wcnt_reg_3: std_logic; + signal rcnt_reg_2: std_logic; + signal rcnt_reg_3: std_logic; signal co1_5: std_logic; - signal wcnt_reg_4: std_logic; - signal wcnt_reg_5: std_logic; + signal rcnt_reg_4: std_logic; + signal rcnt_reg_5: std_logic; signal co2_5: std_logic; - signal wcnt_reg_6: std_logic; - signal wcnt_reg_7: std_logic; - signal af_d: std_logic; - signal af_d_c: std_logic; + signal rcnt_reg_6: std_logic; + signal ae_clrsig: std_logic; + signal ae_setsig: std_logic; + signal ae_d: std_logic; + signal ae_d_c: std_logic; signal scuba_vlo: std_logic; -- local component declarations @@ -438,61 +441,61 @@ architecture Structure of FIFO_DC_36x128_DynThr_OutReg is begin -- component instantiation statements - AND2_t17: AND2 + AND2_t19: AND2 port map (A=>WrEn, B=>invout_1, Z=>wren_i); - INV_1: INV + INV_2: INV port map (A=>full_i, Z=>invout_1); - AND2_t16: AND2 + AND2_t18: AND2 port map (A=>RdEn, B=>invout_0, Z=>rden_i); - INV_0: INV + INV_1: INV port map (A=>empty_i, Z=>invout_0); - OR2_t15: OR2 + OR2_t17: OR2 port map (A=>Reset, B=>RPReset, Z=>rRst); - XOR2_t14: XOR2 + XOR2_t16: XOR2 port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - XOR2_t13: XOR2 + XOR2_t15: XOR2 port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - XOR2_t12: XOR2 + XOR2_t14: XOR2 port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - XOR2_t11: XOR2 + XOR2_t13: XOR2 port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - XOR2_t10: XOR2 + XOR2_t12: XOR2 port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - XOR2_t9: XOR2 + XOR2_t11: XOR2 port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - XOR2_t8: XOR2 + XOR2_t10: XOR2 port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - XOR2_t7: XOR2 + XOR2_t9: XOR2 port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - XOR2_t6: XOR2 + XOR2_t8: XOR2 port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - XOR2_t5: XOR2 + XOR2_t7: XOR2 port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - XOR2_t4: XOR2 + XOR2_t6: XOR2 port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - XOR2_t3: XOR2 + XOR2_t5: XOR2 port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - XOR2_t2: XOR2 + XOR2_t4: XOR2 port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - XOR2_t1: XOR2 + XOR2_t3: XOR2 port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); LUT4_19: ROM16X1A @@ -579,8 +582,8 @@ begin port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - XOR2_t0: XOR2 - port map (A=>wcount_7, B=>r_gcount_w27, Z=>wcnt_sub_msb); + XOR2_t2: XOR2 + port map (A=>w_gcount_r27, B=>rcount_7, Z=>rcnt_sub_msb); LUT4_3: ROM16X1A generic map (initval=> X"0410") @@ -602,6 +605,15 @@ begin port map (AD3=>wptr_7, AD2=>wcount_7, AD1=>r_gcount_w27, AD0=>scuba_vlo, DO0=>full_cmp_clr); + INV_0: INV + port map (A=>rcnt_reg_6, Z=>rcnt_reg_6_inv); + + AND2_t1: AND2 + port map (A=>rcnt_reg_7, B=>rcnt_reg_6_inv, Z=>ae_clrsig); + + AND2_t0: AND2 + port map (A=>rcnt_reg_7, B=>rcnt_reg_6, Z=>ae_setsig); + pdp_ram_0_0_0: PDPW16KC generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) @@ -933,28 +945,28 @@ begin port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); FF_10: FD1S3DX - port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); + port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); FF_9: FD1S3DX - port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); + port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); FF_8: FD1S3DX - port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); + port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); FF_7: FD1S3DX - port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); + port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); FF_6: FD1S3DX - port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); + port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); FF_5: FD1S3DX - port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); + port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); FF_4: FD1S3DX - port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); + port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); FF_3: FD1S3DX - port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); + port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); FF_2: FD1S3BX port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); @@ -962,8 +974,8 @@ begin FF_1: FD1S3DX port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - FF_0: FD1S3DX - port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + FF_0: FD1S3BX + port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); w_gctr_cia: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, @@ -1015,29 +1027,29 @@ begin scuba_vhi_inst: VHI port map (Z=>scuba_vhi); - wcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo, - B1=>rcount_w0, BI=>precin, BOUT=>co0_2, S0=>open, - S1=>wcnt_sub_0); - - wcnt_1: FSUB2B - port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w1, - B1=>rcount_w2, BI=>co0_2, BOUT=>co1_2, S0=>wcnt_sub_1, - S1=>wcnt_sub_2); - - wcnt_2: FSUB2B - port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w3, - B1=>r_g2b_xor_cluster_0, BI=>co1_2, BOUT=>co2_2, - S0=>wcnt_sub_3, S1=>wcnt_sub_4); - - wcnt_3: FSUB2B - port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w5, - B1=>rcount_w6, BI=>co2_2, BOUT=>co3_2, S0=>wcnt_sub_5, - S1=>wcnt_sub_6); - - wcnt_4: FSUB2B - port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, BI=>co3_2, BOUT=>open, S0=>wcnt_sub_7, + rcnt_0: FSUB2B + port map (A0=>scuba_vhi, A1=>wcount_r0, B0=>scuba_vlo, + B1=>rcount_0, BI=>precin, BOUT=>co0_2, S0=>open, + S1=>rcnt_sub_0); + + rcnt_1: FSUB2B + port map (A0=>wcount_r1, A1=>wcount_r2, B0=>rcount_1, + B1=>rcount_2, BI=>co0_2, BOUT=>co1_2, S0=>rcnt_sub_1, + S1=>rcnt_sub_2); + + rcnt_2: FSUB2B + port map (A0=>wcount_r3, A1=>w_g2b_xor_cluster_0, B0=>rcount_3, + B1=>rcount_4, BI=>co1_2, BOUT=>co2_2, S0=>rcnt_sub_3, + S1=>rcnt_sub_4); + + rcnt_3: FSUB2B + port map (A0=>wcount_r5, A1=>wcount_r6, B0=>rcount_5, + B1=>rcount_6, BI=>co2_2, BOUT=>co3_2, S0=>rcnt_sub_5, + S1=>rcnt_sub_6); + + rcnt_4: FSUB2B + port map (A0=>rcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co3_2, BOUT=>open, S0=>rcnt_sub_7, S1=>open); empty_cmp_ci_a: FADD2B @@ -1090,32 +1102,32 @@ begin B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, S1=>open); - af_d_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + ae_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); - af_d_cmp_0: AGEB2 - port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), - B1=>AmFullThresh(1), CI=>cmp_ci_2, GE=>co0_5); + ae_cmp_0: AGEB2 + port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), + B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_5); - af_d_cmp_1: AGEB2 - port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), - B1=>AmFullThresh(3), CI=>co0_5, GE=>co1_5); + ae_cmp_1: AGEB2 + port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), + B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_5, GE=>co1_5); - af_d_cmp_2: AGEB2 - port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), - B1=>AmFullThresh(5), CI=>co1_5, GE=>co2_5); + ae_cmp_2: AGEB2 + port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), + B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_5, GE=>co2_5); - af_d_cmp_3: AGEB2 - port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), - B1=>scuba_vlo, CI=>co2_5, GE=>af_d_c); + ae_cmp_3: AGEB2 + port map (A0=>AmEmptyThresh(6), A1=>ae_setsig, B0=>rcnt_reg_6, + B1=>ae_clrsig, CI=>co2_5, GE=>ae_d_c); scuba_vlo_inst: VLO port map (Z=>scuba_vlo); a2: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); + B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); Empty <= empty_i; Full <= full_i; diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg_generate.log b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg_generate.log index 7309dc6..1078cfa 100644 --- a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg_generate.log +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg_generate.log @@ -2,24 +2,24 @@ Starting process: module Starting process: -SCUBA, Version Diamond (64-bit) 3.4.0.80 -Thu Apr 9 09:22:22 2015 +SCUBA, Version Diamond (64-bit) 3.9.1.119 +Fri Jul 6 11:51:36 2018 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. +Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. BEGIN SCUBA Module Synthesis - Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 7 -data_width 36 -num_words 128 -rdata_width 36 -outdata REGISTERED -no_enable -pe -1 -pf 0 + Issued command : /d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 7 -data_width 36 -num_words 128 -rdata_width 36 -outdata REGISTERED -no_enable -pe 0 -pf -1 Circuit name : FIFO_DC_36x128_DynThr_OutReg Module type : ebfifo - Module Version : 5.7 + Module Version : 5.8 Ports : - Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmFullThresh[6:0] - Outputs : Q[35:0], Empty, Full, AlmostFull + Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[6:0] + Outputs : Q[35:0], Empty, Full, AlmostEmpty I/O buffer : not inserted EDIF output : FIFO_DC_36x128_DynThr_OutReg.edn VHDL output : FIFO_DC_36x128_DynThr_OutReg.vhd @@ -29,7 +29,7 @@ BEGIN SCUBA Module Synthesis Bus notation : big endian Report output : FIFO_DC_36x128_DynThr_OutReg.srp Estimated Resource Usage: - LUT : 106 + LUT : 108 EBR : 1 Reg : 91 diff --git a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd index 15da9ef..7623f25 100644 --- a/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd +++ b/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd @@ -1,6 +1,6 @@ --- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.4.0.80 --- Module Version: 5.7 --- Thu Apr 9 09:22:22 2015 +-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.9.1.119 +-- Module Version: 5.8 +-- Fri Jul 6 11:51:36 2018 -- parameterized module component declaration component FIFO_DC_36x128_DynThr_OutReg @@ -8,13 +8,13 @@ component FIFO_DC_36x128_DynThr_OutReg WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - AmFullThresh: in std_logic_vector(6 downto 0); + AmEmptyThresh: in std_logic_vector(6 downto 0); Q: out std_logic_vector(35 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostFull: out std_logic); + Full: out std_logic; AlmostEmpty: out std_logic); end component; -- parameterized module component instance __ : FIFO_DC_36x128_DynThr_OutReg port map (Data(35 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, AmFullThresh(6 downto 0)=>__, - Q(35 downto 0)=>__, Empty=>__, Full=>__, AlmostFull=>__); + RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(6 downto 0)=>__, + Q(35 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__); diff --git a/base/cores/ecp3/FIFO/generate_core.tcl b/base/cores/ecp3/FIFO/generate_core.tcl index 0e1d16c..63b9fbe 100644 --- a/base/cores/ecp3/FIFO/generate_core.tcl +++ b/base/cores/ecp3/FIFO/generate_core.tcl @@ -85,7 +85,7 @@ set Para(install_dir) $env(TOOLRTF) set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" set scuba "$Para(FPGAPath)/scuba" -set modulename "FIFO_DC_36x64_DynThr_OutReg" +set modulename "FIFO_DC_36x128_DynThr_OutReg" set lang "vhdl" set lpcfile "$Para(sbp_path)/$modulename.lpc" set arch "ep5c00" @@ -94,7 +94,7 @@ set fdcfile "$Para(sbp_path)/$modulename.fdc" if {[file exists $fdcfile] == 0} { append scuba " " $cmd_line } else { - append scuba " " $cmd_line " " -fdc " " $fdcfile + append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" } set Para(result) [catch {eval exec "$scuba"} msg] #puts $msg diff --git a/base/cores/ecp3/FIFO/generate_ngd.tcl b/base/cores/ecp3/FIFO/generate_ngd.tcl index 3ebf887..48b59d9 100644 --- a/base/cores/ecp3/FIFO/generate_ngd.tcl +++ b/base/cores/ecp3/FIFO/generate_ngd.tcl @@ -50,7 +50,7 @@ set Para(install_dir) $env(TOOLRTF) set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" -set Para(ModuleName) "FIFO_DC_36x64_DynThr_OutReg" +set Para(ModuleName) "FIFO_DC_36x128_DynThr_OutReg" set Para(Module) "FIFO_DC" set Para(libname) latticeecp3 set Para(arch_name) ep5c00 diff --git a/base/cores/ecp3/FIFO/msg_file.log b/base/cores/ecp3/FIFO/msg_file.log index 83391a2..6278535 100644 --- a/base/cores/ecp3/FIFO/msg_file.log +++ b/base/cores/ecp3/FIFO/msg_file.log @@ -1,33 +1,33 @@ -SCUBA, Version Diamond (64-bit) 3.5.0.102 -Mon Sep 21 11:51:55 2015 +SCUBA, Version Diamond (64-bit) 3.9.1.119 +Fri Jul 6 11:51:36 2018 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2015 Lattice Semiconductor Corporation, All rights reserved. +Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. BEGIN SCUBA Module Synthesis - Issued command : /opt/lattice/diamond/3.5_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x64_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 6 -data_width 36 -num_words 64 -rdata_width 36 -outdata REGISTERED -no_enable -pe -1 -pf 0 - Circuit name : FIFO_DC_36x64_DynThr_OutReg + Issued command : /d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 7 -data_width 36 -num_words 128 -rdata_width 36 -outdata REGISTERED -no_enable -pe 0 -pf -1 + Circuit name : FIFO_DC_36x128_DynThr_OutReg Module type : ebfifo Module Version : 5.8 Ports : - Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmFullThresh[5:0] - Outputs : Q[35:0], Empty, Full, AlmostFull + Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[6:0] + Outputs : Q[35:0], Empty, Full, AlmostEmpty I/O buffer : not inserted - EDIF output : FIFO_DC_36x64_DynThr_OutReg.edn - VHDL output : FIFO_DC_36x64_DynThr_OutReg.vhd - VHDL template : FIFO_DC_36x64_DynThr_OutReg_tmpl.vhd - VHDL testbench : tb_FIFO_DC_36x64_DynThr_OutReg_tmpl.vhd + EDIF output : FIFO_DC_36x128_DynThr_OutReg.edn + VHDL output : FIFO_DC_36x128_DynThr_OutReg.vhd + VHDL template : FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd + VHDL testbench : tb_FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd VHDL purpose : for synthesis and simulation Bus notation : big endian - Report output : FIFO_DC_36x64_DynThr_OutReg.srp + Report output : FIFO_DC_36x128_DynThr_OutReg.srp Estimated Resource Usage: - LUT : 100 + LUT : 108 EBR : 1 - Reg : 80 + Reg : 91 END SCUBA Module Synthesis diff --git a/base/cores/ecp3/FIFO/tb_FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd b/base/cores/ecp3/FIFO/tb_FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd index eb311c8..535809f 100644 --- a/base/cores/ecp3/FIFO/tb_FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd +++ b/base/cores/ecp3/FIFO/tb_FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd @@ -1,4 +1,4 @@ --- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.9.1.119 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; @@ -17,9 +17,9 @@ architecture test of tb is port (Data : in std_logic_vector(35 downto 0); WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - AmFullThresh : in std_logic_vector(6 downto 0); + AmEmptyThresh : in std_logic_vector(6 downto 0); Q : out std_logic_vector(35 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostFull: out std_logic + Full: out std_logic; AlmostEmpty: out std_logic ); end component; @@ -30,17 +30,17 @@ architecture test of tb is signal RdEn: std_logic := '0'; signal Reset: std_logic := '0'; signal RPReset: std_logic := '0'; - signal AmFullThresh : std_logic_vector(6 downto 0) := (others => '0'); + signal AmEmptyThresh : std_logic_vector(6 downto 0) := (others => '0'); signal Q : std_logic_vector(35 downto 0); signal Empty: std_logic; signal Full: std_logic; - signal AlmostFull: std_logic; + signal AlmostEmpty: std_logic; begin u1 : FIFO_DC_36x128_DynThr_OutReg port map (Data => Data, WrClock => WrClock, RdClock => RdClock, WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - AmFullThresh => AmFullThresh, Q => Q, Empty => Empty, Full => Full, - AlmostFull => AlmostFull + AmEmptyThresh => AmEmptyThresh, Q => Q, Empty => Empty, Full => Full, + AlmostEmpty => AlmostEmpty ); process diff --git a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.cst b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.cst index 1aa3df3..1ed51d2 100644 --- a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.cst +++ b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.cst @@ -1,3 +1,3 @@ -Date=03/17/2015 -Time=15:27:13 +Date=07/06/2018 +Time=16:42:22 diff --git a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.edn b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.edn index f12ce27..7f38535 100644 --- a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.edn +++ b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.edn @@ -4,9 +4,9 @@ (keywordMap (keywordLevel 0)) (status (written - (timestamp 2015 3 17 15 27 16) - (program "SCUBA" (version "Diamond (64-bit) 3.4.0.80")))) - (comment "/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 128 -width 36 -rwidth 36 -regout -no_enable -sync_reset -pe -1 -pf 0 -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.fdc ") + (timestamp 2018 7 6 16 42 28) + (program "SCUBA" (version "Diamond (64-bit) 3.9.1.119")))) + (comment "/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 128 -width 36 -rwidth 36 -regout -no_enable -sync_reset -pe 0 -pf -1 -fdc /d/jspc22/trb/git/dirich/dirich/diamond/test/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.fdc ") (library ORCLIB (edifLevel 0) (technology @@ -413,7 +413,7 @@ (direction INPUT)) (port RPReset (direction INPUT)) - (port (array (rename AmFullThresh "AmFullThresh(6:0)") 7) + (port (array (rename AmEmptyThresh "AmEmptyThresh(6:0)") 7) (direction INPUT)) (port (array (rename Q "Q(35:0)") 36) (direction OUTPUT)) @@ -421,25 +421,31 @@ (direction OUTPUT)) (port Full (direction OUTPUT)) - (port AlmostFull + (port AlmostEmpty (direction OUTPUT))) (property NGD_DRC_MASK (integer 1)) (contents - (instance AND2_t17 + (instance AND2_t19 (viewRef view1 (cellRef AND2))) - (instance INV_1 + (instance INV_2 (viewRef view1 (cellRef INV))) - (instance AND2_t16 + (instance AND2_t18 (viewRef view1 (cellRef AND2))) - (instance INV_0 + (instance INV_1 (viewRef view1 (cellRef INV))) - (instance OR2_t15 + (instance OR2_t17 (viewRef view1 (cellRef OR2))) + (instance XOR2_t16 + (viewRef view1 + (cellRef XOR2))) + (instance XOR2_t15 + (viewRef view1 + (cellRef XOR2))) (instance XOR2_t14 (viewRef view1 (cellRef XOR2))) @@ -476,12 +482,6 @@ (instance XOR2_t3 (viewRef view1 (cellRef XOR2))) - (instance XOR2_t2 - (viewRef view1 - (cellRef XOR2))) - (instance XOR2_t1 - (viewRef view1 - (cellRef XOR2))) (instance LUT4_19 (viewRef view1 (cellRef ROM16X1A)) @@ -562,7 +562,7 @@ (cellRef ROM16X1A)) (property initval (string "0x6996"))) - (instance XOR2_t0 + (instance XOR2_t2 (viewRef view1 (cellRef XOR2))) (instance LUT4_3 @@ -585,6 +585,15 @@ (cellRef ROM16X1A)) (property initval (string "0x4001"))) + (instance INV_0 + (viewRef view1 + (cellRef INV))) + (instance AND2_t1 + (viewRef view1 + (cellRef AND2))) + (instance AND2_t0 + (viewRef view1 + (cellRef AND2))) (instance pdp_ram_0_0_0 (viewRef view1 (cellRef PDPW16KD)) @@ -1062,7 +1071,7 @@ (string "ENABLED"))) (instance FF_0 (viewRef view1 - (cellRef FD1S3DX)) + (cellRef FD1S3BX)) (property GSR (string "ENABLED"))) (instance w_gctr_cia @@ -1186,7 +1195,7 @@ (string "0x0000")) (property INIT0 (string "0x0000"))) - (instance wcnt_0 + (instance rcnt_0 (viewRef view1 (cellRef CCU2C)) (property INJECT1_1 @@ -1197,7 +1206,7 @@ (string "0x99AA")) (property INIT0 (string "0x99AA"))) - (instance wcnt_1 + (instance rcnt_1 (viewRef view1 (cellRef CCU2C)) (property INJECT1_1 @@ -1208,7 +1217,7 @@ (string "0x99AA")) (property INIT0 (string "0x99AA"))) - (instance wcnt_2 + (instance rcnt_2 (viewRef view1 (cellRef CCU2C)) (property INJECT1_1 @@ -1219,7 +1228,7 @@ (string "0x99AA")) (property INIT0 (string "0x99AA"))) - (instance wcnt_3 + (instance rcnt_3 (viewRef view1 (cellRef CCU2C)) (property INJECT1_1 @@ -1230,7 +1239,7 @@ (string "0x99AA")) (property INIT0 (string "0x99AA"))) - (instance wcnt_4 + (instance rcnt_4 (viewRef view1 (cellRef CCU2C)) (property INJECT1_1 @@ -1373,7 +1382,7 @@ (string "0x66AA")) (property INIT0 (string "0x66AA"))) - (instance af_d_cmp_ci_a + (instance ae_cmp_ci_a (viewRef view1 (cellRef CCU2C)) (property INJECT1_1 @@ -1384,7 +1393,7 @@ (string "0x66AA")) (property INIT0 (string "0x66AA"))) - (instance af_d_cmp_0 + (instance ae_cmp_0 (viewRef view1 (cellRef CCU2C)) (property INJECT1_1 @@ -1395,7 +1404,7 @@ (string "0x99AA")) (property INIT0 (string "0x99AA"))) - (instance af_d_cmp_1 + (instance ae_cmp_1 (viewRef view1 (cellRef CCU2C)) (property INJECT1_1 @@ -1406,7 +1415,7 @@ (string "0x99AA")) (property INIT0 (string "0x99AA"))) - (instance af_d_cmp_2 + (instance ae_cmp_2 (viewRef view1 (cellRef CCU2C)) (property INJECT1_1 @@ -1417,7 +1426,7 @@ (string "0x99AA")) (property INIT0 (string "0x99AA"))) - (instance af_d_cmp_3 + (instance ae_cmp_3 (viewRef view1 (cellRef CCU2C)) (property INJECT1_1 @@ -1447,12 +1456,12 @@ (string "0x66AA"))) (net invout_1 (joined - (portRef Z (instanceRef INV_1)) - (portRef B (instanceRef AND2_t17)))) + (portRef Z (instanceRef INV_2)) + (portRef B (instanceRef AND2_t19)))) (net invout_0 (joined - (portRef Z (instanceRef INV_0)) - (portRef B (instanceRef AND2_t16)))) + (portRef Z (instanceRef INV_1)) + (portRef B (instanceRef AND2_t18)))) (net w_g2b_xor_cluster_1 (joined (portRef AD2 (instanceRef LUT4_12)) @@ -1461,34 +1470,38 @@ (joined (portRef AD2 (instanceRef LUT4_4)) (portRef DO0 (instanceRef LUT4_10)))) + (net rcnt_reg_6_inv + (joined + (portRef B (instanceRef AND2_t1)) + (portRef Z (instanceRef INV_0)))) (net w_gdata_0 (joined (portRef D (instanceRef FF_82)) - (portRef Z (instanceRef XOR2_t14)))) + (portRef Z (instanceRef XOR2_t16)))) (net w_gdata_1 (joined (portRef D (instanceRef FF_81)) - (portRef Z (instanceRef XOR2_t13)))) + (portRef Z (instanceRef XOR2_t15)))) (net w_gdata_2 (joined (portRef D (instanceRef FF_80)) - (portRef Z (instanceRef XOR2_t12)))) + (portRef Z (instanceRef XOR2_t14)))) (net w_gdata_3 (joined (portRef D (instanceRef FF_79)) - (portRef Z (instanceRef XOR2_t11)))) + (portRef Z (instanceRef XOR2_t13)))) (net w_gdata_4 (joined (portRef D (instanceRef FF_78)) - (portRef Z (instanceRef XOR2_t10)))) + (portRef Z (instanceRef XOR2_t12)))) (net w_gdata_5 (joined (portRef D (instanceRef FF_77)) - (portRef Z (instanceRef XOR2_t9)))) + (portRef Z (instanceRef XOR2_t11)))) (net w_gdata_6 (joined (portRef D (instanceRef FF_76)) - (portRef Z (instanceRef XOR2_t8)))) + (portRef Z (instanceRef XOR2_t10)))) (net wptr_0 (joined (portRef Q (instanceRef FF_74)) @@ -1525,31 +1538,31 @@ (net r_gdata_0 (joined (portRef D (instanceRef FF_58)) - (portRef Z (instanceRef XOR2_t7)))) + (portRef Z (instanceRef XOR2_t9)))) (net r_gdata_1 (joined (portRef D (instanceRef FF_57)) - (portRef Z (instanceRef XOR2_t6)))) + (portRef Z (instanceRef XOR2_t8)))) (net r_gdata_2 (joined (portRef D (instanceRef FF_56)) - (portRef Z (instanceRef XOR2_t5)))) + (portRef Z (instanceRef XOR2_t7)))) (net r_gdata_3 (joined (portRef D (instanceRef FF_55)) - (portRef Z (instanceRef XOR2_t4)))) + (portRef Z (instanceRef XOR2_t6)))) (net r_gdata_4 (joined (portRef D (instanceRef FF_54)) - (portRef Z (instanceRef XOR2_t3)))) + (portRef Z (instanceRef XOR2_t5)))) (net r_gdata_5 (joined (portRef D (instanceRef FF_53)) - (portRef Z (instanceRef XOR2_t2)))) + (portRef Z (instanceRef XOR2_t4)))) (net r_gdata_6 (joined (portRef D (instanceRef FF_52)) - (portRef Z (instanceRef XOR2_t1)))) + (portRef Z (instanceRef XOR2_t3)))) (net rptr_0 (joined (portRef Q (instanceRef FF_50)) @@ -1721,6 +1734,7 @@ (portRef AD0 (instanceRef LUT4_19)) (portRef AD2 (instanceRef LUT4_17)) (portRef AD1 (instanceRef LUT4_16)) + (portRef A (instanceRef XOR2_t2)) (portRef AD1 (instanceRef LUT4_3)) (portRef AD1 (instanceRef LUT4_2)))) (net w_gcount_r7 @@ -1801,17 +1815,21 @@ (portRef AD0 (instanceRef LUT4_11)) (portRef AD2 (instanceRef LUT4_9)) (portRef AD1 (instanceRef LUT4_8)) - (portRef B (instanceRef XOR2_t0)) (portRef AD1 (instanceRef LUT4_1)) (portRef AD1 (instanceRef LUT4_0)))) (net r_gcount_w7 (joined (portRef D (instanceRef FF_11)) (portRef Q (instanceRef FF_27)))) + (net rcnt_reg_7 + (joined + (portRef Q (instanceRef FF_3)) + (portRef A (instanceRef AND2_t1)) + (portRef A (instanceRef AND2_t0)))) (net rRst (joined - (portRef PD (instanceRef FF_2)) - (portRef Z (instanceRef OR2_t15)) + (portRef PD (instanceRef FF_0)) + (portRef Z (instanceRef OR2_t17)) (portRef PD (instanceRef FF_66)) (portRef CD (instanceRef FF_65)) (portRef CD (instanceRef FF_64)) @@ -1851,7 +1869,16 @@ (portRef CD (instanceRef FF_14)) (portRef CD (instanceRef FF_13)) (portRef CD (instanceRef FF_12)) - (portRef CD (instanceRef FF_11)))) + (portRef CD (instanceRef FF_11)) + (portRef CD (instanceRef FF_10)) + (portRef CD (instanceRef FF_9)) + (portRef CD (instanceRef FF_8)) + (portRef CD (instanceRef FF_7)) + (portRef CD (instanceRef FF_6)) + (portRef CD (instanceRef FF_5)) + (portRef CD (instanceRef FF_4)) + (portRef CD (instanceRef FF_3)) + (portRef PD (instanceRef FF_2)))) (net iwcount_0 (joined (portRef S0 (instanceRef w_gctr_0)) @@ -1906,8 +1933,7 @@ (net wcount_7 (joined (portRef A1 (instanceRef w_gctr_3)) - (portRef B (instanceRef XOR2_t8)) - (portRef A (instanceRef XOR2_t0)) + (portRef B (instanceRef XOR2_t10)) (portRef AD2 (instanceRef LUT4_1)) (portRef AD2 (instanceRef LUT4_0)) (portRef Q (instanceRef FF_83)) @@ -1967,98 +1993,69 @@ (net rcount_7 (joined (portRef A1 (instanceRef r_gctr_3)) - (portRef B (instanceRef XOR2_t1)) + (portRef B (instanceRef XOR2_t3)) + (portRef B (instanceRef XOR2_t2)) (portRef AD2 (instanceRef LUT4_3)) (portRef AD2 (instanceRef LUT4_2)) (portRef Q (instanceRef FF_59)) (portRef D (instanceRef FF_51)) (portRef D (instanceRef FF_43)))) - (net wcnt_sub_0 + (net rcnt_sub_0 (joined - (portRef S1 (instanceRef wcnt_0)) + (portRef S1 (instanceRef rcnt_0)) (portRef D (instanceRef FF_10)))) (net precin (joined - (portRef CIN (instanceRef wcnt_0)) + (portRef CIN (instanceRef rcnt_0)) (portRef COUT (instanceRef precin_inst284)))) - (net wcnt_sub_1 + (net rcnt_sub_1 (joined - (portRef S0 (instanceRef wcnt_1)) + (portRef S0 (instanceRef rcnt_1)) (portRef D (instanceRef FF_9)))) - (net wcnt_sub_2 + (net rcnt_sub_2 (joined - (portRef S1 (instanceRef wcnt_1)) + (portRef S1 (instanceRef rcnt_1)) (portRef D (instanceRef FF_8)))) (net co0_2 (joined - (portRef CIN (instanceRef wcnt_1)) - (portRef COUT (instanceRef wcnt_0)))) - (net wcnt_sub_3 + (portRef CIN (instanceRef rcnt_1)) + (portRef COUT (instanceRef rcnt_0)))) + (net rcnt_sub_3 (joined - (portRef S0 (instanceRef wcnt_2)) + (portRef S0 (instanceRef rcnt_2)) (portRef D (instanceRef FF_7)))) - (net wcnt_sub_4 + (net rcnt_sub_4 (joined - (portRef S1 (instanceRef wcnt_2)) + (portRef S1 (instanceRef rcnt_2)) (portRef D (instanceRef FF_6)))) (net co1_2 (joined - (portRef CIN (instanceRef wcnt_2)) - (portRef COUT (instanceRef wcnt_1)))) - (net wcnt_sub_5 + (portRef CIN (instanceRef rcnt_2)) + (portRef COUT (instanceRef rcnt_1)))) + (net rcnt_sub_5 (joined - (portRef S0 (instanceRef wcnt_3)) + (portRef S0 (instanceRef rcnt_3)) (portRef D (instanceRef FF_5)))) - (net wcnt_sub_6 + (net rcnt_sub_6 (joined - (portRef S1 (instanceRef wcnt_3)) + (portRef S1 (instanceRef rcnt_3)) (portRef D (instanceRef FF_4)))) (net co2_2 (joined - (portRef CIN (instanceRef wcnt_3)) - (portRef COUT (instanceRef wcnt_2)))) - (net wcnt_sub_7 + (portRef CIN (instanceRef rcnt_3)) + (portRef COUT (instanceRef rcnt_2)))) + (net rcnt_sub_7 (joined - (portRef S0 (instanceRef wcnt_4)) + (portRef S0 (instanceRef rcnt_4)) (portRef D (instanceRef FF_3)))) - (net wcnt_sub_msb + (net rcnt_sub_msb (joined - (portRef A0 (instanceRef wcnt_4)) - (portRef Z (instanceRef XOR2_t0)))) + (portRef A0 (instanceRef rcnt_4)) + (portRef Z (instanceRef XOR2_t2)))) (net co3_2 (joined - (portRef CIN (instanceRef wcnt_4)) - (portRef COUT (instanceRef wcnt_3)))) - (net rden_i - (joined - (portRef A1 (instanceRef empty_cmp_ci_a)) - (portRef Z (instanceRef AND2_t16)) - (portRef CSR0 (instanceRef pdp_ram_0_0_0)) - (portRef SP (instanceRef FF_66)) - (portRef SP (instanceRef FF_65)) - (portRef SP (instanceRef FF_64)) - (portRef SP (instanceRef FF_63)) - (portRef SP (instanceRef FF_62)) - (portRef SP (instanceRef FF_61)) - (portRef SP (instanceRef FF_60)) - (portRef SP (instanceRef FF_59)) - (portRef SP (instanceRef FF_58)) - (portRef SP (instanceRef FF_57)) - (portRef SP (instanceRef FF_56)) - (portRef SP (instanceRef FF_55)) - (portRef SP (instanceRef FF_54)) - (portRef SP (instanceRef FF_53)) - (portRef SP (instanceRef FF_52)) - (portRef SP (instanceRef FF_51)) - (portRef SP (instanceRef FF_50)) - (portRef SP (instanceRef FF_49)) - (portRef SP (instanceRef FF_48)) - (portRef SP (instanceRef FF_47)) - (portRef SP (instanceRef FF_46)) - (portRef SP (instanceRef FF_45)) - (portRef SP (instanceRef FF_44)) - (portRef SP (instanceRef FF_43)) - (portRef B1 (instanceRef empty_cmp_ci_a)))) + (portRef CIN (instanceRef rcnt_4)) + (portRef COUT (instanceRef rcnt_3)))) (net cmp_ci (joined (portRef CIN (instanceRef empty_cmp_0)) @@ -2066,26 +2063,30 @@ (net wcount_r0 (joined (portRef B0 (instanceRef empty_cmp_0)) - (portRef DO0 (instanceRef LUT4_12)))) + (portRef DO0 (instanceRef LUT4_12)) + (portRef A1 (instanceRef rcnt_0)))) (net wcount_r1 (joined (portRef B1 (instanceRef empty_cmp_0)) - (portRef DO0 (instanceRef LUT4_13)))) + (portRef DO0 (instanceRef LUT4_13)) + (portRef A0 (instanceRef rcnt_1)))) (net rcount_0 (joined (portRef A0 (instanceRef empty_cmp_0)) - (portRef A (instanceRef XOR2_t7)) + (portRef A (instanceRef XOR2_t9)) (portRef Q (instanceRef FF_66)) (portRef D (instanceRef FF_50)) - (portRef A0 (instanceRef r_gctr_0)))) + (portRef A0 (instanceRef r_gctr_0)) + (portRef B1 (instanceRef rcnt_0)))) (net rcount_1 (joined (portRef A1 (instanceRef empty_cmp_0)) - (portRef B (instanceRef XOR2_t7)) - (portRef A (instanceRef XOR2_t6)) + (portRef B (instanceRef XOR2_t9)) + (portRef A (instanceRef XOR2_t8)) (portRef Q (instanceRef FF_65)) (portRef D (instanceRef FF_49)) - (portRef A1 (instanceRef r_gctr_0)))) + (portRef A1 (instanceRef r_gctr_0)) + (portRef B0 (instanceRef rcnt_1)))) (net co0_3 (joined (portRef CIN (instanceRef empty_cmp_1)) @@ -2093,27 +2094,31 @@ (net wcount_r2 (joined (portRef B0 (instanceRef empty_cmp_1)) - (portRef DO0 (instanceRef LUT4_14)))) + (portRef DO0 (instanceRef LUT4_14)) + (portRef A1 (instanceRef rcnt_1)))) (net wcount_r3 (joined (portRef B1 (instanceRef empty_cmp_1)) - (portRef DO0 (instanceRef LUT4_15)))) + (portRef DO0 (instanceRef LUT4_15)) + (portRef A0 (instanceRef rcnt_2)))) (net rcount_2 (joined (portRef A0 (instanceRef empty_cmp_1)) - (portRef B (instanceRef XOR2_t6)) - (portRef A (instanceRef XOR2_t5)) + (portRef B (instanceRef XOR2_t8)) + (portRef A (instanceRef XOR2_t7)) (portRef Q (instanceRef FF_64)) (portRef D (instanceRef FF_48)) - (portRef A0 (instanceRef r_gctr_1)))) + (portRef A0 (instanceRef r_gctr_1)) + (portRef B1 (instanceRef rcnt_1)))) (net rcount_3 (joined (portRef A1 (instanceRef empty_cmp_1)) - (portRef B (instanceRef XOR2_t5)) - (portRef A (instanceRef XOR2_t4)) + (portRef B (instanceRef XOR2_t7)) + (portRef A (instanceRef XOR2_t6)) (portRef Q (instanceRef FF_63)) (portRef D (instanceRef FF_47)) - (portRef A1 (instanceRef r_gctr_1)))) + (portRef A1 (instanceRef r_gctr_1)) + (portRef B0 (instanceRef rcnt_2)))) (net co1_3 (joined (portRef CIN (instanceRef empty_cmp_2)) @@ -2123,28 +2128,32 @@ (portRef B0 (instanceRef empty_cmp_2)) (portRef DO0 (instanceRef LUT4_19)) (portRef AD0 (instanceRef LUT4_13)) - (portRef AD3 (instanceRef LUT4_12)))) + (portRef AD3 (instanceRef LUT4_12)) + (portRef A1 (instanceRef rcnt_2)))) (net wcount_r5 (joined (portRef B1 (instanceRef empty_cmp_2)) (portRef DO0 (instanceRef LUT4_16)) - (portRef AD0 (instanceRef LUT4_14)))) + (portRef AD0 (instanceRef LUT4_14)) + (portRef A0 (instanceRef rcnt_3)))) (net rcount_4 (joined (portRef A0 (instanceRef empty_cmp_2)) - (portRef B (instanceRef XOR2_t4)) - (portRef A (instanceRef XOR2_t3)) + (portRef B (instanceRef XOR2_t6)) + (portRef A (instanceRef XOR2_t5)) (portRef Q (instanceRef FF_62)) (portRef D (instanceRef FF_46)) - (portRef A0 (instanceRef r_gctr_2)))) + (portRef A0 (instanceRef r_gctr_2)) + (portRef B1 (instanceRef rcnt_2)))) (net rcount_5 (joined (portRef A1 (instanceRef empty_cmp_2)) - (portRef B (instanceRef XOR2_t3)) - (portRef A (instanceRef XOR2_t2)) + (portRef B (instanceRef XOR2_t5)) + (portRef A (instanceRef XOR2_t4)) (portRef Q (instanceRef FF_61)) (portRef D (instanceRef FF_45)) - (portRef A1 (instanceRef r_gctr_2)))) + (portRef A1 (instanceRef r_gctr_2)) + (portRef B0 (instanceRef rcnt_3)))) (net co2_3 (joined (portRef CIN (instanceRef empty_cmp_3)) @@ -2153,7 +2162,8 @@ (joined (portRef B0 (instanceRef empty_cmp_3)) (portRef DO0 (instanceRef LUT4_17)) - (portRef AD0 (instanceRef LUT4_15)))) + (portRef AD0 (instanceRef LUT4_15)) + (portRef A1 (instanceRef rcnt_3)))) (net empty_cmp_clr (joined (portRef B1 (instanceRef empty_cmp_3)) @@ -2161,11 +2171,12 @@ (net rcount_6 (joined (portRef A0 (instanceRef empty_cmp_3)) - (portRef B (instanceRef XOR2_t2)) - (portRef A (instanceRef XOR2_t1)) + (portRef B (instanceRef XOR2_t4)) + (portRef A (instanceRef XOR2_t3)) (portRef Q (instanceRef FF_60)) (portRef D (instanceRef FF_44)) - (portRef A0 (instanceRef r_gctr_3)))) + (portRef A0 (instanceRef r_gctr_3)) + (portRef B1 (instanceRef rcnt_3)))) (net empty_cmp_set (joined (portRef A1 (instanceRef empty_cmp_3)) @@ -2178,6 +2189,36 @@ (joined (portRef CIN (instanceRef a0)) (portRef COUT (instanceRef empty_cmp_3)))) + (net wren_i + (joined + (portRef A1 (instanceRef full_cmp_ci_a)) + (portRef Z (instanceRef AND2_t19)) + (portRef CEW (instanceRef pdp_ram_0_0_0)) + (portRef SP (instanceRef FF_90)) + (portRef SP (instanceRef FF_89)) + (portRef SP (instanceRef FF_88)) + (portRef SP (instanceRef FF_87)) + (portRef SP (instanceRef FF_86)) + (portRef SP (instanceRef FF_85)) + (portRef SP (instanceRef FF_84)) + (portRef SP (instanceRef FF_83)) + (portRef SP (instanceRef FF_82)) + (portRef SP (instanceRef FF_81)) + (portRef SP (instanceRef FF_80)) + (portRef SP (instanceRef FF_79)) + (portRef SP (instanceRef FF_78)) + (portRef SP (instanceRef FF_77)) + (portRef SP (instanceRef FF_76)) + (portRef SP (instanceRef FF_75)) + (portRef SP (instanceRef FF_74)) + (portRef SP (instanceRef FF_73)) + (portRef SP (instanceRef FF_72)) + (portRef SP (instanceRef FF_71)) + (portRef SP (instanceRef FF_70)) + (portRef SP (instanceRef FF_69)) + (portRef SP (instanceRef FF_68)) + (portRef SP (instanceRef FF_67)) + (portRef B1 (instanceRef full_cmp_ci_a)))) (net cmp_ci_1 (joined (portRef CIN (instanceRef full_cmp_0)) @@ -2185,30 +2226,26 @@ (net rcount_w0 (joined (portRef B0 (instanceRef full_cmp_0)) - (portRef DO0 (instanceRef LUT4_4)) - (portRef B1 (instanceRef wcnt_0)))) + (portRef DO0 (instanceRef LUT4_4)))) (net rcount_w1 (joined (portRef B1 (instanceRef full_cmp_0)) - (portRef DO0 (instanceRef LUT4_5)) - (portRef B0 (instanceRef wcnt_1)))) + (portRef DO0 (instanceRef LUT4_5)))) (net wcount_0 (joined (portRef A0 (instanceRef full_cmp_0)) - (portRef A (instanceRef XOR2_t14)) + (portRef A (instanceRef XOR2_t16)) (portRef Q (instanceRef FF_90)) (portRef D (instanceRef FF_74)) - (portRef A0 (instanceRef w_gctr_0)) - (portRef A1 (instanceRef wcnt_0)))) + (portRef A0 (instanceRef w_gctr_0)))) (net wcount_1 (joined (portRef A1 (instanceRef full_cmp_0)) - (portRef B (instanceRef XOR2_t14)) - (portRef A (instanceRef XOR2_t13)) + (portRef B (instanceRef XOR2_t16)) + (portRef A (instanceRef XOR2_t15)) (portRef Q (instanceRef FF_89)) (portRef D (instanceRef FF_73)) - (portRef A1 (instanceRef w_gctr_0)) - (portRef A0 (instanceRef wcnt_1)))) + (portRef A1 (instanceRef w_gctr_0)))) (net co0_4 (joined (portRef CIN (instanceRef full_cmp_1)) @@ -2216,31 +2253,27 @@ (net rcount_w2 (joined (portRef B0 (instanceRef full_cmp_1)) - (portRef DO0 (instanceRef LUT4_6)) - (portRef B1 (instanceRef wcnt_1)))) + (portRef DO0 (instanceRef LUT4_6)))) (net rcount_w3 (joined (portRef B1 (instanceRef full_cmp_1)) - (portRef DO0 (instanceRef LUT4_7)) - (portRef B0 (instanceRef wcnt_2)))) + (portRef DO0 (instanceRef LUT4_7)))) (net wcount_2 (joined (portRef A0 (instanceRef full_cmp_1)) - (portRef B (instanceRef XOR2_t13)) - (portRef A (instanceRef XOR2_t12)) + (portRef B (instanceRef XOR2_t15)) + (portRef A (instanceRef XOR2_t14)) (portRef Q (instanceRef FF_88)) (portRef D (instanceRef FF_72)) - (portRef A0 (instanceRef w_gctr_1)) - (portRef A1 (instanceRef wcnt_1)))) + (portRef A0 (instanceRef w_gctr_1)))) (net wcount_3 (joined (portRef A1 (instanceRef full_cmp_1)) - (portRef B (instanceRef XOR2_t12)) - (portRef A (instanceRef XOR2_t11)) + (portRef B (instanceRef XOR2_t14)) + (portRef A (instanceRef XOR2_t13)) (portRef Q (instanceRef FF_87)) (portRef D (instanceRef FF_71)) - (portRef A1 (instanceRef w_gctr_1)) - (portRef A0 (instanceRef wcnt_2)))) + (portRef A1 (instanceRef w_gctr_1)))) (net co1_4 (joined (portRef CIN (instanceRef full_cmp_2)) @@ -2250,32 +2283,28 @@ (portRef B0 (instanceRef full_cmp_2)) (portRef DO0 (instanceRef LUT4_11)) (portRef AD0 (instanceRef LUT4_5)) - (portRef AD3 (instanceRef LUT4_4)) - (portRef B1 (instanceRef wcnt_2)))) + (portRef AD3 (instanceRef LUT4_4)))) (net rcount_w5 (joined (portRef B1 (instanceRef full_cmp_2)) (portRef DO0 (instanceRef LUT4_8)) - (portRef AD0 (instanceRef LUT4_6)) - (portRef B0 (instanceRef wcnt_3)))) + (portRef AD0 (instanceRef LUT4_6)))) (net wcount_4 (joined (portRef A0 (instanceRef full_cmp_2)) - (portRef B (instanceRef XOR2_t11)) - (portRef A (instanceRef XOR2_t10)) + (portRef B (instanceRef XOR2_t13)) + (portRef A (instanceRef XOR2_t12)) (portRef Q (instanceRef FF_86)) (portRef D (instanceRef FF_70)) - (portRef A0 (instanceRef w_gctr_2)) - (portRef A1 (instanceRef wcnt_2)))) + (portRef A0 (instanceRef w_gctr_2)))) (net wcount_5 (joined (portRef A1 (instanceRef full_cmp_2)) - (portRef B (instanceRef XOR2_t10)) - (portRef A (instanceRef XOR2_t9)) + (portRef B (instanceRef XOR2_t12)) + (portRef A (instanceRef XOR2_t11)) (portRef Q (instanceRef FF_85)) (portRef D (instanceRef FF_69)) - (portRef A1 (instanceRef w_gctr_2)) - (portRef A0 (instanceRef wcnt_3)))) + (portRef A1 (instanceRef w_gctr_2)))) (net co2_4 (joined (portRef CIN (instanceRef full_cmp_3)) @@ -2284,8 +2313,7 @@ (joined (portRef B0 (instanceRef full_cmp_3)) (portRef DO0 (instanceRef LUT4_9)) - (portRef AD0 (instanceRef LUT4_7)) - (portRef B1 (instanceRef wcnt_3)))) + (portRef AD0 (instanceRef LUT4_7)))) (net full_cmp_clr (joined (portRef B1 (instanceRef full_cmp_3)) @@ -2293,12 +2321,11 @@ (net wcount_6 (joined (portRef A0 (instanceRef full_cmp_3)) - (portRef B (instanceRef XOR2_t9)) - (portRef A (instanceRef XOR2_t8)) + (portRef B (instanceRef XOR2_t11)) + (portRef A (instanceRef XOR2_t10)) (portRef Q (instanceRef FF_84)) (portRef D (instanceRef FF_68)) - (portRef A0 (instanceRef w_gctr_3)) - (portRef A1 (instanceRef wcnt_3)))) + (portRef A0 (instanceRef w_gctr_3)))) (net full_cmp_set (joined (portRef A1 (instanceRef full_cmp_3)) @@ -2311,95 +2338,93 @@ (joined (portRef CIN (instanceRef a1)) (portRef COUT (instanceRef full_cmp_3)))) - (net wren_i + (net rden_i (joined - (portRef A1 (instanceRef af_d_cmp_ci_a)) - (portRef Z (instanceRef AND2_t17)) - (portRef CEW (instanceRef pdp_ram_0_0_0)) - (portRef SP (instanceRef FF_90)) - (portRef SP (instanceRef FF_89)) - (portRef SP (instanceRef FF_88)) - (portRef SP (instanceRef FF_87)) - (portRef SP (instanceRef FF_86)) - (portRef SP (instanceRef FF_85)) - (portRef SP (instanceRef FF_84)) - (portRef SP (instanceRef FF_83)) - (portRef SP (instanceRef FF_82)) - (portRef SP (instanceRef FF_81)) - (portRef SP (instanceRef FF_80)) - (portRef SP (instanceRef FF_79)) - (portRef SP (instanceRef FF_78)) - (portRef SP (instanceRef FF_77)) - (portRef SP (instanceRef FF_76)) - (portRef SP (instanceRef FF_75)) - (portRef SP (instanceRef FF_74)) - (portRef SP (instanceRef FF_73)) - (portRef SP (instanceRef FF_72)) - (portRef SP (instanceRef FF_71)) - (portRef SP (instanceRef FF_70)) - (portRef SP (instanceRef FF_69)) - (portRef SP (instanceRef FF_68)) - (portRef SP (instanceRef FF_67)) - (portRef B1 (instanceRef full_cmp_ci_a)) - (portRef A1 (instanceRef full_cmp_ci_a)) - (portRef B1 (instanceRef af_d_cmp_ci_a)))) - (net x - (joined - (portRef CIN (instanceRef af_d_cmp_ci_a)) - (portRef CIN (instanceRef w_gctr_cia)) - (portRef CIN (instanceRef r_gctr_cia)) - (portRef CIN (instanceRef precin_inst284)) - (portRef CIN (instanceRef empty_cmp_ci_a)) - (portRef CIN (instanceRef full_cmp_ci_a)))) + (portRef A1 (instanceRef ae_cmp_ci_a)) + (portRef Z (instanceRef AND2_t18)) + (portRef CSR0 (instanceRef pdp_ram_0_0_0)) + (portRef SP (instanceRef FF_66)) + (portRef SP (instanceRef FF_65)) + (portRef SP (instanceRef FF_64)) + (portRef SP (instanceRef FF_63)) + (portRef SP (instanceRef FF_62)) + (portRef SP (instanceRef FF_61)) + (portRef SP (instanceRef FF_60)) + (portRef SP (instanceRef FF_59)) + (portRef SP (instanceRef FF_58)) + (portRef SP (instanceRef FF_57)) + (portRef SP (instanceRef FF_56)) + (portRef SP (instanceRef FF_55)) + (portRef SP (instanceRef FF_54)) + (portRef SP (instanceRef FF_53)) + (portRef SP (instanceRef FF_52)) + (portRef SP (instanceRef FF_51)) + (portRef SP (instanceRef FF_50)) + (portRef SP (instanceRef FF_49)) + (portRef SP (instanceRef FF_48)) + (portRef SP (instanceRef FF_47)) + (portRef SP (instanceRef FF_46)) + (portRef SP (instanceRef FF_45)) + (portRef SP (instanceRef FF_44)) + (portRef SP (instanceRef FF_43)) + (portRef B1 (instanceRef empty_cmp_ci_a)) + (portRef A1 (instanceRef empty_cmp_ci_a)) + (portRef B1 (instanceRef ae_cmp_ci_a)))) (net cmp_ci_2 (joined - (portRef CIN (instanceRef af_d_cmp_0)) - (portRef COUT (instanceRef af_d_cmp_ci_a)))) - (net wcnt_reg_0 + (portRef CIN (instanceRef ae_cmp_0)) + (portRef COUT (instanceRef ae_cmp_ci_a)))) + (net rcnt_reg_0 (joined - (portRef A0 (instanceRef af_d_cmp_0)) + (portRef B0 (instanceRef ae_cmp_0)) (portRef Q (instanceRef FF_10)))) - (net wcnt_reg_1 + (net rcnt_reg_1 (joined - (portRef A1 (instanceRef af_d_cmp_0)) + (portRef B1 (instanceRef ae_cmp_0)) (portRef Q (instanceRef FF_9)))) (net co0_5 (joined - (portRef CIN (instanceRef af_d_cmp_1)) - (portRef COUT (instanceRef af_d_cmp_0)))) - (net wcnt_reg_2 + (portRef CIN (instanceRef ae_cmp_1)) + (portRef COUT (instanceRef ae_cmp_0)))) + (net rcnt_reg_2 (joined - (portRef A0 (instanceRef af_d_cmp_1)) + (portRef B0 (instanceRef ae_cmp_1)) (portRef Q (instanceRef FF_8)))) - (net wcnt_reg_3 + (net rcnt_reg_3 (joined - (portRef A1 (instanceRef af_d_cmp_1)) + (portRef B1 (instanceRef ae_cmp_1)) (portRef Q (instanceRef FF_7)))) (net co1_5 (joined - (portRef CIN (instanceRef af_d_cmp_2)) - (portRef COUT (instanceRef af_d_cmp_1)))) - (net wcnt_reg_4 + (portRef CIN (instanceRef ae_cmp_2)) + (portRef COUT (instanceRef ae_cmp_1)))) + (net rcnt_reg_4 (joined - (portRef A0 (instanceRef af_d_cmp_2)) + (portRef B0 (instanceRef ae_cmp_2)) (portRef Q (instanceRef FF_6)))) - (net wcnt_reg_5 + (net rcnt_reg_5 (joined - (portRef A1 (instanceRef af_d_cmp_2)) + (portRef B1 (instanceRef ae_cmp_2)) (portRef Q (instanceRef FF_5)))) (net co2_5 (joined - (portRef CIN (instanceRef af_d_cmp_3)) - (portRef COUT (instanceRef af_d_cmp_2)))) - (net wcnt_reg_6 + (portRef CIN (instanceRef ae_cmp_3)) + (portRef COUT (instanceRef ae_cmp_2)))) + (net rcnt_reg_6 (joined - (portRef A0 (instanceRef af_d_cmp_3)) + (portRef B0 (instanceRef ae_cmp_3)) + (portRef A (instanceRef INV_0)) + (portRef B (instanceRef AND2_t0)) (portRef Q (instanceRef FF_4)))) - (net wcnt_reg_7 + (net ae_clrsig (joined - (portRef A1 (instanceRef af_d_cmp_3)) - (portRef Q (instanceRef FF_3)))) - (net af_d + (portRef B1 (instanceRef ae_cmp_3)) + (portRef Z (instanceRef AND2_t1)))) + (net ae_setsig + (joined + (portRef A1 (instanceRef ae_cmp_3)) + (portRef Z (instanceRef AND2_t0)))) + (net ae_d (joined (portRef S0 (instanceRef a2)) (portRef D (instanceRef FF_0)))) @@ -2465,27 +2490,27 @@ (portRef B0 (instanceRef precin_inst284)) (portRef A1 (instanceRef precin_inst284)) (portRef A0 (instanceRef precin_inst284)) - (portRef C1 (instanceRef wcnt_0)) - (portRef C0 (instanceRef wcnt_0)) - (portRef D1 (instanceRef wcnt_0)) - (portRef D0 (instanceRef wcnt_0)) - (portRef A0 (instanceRef wcnt_0)) - (portRef C1 (instanceRef wcnt_1)) - (portRef C0 (instanceRef wcnt_1)) - (portRef D1 (instanceRef wcnt_1)) - (portRef D0 (instanceRef wcnt_1)) - (portRef C1 (instanceRef wcnt_2)) - (portRef C0 (instanceRef wcnt_2)) - (portRef D1 (instanceRef wcnt_2)) - (portRef D0 (instanceRef wcnt_2)) - (portRef C1 (instanceRef wcnt_3)) - (portRef C0 (instanceRef wcnt_3)) - (portRef D1 (instanceRef wcnt_3)) - (portRef D0 (instanceRef wcnt_3)) - (portRef C1 (instanceRef wcnt_4)) - (portRef C0 (instanceRef wcnt_4)) - (portRef D1 (instanceRef wcnt_4)) - (portRef D0 (instanceRef wcnt_4)) + (portRef C1 (instanceRef rcnt_0)) + (portRef C0 (instanceRef rcnt_0)) + (portRef D1 (instanceRef rcnt_0)) + (portRef D0 (instanceRef rcnt_0)) + (portRef A0 (instanceRef rcnt_0)) + (portRef C1 (instanceRef rcnt_1)) + (portRef C0 (instanceRef rcnt_1)) + (portRef D1 (instanceRef rcnt_1)) + (portRef D0 (instanceRef rcnt_1)) + (portRef C1 (instanceRef rcnt_2)) + (portRef C0 (instanceRef rcnt_2)) + (portRef D1 (instanceRef rcnt_2)) + (portRef D0 (instanceRef rcnt_2)) + (portRef C1 (instanceRef rcnt_3)) + (portRef C0 (instanceRef rcnt_3)) + (portRef D1 (instanceRef rcnt_3)) + (portRef D0 (instanceRef rcnt_3)) + (portRef C1 (instanceRef rcnt_4)) + (portRef C0 (instanceRef rcnt_4)) + (portRef D1 (instanceRef rcnt_4)) + (portRef D0 (instanceRef rcnt_4)) (portRef C1 (instanceRef empty_cmp_ci_a)) (portRef C0 (instanceRef empty_cmp_ci_a)) (portRef D1 (instanceRef empty_cmp_ci_a)) @@ -2534,26 +2559,26 @@ (portRef C0 (instanceRef a1)) (portRef D1 (instanceRef a1)) (portRef D0 (instanceRef a1)) - (portRef C1 (instanceRef af_d_cmp_ci_a)) - (portRef C0 (instanceRef af_d_cmp_ci_a)) - (portRef D1 (instanceRef af_d_cmp_ci_a)) - (portRef D0 (instanceRef af_d_cmp_ci_a)) - (portRef D1 (instanceRef af_d_cmp_0)) - (portRef D0 (instanceRef af_d_cmp_0)) - (portRef C1 (instanceRef af_d_cmp_0)) - (portRef C0 (instanceRef af_d_cmp_0)) - (portRef D1 (instanceRef af_d_cmp_1)) - (portRef D0 (instanceRef af_d_cmp_1)) - (portRef C1 (instanceRef af_d_cmp_1)) - (portRef C0 (instanceRef af_d_cmp_1)) - (portRef D1 (instanceRef af_d_cmp_2)) - (portRef D0 (instanceRef af_d_cmp_2)) - (portRef C1 (instanceRef af_d_cmp_2)) - (portRef C0 (instanceRef af_d_cmp_2)) - (portRef D1 (instanceRef af_d_cmp_3)) - (portRef D0 (instanceRef af_d_cmp_3)) - (portRef C1 (instanceRef af_d_cmp_3)) - (portRef C0 (instanceRef af_d_cmp_3)) + (portRef C1 (instanceRef ae_cmp_ci_a)) + (portRef C0 (instanceRef ae_cmp_ci_a)) + (portRef D1 (instanceRef ae_cmp_ci_a)) + (portRef D0 (instanceRef ae_cmp_ci_a)) + (portRef D1 (instanceRef ae_cmp_0)) + (portRef D0 (instanceRef ae_cmp_0)) + (portRef C1 (instanceRef ae_cmp_0)) + (portRef C0 (instanceRef ae_cmp_0)) + (portRef D1 (instanceRef ae_cmp_1)) + (portRef D0 (instanceRef ae_cmp_1)) + (portRef C1 (instanceRef ae_cmp_1)) + (portRef C0 (instanceRef ae_cmp_1)) + (portRef D1 (instanceRef ae_cmp_2)) + (portRef D0 (instanceRef ae_cmp_2)) + (portRef C1 (instanceRef ae_cmp_2)) + (portRef C0 (instanceRef ae_cmp_2)) + (portRef D1 (instanceRef ae_cmp_3)) + (portRef D0 (instanceRef ae_cmp_3)) + (portRef C1 (instanceRef ae_cmp_3)) + (portRef C0 (instanceRef ae_cmp_3)) (portRef C1 (instanceRef a2)) (portRef C0 (instanceRef a2)) (portRef D1 (instanceRef a2)) @@ -2608,10 +2633,10 @@ (portRef B0 (instanceRef r_gctr_2)) (portRef B1 (instanceRef r_gctr_3)) (portRef B0 (instanceRef r_gctr_3)) - (portRef B0 (instanceRef wcnt_0)) - (portRef B1 (instanceRef wcnt_4)) - (portRef B0 (instanceRef wcnt_4)) - (portRef A1 (instanceRef wcnt_4)) + (portRef B0 (instanceRef rcnt_0)) + (portRef B1 (instanceRef rcnt_4)) + (portRef B0 (instanceRef rcnt_4)) + (portRef A1 (instanceRef rcnt_4)) (portRef B0 (instanceRef empty_cmp_ci_a)) (portRef A0 (instanceRef empty_cmp_ci_a)) (portRef B1 (instanceRef a0)) @@ -2624,31 +2649,30 @@ (portRef B0 (instanceRef a1)) (portRef A1 (instanceRef a1)) (portRef A0 (instanceRef a1)) - (portRef B0 (instanceRef af_d_cmp_ci_a)) - (portRef A0 (instanceRef af_d_cmp_ci_a)) - (portRef B1 (instanceRef af_d_cmp_3)) + (portRef B0 (instanceRef ae_cmp_ci_a)) + (portRef A0 (instanceRef ae_cmp_ci_a)) (portRef B1 (instanceRef a2)) (portRef B0 (instanceRef a2)) (portRef A1 (instanceRef a2)) (portRef A0 (instanceRef a2)))) - (net af_d_c + (net ae_d_c (joined (portRef CIN (instanceRef a2)) - (portRef COUT (instanceRef af_d_cmp_3)))) - (net partial_full + (portRef COUT (instanceRef ae_cmp_3)))) + (net partial_empty (joined - (portRef AlmostFull) + (portRef AlmostEmpty) (portRef Q (instanceRef FF_0)))) (net Full (joined (portRef Full) (portRef Q (instanceRef FF_1)) - (portRef A (instanceRef INV_1)))) + (portRef A (instanceRef INV_2)))) (net Empty (joined (portRef Empty) (portRef Q (instanceRef FF_2)) - (portRef A (instanceRef INV_0)))) + (portRef A (instanceRef INV_1)))) (net dataout35 (joined (portRef (member Q 0)) @@ -2793,42 +2817,42 @@ (joined (portRef (member Q 35)) (portRef DO18 (instanceRef pdp_ram_0_0_0)))) - (net AmFullThresh6 + (net AmEmptyThresh6 (joined - (portRef (member AmFullThresh 0)) - (portRef B0 (instanceRef af_d_cmp_3)))) - (net AmFullThresh5 + (portRef (member AmEmptyThresh 0)) + (portRef A0 (instanceRef ae_cmp_3)))) + (net AmEmptyThresh5 (joined - (portRef (member AmFullThresh 1)) - (portRef B1 (instanceRef af_d_cmp_2)))) - (net AmFullThresh4 + (portRef (member AmEmptyThresh 1)) + (portRef A1 (instanceRef ae_cmp_2)))) + (net AmEmptyThresh4 (joined - (portRef (member AmFullThresh 2)) - (portRef B0 (instanceRef af_d_cmp_2)))) - (net AmFullThresh3 + (portRef (member AmEmptyThresh 2)) + (portRef A0 (instanceRef ae_cmp_2)))) + (net AmEmptyThresh3 (joined - (portRef (member AmFullThresh 3)) - (portRef B1 (instanceRef af_d_cmp_1)))) - (net AmFullThresh2 + (portRef (member AmEmptyThresh 3)) + (portRef A1 (instanceRef ae_cmp_1)))) + (net AmEmptyThresh2 (joined - (portRef (member AmFullThresh 4)) - (portRef B0 (instanceRef af_d_cmp_1)))) - (net AmFullThresh1 + (portRef (member AmEmptyThresh 4)) + (portRef A0 (instanceRef ae_cmp_1)))) + (net AmEmptyThresh1 (joined - (portRef (member AmFullThresh 5)) - (portRef B1 (instanceRef af_d_cmp_0)))) - (net AmFullThresh0 + (portRef (member AmEmptyThresh 5)) + (portRef A1 (instanceRef ae_cmp_0)))) + (net AmEmptyThresh0 (joined - (portRef (member AmFullThresh 6)) - (portRef B0 (instanceRef af_d_cmp_0)))) + (portRef (member AmEmptyThresh 6)) + (portRef A0 (instanceRef ae_cmp_0)))) (net RPRst (joined (portRef RPReset) - (portRef B (instanceRef OR2_t15)))) + (portRef B (instanceRef OR2_t17)))) (net reset (joined (portRef Reset) - (portRef A (instanceRef OR2_t15)) + (portRef A (instanceRef OR2_t17)) (portRef RST (instanceRef pdp_ram_0_0_0)) (portRef PD (instanceRef FF_90)) (portRef CD (instanceRef FF_89)) @@ -2870,24 +2894,15 @@ (portRef CD (instanceRef FF_21)) (portRef CD (instanceRef FF_20)) (portRef CD (instanceRef FF_19)) - (portRef CD (instanceRef FF_10)) - (portRef CD (instanceRef FF_9)) - (portRef CD (instanceRef FF_8)) - (portRef CD (instanceRef FF_7)) - (portRef CD (instanceRef FF_6)) - (portRef CD (instanceRef FF_5)) - (portRef CD (instanceRef FF_4)) - (portRef CD (instanceRef FF_3)) - (portRef CD (instanceRef FF_1)) - (portRef CD (instanceRef FF_0)))) + (portRef CD (instanceRef FF_1)))) (net rden (joined (portRef RdEn) - (portRef A (instanceRef AND2_t16)))) + (portRef A (instanceRef AND2_t18)))) (net wren (joined (portRef WrEn) - (portRef A (instanceRef AND2_t17)))) + (portRef A (instanceRef AND2_t19)))) (net rclk (joined (portRef RdClock) @@ -2932,7 +2947,16 @@ (portRef CK (instanceRef FF_21)) (portRef CK (instanceRef FF_20)) (portRef CK (instanceRef FF_19)) - (portRef CK (instanceRef FF_2)))) + (portRef CK (instanceRef FF_10)) + (portRef CK (instanceRef FF_9)) + (portRef CK (instanceRef FF_8)) + (portRef CK (instanceRef FF_7)) + (portRef CK (instanceRef FF_6)) + (portRef CK (instanceRef FF_5)) + (portRef CK (instanceRef FF_4)) + (portRef CK (instanceRef FF_3)) + (portRef CK (instanceRef FF_2)) + (portRef CK (instanceRef FF_0)))) (net wclk (joined (portRef WrClock) @@ -2977,16 +3001,7 @@ (portRef CK (instanceRef FF_13)) (portRef CK (instanceRef FF_12)) (portRef CK (instanceRef FF_11)) - (portRef CK (instanceRef FF_10)) - (portRef CK (instanceRef FF_9)) - (portRef CK (instanceRef FF_8)) - (portRef CK (instanceRef FF_7)) - (portRef CK (instanceRef FF_6)) - (portRef CK (instanceRef FF_5)) - (portRef CK (instanceRef FF_4)) - (portRef CK (instanceRef FF_3)) - (portRef CK (instanceRef FF_1)) - (portRef CK (instanceRef FF_0)))) + (portRef CK (instanceRef FF_1)))) (net datain35 (joined (portRef (member Data 0)) diff --git a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.jhd b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.jhd index e69de29..2f1d423 100644 --- a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.jhd +++ b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.jhd @@ -0,0 +1,2 @@ +VHDL_ENTITY_ONLY FIFO_DC_36x128_DynThr_OutReg DEFIN FIFO_DC_36x128_DynThr_OutReg.vhd +MODULE FIFO_DC_36x128_DynThr_OutReg DEFIN FIFO_DC_36x128_DynThr_OutReg.vhd diff --git a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.lpc b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.lpc index 4838502..c8484c7 100644 --- a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.lpc +++ b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.lpc @@ -1,23 +1,23 @@ [Device] -Family=ecp5um -PartType=LFE5UM-85F -PartName=LFE5UM-85F-8MG285C +Family=ecp5um5g +PartType=LFE5UM5G-85F +PartName=LFE5UM5G-85F-8BG381C SpeedGrade=8 -Package=CSFBGA285 +Package=CABGA381 OperatingCondition=COM -Status=C +Status=P [IP] VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=FIFO_DC -CoreRevision=5.7 +CoreRevision=5.8 ModuleName=FIFO_DC_36x128_DynThr_OutReg -SourceFormat=vhdl +SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/17/2015 -Time=15:27:13 +Date=07/06/2018 +Time=16:42:22 [Parameters] Verilog=0 @@ -35,11 +35,11 @@ RWidth=36 regout=1 ClockEn=0 CtrlByRdEn=0 -EmpFlg=0 -PeMode=Static - Dual Threshold +EmpFlg=1 +PeMode=Dynamic - Single Threshold PeAssert=10 PeDeassert=12 -FullFlg=1 +FullFlg=0 PfMode=Dynamic - Single Threshold PfAssert=508 PfDeassert=506 @@ -50,4 +50,4 @@ WDataCount=0 EnECC=0 [Command] -cmd_line= -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 128 -width 36 -rwidth 36 -regout -no_enable -sync_reset -pe -1 -pf 0 +cmd_line= -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 128 -width 36 -rwidth 36 -regout -no_enable -sync_reset -pe 0 -pf -1 diff --git a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.ngd b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.ngd index ff2a058..e3fea9a 100644 Binary files a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.ngd and b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.ngd differ diff --git a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.ngo b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.ngo index a8d344f..dc564a9 100644 Binary files a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.ngo and b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.ngo differ diff --git a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.srp b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.srp index 27eaff2..5996455 100644 --- a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.srp +++ b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.srp @@ -1,19 +1,19 @@ -SCUBA, Version Diamond (64-bit) 3.4.0.80 -Tue Mar 17 15:27:16 2015 +SCUBA, Version Diamond (64-bit) 3.9.1.119 +Fri Jul 6 16:42:28 2018 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. +Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. - Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 128 -width 36 -rwidth 36 -regout -no_enable -sync_reset -pe -1 -pf 0 -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.fdc + Issued command : /d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 128 -width 36 -rwidth 36 -regout -no_enable -sync_reset -pe 0 -pf -1 -fdc /d/jspc22/trb/git/dirich/dirich/diamond/test/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.fdc Circuit name : FIFO_DC_36x128_DynThr_OutReg Module type : ebfifo - Module Version : 5.7 + Module Version : 5.8 Ports : - Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmFullThresh[6:0] - Outputs : Q[35:0], Empty, Full, AlmostFull + Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[6:0] + Outputs : Q[35:0], Empty, Full, AlmostEmpty I/O buffer : not inserted EDIF output : FIFO_DC_36x128_DynThr_OutReg.edn VHDL output : FIFO_DC_36x128_DynThr_OutReg.vhd @@ -24,17 +24,17 @@ Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. Report output : FIFO_DC_36x128_DynThr_OutReg.srp Element Usage : CCU2C : 34 - AND2 : 2 + AND2 : 4 FD1P3BX : 2 FD1P3DX : 46 - FD1S3BX : 1 - FD1S3DX : 42 - INV : 2 + FD1S3BX : 2 + FD1S3DX : 41 + INV : 3 OR2 : 1 ROM16X1A : 20 XOR2 : 15 PDPW16KD : 1 Estimated Resource Usage: - LUT : 106 + LUT : 108 EBR : 1 Reg : 91 diff --git a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd index da7916d..907d34a 100644 --- a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd +++ b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.4.0.80 --- Module Version: 5.7 ---/opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 128 -width 36 -rwidth 36 -regout -no_enable -sync_reset -pe -1 -pf 0 -fdc /home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.fdc +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.1.119 +-- Module Version: 5.8 +--/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 128 -width 36 -rwidth 36 -regout -no_enable -sync_reset -pe 0 -pf -1 -fdc /d/jspc22/trb/git/dirich/dirich/diamond/test/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.fdc --- Tue Mar 17 15:27:16 2015 +-- Fri Jul 6 16:42:28 2018 library IEEE; use IEEE.std_logic_1164.all; @@ -18,11 +18,11 @@ entity FIFO_DC_36x128_DynThr_OutReg is RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - AmFullThresh: in std_logic_vector(6 downto 0); + AmEmptyThresh: in std_logic_vector(6 downto 0); Q: out std_logic_vector(35 downto 0); Empty: out std_logic; Full: out std_logic; - AlmostFull: out std_logic); + AlmostEmpty: out std_logic); end FIFO_DC_36x128_DynThr_OutReg; architecture Structure of FIFO_DC_36x128_DynThr_OutReg is @@ -32,6 +32,7 @@ architecture Structure of FIFO_DC_36x128_DynThr_OutReg is signal invout_0: std_logic; signal w_g2b_xor_cluster_1: std_logic; signal r_g2b_xor_cluster_1: std_logic; + signal rcnt_reg_6_inv: std_logic; signal w_gdata_0: std_logic; signal w_gdata_1: std_logic; signal w_gdata_2: std_logic; @@ -110,9 +111,10 @@ architecture Structure of FIFO_DC_36x128_DynThr_OutReg is signal r_gcount_w6: std_logic; signal r_gcount_w27: std_logic; signal r_gcount_w7: std_logic; + signal rcnt_reg_7: std_logic; signal empty_i: std_logic; - signal rRst: std_logic; signal full_i: std_logic; + signal rRst: std_logic; signal iwcount_0: std_logic; signal iwcount_1: std_logic; signal w_gctr_ci: std_logic; @@ -141,21 +143,20 @@ architecture Structure of FIFO_DC_36x128_DynThr_OutReg is signal co3_1: std_logic; signal co2_1: std_logic; signal rcount_7: std_logic; - signal wcnt_sub_0: std_logic; + signal rcnt_sub_0: std_logic; signal precin: std_logic; - signal wcnt_sub_1: std_logic; - signal wcnt_sub_2: std_logic; + signal rcnt_sub_1: std_logic; + signal rcnt_sub_2: std_logic; signal co0_2: std_logic; - signal wcnt_sub_3: std_logic; - signal wcnt_sub_4: std_logic; + signal rcnt_sub_3: std_logic; + signal rcnt_sub_4: std_logic; signal co1_2: std_logic; - signal wcnt_sub_5: std_logic; - signal wcnt_sub_6: std_logic; + signal rcnt_sub_5: std_logic; + signal rcnt_sub_6: std_logic; signal co2_2: std_logic; - signal wcnt_sub_7: std_logic; - signal wcnt_sub_msb: std_logic; + signal rcnt_sub_7: std_logic; + signal rcnt_sub_msb: std_logic; signal co3_2: std_logic; - signal rden_i: std_logic; signal cmp_ci: std_logic; signal wcount_r0: std_logic; signal wcount_r1: std_logic; @@ -178,6 +179,7 @@ architecture Structure of FIFO_DC_36x128_DynThr_OutReg is signal empty_cmp_set: std_logic; signal empty_d: std_logic; signal empty_d_c: std_logic; + signal wren_i: std_logic; signal cmp_ci_1: std_logic; signal rcount_w0: std_logic; signal rcount_w1: std_logic; @@ -200,23 +202,24 @@ architecture Structure of FIFO_DC_36x128_DynThr_OutReg is signal full_cmp_set: std_logic; signal full_d: std_logic; signal full_d_c: std_logic; - signal wren_i: std_logic; + signal rden_i: std_logic; signal cmp_ci_2: std_logic; - signal wcnt_reg_0: std_logic; - signal wcnt_reg_1: std_logic; + signal rcnt_reg_0: std_logic; + signal rcnt_reg_1: std_logic; signal co0_5: std_logic; - signal wcnt_reg_2: std_logic; - signal wcnt_reg_3: std_logic; + signal rcnt_reg_2: std_logic; + signal rcnt_reg_3: std_logic; signal co1_5: std_logic; - signal wcnt_reg_4: std_logic; - signal wcnt_reg_5: std_logic; + signal rcnt_reg_4: std_logic; + signal rcnt_reg_5: std_logic; signal co2_5: std_logic; - signal wcnt_reg_6: std_logic; - signal wcnt_reg_7: std_logic; - signal af_d: std_logic; + signal rcnt_reg_6: std_logic; + signal ae_clrsig: std_logic; + signal ae_setsig: std_logic; + signal ae_d: std_logic; signal scuba_vhi: std_logic; signal scuba_vlo: std_logic; - signal af_d_c: std_logic; + signal ae_d_c: std_logic; attribute MEM_LPC_FILE : string; attribute MEM_INIT_FILE : string; @@ -320,61 +323,61 @@ architecture Structure of FIFO_DC_36x128_DynThr_OutReg is begin -- component instantiation statements - AND2_t17: AND2 + AND2_t19: AND2 port map (A=>WrEn, B=>invout_1, Z=>wren_i); - INV_1: INV + INV_2: INV port map (A=>full_i, Z=>invout_1); - AND2_t16: AND2 + AND2_t18: AND2 port map (A=>RdEn, B=>invout_0, Z=>rden_i); - INV_0: INV + INV_1: INV port map (A=>empty_i, Z=>invout_0); - OR2_t15: OR2 + OR2_t17: OR2 port map (A=>Reset, B=>RPReset, Z=>rRst); - XOR2_t14: XOR2 + XOR2_t16: XOR2 port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - XOR2_t13: XOR2 + XOR2_t15: XOR2 port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - XOR2_t12: XOR2 + XOR2_t14: XOR2 port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); - XOR2_t11: XOR2 + XOR2_t13: XOR2 port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); - XOR2_t10: XOR2 + XOR2_t12: XOR2 port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); - XOR2_t9: XOR2 + XOR2_t11: XOR2 port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); - XOR2_t8: XOR2 + XOR2_t10: XOR2 port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); - XOR2_t7: XOR2 + XOR2_t9: XOR2 port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); - XOR2_t6: XOR2 + XOR2_t8: XOR2 port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); - XOR2_t5: XOR2 + XOR2_t7: XOR2 port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); - XOR2_t4: XOR2 + XOR2_t6: XOR2 port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); - XOR2_t3: XOR2 + XOR2_t5: XOR2 port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); - XOR2_t2: XOR2 + XOR2_t4: XOR2 port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - XOR2_t1: XOR2 + XOR2_t3: XOR2 port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6); LUT4_19: ROM16X1A @@ -461,8 +464,8 @@ begin port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1, AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0); - XOR2_t0: XOR2 - port map (A=>wcount_7, B=>r_gcount_w27, Z=>wcnt_sub_msb); + XOR2_t2: XOR2 + port map (A=>w_gcount_r27, B=>rcount_7, Z=>rcnt_sub_msb); LUT4_3: ROM16X1A generic map (initval=> X"0410") @@ -484,6 +487,15 @@ begin port map (AD3=>wptr_7, AD2=>wcount_7, AD1=>r_gcount_w27, AD0=>scuba_vlo, DO0=>full_cmp_clr); + INV_0: INV + port map (A=>rcnt_reg_6, Z=>rcnt_reg_6_inv); + + AND2_t1: AND2 + port map (A=>rcnt_reg_7, B=>rcnt_reg_6_inv, Z=>ae_clrsig); + + AND2_t0: AND2 + port map (A=>rcnt_reg_7, B=>rcnt_reg_6, Z=>ae_setsig); + pdp_ram_0_0_0: PDPW16KD generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "ENABLED", @@ -817,28 +829,28 @@ begin port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27); FF_10: FD1S3DX - port map (D=>wcnt_sub_0, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_0); + port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0); FF_9: FD1S3DX - port map (D=>wcnt_sub_1, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_1); + port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1); FF_8: FD1S3DX - port map (D=>wcnt_sub_2, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_2); + port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2); FF_7: FD1S3DX - port map (D=>wcnt_sub_3, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_3); + port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3); FF_6: FD1S3DX - port map (D=>wcnt_sub_4, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_4); + port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4); FF_5: FD1S3DX - port map (D=>wcnt_sub_5, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_5); + port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5); FF_4: FD1S3DX - port map (D=>wcnt_sub_6, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_6); + port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6); FF_3: FD1S3DX - port map (D=>wcnt_sub_7, CK=>WrClock, CD=>Reset, Q=>wcnt_reg_7); + port map (D=>rcnt_sub_7, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_7); FF_2: FD1S3BX port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); @@ -846,8 +858,8 @@ begin FF_1: FD1S3DX port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); - FF_0: FD1S3DX - port map (D=>af_d, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + FF_0: FD1S3BX + port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty); w_gctr_cia: CCU2C generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", @@ -934,44 +946,44 @@ begin B1=>scuba_vhi, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>precin); - wcnt_0: CCU2C + rcnt_0: CCU2C generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", INIT0=> X"99AA") - port map (A0=>scuba_vhi, A1=>wcount_0, B0=>scuba_vlo, - B1=>rcount_w0, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, - D1=>scuba_vhi, CIN=>precin, S0=>open, S1=>wcnt_sub_0, + port map (A0=>scuba_vhi, A1=>wcount_r0, B0=>scuba_vlo, + B1=>rcount_0, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>precin, S0=>open, S1=>rcnt_sub_0, COUT=>co0_2); - wcnt_1: CCU2C + rcnt_1: CCU2C generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", INIT0=> X"99AA") - port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_w1, - B1=>rcount_w2, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, - D1=>scuba_vhi, CIN=>co0_2, S0=>wcnt_sub_1, S1=>wcnt_sub_2, + port map (A0=>wcount_r1, A1=>wcount_r2, B0=>rcount_1, + B1=>rcount_2, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co0_2, S0=>rcnt_sub_1, S1=>rcnt_sub_2, COUT=>co1_2); - wcnt_2: CCU2C + rcnt_2: CCU2C generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", INIT0=> X"99AA") - port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_w3, - B1=>r_g2b_xor_cluster_0, C0=>scuba_vhi, C1=>scuba_vhi, - D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_2, S0=>wcnt_sub_3, - S1=>wcnt_sub_4, COUT=>co2_2); + port map (A0=>wcount_r3, A1=>w_g2b_xor_cluster_0, B0=>rcount_3, + B1=>rcount_4, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co1_2, S0=>rcnt_sub_3, S1=>rcnt_sub_4, + COUT=>co2_2); - wcnt_3: CCU2C + rcnt_3: CCU2C generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", INIT0=> X"99AA") - port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_w5, - B1=>rcount_w6, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, - D1=>scuba_vhi, CIN=>co2_2, S0=>wcnt_sub_5, S1=>wcnt_sub_6, + port map (A0=>wcount_r5, A1=>wcount_r6, B0=>rcount_5, + B1=>rcount_6, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_2, S0=>rcnt_sub_5, S1=>rcnt_sub_6, COUT=>co3_2); - wcnt_4: CCU2C + rcnt_4: CCU2C generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", INIT0=> X"99AA") - port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + port map (A0=>rcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, - D1=>scuba_vhi, CIN=>co3_2, S0=>wcnt_sub_7, S1=>open, + D1=>scuba_vhi, CIN=>co3_2, S0=>rcnt_sub_7, S1=>open, COUT=>open); empty_cmp_ci_a: CCU2C @@ -1063,43 +1075,43 @@ begin D1=>scuba_vhi, CIN=>full_d_c, S0=>full_d, S1=>open, COUT=>open); - af_d_cmp_ci_a: CCU2C + ae_cmp_ci_a: CCU2C generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"66AA", INIT0=> X"66AA") - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, CIN=>'X', S0=>open, S1=>open, COUT=>cmp_ci_2); - af_d_cmp_0: CCU2C + ae_cmp_0: CCU2C generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", INIT0=> X"99AA") - port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), - B1=>AmFullThresh(1), C0=>scuba_vhi, C1=>scuba_vhi, + port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), + B0=>rcnt_reg_0, B1=>rcnt_reg_1, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, CIN=>cmp_ci_2, S0=>open, S1=>open, COUT=>co0_5); - af_d_cmp_1: CCU2C + ae_cmp_1: CCU2C generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", INIT0=> X"99AA") - port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), - B1=>AmFullThresh(3), C0=>scuba_vhi, C1=>scuba_vhi, + port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), + B0=>rcnt_reg_2, B1=>rcnt_reg_3, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co0_5, S0=>open, S1=>open, COUT=>co1_5); - af_d_cmp_2: CCU2C + ae_cmp_2: CCU2C generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", INIT0=> X"99AA") - port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), - B1=>AmFullThresh(5), C0=>scuba_vhi, C1=>scuba_vhi, + port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), + B0=>rcnt_reg_4, B1=>rcnt_reg_5, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, D1=>scuba_vhi, CIN=>co1_5, S0=>open, S1=>open, COUT=>co2_5); - af_d_cmp_3: CCU2C + ae_cmp_3: CCU2C generic map (INJECT1_1=> "NO", INJECT1_0=> "NO", INIT1=> X"99AA", INIT0=> X"99AA") - port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), - B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, - D1=>scuba_vhi, CIN=>co2_5, S0=>open, S1=>open, COUT=>af_d_c); + port map (A0=>AmEmptyThresh(6), A1=>ae_setsig, B0=>rcnt_reg_6, + B1=>ae_clrsig, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, + D1=>scuba_vhi, CIN=>co2_5, S0=>open, S1=>open, COUT=>ae_d_c); scuba_vhi_inst: VHI port map (Z=>scuba_vhi); @@ -1112,7 +1124,7 @@ begin INIT0=> X"66AA") port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, B1=>scuba_vlo, C0=>scuba_vhi, C1=>scuba_vhi, D0=>scuba_vhi, - D1=>scuba_vhi, CIN=>af_d_c, S0=>af_d, S1=>open, COUT=>open); + D1=>scuba_vhi, CIN=>ae_d_c, S0=>ae_d, S1=>open, COUT=>open); Empty <= empty_i; Full <= full_i; diff --git a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg_generate.log b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg_generate.log index 3986559..c0cef45 100644 --- a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg_generate.log +++ b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg_generate.log @@ -3,24 +3,24 @@ Starting process: Configuration data saved -SCUBA, Version Diamond (64-bit) 3.4.0.80 -Tue Mar 17 15:27:13 2015 +SCUBA, Version Diamond (64-bit) 3.9.1.119 +Fri Jul 6 16:42:22 2018 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. +Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. BEGIN SCUBA Module Synthesis - Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 128 -width 36 -rwidth 36 -regout -no_enable -sync_reset -pe -1 -pf 0 + Issued command : /d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 128 -width 36 -rwidth 36 -regout -no_enable -sync_reset -pe 0 -pf -1 Circuit name : FIFO_DC_36x128_DynThr_OutReg Module type : ebfifo - Module Version : 5.7 + Module Version : 5.8 Ports : - Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmFullThresh[6:0] - Outputs : Q[35:0], Empty, Full, AlmostFull + Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[6:0] + Outputs : Q[35:0], Empty, Full, AlmostEmpty I/O buffer : not inserted EDIF output : FIFO_DC_36x128_DynThr_OutReg.edn VHDL output : FIFO_DC_36x128_DynThr_OutReg.vhd @@ -30,7 +30,7 @@ BEGIN SCUBA Module Synthesis Bus notation : big endian Report output : FIFO_DC_36x128_DynThr_OutReg.srp Estimated Resource Usage: - LUT : 106 + LUT : 108 EBR : 1 Reg : 91 diff --git a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd index 45d014d..27d7158 100644 --- a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd +++ b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd @@ -1,6 +1,6 @@ --- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.4.0.80 --- Module Version: 5.7 --- Tue Mar 17 15:27:16 2015 +-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.9.1.119 +-- Module Version: 5.8 +-- Fri Jul 6 16:42:28 2018 -- parameterized module component declaration component FIFO_DC_36x128_DynThr_OutReg @@ -8,13 +8,13 @@ component FIFO_DC_36x128_DynThr_OutReg WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - AmFullThresh: in std_logic_vector(6 downto 0); + AmEmptyThresh: in std_logic_vector(6 downto 0); Q: out std_logic_vector(35 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostFull: out std_logic); + Full: out std_logic; AlmostEmpty: out std_logic); end component; -- parameterized module component instance __ : FIFO_DC_36x128_DynThr_OutReg port map (Data(35 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, - RdEn=>__, Reset=>__, RPReset=>__, AmFullThresh(6 downto 0)=>__, - Q(35 downto 0)=>__, Empty=>__, Full=>__, AlmostFull=>__); + RdEn=>__, Reset=>__, RPReset=>__, AmEmptyThresh(6 downto 0)=>__, + Q(35 downto 0)=>__, Empty=>__, Full=>__, AlmostEmpty=>__); diff --git a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/generate_core.tcl b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/generate_core.tcl index 1f2afd3..be47d86 100644 --- a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/generate_core.tcl +++ b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/generate_core.tcl @@ -88,13 +88,13 @@ set scuba "$Para(FPGAPath)/scuba" set modulename "FIFO_DC_36x128_DynThr_OutReg" set lang "vhdl" set lpcfile "$Para(sbp_path)/$modulename.lpc" -set arch "sa5p00m" +set arch "sa5p00g" set cmd_line [GetCmdLine $lpcfile] set fdcfile "$Para(sbp_path)/$modulename.fdc" if {[file exists $fdcfile] == 0} { append scuba " " $cmd_line } else { - append scuba " " $cmd_line " " -fdc " " $fdcfile + append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" } set Para(result) [catch {eval exec "$scuba"} msg] #puts $msg diff --git a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/generate_ngd.tcl b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/generate_ngd.tcl index 8e87ae6..9b55da5 100644 --- a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/generate_ngd.tcl +++ b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/generate_ngd.tcl @@ -52,13 +52,13 @@ set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" set Para(ModuleName) "FIFO_DC_36x128_DynThr_OutReg" set Para(Module) "FIFO_DC" -set Para(libname) ecp5um -set Para(arch_name) sa5p00m -set Para(PartType) "LFE5UM-85F" +set Para(libname) ecp5um5g +set Para(arch_name) sa5p00g +set Para(PartType) "LFE5UM5G-85F" -set Para(tech_syn) ecp5um -set Para(tech_cae) ecp5um -set Para(Package) "CSFBGA285" +set Para(tech_syn) ecp5um5g +set Para(tech_cae) ecp5um5g +set Para(Package) "CABGA381" set Para(SpeedGrade) "8" set Para(FMax) "100" set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" diff --git a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/msg_file.log b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/msg_file.log index 4fd4900..27f8086 100644 --- a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/msg_file.log +++ b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/msg_file.log @@ -1,21 +1,21 @@ -SCUBA, Version Diamond (64-bit) 3.4.0.80 -Tue Mar 17 15:27:13 2015 +SCUBA, Version Diamond (64-bit) 3.9.1.119 +Fri Jul 6 16:42:22 2018 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved. +Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. BEGIN SCUBA Module Synthesis - Issued command : /opt/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 128 -width 36 -rwidth 36 -regout -no_enable -sync_reset -pe -1 -pf 0 + Issued command : /d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n FIFO_DC_36x128_DynThr_OutReg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type ebfifo -depth 128 -width 36 -rwidth 36 -regout -no_enable -sync_reset -pe 0 -pf -1 Circuit name : FIFO_DC_36x128_DynThr_OutReg Module type : ebfifo - Module Version : 5.7 + Module Version : 5.8 Ports : - Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmFullThresh[6:0] - Outputs : Q[35:0], Empty, Full, AlmostFull + Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset, AmEmptyThresh[6:0] + Outputs : Q[35:0], Empty, Full, AlmostEmpty I/O buffer : not inserted EDIF output : FIFO_DC_36x128_DynThr_OutReg.edn VHDL output : FIFO_DC_36x128_DynThr_OutReg.vhd @@ -25,7 +25,7 @@ BEGIN SCUBA Module Synthesis Bus notation : big endian Report output : FIFO_DC_36x128_DynThr_OutReg.srp Estimated Resource Usage: - LUT : 106 + LUT : 108 EBR : 1 Reg : 91 diff --git a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/tb_FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/tb_FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd index eb311c8..535809f 100644 --- a/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/tb_FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd +++ b/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/tb_FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd @@ -1,4 +1,4 @@ --- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.4.0.80 +-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.9.1.119 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; @@ -17,9 +17,9 @@ architecture test of tb is port (Data : in std_logic_vector(35 downto 0); WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic; - AmFullThresh : in std_logic_vector(6 downto 0); + AmEmptyThresh : in std_logic_vector(6 downto 0); Q : out std_logic_vector(35 downto 0); Empty: out std_logic; - Full: out std_logic; AlmostFull: out std_logic + Full: out std_logic; AlmostEmpty: out std_logic ); end component; @@ -30,17 +30,17 @@ architecture test of tb is signal RdEn: std_logic := '0'; signal Reset: std_logic := '0'; signal RPReset: std_logic := '0'; - signal AmFullThresh : std_logic_vector(6 downto 0) := (others => '0'); + signal AmEmptyThresh : std_logic_vector(6 downto 0) := (others => '0'); signal Q : std_logic_vector(35 downto 0); signal Empty: std_logic; signal Full: std_logic; - signal AlmostFull: std_logic; + signal AlmostEmpty: std_logic; begin u1 : FIFO_DC_36x128_DynThr_OutReg port map (Data => Data, WrClock => WrClock, RdClock => RdClock, WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset, - AmFullThresh => AmFullThresh, Q => Q, Empty => Empty, Full => Full, - AlmostFull => AlmostFull + AmEmptyThresh => AmEmptyThresh, Q => Q, Empty => Empty, Full => Full, + AlmostEmpty => AlmostEmpty ); process diff --git a/releases/tdc_v2.3/Channel_200.vhd b/releases/tdc_v2.3/Channel_200.vhd index 091aff6..9bca469 100644 --- a/releases/tdc_v2.3/Channel_200.vhd +++ b/releases/tdc_v2.3/Channel_200.vhd @@ -68,7 +68,7 @@ architecture Channel_200 of Channel_200 is signal data_a : std_logic_vector(327-FPGA_TYPE*8 downto 0); signal data_b : std_logic_vector(327-FPGA_TYPE*8 downto 0); signal result : std_logic_vector(327-FPGA_TYPE*8 downto 0); - signal ff_array_en : std_logic; + signal ff_array_en : std_logic := '0'; -- hit detection signal result_2_r : std_logic := '0'; @@ -120,6 +120,7 @@ architecture Channel_200 of Channel_200 is signal ringBuffer_empty : std_logic; signal ringBuffer_full : std_logic; signal ringBuffer_almost_full_sync : std_logic; + signal ringBuffer_almost_empty : std_logic := '0'; signal ringBuffer_almost_full : std_logic := '0'; signal ringBuffer_almost_full_flag : std_logic := '0'; signal ringBuffer_wr_en : std_logic; @@ -376,9 +377,10 @@ begin -- Channel_200 CHAIN_DATA_OUT => chain ); -- end generate; - + assert RING_BUFFER_SIZE = 7 report "only ring buffer size 7 is available at the moment" severity error; + RingBuffer_128_dyn : if RING_BUFFER_SIZE = 7 generate - FIFO : FIFO_DC_36x128_DynThr_OutReg + FIFO : entity work.FIFO_DC_36x128_DynThr_OutReg port map ( Data => ringBuffer_data_in, WrClock => CLK_200, @@ -387,13 +389,15 @@ begin -- Channel_200 RdEn => ringBuffer_rd_en, Reset => RESET_100, RPReset => RESET_100, - AmFullThresh => RING_BUFFER_FULL_THRES_IN, + AmEmptyThresh => RING_BUFFER_FULL_THRES_IN, Q => ringBuffer_data_out, Empty => ringBuffer_empty, Full => ringBuffer_full, - AlmostFull => ringBuffer_almost_full); + AlmostEmpty => ringBuffer_almost_empty); end generate RingBuffer_128_dyn; + ringBuffer_almost_full <= not ringBuffer_almost_empty; + RingBuffer_64_dyn : if RING_BUFFER_SIZE = 5 generate FIFO : FIFO_DC_36x64_DynThr_OutReg port map ( @@ -459,8 +463,8 @@ begin -- Channel_200 AlmostFull => ringBuffer_almost_full); end generate RingBuffer_32; - ringBuffer_almost_full_sync <= ringBuffer_almost_full when rising_edge(CLK_100); - ringBuffer_rd_en <= ringBuffer_rd_data or ringBuffer_almost_full_sync when rising_edge(CLK_100); + ringBuffer_almost_full_sync <= ringBuffer_almost_full when rising_edge(CLK_100); + ringBuffer_rd_en <= ringBuffer_rd_data or (ringBuffer_almost_full and ringBuffer_almost_full_sync and not ringBuffer_rd_en) when rising_edge(CLK_100); FIFO_ALMOST_FULL_OUT <= ringBuffer_almost_full_flag; FifoAlmostEmptyFlag : process (CLK_100) @@ -470,7 +474,7 @@ begin -- Channel_200 ringBuffer_almost_full_flag <= '0'; elsif FSM_RD_STATE = READOUT_DATA_C then ringBuffer_almost_full_flag <= '0'; - elsif ringBuffer_almost_full_sync = '1' then + elsif ringBuffer_almost_full = '1' then ringBuffer_almost_full_flag <= '1'; end if; end if;