From: Peter Lemmens Date: Wed, 11 Sep 2013 12:40:05 +0000 (+0200) Subject: New ipx files constructed for serdesses. Different serdes for up an downstream X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b71da1c169c44d93f9ead96f467e91ba8cb67a83;p=soda.git New ipx files constructed for serdesses. Different serdes for up an downstream downstream: no tx-fifo for sync operation but does have rx-fifo for reply (async) upstream: no rx-fifo for sync operation but does have tx-fifo for reply (asynx) Clock domains now separated. SOURCE: tx-clock=fabric-clock (200MHz). THis is the origin of SODA/master-clock rx-clock=fabric clock. Phase differences taken care of by rx-fifo CLIENT: rx-clock=reconstructed clock tx-clock=rx-clock --- diff --git a/soda_client.ldf b/soda_client.ldf index a2c60d4..874c4b5 100644 --- a/soda_client.ldf +++ b/soda_client.ldf @@ -26,6 +26,18 @@ + + + + + + + + + + + + @@ -281,9 +293,6 @@ - - - diff --git a/soda_source.ldf b/soda_source.ldf index 5933fd5..a9f9e31 100644 --- a/soda_source.ldf +++ b/soda_source.ldf @@ -14,16 +14,28 @@ - + + + + - + - + + + + + + + + + + @@ -68,9 +80,6 @@ - - - @@ -254,9 +263,6 @@ - - - @@ -281,9 +287,6 @@ - - - @@ -308,6 +311,9 @@ + + + diff --git a/source/TB_soda_chain.vhd b/source/TB_soda_chain.vhd index b928d27..0ada9e4 100644 --- a/source/TB_soda_chain.vhd +++ b/source/TB_soda_chain.vhd @@ -18,12 +18,14 @@ end entity; architecture TestBench of TB_soda_chain is -- Clock period definitions - constant clk_period: time:= 4ns; + constant sysclk_period: time:= 5ns; + constant sodaclk_period: time:= 4.999ns; --Inputs signal rst_S : std_logic; - signal clk_S : std_logic; + signal sys_clk_S : std_logic; + signal soda_clk_S : std_logic; signal enable_S : std_logic := '0'; signal SOB_S : std_logic := '0'; signal src_dnstream_dlm_word_S : std_logic_vector(7 downto 0) := (others => '0'); @@ -50,7 +52,7 @@ begin THE_SOB_SOURCE : soda_start_of_burst_faker port map( - SYSCLK => clk_S, + SYSCLK => sys_clk_S, RESET => rst_S, SODA_BURST_PULSE_OUT => SOB_S ); @@ -58,7 +60,7 @@ begin THE_SODA_SOURCE : soda_source port map( - SYSCLK => clk_S, + SYSCLK => sys_clk_S, RESET => rst_S, CLEAR => '0', CLK_EN => '1', @@ -75,14 +77,13 @@ begin SODA_READ_IN => soda_read, SODA_WRITE_IN => soda_write, SODA_ACK_OUT => soda_ack, - LEDS_OUT => soda_leds, - TEST_LINE => open, - STAT => open + LEDS_OUT => soda_leds ); A_SODA_HUB : soda_hub port map( - SYSCLK => clk_S, + SYSCLK => sys_clk_S, + SODACLK => soda_clk_S, RESET => rst_S, CLEAR => '0', CLK_EN => '1', @@ -110,7 +111,8 @@ begin A_SODA_CLIENT : soda_client port map( - SYSCLK => clk_S, + SYSCLK => sys_clk_S, + SODACLK => soda_clk_S, RESET => rst_S, CLEAR => '0', CLK_EN => '1', @@ -126,7 +128,8 @@ begin SODA_READ_IN => soda_read, SODA_WRITE_IN => soda_write, SODA_ACK_OUT => soda_ack, - STAT => open + LEDS_OUT => open, + LINK_DEBUG_IN => (others => '0') ); end generate; @@ -141,71 +144,73 @@ begin soda_addr <= "0000"; soda_data_in <= x"08000000"; -- soda_reset soda_write <= '1'; - wait for clk_period; + wait for sysclk_period; soda_write <= '0'; - wait for clk_period; + wait for sysclk_period; soda_addr <= "0000"; soda_data_in <= x"00000000"; -- soda_reset soda_write <= '1'; - wait for clk_period; + wait for sysclk_period; soda_write <= '0'; ------------------------------------------------------------------------------------------------------------ wait for 2us; soda_addr <= "0100"; soda_data_in <= x"FFFFFFFD"; -- soda_write <= '1'; - wait for clk_period; + wait for sysclk_period; soda_write <= '0'; ------------------------------------------------------------------------------------------------------------ wait for 700us; soda_addr <= "0000"; soda_data_in <= x"40000000"; -- time_calibration soda_write <= '1'; - wait for clk_period; + wait for sysclk_period; soda_write <= '0'; ------------------------------------------------------------------------------------------------------------ wait for 700us; soda_addr <= "0100"; soda_data_in <= x"FFFFFFFE"; -- time_calibration soda_write <= '1'; - wait for clk_period; + wait for sysclk_period; soda_write <= '0'; ------------------------------------------------------------------------------------------------------------ wait for 100us; soda_addr <= "1001"; soda_read <= '1'; - wait for clk_period; + wait for sysclk_period; soda_read <= '0'; end process; ------------------------------------------------------------------------------------------------------------ -- Clock process definitions ------------------------------------------------------------------------------------------------------------ - clk_proc :process - begin - clk_S <= '0'; - wait for clk_period/2; - clk_S <= '1'; - wait for clk_period/2; - end process; - - -- reset process - reset_proc: process - begin -rst_S <= '1'; -wait for clk_period * 5; -rst_S <= '0'; -wait; - end process; - --- burst_proc :process --- begin ---SOB_S <= '0'; ---wait for 2.35us; ---SOB_S <= '1'; ---wait for 50ns; --- end process; + sysclk_proc :process + begin + sys_clk_S <= '0'; + wait for sysclk_period/2; + sys_clk_S <= '1'; + wait for sysclk_period/2; + end process; + + sodaclk_proc :process + begin + soda_clk_S <= '0'; + wait for sodaclk_period/2; + soda_clk_S <= '1'; + wait for sodaclk_period/2; + end process; + +------------------------------------------------------------------------------------------------------------ +-- reset process +------------------------------------------------------------------------------------------------------------ + reset_proc: process + begin + rst_S <= '1'; + wait for sysclk_period * 5; + rst_S <= '0'; + wait; + end process; end TestBench; diff --git a/source/serdes_sync_downstream.txt b/source/serdes_sync_downstream.txt index 7fe2574..7ea13c8 100644 --- a/source/serdes_sync_downstream.txt +++ b/source/serdes_sync_downstream.txt @@ -52,7 +52,7 @@ CCLMARK "7" CH0_SSLB "DISABLED" CH0_SPLBPORTS "DISABLED" CH0_PCSLBPORTS "DISABLED" -INT_ALL "ENABLED" -QD_REFCK2CORE "ENABLED" +INT_ALL "DISABLED" +QD_REFCK2CORE "DISABLED" diff --git a/source/serdes_sync_downstream.vhd b/source/serdes_sync_downstream.vhd index e79f778..36d0a69 100644 --- a/source/serdes_sync_downstream.vhd +++ b/source/serdes_sync_downstream.vhd @@ -1580,7 +1580,6 @@ entity serdes_sync_downstream is tx_serdes_rst_c : in std_logic; tx_pll_lol_qd_s : out std_logic; rst_qd_c : in std_logic; - refclk2fpga : out std_logic; serdes_rst_qd_c : in std_logic); end serdes_sync_downstream; @@ -2138,8 +2137,6 @@ end component; attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100"; attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100"; - attribute FREQUENCY_PIN_REFCK2CORE: string; - attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200"; attribute black_box_pad_pin: string; attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; @@ -2170,7 +2167,6 @@ begin vlo_inst : VLO port map(Z => fpsc_vlo); vhi_inst : VHI port map(Z => fpsc_vhi); - refclk2fpga <= refclk2fpga_sig; rx_los_low_ch0_s <= rx_los_low_ch0_sig; rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig; tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; diff --git a/source/serdes_sync_upstream.txt b/source/serdes_sync_upstream.txt index df3f7f3..1c55bd7 100644 --- a/source/serdes_sync_upstream.txt +++ b/source/serdes_sync_upstream.txt @@ -52,7 +52,7 @@ CCLMARK "7" CH0_SSLB "DISABLED" CH0_SPLBPORTS "DISABLED" CH0_PCSLBPORTS "DISABLED" -INT_ALL "ENABLED" -QD_REFCK2CORE "ENABLED" +INT_ALL "DISABLED" +QD_REFCK2CORE "DISABLED" diff --git a/source/serdes_sync_upstream.vhd b/source/serdes_sync_upstream.vhd index a73106d..af538de 100644 --- a/source/serdes_sync_upstream.vhd +++ b/source/serdes_sync_upstream.vhd @@ -1579,7 +1579,6 @@ entity serdes_sync_upstream is tx_serdes_rst_c : in std_logic; tx_pll_lol_qd_s : out std_logic; rst_qd_c : in std_logic; - refclk2fpga : out std_logic; serdes_rst_qd_c : in std_logic); end serdes_sync_upstream; @@ -2137,8 +2136,6 @@ end component; attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100"; attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100"; - attribute FREQUENCY_PIN_REFCK2CORE: string; - attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200"; attribute black_box_pad_pin: string; attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; @@ -2169,7 +2166,6 @@ begin vlo_inst : VLO port map(Z => fpsc_vlo); vhi_inst : VHI port map(Z => fpsc_vhi); - refclk2fpga <= refclk2fpga_sig; rx_los_low_ch0_s <= rx_los_low_ch0_sig; rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig; tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; diff --git a/source/soda_client.vhd b/source/soda_client.vhd index 5696766..6642b41 100644 --- a/source/soda_client.vhd +++ b/source/soda_client.vhd @@ -12,6 +12,7 @@ use work.soda_components.all; entity soda_client is port( SYSCLK : in std_logic; -- fabric clock + SODACLK : in std_logic; -- recovered clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; @@ -35,8 +36,6 @@ end soda_client; architecture Behavioral of soda_client is --SODA - - signal enable_S : std_logic := '0'; signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0'); signal soda_cmd_valid_S : std_logic := '0'; signal start_of_superburst_S : std_logic := '0'; @@ -48,7 +47,7 @@ architecture Behavioral of soda_client is type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); signal CURRENT_STATE, NEXT_STATE: STATES; - -- slave bus signals +-- slave bus signals signal bus_ack_x : std_logic; signal bus_ack : std_logic; signal store_wr_x : std_logic; @@ -60,34 +59,34 @@ architecture Behavioral of soda_client is signal tx_dlm_out_S : std_logic; -- debug -signal debug_status_S : std_logic_vector(31 downto 0) := (others => '0'); -signal debug_rx_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); -signal debug_tx_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); -signal debug_SOS_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); -signal debug_cmd_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); + signal debug_status_S : std_logic_vector(31 downto 0) := (others => '0'); + signal debug_rx_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); + signal debug_tx_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); + signal debug_SOS_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); + signal debug_cmd_cnt_S : std_logic_vector(31 downto 0) := (others => '0'); begin packet_handler : soda_packet_handler port map( - SYSCLK => SYSCLK, - RESET => RESET, - CLEAR => '0', - CLK_EN => '1', + SODACLK => SODACLK, + RESET => RESET, + CLEAR => '0', + CLK_EN => '1', --Internal Connection - START_OF_SUPERBURST => start_of_superburst_S, - SUPER_BURST_NR => super_burst_nr_S, - SODA_CMD_VALID_S => soda_cmd_valid_S, - SODA_CMD_WORD_S => soda_cmd_word_S, - CRC_VALID_OUT => crc_valid_S, - CRC_DATA_OUT => crc_data_S, - RX_DLM_IN => RX_DLM_IN, - RX_DLM_WORD_IN => RX_DLM_WORD_IN + START_OF_SUPERBURST_OUT => start_of_superburst_S, + SUPER_BURST_NR_OUT => super_burst_nr_S, + SODA_CMD_VALID_OUT => soda_cmd_valid_S, + SODA_CMD_WORD_OUT => soda_cmd_word_S, + CRC_VALID_OUT => crc_valid_S, + CRC_DATA_OUT => crc_data_S, + RX_DLM_IN => RX_DLM_IN, + RX_DLM_WORD_IN => RX_DLM_WORD_IN ); reply_packet_builder : soda_reply_pkt_builder port map( - SYSCLK => SYSCLK, + SODACLK => SODACLK, RESET => RESET, CLEAR => '0', CLK_EN => CLK_EN, @@ -115,7 +114,7 @@ begin CURRENT_STATE <= NEXT_STATE; bus_ack <= bus_ack_x; store_wr <= store_wr_x; - store_rd <= store_rd_x; + store_rd <= store_rd_x; end if; end if; end process STATE_MEM; diff --git a/source/soda_components.vhd b/source/soda_components.vhd index 6894a56..4c5d9b6 100644 --- a/source/soda_components.vhd +++ b/source/soda_components.vhd @@ -24,20 +24,20 @@ package soda_components is BURST_COUNT : integer range 1 to 64 := 16 -- number of bursts to be counted between super-bursts ); port( - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; + SODACLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; --Internal Connection - SODA_BURST_PULSE_IN : in std_logic := '0'; -- - START_OF_SUPERBURST : out std_logic := '0'; - SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0') + SODA_BURST_PULSE_IN : in std_logic := '0'; -- + START_OF_SUPERBURST_OUT : out std_logic := '0'; + SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0') ); end component; component soda_packet_builder port( - SYSCLK : in std_logic; -- fabric clock + SODACLK : in std_logic; -- fabric clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; @@ -56,20 +56,20 @@ package soda_components is component soda_packet_handler port( - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; + SODACLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; --Internal Connection - START_OF_SUPERBURST : out std_logic := '0'; - SUPER_BURST_NR : out std_logic_vector(30 downto 0) := (others => '0'); - SODA_CMD_VALID_S : out std_logic := '0'; - SODA_CMD_WORD_S : out std_logic_vector(30 downto 0) := (others => '0'); - EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); - CRC_VALID_OUT : out std_logic := '0'; - CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); - RX_DLM_IN : in std_logic; - RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0') + START_OF_SUPERBURST_OUT : out std_logic := '0'; + SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0'); + SODA_CMD_VALID_OUT : out std_logic := '0'; + SODA_CMD_WORD_OUT : out std_logic_vector(30 downto 0) := (others => '0'); + EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + CRC_VALID_OUT : out std_logic := '0'; + CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + RX_DLM_IN : in std_logic; + RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0') ); end component; @@ -113,6 +113,7 @@ package soda_components is component soda_hub port( SYSCLK : in std_logic; -- fabric clock + SODACLK : in std_logic; -- recovered clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; @@ -140,6 +141,7 @@ package soda_components is component soda_client -- box containing soda_source components port( SYSCLK : in std_logic; -- fabric clock + SODACLK : in std_logic; -- recovered clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; @@ -162,7 +164,7 @@ package soda_components is component soda_reply_pkt_builder port( - SYSCLK : in std_logic; -- fabric clock + SODACLK : in std_logic; -- fabric clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; @@ -183,7 +185,7 @@ package soda_components is CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; --Internal Connection - LAST_PACKET : in t_PACKET_TYPE_SENT := c_NO_PACKET; + -- LAST_PACKET : in t_PACKET_TYPE_SENT := c_NO_PACKET; EXPECTED_REPLY_IN : in std_logic_vector(7 downto 0) := (others => '0'); RX_DLM_IN : in std_logic := '0'; RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); @@ -242,5 +244,15 @@ package soda_components is SODA_BURST_PULSE_OUT : out std_logic := '0' ); end component; + + component posedge_to_pulse + port ( + IN_CLK : in std_logic; + OUT_CLK : in std_logic; + CLK_EN : in std_logic; + SINGAL_IN : in std_logic; + PULSE_OUT : out std_logic + ); + end component; end package; diff --git a/source/soda_hub.vhd b/source/soda_hub.vhd index d8b6a6d..d42d4d2 100644 --- a/source/soda_hub.vhd +++ b/source/soda_hub.vhd @@ -12,6 +12,7 @@ use work.soda_components.all; entity soda_hub is port( SYSCLK : in std_logic; -- fabric clock + SODACLK : in std_logic; -- fabric clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; @@ -77,25 +78,25 @@ architecture Behavioral of soda_hub is hub_packet_handler : soda_packet_handler port map( - SYSCLK => SYSCLK, - RESET => RESET, - CLEAR => '0', - CLK_EN => '1', + SODACLK => SODACLK, + RESET => RESET, + CLEAR => '0', + CLK_EN => '1', --Internal Connection - START_OF_SUPERBURST => start_of_superburst_S, - SUPER_BURST_NR => super_burst_nr_S, - SODA_CMD_VALID_S => soda_cmd_valid_S, - SODA_CMD_WORD_S => soda_cmd_word_S, - EXPECTED_REPLY_OUT => expected_reply_S, - CRC_VALID_OUT => crc_valid_S, - CRC_DATA_OUT => crc_data_S, - RX_DLM_IN => RXTOP_DLM_IN, - RX_DLM_WORD_IN => RXTOP_DLM_WORD_IN + START_OF_SUPERBURST_OUT => start_of_superburst_S, + SUPER_BURST_NR_OUT => super_burst_nr_S, + SODA_CMD_VALID_OUT => soda_cmd_valid_S, + SODA_CMD_WORD_OUT => soda_cmd_word_S, + EXPECTED_REPLY_OUT => expected_reply_S, + CRC_VALID_OUT => crc_valid_S, + CRC_DATA_OUT => crc_data_S, + RX_DLM_IN => RXTOP_DLM_IN, + RX_DLM_WORD_IN => RXTOP_DLM_WORD_IN ); reply_packet_builder : soda_reply_pkt_builder port map( - SYSCLK => SYSCLK, + SODACLK => SODACLK, RESET => RESET, CLEAR => '0', CLK_EN => CLK_EN, @@ -112,7 +113,7 @@ architecture Behavioral of soda_hub is packet_builder : soda_packet_builder port map( - SYSCLK => SYSCLK, + SODACLK => SODACLK, RESET => RESET, CLEAR => '0', CLK_EN => CLK_EN, @@ -134,7 +135,7 @@ architecture Behavioral of soda_hub is CLEAR => '0', CLK_EN => '1', --Internal Connection - LAST_PACKET => last_packet_sent_S, +-- LAST_PACKET => last_packet_sent_S, EXPECTED_REPLY_IN => expected_reply_S, RX_DLM_IN => RXBTM_DLM_IN(i), RX_DLM_WORD_IN => RXBTM_DLM_WORD_IN(i), diff --git a/source/soda_packet_builder.vhd b/source/soda_packet_builder.vhd index 145ffd8..d86a6b0 100644 --- a/source/soda_packet_builder.vhd +++ b/source/soda_packet_builder.vhd @@ -10,7 +10,7 @@ use work.soda_components.all; entity soda_packet_builder is port( - SYSCLK : in std_logic; -- fabric clock + SODACLK : in std_logic; -- fabric clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; @@ -53,7 +53,7 @@ begin tx_crc8: soda_d8crc8 port map( - CLOCK => SYSCLK, + CLOCK => SODACLK, RESET => RESET, SOC_IN => soc_S, DATA_IN => crc_datain_S, @@ -71,9 +71,9 @@ begin TX_DLM_OUT <= soda_pkt_valid_S; - packet_fsm_proc : process(SYSCLK)--, RESET, packet_state_S, crc_valid_S, START_OF_SUPERBURST, soda_cmd_strobe_S) + packet_fsm_proc : process(SODACLK)--, RESET, packet_state_S, crc_valid_S, START_OF_SUPERBURST, soda_cmd_strobe_S) begin - if rising_edge(SYSCLK) then + if rising_edge(SODACLK) then if (RESET='1') then packet_state_S <= c_IDLE; else @@ -161,9 +161,9 @@ begin end if; end process; - soda_packet_fill_proc : process(SYSCLK, packet_state_S) + soda_packet_fill_proc : process(SODACLK, packet_state_S) begin - if rising_edge(SYSCLK) then + if rising_edge(SODACLK) then case packet_state_S is when c_IDLE => TIME_CAL_OUT <= '0'; @@ -224,9 +224,9 @@ begin end process; - crc_gen_proc : process(SYSCLK, packet_state_S) + crc_gen_proc : process(SODACLK, packet_state_S) begin - if rising_edge(SYSCLK) then + if rising_edge(SODACLK) then case packet_state_S is when c_IDLE => crc_data_valid_S <= '0'; diff --git a/source/soda_packet_handler.vhd b/source/soda_packet_handler.vhd index eb07be1..48690fe 100644 --- a/source/soda_packet_handler.vhd +++ b/source/soda_packet_handler.vhd @@ -10,20 +10,20 @@ use work.soda_components.all; entity soda_packet_handler is port( - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; + SODACLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; --Internal Connection - START_OF_SUPERBURST : out std_logic := '0'; - SUPER_BURST_NR : out std_logic_vector(30 downto 0) := (others => '0'); - SODA_CMD_VALID_S : out std_logic := '0'; - SODA_CMD_WORD_S : out std_logic_vector(30 downto 0) := (others => '0'); - EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); - CRC_VALID_OUT : out std_logic := '0'; - CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); - RX_DLM_IN : in std_logic; - RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0') + START_OF_SUPERBURST_OUT : out std_logic := '0'; + SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0'); + SODA_CMD_VALID_OUT : out std_logic := '0'; + SODA_CMD_WORD_OUT : out std_logic_vector(30 downto 0) := (others => '0'); + EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + CRC_VALID_OUT : out std_logic := '0'; + CRC_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0'); + RX_DLM_IN : in std_logic; + RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0') ); end soda_packet_handler; @@ -49,9 +49,9 @@ architecture Behavioral of soda_packet_handler is begin - packet_fsm_proc : process(SYSCLK) + packet_fsm_proc : process(SODACLK) begin - if rising_edge(SYSCLK) then + if rising_edge(SODACLK) then if (RESET='1') then packet_state_S <= c_RST; else @@ -126,18 +126,18 @@ begin end if; end process; - soda_packet_collector_proc : process(SYSCLK, packet_state_S) + soda_packet_collector_proc : process(SODACLK, packet_state_S) begin - if rising_edge(SYSCLK) then + if rising_edge(SODACLK) then case packet_state_S is when c_RST => - START_OF_SUPERBURST <= '0'; - soda_cmd_valid_S <= '0'; + START_OF_SUPERBURST_OUT <= '0'; + SODA_CMD_VALID_OUT <= '0'; soda_pkt_valid_S <= '0'; soda_pkt_word_S <= (others=>'0'); when c_IDLE => - START_OF_SUPERBURST <= '0'; - soda_cmd_valid_S <= '0'; + START_OF_SUPERBURST_OUT <= '0'; + SODA_CMD_VALID_OUT <= '0'; soda_pkt_valid_S <= '0'; soda_pkt_word_S <= (others=>'0'); when c_SODA_PKT1 => @@ -158,26 +158,26 @@ begin soda_pkt_valid_S <= '1'; EXPECTED_REPLY_OUT <= soda_pkt_word_S(7 downto 0); if (soda_pkt_word_S(31)= '1') then - START_OF_SUPERBURST <= '1'; - SUPER_BURST_NR <= soda_pkt_word_S(30 downto 0); + START_OF_SUPERBURST_OUT <= '1'; + SUPER_BURST_NR_OUT <= soda_pkt_word_S(30 downto 0); else - soda_cmd_valid_S <= '1'; - soda_cmd_word_S <= soda_pkt_word_S(30 downto 0); + SODA_CMD_VALID_OUT <= '1'; + SODA_CMD_WORD_OUT <= soda_pkt_word_S(30 downto 0); end if; when others => - START_OF_SUPERBURST <= '0'; + START_OF_SUPERBURST_OUT <= '0'; soda_pkt_valid_S <= '0'; soda_pkt_word_S <= (others=>'0'); - soda_cmd_valid_S <= '0'; - soda_cmd_word_S <= (others=>'0'); + SODA_CMD_VALID_OUT <= '0'; + SODA_CMD_WORD_OUT <= (others=>'0'); end case; end if; end process; - crc_check_proc : process(SYSCLK, packet_state_S) + crc_check_proc : process(SODACLK, packet_state_S) begin - if rising_edge(SYSCLK) then + if rising_edge(SODACLK) then case packet_state_S is when c_RST=> CRC_VALID_OUT <= '0'; diff --git a/source/soda_reply_handler.vhd b/source/soda_reply_handler.vhd index 4d33d05..db11bd8 100644 --- a/source/soda_reply_handler.vhd +++ b/source/soda_reply_handler.vhd @@ -15,7 +15,7 @@ entity soda_reply_handler is CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; --Internal Connection - LAST_PACKET : in t_PACKET_TYPE_SENT := c_NO_PACKET; +-- LAST_PACKET _IN : in t_PACKET_TYPE_SENT := c_NO_PACKET; EXPECTED_REPLY_IN : in std_logic_vector(7 downto 0) := (others => '0'); RX_DLM_IN : in std_logic := '0'; RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); diff --git a/source/soda_reply_pkt_builder.vhd b/source/soda_reply_pkt_builder.vhd index ccb1349..259b20a 100644 --- a/source/soda_reply_pkt_builder.vhd +++ b/source/soda_reply_pkt_builder.vhd @@ -10,7 +10,7 @@ use work.soda_components.all; entity soda_reply_pkt_builder is port( - SYSCLK : in std_logic; -- fabric clock + SODACLK : in std_logic; -- fabric clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; @@ -31,9 +31,9 @@ architecture Behavioral of soda_reply_pkt_builder is begin - reply_fsm_proc : process(SYSCLK) + reply_fsm_proc : process(SODACLK) begin - if rising_edge(SYSCLK) then + if rising_edge(SODACLK) then if (RESET='1') then packet_state_S <= c_IDLE; else @@ -53,9 +53,9 @@ begin end if; end process; - collect_reply_proc : process(SYSCLK) + collect_reply_proc : process(SODACLK) begin - if rising_edge(SYSCLK) then + if rising_edge(SODACLK) then if (RESET='1') then TX_DLM_OUT <= '0'; TX_DLM_WORD_OUT <= (others=>'0'); diff --git a/source/soda_source.vhd b/source/soda_source.vhd index ed7ae7c..37a0d68 100644 --- a/source/soda_source.vhd +++ b/source/soda_source.vhd @@ -29,8 +29,6 @@ entity soda_source is SODA_WRITE_IN : in std_logic := '0'; SODA_ACK_OUT : out std_logic := '0'; LEDS_OUT : out std_logic_vector(3 downto 0) --- TEST_LINE : out std_logic_vector(15 downto 0); --- STAT : out std_logic_vector(31 downto 0) -- DEBUG ); end soda_source; @@ -75,19 +73,19 @@ begin superburst_gen : soda_superburst_generator generic map(BURST_COUNT => 16) port map( - SYSCLK => SYSCLK, - RESET => RESET, - CLEAR => '0', - CLK_EN => CLK_EN, + SODACLK => SYSCLK, -- Here sysclk is the same as sodaclk; we are still at the source + RESET => RESET, + CLEAR => '0', + CLK_EN => CLK_EN, --Internal Connection - SODA_BURST_PULSE_IN => SODA_BURST_PULSE_IN, - START_OF_SUPERBURST => start_of_superburst_S, - SUPER_BURST_NR_OUT => super_burst_nr_S + SODA_BURST_PULSE_IN => SODA_BURST_PULSE_IN, + START_OF_SUPERBURST_OUT => start_of_superburst_S, + SUPER_BURST_NR_OUT => super_burst_nr_S ); packet_builder : soda_packet_builder port map( - SYSCLK => SYSCLK, + SODACLK => SYSCLK, RESET => RESET, CLEAR => '0', CLK_EN => CLK_EN, @@ -110,7 +108,7 @@ begin CLEAR => '0', CLK_EN => '1', --Internal Connection - LAST_PACKET => last_packet_sent_S, +-- LAST_PACKET => last_packet_sent_S, EXPECTED_REPLY_IN => expected_reply_S, RX_DLM_IN => RX_DLM_IN, RX_DLM_WORD_IN => RX_DLM_WORD_IN, @@ -160,18 +158,18 @@ begin ----------------------------------------------------------- -- Transmission history for reply-checking -- ----------------------------------------------------------- - packet_history_proc : process(SYSCLK) - begin - if rising_edge(SYSCLK) then - if( RESET = '1' ) then - last_packet_sent_S <= c_NO_PACKET; - elsif (start_of_superburst_S='1') then - last_packet_sent_S <= c_BST_PACKET; - elsif (soda_cmd_strobe_S='1') then - last_packet_sent_S <= c_CMD_PACKET; - end if; - end if; - end process; +-- packet_history_proc : process(SYSCLK) +-- begin +-- if rising_edge(SYSCLK) then +-- if( RESET = '1' ) then +-- last_packet_sent_S <= c_NO_PACKET; +-- elsif (start_of_superburst_S='1') then +-- last_packet_sent_S <= c_BST_PACKET; +-- elsif (soda_cmd_strobe_S='1') then +-- last_packet_sent_S <= c_CMD_PACKET; +-- end if; +-- end if; +-- end process; --------------------------------------------------------- -- RegIO Statemachine diff --git a/source/soda_superburst_gen.vhd b/source/soda_superburst_gen.vhd index 7ba315b..2bad6c7 100644 --- a/source/soda_superburst_gen.vhd +++ b/source/soda_superburst_gen.vhd @@ -15,14 +15,14 @@ entity soda_superburst_generator is BURST_COUNT : natural range 1 to 256 := 16 -- number of bursts to be counted between super-bursts ); port( - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; + SODACLK : in std_logic; -- fabric clock + RESET : in std_logic; -- synchronous reset + CLEAR : in std_logic; -- asynchronous reset + CLK_EN : in std_logic; --Internal Connection - SODA_BURST_PULSE_IN : in std_logic := '0'; -- - START_OF_SUPERBURST : out std_logic := '0'; - SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0') + SODA_BURST_PULSE_IN : in std_logic := '0'; -- + START_OF_SUPERBURST_OUT : out std_logic := '0'; + SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0') ); end soda_superburst_generator; @@ -30,8 +30,6 @@ architecture Behavioral of soda_superburst_generator is constant cBURST_COUNT : std_logic_vector(7 downto 0) := conv_std_logic_vector(BURST_COUNT - 1,8); - signal clk_S : std_logic; - signal rst_S : std_logic; signal soda_burst_pulse_S : std_logic := '0'; signal start_of_superburst_S : std_logic := '0'; signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator @@ -40,33 +38,29 @@ architecture Behavioral of soda_superburst_generator is begin - clk_S <= SYSCLK; - rst_S <= RESET; - START_OF_SUPERBURST <= start_of_superburst_S; SUPER_BURST_NR_OUT <= super_burst_nr_S; - burst_pulse_edge_proc : process(clk_S, rst_S, SODA_BURST_PULSE_IN, soda_burst_pulse_S, burst_counter_S) + burst_pulse_edge_proc : process(SODACLK) begin - if rising_edge(clk_S) then + if rising_edge(SODACLK) then soda_burst_pulse_S <= SODA_BURST_PULSE_IN; - if (rst_S='1') then + if (RESET='1') then burst_counter_S <= cBURST_COUNT; - start_of_superburst_S <= '0'; + START_OF_SUPERBURST_OUT <= '0'; super_burst_nr_S <= (others => '0'); elsif ((SODA_BURST_PULSE_IN = '1') and (soda_burst_pulse_S = '0')) then if (burst_counter_S = x"00") then - start_of_superburst_S <= '1'; + START_OF_SUPERBURST_OUT <= '1'; super_burst_nr_S <= super_burst_nr_S + 1; burst_counter_S <= cBURST_COUNT; else - start_of_superburst_S <= '0'; + START_OF_SUPERBURST_OUT <= '0'; burst_counter_s <= burst_counter_s - 1; end if; else - start_of_superburst_S <= '0'; + START_OF_SUPERBURST_OUT <= '0'; end if; end if; end process; - end Behavioral; diff --git a/source/trb3_periph_sodasource.vhd b/source/trb3_periph_sodasource.vhd index 52f059d..1abcca7 100644 --- a/source/trb3_periph_sodasource.vhd +++ b/source/trb3_periph_sodasource.vhd @@ -215,16 +215,16 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is signal rx_dlm_word : std_logic_vector(7 downto 0); --SODA - signal rst_S : std_logic; - signal clk_S : std_logic; - signal enable_S : std_logic := '0'; - signal soda_cmd_word_S : std_logic_vector(31 downto 0) := (others => '0'); - signal soda_cmd_strobe_S : std_logic := '0'; - signal SOS_S : std_logic := '0'; - signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator - signal SOB_S : std_logic := '0'; - signal dlm_word_S : std_logic_vector(7 downto 0) := (others => '0'); - signal dlm_valid_S : std_logic; +-- signal rst_S : std_logic; +-- signal clk_S : std_logic; +-- signal enable_S : std_logic := '0'; +-- signal soda_cmd_word_S : std_logic_vector(31 downto 0) := (others => '0'); +-- signal soda_cmd_strobe_S : std_logic := '0'; +-- signal SOS_S : std_logic := '0'; +-- signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator +-- signal SOB_S : std_logic := '0'; +-- signal dlm_word_S : std_logic_vector(7 downto 0) := (others => '0'); +-- signal dlm_valid_S : std_logic; begin --------------------------------------------------------------------------- @@ -573,8 +573,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync --------------------------------------------------------------------------- -- The Soda Central --------------------------------------------------------------------------- --- tx_dlm_i <= '0'; --- tx_dlm_word <= x"00"; + THE_SOB_SOURCE : soda_start_of_burst_faker port map( SYSCLK => clk_sys_i,