From: Thomas Gessler Date: Tue, 20 Apr 2021 14:29:30 +0000 (+0200) Subject: XCKU MGTs: Set free-running clock freq to 40 MHz X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b7735a9194eaf5533538dfb3982fecc13e11dabd;p=trbnet.git XCKU MGTs: Set free-running clock freq to 40 MHz This makes it easier to use the CRI's 40 MHz free-running ("boot") clock. --- diff --git a/media_interfaces/med_xcku_sfp_sync.vhd b/media_interfaces/med_xcku_sfp_sync.vhd index b34808d..93c577f 100644 --- a/media_interfaces/med_xcku_sfp_sync.vhd +++ b/media_interfaces/med_xcku_sfp_sync.vhd @@ -19,7 +19,7 @@ entity med_xcku_sfp_sync is ); port ( SYSCLK : in std_logic; - CLK_100 : in std_logic; + CLK_40 : in std_logic; RESET_ALL : in std_logic := '0'; GTREFCLK : in std_logic; GTREFCLK_BUFG : in std_logic; @@ -150,7 +150,7 @@ begin REFCLK_FREQ_HZ => REFCLK_FREQ_HZ ) port map ( - CLK_100 => CLK_100, + CLK_40 => CLK_40, GTREFCLK => GTREFCLK, RXOUTCLK => RXOUTCLK, TXOUTCLK => TXOUTCLK, diff --git a/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xci b/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xci index 3f3d41d..526ee3f 100644 --- a/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xci +++ b/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xci @@ -14,7 +14,7 @@ 2000.0 0 0 - 100 + 40 17 0 2 @@ -106,7 +106,7 @@ 1 0 rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpippmen_in txpippmovrden_in txpippmpd_in txpippmsel_in txpippmstepsize_in txpmareset_in rxresetdone_out txbufstatus_out txresetdone_out - 100 + 40 BOTH 0 GTH diff --git a/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xci b/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xci index 9e3276d..cf33734 100644 --- a/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xci +++ b/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xci @@ -14,7 +14,7 @@ 2000.0 0 0 - 100 + 40 17 0 2 @@ -106,7 +106,7 @@ 1 0 rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpippmen_in txpippmovrden_in txpippmpd_in txpippmsel_in txpippmstepsize_in txpmareset_in rxresetdone_out txbufstatus_out txresetdone_out - 100 + 40 BOTH 0 GTH diff --git a/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xci b/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xci index 8d299ec..60b366e 100644 --- a/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xci +++ b/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xci @@ -14,7 +14,7 @@ 2400.0 0 0 - 100 + 40 17 0 2 @@ -106,7 +106,7 @@ 1 0 rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpippmen_in txpippmovrden_in txpippmpd_in txpippmsel_in txpippmstepsize_in txpmareset_in rxresetdone_out txbufstatus_out txresetdone_out - 100 + 40 BOTH 0 GTH diff --git a/media_interfaces/xcku/gth_xcku_top.vhd b/media_interfaces/xcku/gth_xcku_top.vhd index 8b5078f..4042612 100644 --- a/media_interfaces/xcku/gth_xcku_top.vhd +++ b/media_interfaces/xcku/gth_xcku_top.vhd @@ -10,7 +10,7 @@ entity gth_xcku_top is REFCLK_FREQ_HZ : integer := 100000000 ); port ( - CLK_100 : in std_logic; + CLK_40 : in std_logic; GTREFCLK : in std_logic; RXOUTCLK : out std_logic; TXOUTCLK : out std_logic; @@ -423,7 +423,7 @@ begin port map ( gtwiz_userclk_tx_active_in(0) => TXUSRCLK_ACTIVE, gtwiz_userclk_rx_active_in(0) => RXUSRCLK_ACTIVE, - gtwiz_reset_clk_freerun_in(0) => CLK_100, + gtwiz_reset_clk_freerun_in(0) => CLK_40, gtwiz_reset_all_in(0) => RESET_ALL, gtwiz_reset_tx_pll_and_datapath_in(0) => '0', gtwiz_reset_tx_datapath_in(0) => '0', @@ -502,7 +502,7 @@ begin port map ( gtwiz_userclk_tx_active_in(0) => TXUSRCLK_ACTIVE, gtwiz_userclk_rx_active_in(0) => RXUSRCLK_ACTIVE, - gtwiz_reset_clk_freerun_in(0) => CLK_100, + gtwiz_reset_clk_freerun_in(0) => CLK_40, gtwiz_reset_all_in(0) => RESET_ALL, gtwiz_reset_tx_pll_and_datapath_in(0) => '0', gtwiz_reset_tx_datapath_in(0) => '0', @@ -581,7 +581,7 @@ begin port map ( gtwiz_userclk_tx_active_in(0) => TXUSRCLK_ACTIVE, gtwiz_userclk_rx_active_in(0) => RXUSRCLK_ACTIVE, - gtwiz_reset_clk_freerun_in(0) => CLK_100, + gtwiz_reset_clk_freerun_in(0) => CLK_40, gtwiz_reset_all_in(0) => RESET_ALL, gtwiz_reset_tx_pll_and_datapath_in(0) => '0', gtwiz_reset_tx_datapath_in(0) => '0',