From: Jan Michel Date: Fri, 10 Nov 2017 21:56:45 +0000 (+0100) Subject: add new PLL for 200 MHz internal oscillator X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b7ac3e05f1758bec5c80625b581adae4e36f2c20;p=trb3sc.git add new PLL for 200 MHz internal oscillator --- diff --git a/backplanemaster/trb3sc_master.prj b/backplanemaster/trb3sc_master.prj index af8aef6..e564ff2 100644 --- a/backplanemaster/trb3sc_master.prj +++ b/backplanemaster/trb3sc_master.prj @@ -215,6 +215,8 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" + add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd" add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v" add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v" diff --git a/cores/pll.txt b/cores/pll.txt new file mode 100644 index 0000000..35c2a2a --- /dev/null +++ b/cores/pll.txt @@ -0,0 +1,5 @@ +Name In OP OS OK +200_200 200 200 bypass 100 +200_100 200 100 100 200 +240_200 240 200 200 100 +240_240 240 120 -- bypass diff --git a/cores/pll_in200_out200.ipx b/cores/pll_in200_out200.ipx new file mode 100644 index 0000000..72bd5a3 --- /dev/null +++ b/cores/pll_in200_out200.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/cores/pll_in200_out200.lpc b/cores/pll_in200_out200.lpc new file mode 100644 index 0000000..4440411 --- /dev/null +++ b/cores/pll_in200_out200.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=pll_in200_out200 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/08/2017 +Time=16:20:47 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=200 +Div=1 +ClkOPBp=0 +Post=4 +U_OFrq=200 +OP_Tol=0.0 +OFrq=200.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=1 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=100 +OK_Tol=0.0 +KFrq=100.000000 +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=2.970786 +;DelayControl=No +EnCLKOS=1 +ClkOSBp=1 +EnCLKOK=1 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_in200_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 200 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw diff --git a/cores/pll_in200_out200.vhd b/cores/pll_in200_out200.vhd new file mode 100644 index 0000000..030239e --- /dev/null +++ b/cores/pll_in200_out200.vhd @@ -0,0 +1,102 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.1.119 +-- Module Version: 5.7 +--/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 200 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw + +-- Wed Nov 8 16:20:47 2017 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_in200_out200 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + CLKOK: out std_logic; + LOCK: out std_logic); +end pll_in200_out200; + +architecture Structure of pll_in200_out200 is + + -- internal signal declarations + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "100.000000"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "ENABLED", CLKOP_BYPASS=> "DISABLED", CLKOK_INPUT=> "CLKOP", + DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, CLKOS_TRIM_DELAY=> 0, + CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 1, CLKI_DIV=> 1, + FIN=> "200.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>CLKOS_t, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOS <= CLKOS_t; + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_in200_out200 is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/cts/config.vhd b/cts/config.vhd index 1a8b29b..b428079 100644 --- a/cts/config.vhd +++ b/cts/config.vhd @@ -18,7 +18,7 @@ package config is --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; - constant USE_200MHZOSCILLATOR : integer := c_NO; + constant USE_200MHZOSCILLATOR : integer := c_YES; constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. constant CLOCK_FAST_SELECT : integer := c_YES; --fast clock select (135us) or slow (280ms)? diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 7ef0714..2b5ebda 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -501,7 +501,7 @@ end generate; BROADCAST_SPECIAL_ADDR => x"35", RDO_ADDITIONAL_PORT => cts_rdo_additional_ports, RDO_DATA_BUFFER_DEPTH => 10, - RDO_DATA_BUFFER_FULL_THRESH => 2**9-2, + RDO_DATA_BUFFER_FULL_THRESH => 2**9+2, RDO_HEADER_BUFFER_DEPTH => 9, RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16 ) diff --git a/scripts/nodes_frankfurt.txt b/scripts/nodes_frankfurt.txt index 5bf93eb..5ac6e94 100644 --- a/scripts/nodes_frankfurt.txt +++ b/scripts/nodes_frankfurt.txt @@ -3,11 +3,11 @@ [jspc29] SYSTEM = linux CORENUM = 3 -ENV = /d/jspc29/lattice/37_settings.sh +ENV = /d/jspc29/lattice/38_settings.sh WORKDIR = /d/jspc22/trb/git/trb3sc/tdctemplate/workdir [jspc57] SYSTEM = linux CORENUM = 7 -ENV = /d/jspc29/lattice/37_settings.sh +ENV = /d/jspc29/lattice/38_settings.sh WORKDIR = /d/jspc22/trb/git/trb3sc/tdctemplate/workdir diff --git a/tdctemplate/config_compile_frankfurt.pl b/tdctemplate/config_compile_frankfurt.pl index a37b756..1c5bcb3 100644 --- a/tdctemplate/config_compile_frankfurt.pl +++ b/tdctemplate/config_compile_frankfurt.pl @@ -2,7 +2,7 @@ TOPNAME => "trb3sc_tdctemplate", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@hadeb05.gsi.de", lattice_path => '/d/jspc29/lattice/diamond/3.9_x64', -synplify_path => '/d/jspc29/lattice/synplify/M-2017.03/', +synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/', nodelist_file => 'nodes_frankfurt.txt', # synplify_command => "ssh -p 52238 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/tdctemplate/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/L-2016.09-1/bin/synplify_premier_dp -batch ../trb3sc_tdctemplate.prj\" #", #Include only necessary lpf files diff --git a/tdctemplate/par.p2t b/tdctemplate/par.p2t index 1eb1972..c35a699 100644 --- a/tdctemplate/par.p2t +++ b/tdctemplate/par.p2t @@ -14,7 +14,7 @@ -l 5 -i 6 -n 1 --t 4 +-t 6 -s 1 -c 0 -e 0 diff --git a/template/config.vhd b/template/config.vhd index 7358a6b..92d55fe 100644 --- a/template/config.vhd +++ b/template/config.vhd @@ -10,6 +10,10 @@ package config is --Begin of design configuration ------------------------------------------------------------------------------ + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 + + --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. @@ -23,7 +27,7 @@ package config is constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"60"; --set to 0 for backplane serdes, set to 3 for front SFP serdes - constant SERDES_NUM : integer := 0; + constant SERDES_NUM : integer := 3; constant INCLUDE_UART : integer := c_YES; constant INCLUDE_SPI : integer := c_YES; diff --git a/template/par.p2t b/template/par.p2t index e13de7d..cb0ad8d 100644 --- a/template/par.p2t +++ b/template/par.p2t @@ -4,7 +4,7 @@ -n 1 -y -s 12 --t 25 +-t 26 -c 1 -e 2 #-g guidefile.ncd diff --git a/template/trb3sc_basic.prj b/template/trb3sc_basic.prj index c24b807..4d7d00e 100644 --- a/template/trb3sc_basic.prj +++ b/template/trb3sc_basic.prj @@ -65,6 +65,7 @@ add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd" #Basic Infrastructure add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd" add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200_200oscillator.vhd" add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd" add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd" add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"