From: hadaq Date: Mon, 21 Jun 2010 08:04:30 +0000 (+0000) Subject: trb_net_sbuf5.vhd X-Git-Tag: oldGBE~273 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b7ef90fd90edb04de04d46080bb2d8c2a15eca41;p=trbnet.git trb_net_sbuf5.vhd --- diff --git a/lattice/ecp2m/fifo/fifo_19x16_obuf.lpc b/lattice/ecp2m/fifo/fifo_19x16_obuf.lpc index b27ac4a..5cead58 100644 --- a/lattice/ecp2m/fifo/fifo_19x16_obuf.lpc +++ b/lattice/ecp2m/fifo/fifo_19x16_obuf.lpc @@ -1,44 +1,44 @@ -[Device] -Family=latticeecp2m -PartType=LFE2M100E -PartName=LFE2M100E-5F900I -SpeedGrade=-5 -Package=FPBGA900 -OperatingCondition=IND -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=FIFO -CoreRevision=4.8 -ModuleName=fifo_19x16_obuf -SourceFormat=Schematic/VHDL -ParameterFileVersion=1.0 -Date=06/18/2010 -Time=10:57:41 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -FIFOImp=LUT Based -Depth=16 -Width=19 -regout=0 -CtrlByRdEn=0 -EmpFlg=1 -PeMode=Dynamic - Single Threshold -PeAssert=10 -PeDeassert=12 -FullFlg=1 -PfMode=Dynamic - Single Threshold -PfAssert=13 -PfDeassert=506 -RDataCount=0 -EnECC=0 +[Device] +Family=latticeecp2m +PartType=LFE2M100E +PartName=LFE2M100E-6F900C +SpeedGrade=-6 +Package=FPBGA900 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=4.8 +ModuleName=fifo_19x16_obuf +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=06/18/2010 +Time=11:50:14 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=LUT Based +Depth=16 +Width=19 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Dynamic - Single Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Dynamic - Single Threshold +PfAssert=13 +PfDeassert=506 +RDataCount=1 +EnECC=0 diff --git a/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd b/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd index a6f8869..737c8e0 100644 --- a/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd +++ b/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build -- Module Version: 4.8 ---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -pfu_fifo -depth 16 -width 19 -depth 16 -no_enable -pe 0 -pf 0 -e +--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -pfu_fifo -depth 16 -width 19 -depth 16 -no_enable -pe 0 -pf 0 -fill -e --- Fri Jun 18 10:57:46 2010 +-- Fri Jun 18 11:50:14 2010 library IEEE; use IEEE.std_logic_1164.all; @@ -13,17 +13,18 @@ use ecp2m.components.all; entity fifo_19x16_obuf is port ( - Data: in std_logic_vector(18 downto 0); - Clock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - AmEmptyThresh: in std_logic_vector(3 downto 0); - AmFullThresh: in std_logic_vector(3 downto 0); - Q: out std_logic_vector(18 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic; + Data: in std_logic_vector(18 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + AmEmptyThresh: in std_logic_vector(3 downto 0); + AmFullThresh: in std_logic_vector(3 downto 0); + Q: out std_logic_vector(18 downto 0); + WCNT: out std_logic_vector(4 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; AlmostFull: out std_logic); end fifo_19x16_obuf; @@ -177,61 +178,61 @@ architecture Structure of fifo_19x16_obuf is -- local component declarations component AGEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; B1: in std_logic; CI: in std_logic; GE: out std_logic); end component; component ALEB2 - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; B1: in std_logic; CI: in std_logic; LE: out std_logic); end component; component AND2 port (A: in std_logic; B: in std_logic; Z: out std_logic); end component; component CU2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; CO: out std_logic; NC0: out std_logic; NC1: out std_logic); end component; component CB2 - port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; - CON: in std_logic; CO: out std_logic; NC0: out std_logic; + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; NC1: out std_logic); end component; component FADD2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; CI: in std_logic; COUT: out std_logic; + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; S0: out std_logic; S1: out std_logic); end component; component FSUB2B - port (A0: in std_logic; A1: in std_logic; B0: in std_logic; - B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; S0: out std_logic; S1: out std_logic); end component; component FD1P3BX -- synopsys translate_off generic (GSR : in String); -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; + port (D: in std_logic; SP: in std_logic; CK: in std_logic; PD: in std_logic; Q: out std_logic); end component; component FD1P3DX -- synopsys translate_off generic (GSR : in String); -- synopsys translate_on - port (D: in std_logic; SP: in std_logic; CK: in std_logic; + port (D: in std_logic; SP: in std_logic; CK: in std_logic; CD: in std_logic; Q: out std_logic); end component; component FD1S3BX -- synopsys translate_off generic (GSR : in String); -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; PD: in std_logic; + port (D: in std_logic; CK: in std_logic; PD: in std_logic; Q: out std_logic); end component; component FD1S3DX -- synopsys translate_off generic (GSR : in String); -- synopsys translate_on - port (D: in std_logic; CK: in std_logic; CD: in std_logic; + port (D: in std_logic; CK: in std_logic; CD: in std_logic; Q: out std_logic); end component; component INV @@ -241,17 +242,17 @@ architecture Structure of fifo_19x16_obuf is -- synopsys translate_off generic (initval : in String); -- synopsys translate_on - port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; AD0: in std_logic; DO0: out std_logic); end component; component DPR16X4A - port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; - DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; - RAD0: in std_logic; RAD1: in std_logic; - RAD2: in std_logic; RAD3: in std_logic; - WAD0: in std_logic; WAD1: in std_logic; - WAD2: in std_logic; WAD3: in std_logic; - DO0: out std_logic; DO1: out std_logic; + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; DO2: out std_logic; DO3: out std_logic); end component; component VHI @@ -263,8 +264,8 @@ architecture Structure of fifo_19x16_obuf is component XOR2 port (A: in std_logic; B: in std_logic; Z: out std_logic); end component; - attribute initval : string; - attribute GSR : string; + attribute initval : string; + attribute GSR : string; attribute initval of LUT4_2 : label is "0x3232"; attribute initval of LUT4_1 : label is "0x3232"; attribute initval of LUT4_0 : label is "0x8000"; @@ -358,21 +359,21 @@ begin -- synopsys translate_off generic map (initval=> "0x3232") -- synopsys translate_on - port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, AD0=>empty_i, DO0=>empty_d); LUT4_1: ROM16X1 -- synopsys translate_off generic map (initval=> "0x3232") -- synopsys translate_on - port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, AD0=>full_i, DO0=>full_d); LUT4_0: ROM16X1 -- synopsys translate_off generic map (initval=> "0x8000") -- synopsys translate_on - port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, + port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, AD0=>scuba_vhi, DO0=>dec0_wre3); AND2_t4: AND2 @@ -409,35 +410,35 @@ begin -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_0); FF_56: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_1); FF_55: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_2); FF_54: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_3); FF_53: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_4); FF_52: FD1S3BX @@ -456,273 +457,273 @@ begin -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, Q=>wcount_0); FF_49: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_1); FF_48: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_2); FF_47: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_3); FF_46: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_4); FF_45: FD1P3BX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, Q=>rcount_0); FF_44: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_1); FF_43: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_2); FF_42: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_3); FF_41: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_4); FF_40: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_0); FF_39: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_1); FF_38: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_2); FF_37: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_3); FF_36: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_4); FF_35: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_0); FF_34: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_1); FF_33: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_2); FF_32: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_3); FF_31: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_4); FF_30: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout0, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout0, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(0)); FF_29: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout1, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout1, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(1)); FF_28: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout2, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout2, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(2)); FF_27: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout3, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout3, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(3)); FF_26: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout4, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout4, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(4)); FF_25: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout5, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout5, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(5)); FF_24: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout6, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout6, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(6)); FF_23: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout7, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout7, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(7)); FF_22: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout8, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout8, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(8)); FF_21: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout9, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout9, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(9)); FF_20: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout10, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout10, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(10)); FF_19: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout11, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout11, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(11)); FF_18: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout12, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout12, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(12)); FF_17: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout13, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout13, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(13)); FF_16: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout14, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout14, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(14)); FF_15: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout15, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout15, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(15)); FF_14: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout16, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout16, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(16)); FF_13: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout17, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout17, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(17)); FF_12: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>rdataout18, SP=>rden_i, CK=>Clock, CD=>Reset, + port map (D=>rdataout18, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>Q(18)); FF_11: FD1S3DX @@ -798,217 +799,222 @@ begin port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); bdcnt_bctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); bdcnt_bctr_0: CB2 - port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); bdcnt_bctr_1: CB2 - port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); bdcnt_bctr_2: CB2 - port map (CI=>co1, PC0=>fcount_4, PC1=>scuba_vlo, CON=>cnt_con, + port map (CI=>co1, PC0=>fcount_4, PC1=>scuba_vlo, CON=>cnt_con, CO=>co2, NC0=>ifcount_4, NC1=>open); e_cmp_ci_a: FADD2B - port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); e_cmp_0: ALEB2 - port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, CI=>cmp_ci, LE=>co0_1); e_cmp_1: ALEB2 - port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); e_cmp_2: ALEB2 - port map (A0=>fcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>scuba_vlo, B1=>scuba_vlo, CI=>co1_1, LE=>cmp_le_1_c); a0: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, S1=>open); g_cmp_ci_a: FADD2B - port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); g_cmp_0: AGEB2 - port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, CI=>cmp_ci_1, GE=>co0_2); g_cmp_1: AGEB2 - port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, CI=>co0_2, GE=>co1_2); g_cmp_2: AGEB2 - port map (A0=>fcount_4, A1=>scuba_vlo, B0=>wren_i_inv, + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>wren_i_inv, B1=>scuba_vlo, CI=>co1_2, GE=>cmp_ge_d1_c); a1: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, S1=>open); w_ctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, S1=>open); w_ctr_0: CU2 - port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, NC0=>iwcount_0, NC1=>iwcount_1); w_ctr_1: CU2 - port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, NC0=>iwcount_2, NC1=>iwcount_3); w_ctr_2: CU2 - port map (CI=>co1_3, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2_1, + port map (CI=>co1_3, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2_1, NC0=>iwcount_4, NC1=>open); scuba_vhi_inst: VHI port map (Z=>scuba_vhi); r_ctr_cia: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, S1=>open); r_ctr_0: CU2 - port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, NC0=>ircount_0, NC1=>ircount_1); r_ctr_1: CU2 - port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, NC0=>ircount_2, NC1=>ircount_3); r_ctr_2: CU2 - port map (CI=>co1_4, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_2, + port map (CI=>co1_4, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_2, NC0=>ircount_4, NC1=>open); rcnt_0: FSUB2B - port map (A0=>r_nw_inv, A1=>wcount_0, B0=>r_nw_inv_inv, - B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, + port map (A0=>r_nw_inv, A1=>wcount_0, B0=>r_nw_inv_inv, + B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open, S1=>rcnt_sub_0); rcnt_1: FSUB2B - port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_1, B1=>rcount_2, + port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_1, B1=>rcount_2, BI=>co0_5, BOUT=>co1_5, S0=>rcnt_sub_1, S1=>rcnt_sub_2); rcnt_2: FSUB2B - port map (A0=>wcount_3, A1=>rcnt_sub_msb, B0=>rcount_3, - B1=>scuba_vlo, BI=>co1_5, BOUT=>co2_3, S0=>rcnt_sub_3, + port map (A0=>wcount_3, A1=>rcnt_sub_msb, B0=>rcount_3, + B1=>scuba_vlo, BI=>co1_5, BOUT=>co2_3, S0=>rcnt_sub_3, S1=>rcnt_sub_4); rcntd: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, B1=>scuba_vlo, CI=>co2_3, COUT=>open, S0=>co2_3d, S1=>open); ae_set_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); ae_set_cmp_0: AGEB2 - port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), + port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_6); ae_set_cmp_1: AGEB2 - port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), + port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_6, GE=>co1_6); ae_set_cmp_2: AGEB2 - port map (A0=>ae_set_setsig, A1=>scuba_vlo, B0=>ae_set_clrsig, + port map (A0=>ae_set_setsig, A1=>scuba_vlo, B0=>ae_set_clrsig, B1=>scuba_vlo, CI=>co1_6, GE=>ae_set_d_c); a2: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d, + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d, S1=>open); wcnt_0: FSUB2B - port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_7, S0=>open, S1=>wcnt_sub_0); wcnt_1: FSUB2B - port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, BI=>co0_7, BOUT=>co1_7, S0=>wcnt_sub_1, S1=>wcnt_sub_2); wcnt_2: FSUB2B - port map (A0=>wcount_3, A1=>wcnt_sub_msb, B0=>rptr_3, - B1=>scuba_vlo, BI=>co1_7, BOUT=>co2_4, S0=>wcnt_sub_3, + port map (A0=>wcount_3, A1=>wcnt_sub_msb, B0=>rptr_3, + B1=>scuba_vlo, BI=>co1_7, BOUT=>co2_4, S0=>wcnt_sub_3, S1=>wcnt_sub_4); wcntd: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, B1=>scuba_vlo, CI=>co2_4, COUT=>open, S0=>co2_4d, S1=>open); af_set_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); af_set_cmp_0: AGEB2 - port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_8); af_set_cmp_1: AGEB2 - port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), B1=>AmFullThresh(3), CI=>co0_8, GE=>co1_8); af_set_cmp_2: AGEB2 - port map (A0=>wcnt_reg_4, A1=>scuba_vlo, B0=>scuba_vlo, + port map (A0=>wcnt_reg_4, A1=>scuba_vlo, B0=>scuba_vlo, B1=>scuba_vlo, CI=>co1_8, GE=>af_set_c); a3: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, S1=>open); scuba_vlo_inst: VLO port map (Z=>scuba_vlo); fifo_pfu_0_0: DPR16X4A - port map (DI0=>Data(16), DI1=>Data(17), DI2=>Data(18), - DI3=>scuba_vlo, WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0, - RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, - WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout16, + port map (DI0=>Data(16), DI1=>Data(17), DI2=>Data(18), + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout16, DO1=>rdataout17, DO2=>rdataout18, DO3=>open); fifo_pfu_0_1: DPR16X4A - port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14), - DI3=>Data(15), WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0, - RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, - WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout12, + port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14), + DI3=>Data(15), WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout12, DO1=>rdataout13, DO2=>rdataout14, DO3=>rdataout15); fifo_pfu_0_2: DPR16X4A - port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10), - DI3=>Data(11), WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0, - RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, - WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout8, + port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10), + DI3=>Data(11), WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout8, DO1=>rdataout9, DO2=>rdataout10, DO3=>rdataout11); fifo_pfu_0_3: DPR16X4A - port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), - WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, - RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1, - WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout4, DO1=>rdataout5, + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, + RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1, + WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout4, DO1=>rdataout5, DO2=>rdataout6, DO3=>rdataout7); fifo_pfu_0_4: DPR16X4A - port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), - WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, - RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1, - WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout0, DO1=>rdataout1, + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, + RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1, + WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout0, DO1=>rdataout1, DO2=>rdataout2, DO3=>rdataout3); + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; Empty <= empty_i; Full <= full_i; end Structure; diff --git a/trb_net_sbuf5.vhd b/trb_net_sbuf5.vhd index 7736732..c1dda29 100644 --- a/trb_net_sbuf5.vhd +++ b/trb_net_sbuf5.vhd @@ -1,78 +1,253 @@ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.numeric_std.all; - -library work; -use work.trb_net_std.all; - -entity trb_net_sbuf5 is - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- input - COMB_DATAREADY_IN : in STD_LOGIC; - COMB_next_READ_OUT : out STD_LOGIC; - COMB_DATA_IN : in STD_LOGIC_VECTOR (18 downto 0); - -- output - SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (18 downto 0); -- Data word - SYN_READ_IN : in STD_LOGIC; - -- Status and control port - STAT_BUFFER : out STD_LOGIC - ); -end entity; - -architecture trb_net_sbuf5_arch of trb_net_sbuf5 is - - signal data_i : std_logic_vector(18 downto 0); - signal data_o : std_logic_vector(18 downto 0); - signal wr_en : std_logic; - signal rd_en : std_logic; - signal almostempty : std_logic; - signal almostfull : std_logic; - signal almostemptythresh : std_logic_vector(3 downto 0); - signal almostfullthresh : std_logic_vector(3 downto 0); - signal fifo_reset : std_logic; - signal full : std_logic; - signal empty : std_logic; - - -begin - ---------------------------------------------------------------------- --- I/O ---------------------------------------------------------------------- - - data_i <= COMB_DATA_IN; - wr_en <= COMB_DATAREADY_IN; - COMB_next_READ_OUT <= not almostfull; - ---------------------------------------------------------------------- --- Fifo ---------------------------------------------------------------------- - - THE_FIFO : fifo_19x16_obuf is - port ( - Data => data_i, - Clock => CLK, - WrEn => wr_en, - RdEn => rd_en, - Reset => fifo_reset, - AmEmptyThresh => x"5", - AmFullThresh => x"C", - Q => data_o, - Empty => empty, - Full => full, - AlmostEmpty => almostempty, - AlmostFull => almostfull - ); - ---------------------------------------------------------------------- --- Read control ---------------------------------------------------------------------- - -end architecture; - + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.numeric_std.all; + +library work; +--use work.trb_net_std.all; +--use work.lattice_ecp2m_fifo.all; +--use work.trb_net_components.all; + +entity trb_net_sbuf5 is +port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- input + COMB_DATAREADY_IN : in std_logic; + COMB_next_READ_OUT : out std_logic; + COMB_DATA_IN : in std_logic_vector(18 downto 0); + -- output + SYN_DATAREADY_OUT : out std_logic; + SYN_DATA_OUT : out std_logic_vector(18 downto 0); -- Data word + SYN_READ_IN : in std_logic; + -- Status and control port + DEBUG : out std_logic_vector(15 downto 0); + DEBUG_DATA : out std_logic_vector(18 downto 0); + STAT_BUFFER : out std_logic +); +end entity; + +architecture trb_net_sbuf5_arch of trb_net_sbuf5 is + +-- FIFO for buffering at least two packets +component fifo_19x16_obuf is +port( + Data : in std_logic_vector(18 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmEmptyThresh : in std_logic_vector(3 downto 0); + AmFullThresh : in std_logic_vector(3 downto 0); + Q : out std_logic_vector(18 downto 0); + WCNT : out std_logic_vector(4 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic; + AlmostFull : out std_logic +); +end component fifo_19x16_obuf; + +type STATES is (IDLE, RD1, RD2, RD3, RD4, RD5, WT5, WR5, WD5, DEL); +signal CURRENT_STATE, NEXT_STATE: STATES; +signal bsm_x : std_logic_vector(3 downto 0); + +signal syn_dataready_x : std_logic; +signal syn_dataready : std_logic; +signal update_x : std_logic; +signal update : std_logic; + +signal syn_data : std_logic_vector(18 downto 0); + +signal p_wait_x : std_logic; +signal p_avail_x : std_logic; + +signal fifo_data_i : std_logic_vector(18 downto 0); +signal fifo_data_o : std_logic_vector(18 downto 0); +signal fifo_wr_en : std_logic; +signal fifo_rd_en_x : std_logic; +signal fifo_reset : std_logic; +signal fifo_wcnt : std_logic_vector(4 downto 0); +signal fifo_full : std_logic; +signal fifo_almostfull : std_logic; + +signal debug_x : std_logic_vector(15 downto 0); + +begin + +--------------------------------------------------------------------- +-- I/O +--------------------------------------------------------------------- +fifo_data_i <= COMB_DATA_IN; +fifo_wr_en <= COMB_DATAREADY_IN; -- mind the special nature of SBUF! +fifo_reset <= RESET; +COMB_next_READ_OUT <= not fifo_almostfull; + +DEBUG <= debug_x; +DEBUG_DATA <= fifo_data_o; +STAT_BUFFER <= fifo_full; + +SYN_DATA_OUT <= syn_data; +SYN_DATAREADY_OUT <= syn_dataready; + +--------------------------------------------------------------------- +-- Fifo +--------------------------------------------------------------------- +THE_FIFO: fifo_19x16_obuf +port map( + Data => fifo_data_i, + Clock => CLK, + WrEn => fifo_wr_en, + RdEn => fifo_rd_en_x, + Reset => fifo_reset, + AmEmptyThresh => x"5", + AmFullThresh => x"C", + Q => fifo_data_o, + WCNT => fifo_wcnt, + Empty => open, + Full => fifo_full, + AlmostEmpty => open, + AlmostFull => fifo_almostfull --open +); + +p_wait_x <= '1' when (unsigned(fifo_wcnt) > x"0") else '0'; +p_avail_x <= '1' when ((unsigned(fifo_wcnt) >= x"2") and (COMB_DATAREADY_IN = '1')) or + (unsigned(fifo_wcnt) >= x"3") + else '0'; + +-- was 3 and 4 + +--------------------------------------------------------------------- +-- State machine +--------------------------------------------------------------------- +-- state registers +STATE_MEM: process( CLK ) +begin + if( rising_edge(CLK) ) then + if( RESET = '1' ) then + CURRENT_STATE <= IDLE; + syn_dataready <= '0'; + update <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + syn_dataready <= syn_dataready_x; + update <= update_x; + end if; + end if; +end process STATE_MEM; + +-- state transitions +STATE_TRANSFORM: process( CURRENT_STATE, p_wait_x, p_avail_x, SYN_READ_IN, syn_dataready ) +begin + NEXT_STATE <= IDLE; -- avoid latches + fifo_rd_en_x <= '0'; + syn_dataready_x <= '0'; + update_x <= '0'; + case CURRENT_STATE is + when IDLE => bsm_x <= x"0"; + if( p_wait_x = '1' ) then + NEXT_STATE <= RD1; + fifo_rd_en_x <= '1'; + update_x <= '1'; + else + NEXT_STATE <= IDLE; + end if; + when RD1 => bsm_x <= x"1"; + if( p_wait_x = '1' ) then + NEXT_STATE <= RD2; + fifo_rd_en_x <= '1'; + else + NEXT_STATE <= RD1; + end if; + when RD2 => bsm_x <= x"2"; + if ( (p_avail_x = '1') and (SYN_READ_IN = '1') and (syn_dataready = '1') ) then + NEXT_STATE <= RD3; + syn_dataready_x <= '1'; + fifo_rd_en_x <= '1'; + elsif( (p_avail_x = '1') and (SYN_READ_IN = '1') and (syn_dataready = '0') ) then + NEXT_STATE <= DEL; + syn_dataready_x <= '1'; + else + NEXT_STATE <= RD2; + syn_dataready_x <= p_avail_x; + end if; + when DEL => bsm_x <= x"8"; + if( SYN_READ_IN = '1' ) then + NEXT_STATE <= RD3; + fifo_rd_en_x <= '1'; + syn_dataready_x <= '1'; + else + NEXT_STATE <= DEL; + syn_dataready_x <= '1'; + end if; + when RD3 => bsm_x <= x"3"; + if( SYN_READ_IN = '1' ) then + NEXT_STATE <= RD4; + syn_dataready_x <= '1'; + fifo_rd_en_x <= '1'; + else + NEXT_STATE <= RD3; + syn_dataready_x <= '1'; + end if; + when RD4 => bsm_x <= x"4"; + if( SYN_READ_IN = '1' ) then + NEXT_STATE <= RD5; + syn_dataready_x <= '1'; + fifo_rd_en_x <= '1'; + else + NEXT_STATE <= RD4; + syn_dataready_x <= '1'; + end if; + when RD5 => bsm_x <= x"5"; + syn_dataready_x <= '1'; + if ( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then + NEXT_STATE <= WR5; + fifo_rd_en_x <= '1'; + elsif( (SYN_READ_IN = '1') and (p_avail_x = '0') ) then + NEXT_STATE <= WT5; + else + NEXT_STATE <= RD5; + end if; + when WT5 => bsm_x <= x"6"; + if( SYN_READ_IN = '1' ) then + NEXT_STATE <= IDLE; + else + NEXT_STATE <= WT5; + syn_dataready_x <= '1'; + end if; + when WR5 => bsm_x <= x"7"; + syn_dataready_x <= '1'; + if( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then + NEXT_STATE <= RD2; + fifo_rd_en_x <= '1'; + else + NEXT_STATE <= WR5; + end if; + when others => bsm_x <= x"f"; + end case; +end process STATE_TRANSFORM; + +THE_SYNC_PROC: process( CLK ) +begin + if( rising_edge(CLK) ) then +-- if( ((syn_dataready_x = '1') and (syn_read_in = '1')) or (update = '1') ) then + if( ((syn_dataready = '1') and (syn_read_in = '1')) or (update = '1') ) then + syn_data <= fifo_data_o; + end if; + end if; +end process THE_SYNC_PROC; + +--------------------------------------------------------------------- +-- DEBUG +--------------------------------------------------------------------- +debug_x(15 downto 12) <= bsm_x; +debug_x(11) <= '0'; +debug_x(10) <= fifo_rd_en_x; +debug_x(9) <= p_avail_x; +debug_x(8) <= p_wait_x; +debug_x(7 downto 5) <= (others => '0'); +debug_x(4 downto 0) <= fifo_wcnt; + +end architecture; \ No newline at end of file