From: hadeshyp <hadeshyp>
Date: Thu, 3 Jan 2013 17:25:03 +0000 (+0000)
Subject: new wasa spi mode
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b83dea4adb293480758b317a59d671f63dcbc27f;p=trb3.git

new wasa spi mode
---

diff --git a/wasa/compile_padiwa_frankfurt.pl b/wasa/compile_padiwa_frankfurt.pl
index 084cf2d..6b41d05 100755
--- a/wasa/compile_padiwa_frankfurt.pl
+++ b/wasa/compile_padiwa_frankfurt.pl
@@ -12,10 +12,11 @@ my $TOPNAME                      = "trb3_periph_padiwa";  #Name of top-level ent
 my $lattice_path                 = '/d/jspc29/lattice/diamond/2.0';
 my $synplify_path                = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
 my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
-my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
+#my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
+my $lm_license_file_for_par      = "1710\@cronos.e12.physik.tu-muenchen.de";
 ###################################################################################
 
-
+$ENV{'PAR_DESIGN_NAME'}=$TOPNAME;
 
 
 
diff --git a/wasa/panda_dirc_wasa.vhd b/wasa/panda_dirc_wasa.vhd
index bed5e96..1fc24af 100644
--- a/wasa/panda_dirc_wasa.vhd
+++ b/wasa/panda_dirc_wasa.vhd
@@ -13,6 +13,9 @@ use machxo2.all;
 
 
 entity panda_dirc_wasa is
+  generic(
+    SAME_ORDER : integer := 0
+    );
   port(
     CON        : out std_logic_vector(16 downto 1);
     INP        : in  std_logic_vector(16 downto 1);
@@ -161,7 +164,7 @@ type ram_t is array(0 to 15) of std_logic_vector(15 downto 0);
 signal ram   : ram_t;
 
 signal pwm_i : std_logic_vector(31 downto 0);
-
+signal tmp_con     : std_logic_vector(15 downto 0);
 signal spi_reg00_i : std_logic_vector(15 downto 0);
 signal spi_reg10_i : std_logic_vector(15 downto 0);
 signal spi_reg20_i : std_logic_vector(15 downto 0);
@@ -531,7 +534,16 @@ end process;
 ---------------------------------------------------------------------------
 
 inp_gated <= (INP xor inp_invert) and not input_enable;
-CON <= inp_gated or (inp_stretched and inp_stretch);
+tmp_con <= inp_gated or (inp_stretched and inp_stretch);
+
+gen_outputs_1 : if SAME_ORDER = 1 generate
+  CON <= tmp_con;
+end generate;
+gen_outputs_2 : if SAME_ORDER = 0 generate
+  CON <= tmp_con;
+end generate;
+
+
 
 SPARE_LINE(0) <= '0'; --clk_26;
 SPARE_LINE(1) <= '0'; --clk_i;
@@ -581,7 +593,9 @@ last_inp_long_reg <= inp_long_reg when rising_edge(clk_i);
 -- TEST_LINE(13)           <= ;
 -- TEST_LINE(14)           <= '1' when fsm_copydat = PWM_WRITE_GET_1 or fsm_copydat = PWM_WRITE_GET_2 else '0';
 -- TEST_LINE(15)           <= '1' when fsm_copydat = PWM_WRITE_GET_2 or fsm_copydat = PWM_WRITE else '0';
--- 
+
+
+TEST_LINE               <= spi_debug_i;
 
 
 LED_GREEN  <= not leds(0) when led_status(4) = '0' else not led_status(0);
diff --git a/wasa/source/spi_slave.vhd b/wasa/source/spi_slave.vhd
index 13b4a02..4829289 100644
--- a/wasa/source/spi_slave.vhd
+++ b/wasa/source/spi_slave.vhd
@@ -150,8 +150,8 @@ DEBUG_OUT(1) <= spi_cs_reg;
 DEBUG_OUT(2) <= spi_in_reg;
 DEBUG_OUT(3) <= buf_SPI_OUT;
 DEBUG_OUT(7 downto 4) <= std_logic_vector(to_unsigned(bitcnt,4));
--- DEBUG_OUT(8) <= 
-DEBUG_OUT(15 downto 8) <= input(31 downto 24);
+DEBUG_OUT(14 downto 8) <= input(30 downto 24);
+DEBUG_OUT(15) <= write_i(4);
 
 
 
diff --git a/wasa/trb3_periph_padiwa.p2t b/wasa/trb3_periph_padiwa.p2t
index 995161f..de1c3be 100644
--- a/wasa/trb3_periph_padiwa.p2t
+++ b/wasa/trb3_periph_padiwa.p2t
@@ -4,7 +4,7 @@
 -n 1
 -y
 -s 12
--t 11
+-t 10
 -c 1
 -e 2
 -m nodelist.txt
diff --git a/wasa/trb3_periph_padiwa.prj b/wasa/trb3_periph_padiwa.prj
index cde14cd..f2239b8 100644
--- a/wasa/trb3_periph_padiwa.prj
+++ b/wasa/trb3_periph_padiwa.prj
@@ -23,8 +23,8 @@ set_option -retiming 0
 set_option -pipe 0
 #set_option -force_gsr 
 set_option -force_gsr false
-set_option -fixgatedclocks 3
-set_option -fixgeneratedclocks 3
+set_option -fixgatedclocks false #3
+set_option -fixgeneratedclocks false #3
 set_option -compiler_compatible true
 
 
diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd
index 6cf5562..2fd5fbe 100644
--- a/wasa/trb3_periph_padiwa.vhd
+++ b/wasa/trb3_periph_padiwa.vhd
@@ -683,7 +683,7 @@ begin
       CLK_TDC               => CLK_PCLK_LEFT,  -- Clock used for the time measurement
       CLK_READOUT           => clk_100_i,   -- Clock for the readout
       REFERENCE_TIME        => timing_trg_received_i,  -- Reference time input
-      HIT_IN                => hit_in_i(63 downto 0),  -- Channel start signals
+      HIT_IN                => hit_in_i(3 downto 0),  -- Channel start signals
       TRG_WIN_PRE           => ctrl_reg(42 downto 32),  -- Pre-Trigger window width
       TRG_WIN_POST          => ctrl_reg(58 downto 48),  -- Post-Trigger window width
       --