From: Jan Michel <j.michel@gsi.de>
Date: Fri, 26 Aug 2016 07:34:21 +0000 (+0200)
Subject: add information to docu
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b8553014679333264d2dd08c1d7edbd61d6103f7;p=logicbox.git

add information to docu
---

diff --git a/docu/main.tex b/docu/main.tex
index ecd53e6..4caa59f 100644
--- a/docu/main.tex
+++ b/docu/main.tex
@@ -120,6 +120,8 @@
 \end{figure}
 \clearpage
 \section{Modules}
+A Logicbox consists of three modules: One mainboard and two AddOns. 
+
 \subsection{Mainboard Simple}
 The simple mainboard has two AddOn connectors, one dedicated for input modules, one for output modules only.
 Power is supplied on a 2-pin connector at 4-5 V. It supports the input select switch available on some input modules
@@ -135,12 +137,41 @@ but has no further logic capability.
     \item all LVDS or all LVTTL
     \item channel 0/2 LVDS, channel 1/3 LVTTL
   \end{itemize*}
+ \item Routing of signals can be selected by a switch, see drawing
 \end{itemize*}
 
 
 \subsection{Input: LEMO}
+\begin{itemize*}
+\item 2 inputs on LEMO connectors
+\item Inputs are connected to channels 0 and 2
+\item Inputs are terminated with 50 ohms. Strong TTL driver required, at least 35 mA
+\item Inputs are sensitive to positive (LV)TTL (threshold 1.5V) and NIM (threshold -0.4V) signals
+\end{itemize*}
+
 \subsection{Output: LVDS / TTL}
+\begin{itemize*}
+\item Four output channels on a 5x2 pin-header
+\item Output is either LVTTL or LVDS, configured in hardware, the typical configurations are
+  \begin{itemize*}
+    \item all LVDS or all LVTTL
+    \item channel 0/2 LVDS, channel 1/3 LVTTL
+  \end{itemize*}
+\item Routing of output signals can be selected, see drawing
+\item Can be used as 1:2 (by swtich) or 1:4 fan-out (by jumper)
+\end{itemize*}
+
+
 \subsection{Output: LEMO}
+\begin{itemize*}
+\item Three LEMO output channels
+\item Output standard can be selected by switch: NIM or LVTTL
+\item LVTTL can drive up to 48 mA
+\item NIM outputs can be built with 600 ps or 300 ps rise time, faster has a higher idle power consumption 
+
+\end{itemize*}
+
+
 \subsection{Breakout}
 AddOn with small prototyping area, but no components. Used as adapter for FPGA programming or any custom electronics.
 
@@ -155,6 +186,30 @@ There are few main configuration options:
 \subsection{Level Converter}
 
 \subsection{Logic Box}
+When used with an FPGA, several signal processing modes are available, based on selection using the on-board switch. 
+
+\begin{description*}
+\item[0] 1:1 connection of inputs and outputs
+\item[1] 1:4 fan-out - all outputs are input 1
+\item[2] Input 0/2 to Output 0/2. Output 1 is 'or', Output 3 'and' of  Input 0/2
+\item[3] like 0, but inverted
+\item[4] like 1, but inverted
+\item[5] like 2, but inputs inverted
+\item[6] 1:1, Edge detect, rising edge of input generates 14-21 ns output pulse on all channels
+\item[7] 1:1, Edge detect, falling edge of input generates 14-21 ns output pulse on all channels
+\item[8] like 0, input signals are stretched by adding 14 - 21 ns
+\item[9] like 1, input signals are stretched by adding 14 - 21 ns
+\item[A] like 2, input signals are stretched by adding 14 - 21 ns
+\item[B] not used
+\item[C] not used
+\item[D] not used
+\item[E] Basic pulser, 8.1 kHz, 60 ns long signals
+\item[F] like E, but inverted
+\end{description*}
+\begin{itemize*}
+\item In all modes, the switch on input modules can be used to swap inputs 0/2 with inputs 1/3
+\item All modes preserve the timing of the signal edges. Trailing edge is synchronous to clock in stretched and edge detect modes
+\end{itemize*}
 
 \subsection{Pulse Generator}
 
@@ -164,6 +219,39 @@ In pulse generator mode, the FPGA is loaded with a design that can produce up to
 
 
 \subsection{TDC}
+\begin{itemize*}
+\item 8 channel (9 with trigger on MDC MBO Adapter)
+\item Average binning 500 ps (125 MHz times 8)
+\item Must use a PCB with oscillator
+\item Each channel has an intermediate two-word buffer (e.g. to store two edges)
+\item The main buffer for all channels is 1k words deep
+\item Data is copied from channel  buffer to main buffer one word at a time, round-robin at 125 MHz. That is, the maximum rate per channel is 7 MHz
+\item At most one edge per 125 MHz clock cycle can be converted
+\item If rising and falling edge are within the same 250 MHz period, the hit can not be decoded. Minimum pulse width 4 ns. 
+\item Serial interface runs at 921 kBaud, about 8000 Words/second
+\item LED show input edges on first four channels
+\item Data can either be polled in register d0, or be written in streaming mode. No register read is possible while in streaming mode.
+\end{itemize*}
+
+
+\subsection{Registers}
+\begin{description*}
+\item[0x00 - Config] Bit 0: Enable streaming read-out. Bit 7-4 read status of config switch
+\item[0x01 - Input] 8 Bit of current status of the inputs
+\item[0x10 - Input Disable]8 Bits to disable individual inputs
+\item[0xd0 - Data] Read TDC data when not in streaming mode
+\end{description*}
+
+\subsection[Data Format]
+\begin{description*}
+\item[Bit 0-2] Fine time (8 bins)
+\item[Bit 3] fine time decoding error
+\item[Bit 25 - 4] 21 Bit coarse time (units of 4 ns)
+\item[Bit 29 - 26] Channel number
+\item[Bit 30] rising/falling edge
+\item[Bit 31] valid data
+\item[ 
+\end{description*}
 
 % \cleardoublepage
 % \begin{appendices}