From: Michael Boehmer Date: Sat, 11 Dec 2021 13:40:54 +0000 (+0100) Subject: Signal probing added X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b855ced5f1094c57479463d001f816ee7b7947c1;p=daqdocu.git Signal probing added --- diff --git a/trb3/DS_ProbingSignals.tex b/trb3/DS_ProbingSignals.tex new file mode 100644 index 0000000..d808e44 --- /dev/null +++ b/trb3/DS_ProbingSignals.tex @@ -0,0 +1,52 @@ +\subsection{Probing internal signals} + +For logic analyzer connection, there are several ways of providing access +to internal nodes inside the FPGA. + +\subsubsection{Simple, but ineffective ways} + +The Lattice way (using Reveal over JTAG) is not an option, as loads of changes +need to be made to the designs to get the Reveal logic inserted. + +The "old man's way" is to include debug ports in any VHDL module, and taking care +to route debug signals to the top level entity. This is possible, but may need a lot +of debug ports in entities, and especially for entities embedded in other entities, +the work load is not appropriate. + +Synplify allows to short cut this procedure by assigning signals inside an entity +the attribute \texttt{syn{\_}probe}. Synplify will route this signal to the top level entity +and (automatically) assign I/O pins to the signals. + +Unfortunately the last two ways strongly influence the way the test signals are routed, +and including test pins into the inital PAR process can lead to bad timing closure, +especially if timing sensitive signals (like SerDes control/status signals) are to be +monitored. + +\subsubsection{Post routing} + +Using the EPIC editor, a completely routed (and timing controlled design) can simply +be extended by routing internal nodes to test pins without altering the design. + +Steps needed: + +\begin{itemize*} + \item Decide which internal nodes you need later, and make sure that these nodes + are not optimized away. Apply the \texttt{syn{\_}keep} and \texttt{syn{\_}preserve} + attributes to the signals you want to be accessible.\newline + Depending on the nature of the signal one of the two attributes will fit. + \item Remove the test pins you want to use in the top level entity (e.g. \texttt{HDR{\_}IO}). + \item Compile your design as usual, and make sure that timing closure is met. + \item Make a backup of the NCD and PRF file, both are needed for post-routing. + \item Start the EPIC editor, load the NCD design. + \item Open the "Design" -- "Signal Probing" menu. + \item Find the I/O pin you want to use for a signal in the right list. + \item Use the wild card filter to narrow down the signal you want to assign.\newline + Tip: do not use the asterix, but only part of the name. It seems to be much faster. + \item Drag and drop the signal to the pin, and wait for the PIO attribute window to appear. + \item Check the status row of the signal you just assigned. It should show "Routed". + \item You can alter the I/O cells by right mouse button, or remove already routed signals. + \item When finished, export the setting as text file, so you can import it in case the design + gets recompiled. + \item Dismiss the dialogue, and save the NCD file. + \item Regenerate the bit file by \texttt{compile.pl -b}. +\end{itemize*} diff --git a/trb3/DS_SignalDescription.tex b/trb3/DS_SignalDescription.tex index c21132f..80a9a78 100644 --- a/trb3/DS_SignalDescription.tex +++ b/trb3/DS_SignalDescription.tex @@ -11,7 +11,9 @@ to include TX channel serializer synchronization and RX channel WordAlignment. \begin{itemize*} \item \texttt{RX{\_}DLM{\_}OUT} -- DLM komma received, per channel.\newline - Signal is set for one clock cycle of \texttt{RXI{\_}CLK}. + Signal is set for one clock cycle of \texttt{RXI{\_}CLK}.\newline + This signal has a delay of two clock cycles, it appears synchronous to \texttt{RX\_K} + on the output of the SerDes. \item \texttt{RX{\_}DLM{\_}WORD{\_}OUT} -- DLM data byte received, per channel. \item \texttt{TX{\_}DLM{\_}IN} -- send one DLM komma.\newline Data byte must be valid when this signal is set for one clock cycle diff --git a/trb3/main.tex b/trb3/main.tex index 2a406db..3bf3243 100644 --- a/trb3/main.tex +++ b/trb3/main.tex @@ -291,6 +291,7 @@ \section{Technical details} \input{DS_SignalDescription} \input{DS_PLLandCDR} + \input{DS_ProbingSignals} \cleardoublepage \part{Appendix}