From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Thu, 2 Jun 2022 07:44:46 +0000 (+0200)
Subject: Flash stuff
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b8af867bafe0e6df734d21c6264df37d40375544;p=trbnet.git

Flash stuff
---

diff --git a/special/fpga_reboot.vhd b/special/fpga_reboot.vhd
index 9be0432..f7dd4db 100644
--- a/special/fpga_reboot.vhd
+++ b/special/fpga_reboot.vhd
@@ -9,7 +9,7 @@ entity fpga_reboot is
     RESET     : in std_logic;
     DO_REBOOT : in std_logic;
     PROGRAMN  : out std_logic := '1'
-    );
+  );
 end entity;
 
 architecture fpga_reboot_arch of fpga_reboot is
@@ -41,4 +41,4 @@ PROC_REBOOT : process
 
 PROGRAMN                 <= not delayed_restart_fpga;    
     
-end architecture;
\ No newline at end of file
+end architecture;
diff --git a/special/spi_flash_and_fpga_reload_record.vhd b/special/spi_flash_and_fpga_reload_record.vhd
index 7243d4b..aaa37c8 100644
--- a/special/spi_flash_and_fpga_reload_record.vhd
+++ b/special/spi_flash_and_fpga_reload_record.vhd
@@ -10,11 +10,11 @@ use work.trb_net_components.all;
 
 entity spi_flash_and_fpga_reload_record is
   port(
-    CLK_IN               : in  std_logic;
-    RESET_IN             : in  std_logic;
+    CLK_IN         : in  std_logic;
+    RESET_IN       : in  std_logic;
     
-    BUS_TX               : out CTRLBUS_TX;
-    BUS_RX               : in  CTRLBUS_RX; 
+    BUS_TX         : out CTRLBUS_TX;
+    BUS_RX         : in  CTRLBUS_RX; 
 
     DO_REBOOT_IN   : in  std_logic;      
     PROGRAMN       : out std_logic;
@@ -23,7 +23,7 @@ entity spi_flash_and_fpga_reload_record is
     SPI_SCK_OUT    : out std_logic;
     SPI_SDO_OUT    : out std_logic;
     SPI_SDI_IN     : in  std_logic
-    );
+  );
 end entity;
 
 
@@ -59,7 +59,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
     PORT_NUMBER    => 2,
     PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", others => x"0000"),
     PORT_ADDR_MASK => (0 => 1,       1 => 6,       others => 0)
-    )
+  )
   port map(
     CLK                   => CLK_IN,
     RESET                 => RESET_IN,
@@ -102,7 +102,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
     BUS_UNKNOWN_ADDR_IN(1)              => '0',
     
     STAT_DEBUG => open
-    );
+  );
 
 
 THE_SPI_MASTER: spi_master
@@ -129,7 +129,7 @@ THE_SPI_MASTER: spi_master
     BRAM_WE_OUT    => spi_bram_we,
     -- Status lines
     STAT           => open
-    );
+  );
 
 -- data memory for SPI accesses
 THE_SPI_MEMORY: spi_databus_memory
@@ -150,7 +150,7 @@ THE_SPI_MEMORY: spi_databus_memory
     BRAM_WE_IN    => spi_bram_we,
     -- Status lines
     STAT          => open
-    );
+  );
     
 ---------------------------------------------------------------------------
 -- Reboot FPGA
@@ -161,7 +161,6 @@ THE_FPGA_REBOOT : fpga_reboot
     RESET     => RESET_IN,
     DO_REBOOT => DO_REBOOT_IN,
     PROGRAMN  => PROGRAMN
-    );
-
+  );
     
 end architecture;