From: Cahit Date: Wed, 23 Mar 2016 16:22:09 +0000 (+0100) Subject: added different tdc data format options X-Git-Tag: v2.3~45 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b8b74be2ee8b0b57613a8d2229fd640e22bf4f4a;p=tdc.git added different tdc data format options --- diff --git a/releases/tdc_v2.3/Channel_200.vhd b/releases/tdc_v2.3/Channel_200.vhd index 5542ca6..3b3a490 100644 --- a/releases/tdc_v2.3/Channel_200.vhd +++ b/releases/tdc_v2.3/Channel_200.vhd @@ -5,7 +5,7 @@ -- File : Channel_200.vhd -- Author : c.ugur@gsi.de -- Created : 2012-08-28 --- Last update: 2016-01-25 +-- Last update: 2016-03-23 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -104,6 +104,7 @@ architecture Channel_200 of Channel_200 is signal encoder_start : std_logic; signal encoder_finished : std_logic; signal encoder_data_out : std_logic_vector(9 downto 0); + signal encoder_info : std_logic; signal encoder_debug : std_logic_vector(31 downto 0); signal thermocode : std_logic_vector(287 downto 0); @@ -143,6 +144,8 @@ architecture Channel_200 of Channel_200 is signal write_stop_b : std_logic := '0'; signal write_data_flag_fsm : std_logic; signal write_data_flag : std_logic := '0'; + signal write_chain : std_logic := '0'; + signal chain : std_logic_vector(15 downto 0); signal trg_win_end_tdc_flag_fsm : std_logic; signal trg_win_end_tdc_flag : std_logic := '0'; signal trg_win_end_tdc : std_logic := '0'; @@ -170,9 +173,9 @@ begin -- Channel_200 GEN_TrgWinEndTdcDist : if SIMULATION = 0 generate TrgWinEndTdcDist : FD1P3IX port map (D => '1', - SP => TRG_WIN_END_TDC_IN, --CLKen + SP => TRG_WIN_END_TDC_IN, CK => CLK_200, - CD => trg_win_end_tdc, --reset + CD => trg_win_end_tdc, Q => trg_win_end_tdc); end generate GEN_TrgWinEndTdcDist; @@ -180,18 +183,18 @@ begin -- Channel_200 trg_win_end_tdc <= TRG_WIN_END_TDC_IN when rising_edge(CLK_200); end generate GEN_TrgWinEndTdcDist_Sim; - + SimAdderYes : if SIMULATION = c_YES generate --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition FC : Adder_304 port map ( CLK => CLK_200, - RESET => RESET_200, + RESET => '0', DataA => data_a, DataB => data_b, ClkEn => ff_array_en, Result => result); - data_a <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0001FF"&x"7FFFFFF"; + data_a <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFc030c0F"&x"7FFFFFF"; data_b <= x"000000000000000000000000000000000000000000000000000000000000000000000"& HIT_IN & x"000000"&"00" & not(HIT_IN); end generate SimAdderYes; SimAdderNo : if SIMULATION = c_NO generate @@ -199,7 +202,7 @@ begin -- Channel_200 FC : Adder_304 port map ( CLK => CLK_200, - RESET => RESET_200, + RESET => '0', DataA => data_a, DataB => data_b, ClkEn => ff_array_en, @@ -257,21 +260,40 @@ begin -- Channel_200 end process EdgeTypeCapture; end generate isChannelEdge; - TimeStampCapture : process (CLK_200) - begin - if rising_edge(CLK_200) then - if hit_detect_r = '1' then - time_stamp <= coarse_cntr_r; + DATA_FORMAT_0 : if TDC_DATA_FORMAT = 0 or TDC_DATA_FORMAT = 13 or TDC_DATA_FORMAT = 14 generate + TimeStampCapture : process (CLK_200) + begin + if rising_edge(CLK_200) then + if hit_detect_r = '1' then + time_stamp <= coarse_cntr_r; + end if; + time_stamp_r <= time_stamp; + time_stamp_2r <= time_stamp_r; + time_stamp_3r <= time_stamp_2r; + time_stamp_4r <= time_stamp_3r; + time_stamp_5r <= time_stamp_4r; + time_stamp_6r <= time_stamp_5r; + time_stamp_7r <= time_stamp_6r; end if; - time_stamp_r <= time_stamp; - time_stamp_2r <= time_stamp_r; - time_stamp_3r <= time_stamp_2r; - time_stamp_4r <= time_stamp_3r; - time_stamp_5r <= time_stamp_4r; - time_stamp_6r <= time_stamp_5r; - time_stamp_7r <= time_stamp_6r; - end if; - end process TimeStampCapture; + end process TimeStampCapture; + end generate DATA_FORMAT_0; + + DATA_FORMAT_1 : if TDC_DATA_FORMAT = 1 generate + TimeStampCapture : process (CLK_200) + begin + if rising_edge(CLK_200) then + if hit_detect_r = '1' then + time_stamp_r <= coarse_cntr_r; + end if; + time_stamp_2r <= time_stamp_r; + time_stamp_3r <= time_stamp_2r; + time_stamp_4r <= time_stamp_3r; + time_stamp_5r <= time_stamp_4r; + time_stamp_6r <= time_stamp_5r; + time_stamp_7r <= time_stamp_6r; + end if; + end process TimeStampCapture; + end generate DATA_FORMAT_1; CoarseCounterOverflow : entity work.fallingEdgeDetect port map ( @@ -307,19 +329,23 @@ begin -- Channel_200 -- START_IN => encoder_start, -- THERMOCODE_IN => result, -- FINISHED_OUT => encoder_finished, - -- BINARY_CODE_OUT => encoder_data_out, + -- DECIMAL_CODE_OUT => encoder_data_out, -- ENCODER_DEBUG => encoder_debug); --purpose: Encoder Encoder : Encoder_288_Bit port map ( - RESET => RESET_200, - CLK => CLK_200, - START_IN => encoder_start, - THERMOCODE_IN => thermocode, - FINISHED_OUT => encoder_finished, - BINARY_CODE_OUT => encoder_data_out, - ENCODER_DEBUG => encoder_debug); + RESET => RESET_200, + CLK => CLK_200, + START_IN => encoder_start, + THERMOCODE_IN => thermocode, + FINISHED_OUT => encoder_finished, + DECIMAL_CODE_OUT => encoder_data_out, + ENCODER_INFO_OUT => encoder_info, + ENCODER_DEBUG => encoder_debug, + CHAIN_VALID_OUT => write_chain, + CHAIN_DATA_OUT => chain + ); RingBuffer_128_dyn : if RING_BUFFER_SIZE = 7 generate FIFO : FIFO_DC_36x128_DynThr_OutReg @@ -559,39 +585,88 @@ begin -- Channel_200 end process TriggerWindowFlag; -- purpose: Generate Fifo Wr Signal - FifoWriteSignal : process (CLK_200) - begin - if rising_edge(CLK_200) then - if write_epoch = '1' and EPOCH_WRITE_EN_IN = '1' then - ringBuffer_data_in(35 downto 32) <= x"1"; - ringBuffer_data_in(31 downto 29) <= "011"; - ringBuffer_data_in(28) <= '0'; - ringBuffer_data_in(27 downto 0) <= epoch_cntr; - ringBuffer_wr_en <= '1'; - elsif write_data = '1' then - ringBuffer_data_in(35 downto 32) <= x"1"; - ringBuffer_data_in(31) <= '1'; -- data marker - ringBuffer_data_in(30 downto 29) <= "00"; -- reserved bits - ringBuffer_data_in(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number - ringBuffer_data_in(21 downto 12) <= encoder_data_out; -- fine time from the encoder - ringBuffer_data_in(11) <= edge_type; -- rising '1' or falling '0' edge - ringBuffer_data_in(10 downto 0) <= time_stamp_7r; -- hit time stamp - ringBuffer_wr_en <= '1'; - elsif write_stop_a = '1' then - ringBuffer_data_in(35 downto 32) <= x"f"; - ringBuffer_data_in(31 downto 0) <= (others => '0'); - ringBuffer_wr_en <= '1'; - elsif write_stop_b = '1' then - ringBuffer_data_in(35 downto 32) <= x"0"; - ringBuffer_data_in(31 downto 0) <= (others => '0'); - ringBuffer_wr_en <= '1'; - else - ringBuffer_data_in(35 downto 32) <= x"e"; - ringBuffer_data_in(31 downto 0) <= (others => '0'); - ringBuffer_wr_en <= '0'; + DATA_FORMAT_NORMAL : if TDC_DATA_FORMAT = 0 or TDC_DATA_FORMAT = 1 generate + FifoWriteSignal : process (CLK_200) + begin + if rising_edge(CLK_200) then + if write_epoch = '1' and EPOCH_WRITE_EN_IN = '1' then + ringBuffer_data_in(35 downto 32) <= x"1"; + ringBuffer_data_in(31 downto 29) <= "011"; + ringBuffer_data_in(28) <= '0'; + ringBuffer_data_in(27 downto 0) <= epoch_cntr; + ringBuffer_wr_en <= '1'; + elsif write_data = '1' then + ringBuffer_data_in(35 downto 32) <= x"1"; + ringBuffer_data_in(31) <= '1'; -- data marker + ringBuffer_data_in(30) <= '0'; -- reserved bits + ringBuffer_data_in(29) <= encoder_info; -- reserved bits + ringBuffer_data_in(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number + ringBuffer_data_in(21 downto 12) <= encoder_data_out; -- fine time from the encoder + ringBuffer_data_in(11) <= edge_type; -- rising '1' or falling '0' edge + ringBuffer_data_in(10 downto 0) <= time_stamp_7r; -- hit time stamp + ringBuffer_wr_en <= '1'; + elsif write_stop_a = '1' then + ringBuffer_data_in(35 downto 32) <= x"f"; + ringBuffer_data_in(31 downto 0) <= (others => '0'); + ringBuffer_wr_en <= '1'; + elsif write_stop_b = '1' then + ringBuffer_data_in(35 downto 32) <= x"0"; + ringBuffer_data_in(31 downto 0) <= (others => '0'); + ringBuffer_wr_en <= '1'; + else + ringBuffer_data_in(35 downto 32) <= x"e"; + ringBuffer_data_in(31 downto 0) <= (others => '0'); + ringBuffer_wr_en <= '0'; + end if; end if; - end if; - end process FifoWriteSignal; + end process FifoWriteSignal; + end generate DATA_FORMAT_NORMAL; + + DATA_FORMAT_DEBUG : if TDC_DATA_FORMAT = 13 or TDC_DATA_FORMAT = 14 or TDC_DATA_FORMAT = 15 generate + FifoWriteSignal : process (CLK_200) + begin + if rising_edge(CLK_200) then + if write_epoch = '1' and EPOCH_WRITE_EN_IN = '1' then + ringBuffer_data_in(35 downto 32) <= x"1"; + ringBuffer_data_in(31 downto 29) <= "011"; + ringBuffer_data_in(28) <= '0'; + ringBuffer_data_in(27 downto 0) <= epoch_cntr; + ringBuffer_wr_en <= '1'; + elsif write_data = '1' then + ringBuffer_data_in(35 downto 32) <= x"1"; + ringBuffer_data_in(31) <= '1'; -- data marker + ringBuffer_data_in(30) <= '0'; -- reserved bits + ringBuffer_data_in(29) <= encoder_info; -- reserved bits + ringBuffer_data_in(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number + ringBuffer_data_in(21 downto 12) <= encoder_data_out; -- fine time from the encoder + ringBuffer_data_in(11) <= edge_type; -- rising '1' or falling '0' edge + ringBuffer_data_in(10 downto 0) <= time_stamp_7r; -- hit time stamp + ringBuffer_wr_en <= '1'; + elsif write_stop_a = '1' then + ringBuffer_data_in(35 downto 32) <= x"f"; + ringBuffer_data_in(31 downto 0) <= (others => '0'); + ringBuffer_wr_en <= '1'; + elsif write_stop_b = '1' then + ringBuffer_data_in(35 downto 32) <= x"0"; + ringBuffer_data_in(31 downto 0) <= (others => '0'); + ringBuffer_wr_en <= '1'; + elsif write_chain = '1' then + ringBuffer_data_in(35 downto 32) <= x"1"; + ringBuffer_data_in(31) <= '1'; -- data marker + ringBuffer_data_in(30) <= '1'; -- reserved bits + ringBuffer_data_in(29) <= '1'; -- reserved bits + ringBuffer_data_in(28 downto 22) <= std_logic_vector(to_unsigned(CHANNEL_ID, 7)); -- channel number + ringBuffer_data_in(21 downto 16) <= (others => '0'); -- fine time from the encoder + ringBuffer_data_in(15 downto 0) <= chain; -- hit time stamp + ringBuffer_wr_en <= '1'; + else + ringBuffer_data_in(35 downto 32) <= x"e"; + ringBuffer_data_in(31 downto 0) <= (others => '0'); + ringBuffer_wr_en <= '0'; + end if; + end if; + end process FifoWriteSignal; + end generate DATA_FORMAT_DEBUG; FIFO_WRITE_OUT <= ringBuffer_wr_en; ENCODER_FINISHED_OUT <= encoder_finished; @@ -752,8 +827,8 @@ begin -- Channel_200 --CHANNEL_200_DEBUG_OUT(17) <= fifo_data_valid; --CHANNEL_200_DEBUG_OUT(18) <= ringBuffer_rd_en; --CHANNEL_200_DEBUG_OUT(23 downto 19) <= (others => '0'); - CHANNEL_200_DEBUG_OUT(0) <= ff_array_en when rising_edge(CLK_200); - CHANNEL_200_DEBUG_OUT(23 downto 1) <= (others => '0'); +-- CHANNEL_200_DEBUG_OUT(0) <= ff_array_en; + CHANNEL_200_DEBUG_OUT(23 downto 0) <= (others => '0'); CHANNEL_200_DEBUG_OUT(27 downto 24) <= fsm_rd_debug; CHANNEL_200_DEBUG_OUT(31 downto 28) <= fsm_wr_debug; diff --git a/releases/tdc_v2.3/Encoder_288_Bit.vhd b/releases/tdc_v2.3/Encoder_288_Bit.vhd index f98a5dd..1f0a875 100644 --- a/releases/tdc_v2.3/Encoder_288_Bit.vhd +++ b/releases/tdc_v2.3/Encoder_288_Bit.vhd @@ -4,7 +4,7 @@ -- File : Encoder_288_Bit.vhd -- Author : Cahit Ugur -- Created : 2011-11-28 --- Last update: 2016-01-26 +-- Last update: 2016-03-23 ------------------------------------------------------------------------------- -- Description: Encoder for 288 bits ------------------------------------------------------------------------------- @@ -21,6 +21,7 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; use work.tdc_components.all; +use work.config.all; -- synopsys translate_off library ecp3; @@ -34,9 +35,11 @@ entity Encoder_288_Bit is START_IN : in std_logic; THERMOCODE_IN : in std_logic_vector(287 downto 0); FINISHED_OUT : out std_logic; - BINARY_CODE_OUT : out std_logic_vector(9 downto 0); - ENCODER_INFO_OUT : out std_logic_vector(1 downto 0); - ENCODER_DEBUG : out std_logic_vector(31 downto 0) + DECIMAL_CODE_OUT : out std_logic_vector(9 downto 0); + ENCODER_INFO_OUT : out std_logic; + ENCODER_DEBUG : out std_logic_vector(31 downto 0); + CHAIN_VALID_OUT : out std_logic; + CHAIN_DATA_OUT : out std_logic_vector(15 downto 0) ); end Encoder_288_Bit; @@ -58,26 +61,33 @@ architecture behavioral of Encoder_288_Bit is ------------------------------------------------------------------------------- signal P_lut : std_logic_vector(35 downto 0); signal P_one : std_logic_vector(35 downto 0); + signal P_mux : std_logic_vector(34 downto 0); signal mux_control : std_logic_vector(5 downto 0); signal mux_control_reg : std_logic_vector(5 downto 0); signal mux_control_2reg : std_logic_vector(5 downto 0); signal mux_control_3reg : std_logic_vector(5 downto 0); signal interval_reg : std_logic_vector(8 downto 0); - signal interval_binary : std_logic_vector(2 downto 0); - signal binary_code_f : std_logic_vector(8 downto 0); - signal binary_code_r : std_logic_vector(8 downto 0); - signal start_reg : std_logic; - signal start_2reg : std_logic; - signal start_3reg : std_logic; + signal interval_decimal : std_logic_vector(2 downto 0); + signal decimal_code_f : std_logic_vector(8 downto 0); + signal decimal_code_r : std_logic_vector(8 downto 0); signal address : std_logic_vector(9 downto 0); + signal address_r : std_logic_vector(9 downto 0); signal q_reg : std_logic_vector(7 downto 0); signal info : std_logic_vector(1 downto 0); signal info_reg : std_logic_vector(1 downto 0); signal info_2reg : std_logic_vector(1 downto 0); + signal info_3reg : std_logic_vector(1 downto 0); -- signal conv_finished : std_logic; signal thermocode : std_logic_vector(288 downto 0); - signal start_pipeline : std_logic_vector(6 downto 0) := (others => '0'); + signal thermocode_r : std_logic_vector(287 downto 0); + signal start_pipeline : std_logic_vector(10 downto 0) := (others => '0'); + signal chain_pipeline : std_logic_vector(18 downto 0) := (others => '0'); +--debug + type std_logic_vector_array_10 is array(integer range <>) of std_logic_vector(9 downto 0); + signal decimal_code_i : std_logic_vector_array_10(0 to 3); + signal chain : std_logic_vector(15 downto 0); + signal chain_valid : std_logic; attribute syn_keep : boolean; attribute syn_keep of mux_control : signal is true; @@ -87,24 +97,20 @@ architecture behavioral of Encoder_288_Bit is ------------------------------------------------------------------------------- begin - thermocode(288 downto 1) <= THERMOCODE_IN; thermocode(0) <= '1'; - start_reg <= START_IN when rising_edge(CLK); - start_2reg <= start_reg when rising_edge(CLK); - start_3reg <= start_2reg when rising_edge(CLK); mux_control_reg <= mux_control when rising_edge(CLK); mux_control_2reg <= mux_control_reg when rising_edge(CLK); mux_control_3reg <= mux_control_2reg when rising_edge(CLK); Interval_Determination_First : LUT4 - generic map (INIT => X"15A8") + generic map (INIT => X"37A8") port map (A => '1', B => '1', C => THERMOCODE_IN(0), D => START_IN, Z => P_lut(0)); Interval_Determination : for i in 1 to 35 generate U : LUT4 - generic map (INIT => X"15A8") + generic map (INIT => X"37A8") port map (A => THERMOCODE_IN(8*i-2), B => THERMOCODE_IN(8*i-1), C => THERMOCODE_IN(8*i), D => START_IN, Z => P_lut(i)); end generate Interval_Determination; @@ -113,44 +119,36 @@ begin Gen_P_one : for i in 0 to 34 generate P_one(i) <= P_lut(i) and (not P_lut(i+1)) when rising_edge(CLK); end generate Gen_P_one; + P_one(35) <= P_lut(35) and START_IN when rising_edge(CLK); - P_one_assign : process (CLK) - begin - if rising_edge(CLK) then - if START_IN = '0' then - P_one(35) <= '0'; - else - P_one(35) <= P_lut(35); - end if; - end if; - end process P_one_assign; + P_mux(34 downto 0) <= P_one(35 downto 1); - Interval_Number_to_Binary : process (CLK) - begin -- The interval number with the 0-1 transition is converted from 1-of-N code to binary + Interval_Number_to_Decimal : process (CLK) + begin -- The interval number with the 0-1 transition is converted from 1-of-N code to decimal -- code for the control of the MUX. if rising_edge(CLK) then - if start_2reg = '1' or start_reg = '1' then - mux_control(0) <= P_one(0) or P_one(2) or P_one(4) or P_one(6) or P_one(8) or P_one(10) or - P_one(12) or P_one(14) or P_one(16) or P_one(18) or P_one(20) or P_one(22) or - P_one(24) or P_one(26) or P_one(28) or P_one(30) or P_one(32) or P_one(34); - mux_control(1) <= P_one(1) or P_one(2) or P_one(5) or P_one(6) or P_one(9) or P_one(10) or - P_one(13) or P_one(14) or P_one(17) or P_one(18) or P_one(21) or P_one(22) or - P_one(25) or P_one(26) or P_one(29) or P_one(30) or P_one(33) or P_one(34); - mux_control(2) <= P_one(3) or P_one(4) or P_one(5) or P_one(6) or P_one(11) or P_one(12) or - P_one(13) or P_one(14) or P_one(19) or P_one(20) or P_one(21) or P_one(22) or - P_one(27) or P_one(28) or P_one(29) or P_one(30) or P_one(35); - mux_control(3) <= P_one(7) or P_one(8) or P_one(9) or P_one(10) or P_one(11) or P_one(12) or - P_one(13) or P_one(14) or P_one(23) or P_one(24) or P_one(25) or P_one(26) or - P_one(27) or P_one(28) or P_one(29) or P_one(30); - mux_control(4) <= P_one(15) or P_one(16) or P_one(17) or P_one(18) or P_one(19) or P_one(20) or - P_one(21) or P_one(22) or P_one(23) or P_one(24) or P_one(25) or P_one(26) or - P_one(27) or P_one(28) or P_one(29) or P_one(30); - mux_control(5) <= P_one(31) or P_one(32) or P_one(33) or P_one(34) or P_one(35); + if start_pipeline(1) = '1' or start_pipeline(0) = '1' then + mux_control(0) <= P_mux(0) or P_mux(2) or P_mux(4) or P_mux(6) or P_mux(8) or P_mux(10) or + P_mux(12) or P_mux(14) or P_mux(16) or P_mux(18) or P_mux(20) or P_mux(22) or + P_mux(24) or P_mux(26) or P_mux(28) or P_mux(30) or P_mux(32) or P_mux(34); + mux_control(1) <= P_mux(1) or P_mux(2) or P_mux(5) or P_mux(6) or P_mux(9) or P_mux(10) or + P_mux(13) or P_mux(14) or P_mux(17) or P_mux(18) or P_mux(21) or P_mux(22) or + P_mux(25) or P_mux(26) or P_mux(29) or P_mux(30) or P_mux(33) or P_mux(34); + mux_control(2) <= P_mux(3) or P_mux(4) or P_mux(5) or P_mux(6) or P_mux(11) or P_mux(12) or + P_mux(13) or P_mux(14) or P_mux(19) or P_mux(20) or P_mux(21) or P_mux(22) or + P_mux(27) or P_mux(28) or P_mux(29) or P_mux(30); + mux_control(3) <= P_mux(7) or P_mux(8) or P_mux(9) or P_mux(10) or P_mux(11) or P_mux(12) or + P_mux(13) or P_mux(14) or P_mux(23) or P_mux(24) or P_mux(25) or P_mux(26) or + P_mux(27) or P_mux(28) or P_mux(29) or P_mux(30); + mux_control(4) <= P_mux(15) or P_mux(16) or P_mux(17) or P_mux(18) or P_mux(19) or P_mux(20) or + P_mux(21) or P_mux(22) or P_mux(23) or P_mux(24) or P_mux(25) or P_mux(26) or + P_mux(27) or P_mux(28) or P_mux(29) or P_mux(30); + mux_control(5) <= P_mux(31) or P_mux(32) or P_mux(33) or P_mux(34); else mux_control <= (others => '0'); end if; end if; - end process Interval_Number_to_Binary; + end process Interval_Number_to_Decimal; Interval_Selection : process (CLK) variable tmp : std_logic_vector(9 downto 1); @@ -166,8 +164,6 @@ begin end if; end process Interval_Selection; - address <= start_2reg & interval_reg; - The_ROM : entity work.ROM_encoder_3 port map ( Address => address, @@ -176,63 +172,196 @@ begin Reset => RESET, Q => q_reg); - interval_binary <= q_reg(2 downto 0) when rising_edge(CLK); - info <= q_reg(7 downto 6) when rising_edge(CLK); - info_reg <= info when rising_edge(CLK); - info_2reg <= info_reg when rising_edge(CLK); + address <= start_pipeline(1) & interval_reg; + interval_decimal <= q_reg(2 downto 0) when rising_edge(CLK); + info <= q_reg(7 downto 6) when rising_edge(CLK); + info_reg <= info when rising_edge(CLK); + info_2reg <= info_reg when rising_edge(CLK); + info_3reg <= info_2reg when rising_edge(CLK); + start_pipeline <= start_pipeline(9 downto 0) & START_IN when rising_edge(CLK); - Binary_Code_Calculation_rf : process (CLK) - begin - if rising_edge(CLK) then - binary_code_r <= (mux_control_3reg - 1) & interval_binary; - binary_code_f <= binary_code_r; - end if; - end process Binary_Code_Calculation_rf; + DATA_FORMAT_0 : if TDC_DATA_FORMAT = 0 generate -- Fine time as the sum of the two transitions + Decimal_Code_Calculation : process (CLK) + begin + if rising_edge(CLK) then + if conv_finished = '1' then + if info_reg(1) = '1' and info_2reg(1) = '1' then + DECIMAL_CODE_OUT <= ('0' & decimal_code_r) + ('0' & decimal_code_f); + else + DECIMAL_CODE_OUT <= (others => '1'); + end if; + ENCODER_INFO_OUT <= info(0) or info_reg(0); + end if; - Binary_Code_Calculation : process (CLK) - begin - if rising_edge(CLK) then - if conv_finished = '1' then - if info_reg(1) = '1' and info_2reg(1) = '1' then - BINARY_CODE_OUT <= ('0' & binary_code_r) + ('0' & binary_code_f); + FINISHED_OUT <= conv_finished; + decimal_code_r <= mux_control_3reg & interval_decimal; + decimal_code_f <= decimal_code_r; + conv_finished <= start_pipeline(5); + end if; + end process Decimal_Code_Calculation; + end generate DATA_FORMAT_0; + + DATA_FORMAT_1 : if TDC_DATA_FORMAT = 1 generate -- Fine time seperate two transitions + Decimal_Code_Calculation : process (CLK) + begin + if rising_edge(CLK) then + if conv_finished = '1' then + if info(1) = '1' then + DECIMAL_CODE_OUT <= '0' & decimal_code_r; + else + DECIMAL_CODE_OUT <= (others => '1'); + end if; + ENCODER_INFO_OUT <= info(0); + end if; + + FINISHED_OUT <= conv_finished; + if (start_pipeline(4) = '1' or start_pipeline(5) = '1') then + decimal_code_r <= mux_control_3reg & interval_decimal; + end if; + conv_finished <= start_pipeline(2) or start_pipeline(3) or start_pipeline(4) or start_pipeline(5); + end if; + end process Decimal_Code_Calculation; + end generate DATA_FORMAT_1; + +------------------------------------------------------------------------------- +-- DEBUG DATA FORMATS +------------------------------------------------------------------------------- + DATA_FORMAT_13 : if TDC_DATA_FORMAT = 13 generate + SampleThermocode : process (CLK) is + begin + if rising_edge(CLK) then -- rising clock edge + if START_IN = '1' then + thermocode_r <= THERMOCODE_IN; + end if; + end if; + end process SampleThermocode; +-- + Decimal_Code_Calculation : process (CLK) + begin + if rising_edge(CLK) then + if conv_finished = '1' then + if info_reg(1) = '1' and info_2reg(1) = '1' then + DECIMAL_CODE_OUT <= ('0' & decimal_code_r) + ('0' & decimal_code_f); + chain_pipeline(0) <= '0'; + else + DECIMAL_CODE_OUT <= (others => '1'); + chain_pipeline(0) <= '1'; + end if; + ENCODER_INFO_OUT <= info(0) or info_reg(0); else - BINARY_CODE_OUT <= (others => '1'); + chain_pipeline(0) <= '0'; end if; - ENCODER_INFO_OUT <= (others => '0'); --info_reg or info_2reg; - FINISHED_OUT <= '1'; - else - FINISHED_OUT <= '0'; + + FINISHED_OUT <= conv_finished; + decimal_code_r <= mux_control_3reg & interval_decimal; + decimal_code_f <= decimal_code_r; + conv_finished <= start_pipeline(5); + chain_pipeline(18 downto 1) <= chain_pipeline(17 downto 0); end if; - end if; - end process Binary_Code_Calculation; + end process Decimal_Code_Calculation; +-- + Chain_Readout : process (CLK) + variable tmp : std_logic_vector(15 downto 0); + begin + if rising_edge(CLK) then + tmp := (others => '0'); + make_mux : for i in 0 to 17 loop + make_mux_2 : for j in 0 to 15 loop + tmp(j) := tmp(j) or (thermocode_r(i*16+j) and chain_pipeline(i+1)); + end loop; + end loop; + chain <= tmp; + chain_valid <= or_all(chain_pipeline(18 downto 1)); + CHAIN_DATA_OUT <= chain; + CHAIN_VALID_OUT <= chain_valid; + end if; + end process Chain_Readout; + end generate DATA_FORMAT_13; - StartSignalPipeLine : process (CLK) - begin - if rising_edge(CLK) then - start_pipeline <= start_pipeline(5 downto 0) & START_IN; - end if; - end process StartSignalPipeLine; - conv_finished <= start_pipeline(6); + DATA_FORMAT_14 : if TDC_DATA_FORMAT = 14 generate + Decimal_Code_Calculation : process (CLK) + begin + if rising_edge(CLK) then + if start_pipeline(2) = '1' then + address_r <= address; + end if; + if start_pipeline(1) = '1' then + DECIMAL_CODE_OUT <= address; + FINISHED_OUT <= '1'; + ENCODER_INFO_OUT <= '1'; + elsif start_pipeline(4) = '1' then + DECIMAL_CODE_OUT <= address_r; + FINISHED_OUT <= '1'; + ENCODER_INFO_OUT <= '1'; + elsif conv_finished = '1' then + if info_2reg(1) = '1' and info_3reg(1) = '1' then + DECIMAL_CODE_OUT <= decimal_code_i(0); + else + DECIMAL_CODE_OUT <= (others => '1'); + end if; + ENCODER_INFO_OUT <= info_2reg(0) or info_3reg(0); + FINISHED_OUT <= '1'; + else + FINISHED_OUT <= '0'; + end if; + + decimal_code_r <= mux_control_3reg & interval_decimal; + decimal_code_f <= decimal_code_r; + decimal_code_i(0) <= ('0' & decimal_code_r) + ('0' & decimal_code_f); + decimal_code_i(1 to 3) <= decimal_code_i(0 to 2); + conv_finished <= start_pipeline(6); + end if; + end process Decimal_Code_Calculation; + end generate DATA_FORMAT_14; + + DATA_FORMAT_15 : if TDC_DATA_FORMAT = 15 generate + SampleThermocode : process (CLK) is + begin + if rising_edge(CLK) then -- rising clock edge + if START_IN = '1' then + thermocode_r <= THERMOCODE_IN; + end if; + end if; + end process SampleThermocode; +-- + Chain_Readout : process (CLK) + variable tmp : std_logic_vector(15 downto 0); + begin + if rising_edge(CLK) then + tmp := (others => '0'); + make_mux : for i in 0 to 17 loop + make_mux_2 : for j in 0 to 15 loop + tmp(j) := tmp(j) or (thermocode_r(i*16+j) and chain_pipeline(i)); + end loop; + end loop; + chain <= tmp; + chain_valid <= or_all(chain_pipeline(17 downto 0)); + CHAIN_DATA_OUT <= chain; + CHAIN_VALID_OUT <= chain_valid; + chain_pipeline(17 downto 0) <= chain_pipeline(16 downto 0) & START_IN; + end if; + end process Chain_Readout; + end generate DATA_FORMAT_15; ------------------------------------------------------------------------------- -- DEBUG ------------------------------------------------------------------------------- - --Binary_Code_Calculation : process (CLK, RESET) + --Decimal_Code_Calculation : process (CLK, RESET) --begin -- if rising_edge(CLK) then -- if RESET = '1' then - -- BINARY_CODE_OUT <= (others => '0'); + -- DECIMAL_CODE_OUT <= (others => '0'); -- FINISHED_OUT <= '0'; - -- elsif start_2reg = '1' or start_3reg = '1' then - -- BINARY_CODE_OUT <= address; + -- elsif start_pipeline(1) = '1' or start_pipeline(2) = '1' then + -- DECIMAL_CODE_OUT <= address; -- FINISHED_OUT <= '1'; -- else - -- BINARY_CODE_OUT <= (others => '0'); + -- DECIMAL_CODE_OUT <= (others => '0'); -- FINISHED_OUT <= '0'; -- end if; -- end if; - --end process Binary_Code_Calculation; + --end process Decimal_Code_Calculation; --ENCODER_DEBUG(8 downto 0) <= interval_reg; diff --git a/releases/tdc_v2.3/Readout_record.vhd b/releases/tdc_v2.3/Readout_record.vhd index b408cb5..9e84741 100644 --- a/releases/tdc_v2.3/Readout_record.vhd +++ b/releases/tdc_v2.3/Readout_record.vhd @@ -5,7 +5,7 @@ -- File : Readout_record.vhd -- Author : cugur@gsi.de -- Created : 2012-10-25 --- Last update: 2016-01-22 +-- Last update: 2016-03-22 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -20,6 +20,7 @@ library work; use work.trb_net_std.all; use work.tdc_components.all; use work.version.all; +use work.config.all; entity Readout_record is generic ( @@ -203,8 +204,27 @@ architecture behavioral of Readout_record is signal wr_fsm_debug_r : std_logic_vector(3 downto 0); signal history_wr_fsm : std_logic_vector(31 downto 0) := (others => '0'); signal any_hit : std_logic := '0'; + signal data_format_i : std_logic_vector(3 downto 0); begin -- behavioral + DATA_FORMAT_0 : if TDC_DATA_FORMAT = 0 generate + data_format_i <= x"0"; + end generate DATA_FORMAT_0; + DATA_FORMAT_1 : if TDC_DATA_FORMAT = 1 generate + data_format_i <= x"1"; + end generate DATA_FORMAT_1; + DATA_FORMAT_2 : if TDC_DATA_FORMAT = 2 generate + data_format_i <= x"2"; + end generate DATA_FORMAT_2; + DATA_FORMAT_13 : if TDC_DATA_FORMAT = 13 generate + data_format_i <= x"d"; + end generate DATA_FORMAT_13; + DATA_FORMAT_14 : if TDC_DATA_FORMAT = 14 generate + data_format_i <= x"e"; + end generate DATA_FORMAT_14; + DATA_FORMAT_15 : if TDC_DATA_FORMAT = 15 generate + data_format_i <= x"f"; + end generate DATA_FORMAT_15; trg_win_pre <= unsigned(TRG_WIN_PRE_IN); trg_win_post <= unsigned(TRG_WIN_POST_IN); @@ -598,14 +618,13 @@ begin -- behavioral end if; end process TriggerWindowElimination; - Data_Out_MUX : process (CLK_100) variable i : integer := 0; begin if rising_edge(CLK_100) then if wr_header = '1' then --data_out_r <= "001" & "0" & READOUT_RX.trg_type & READOUT_RX.trg_code & header_error_bits; - data_out_r <= "001" & "0" & x"000" & header_error_bits; + data_out_r <= "001" & "0" & data_format_i & x"00" & header_error_bits; stop_status <= '0'; elsif wr_ch_data_r = '1' then data_out_r <= ch_data_4r; diff --git a/releases/tdc_v2.3/Readout_record_noDecode.vhd b/releases/tdc_v2.3/Readout_record_noDecode.vhd new file mode 100644 index 0000000..0f0cf7b --- /dev/null +++ b/releases/tdc_v2.3/Readout_record_noDecode.vhd @@ -0,0 +1,982 @@ +------------------------------------------------------------------------------- +-- Title : Readout Entity +-- Project : +------------------------------------------------------------------------------- +-- File : Readout_record.vhd +-- Author : cugur@gsi.de +-- Created : 2012-10-25 +-- Last update: 2016-03-23 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2012 +------------------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.tdc_components.all; +use work.version.all; + +entity Readout_record is + generic ( + CHANNEL_NUMBER : integer range 2 to 65; + STATUS_REG_NR : integer range 0 to 31); + port ( + RESET_100 : in std_logic; + RESET_200 : in std_logic; + RESET_COUNTERS : in std_logic; + CLK_100 : in std_logic; + CLK_200 : in std_logic; + HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1); +-- from the channels + CH_DATA_IN : in std_logic_vector_array_36(0 to CHANNEL_NUMBER); + CH_DATA_VALID_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_ALMOST_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); + CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); +-- endpoint bus + READOUT_RX : in READOUT_RX; + READOUT_TX : out READOUT_TX; +-- to the channels + READ_EN_OUT : out std_logic_vector(CHANNEL_NUMBER-1 downto 0); +-- trigger window settings + TRG_WIN_PRE_IN : in std_logic_vector(10 downto 0); + TRG_WIN_POST_IN : in std_logic_vector(10 downto 0); + TRG_WIN_EN_IN : in std_logic; +-- from the trigger handler + TRG_WIN_END_TDC_IN : in std_logic; + TRG_WIN_END_RDO_IN : in std_logic; + TRG_TDC_IN : in std_logic; + TRG_TIME_IN : in std_logic_vector(38 downto 0); + MISSING_REF_TIME_IN : in std_logic; +-- miscellaneous + LIGHT_MODE_IN : in std_logic; + DEBUG_MODE_EN_IN : in std_logic; + INFO_IN : in TIMERS; + STATISTICS_OUT : out std_logic_vector_array_24(0 to 15); + READOUT_DEBUG : out std_logic_vector(31 downto 0) + ); +end entity Readout_record; + +architecture behavioral of Readout_record is + +------------------------------------------------------------------------------- +-- Signal Declarations +------------------------------------------------------------------------------- + + -- trigger window + signal trg_win_pre : unsigned(10 downto 0); + signal trg_win_post : unsigned(10 downto 0); + signal trg_time : std_logic_vector(38 downto 0); + signal TW_pre : std_logic_vector(38 downto 0); + signal TW_post : std_logic_vector(38 downto 0); + signal trg_win_l : std_logic; + signal trg_win_r : std_logic; + signal start_trg_win_cnt : std_logic := '0'; + signal start_trg_win_cnt_200_p : std_logic; + signal trg_win_cnt : std_logic_vector(11 downto 0); + signal trg_win_end_200 : std_logic := '0'; + signal trg_win_end_200_p : std_logic; + signal trg_win_end_100_p : std_logic; + signal trg_win_end_100_r : std_logic; + signal trg_win_end_100_2r : std_logic; + signal trg_win_end_100_3r : std_logic; + signal trg_win_end_100_4r : std_logic; + -- channel signals + signal ch_data_r : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + signal ch_data_2r : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + signal ch_data_3r : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + signal ch_data_4r : std_logic_vector(31 downto 0); + signal ch_hit_time : std_logic_vector(38 downto 0); + signal ch_epoch_cntr : std_logic_vector(27 downto 0); + signal buffer_transfer_done : std_logic; + signal buffer_transfer_done_r : std_logic; + signal buffer_transfer_done_2r : std_logic; + -- readout fsm + type FSM_READ is (IDLE, WAIT_FOR_TRG_WIND_END, RD_CH, WAIT_FOR_DATA_FINISHED, WAIT_FOR_LVL1_TRG_A, + WAIT_FOR_LVL1_TRG_B, WAIT_FOR_LVL1_TRG_C, SEND_STATUS, SEND_TRG_RELEASE_A, + SEND_TRG_RELEASE_B, SEND_TRG_RELEASE_C, SEND_TRG_RELEASE_D, WAIT_FOR_BUFFER_TRANSFER); + signal RD_CURRENT : FSM_READ := IDLE; + signal RD_NEXT : FSM_READ; + type FSM_WRITE is (IDLE, WR_CH, WAIT_A, WAIT_B, WAIT_C, WAIT_D); + signal WR_CURRENT : FSM_WRITE := IDLE; + signal WR_NEXT : FSM_WRITE; + signal start_trg_win_cnt_fsm : std_logic; + signal rd_fsm_debug_fsm : std_logic_vector(3 downto 0); + signal wr_fsm_debug_fsm : std_logic_vector(3 downto 0); + signal rd_en_fsm : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal data_finished_fsm : std_logic; + signal wr_finished_fsm : std_logic; + signal trg_release_fsm : std_logic; + signal wr_header_fsm : std_logic; + signal wr_trailer_fsm : std_logic; + signal wr_ch_data_fsm : std_logic; + signal wr_status_fsm : std_logic; + signal missing_ref_time_fsm : std_logic; + signal missing_ref_time : std_logic; + signal invalid_trg_fsm : std_logic; + signal invalid_trg : std_logic; + signal unknown_trg_fsm : std_logic; + signal unknown_trg : std_logic; + signal fifo_nr_rd_fsm : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_fsm : integer range 0 to CHANNEL_NUMBER := 0; + signal buf_delay_fsm : integer range 0 to 63 := 0; + signal buf_delay : integer range 0 to 63 := 0; + signal idle_fsm : std_logic; + signal readout_fsm : std_logic; + signal wait_fsm : std_logic; + -- fifo number + type Std_Logic_8_array is array (0 to 8) of std_logic_vector(3 downto 0); + signal empty_channels : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + signal fifo_nr_rd : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_r : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_2r : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_wr_3r : integer range 0 to CHANNEL_NUMBER := 0; + -- fifo read + signal rd_en : std_logic_vector(CHANNEL_NUMBER-1 downto 0); + -- data mux + signal start_write : std_logic := '0'; + signal wr_header : std_logic; + signal wr_ch_data : std_logic; + signal wr_ch_data_r : std_logic; + signal wr_status : std_logic; + signal wr_trailer : std_logic; + signal wr_info : std_logic; + signal wr_time : std_logic; + signal wr_epoch : std_logic; + signal stop_status : std_logic; + -- to endpoint + signal data_out_r : std_logic_vector(31 downto 0); + signal data_wr_r : std_logic; + signal data_finished : std_logic; + signal wr_finished : std_logic; + signal trg_release : std_logic; + signal trg_statusbit : std_logic_vector(31 downto 0) := (others => '0'); + -- statistics + signal compile_time : std_logic_vector(31 downto 0); + signal trg_number : unsigned(23 downto 0) := (others => '0'); + signal release_number : unsigned(23 downto 0) := (others => '0'); + signal valid_tmg_trg_number : unsigned(23 downto 0) := (others => '0'); + signal valid_NOtmg_trg_number : unsigned(23 downto 0) := (others => '0'); + signal invalid_trg_number : unsigned(23 downto 0) := (others => '0'); + signal multi_tmg_trg_number : unsigned(23 downto 0) := (others => '0'); + signal spurious_trg_number : unsigned(23 downto 0) := (others => '0'); + signal wrong_readout_number : unsigned(23 downto 0) := (others => '0'); + signal spike_number : unsigned(23 downto 0) := (others => '0'); + signal timeout_number : unsigned(23 downto 0) := (others => '0'); + signal total_empty_channel : unsigned(23 downto 0) := (others => '0'); + signal idle_time : unsigned(23 downto 0) := (others => '0'); + signal readout_time : unsigned(23 downto 0) := (others => '0'); + signal wait_time : unsigned(23 downto 0) := (others => '0'); + signal finished_number : unsigned(23 downto 0) := (others => '0'); + signal valid_timing_trg_p : std_logic; + signal valid_notiming_trg_p : std_logic; + signal invalid_trg_p : std_logic; + signal multi_tmg_trg_p : std_logic; + signal spurious_trg_p : std_logic; + signal spike_detected_p : std_logic; + signal timeout_detected_p : std_logic; + signal idle_time_up : std_logic; + signal readout_time_up : std_logic; + signal wait_time_up : std_logic; + signal wrong_readout_up : std_logic; + signal finished : std_logic; + -- control + signal sync_q : std_logic_vector((CHANNEL_NUMBER-2)*3+2 downto 0); + signal isNoHit : std_logic := '1'; + signal isNoHit_r : std_logic := '1'; + signal isCalTrig : std_logic := '0'; + signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 1); + -- debug + signal header_error_bits : std_logic_vector(15 downto 0); + signal trailer_trg_type : std_logic_vector(3 downto 0); + signal trailer_trg_code : std_logic_vector(7 downto 0); + signal trailer_error_bits : std_logic_vector(15 downto 0); + signal rd_fsm_debug : std_logic_vector(3 downto 0); + signal rd_fsm_debug_r : std_logic_vector(3 downto 0); + signal history_rd_fsm : std_logic_vector(31 downto 0) := (others => '0'); + signal wr_fsm_debug : std_logic_vector(3 downto 0); + signal wr_fsm_debug_r : std_logic_vector(3 downto 0); + signal history_wr_fsm : std_logic_vector(31 downto 0) := (others => '0'); + signal any_hit : std_logic := '0'; + +begin -- behavioral + + trg_win_pre <= unsigned(TRG_WIN_PRE_IN); + trg_win_post <= unsigned(TRG_WIN_POST_IN); + +------------------------------------------------------------------------------- +-- Trigger window +------------------------------------------------------------------------------- +-- Trigger window borders + TrigWinCalculation : process (CLK_100) + begin + if rising_edge(CLK_100) then + TW_pre <= std_logic_vector(unsigned(trg_time)-trg_win_pre); + TW_post <= std_logic_vector(unsigned(trg_time)+trg_win_post); + end if; + end process TrigWinCalculation; + +-- Trigger Time Determination + DefineTriggerTime : process (CLK_200) + begin + if rising_edge(CLK_200) then + if RESET_200 = '1' then + trg_time <= (others => '0'); + elsif TRG_TDC_IN = '1' then + trg_time <= TRG_TIME_IN; + end if; + end if; + end process DefineTriggerTime; + +-- Channel Hit Time Determination + ChannelHitTime : process (CLK_100) + begin + if rising_edge(CLK_100) then + if ch_data_r(fifo_nr_wr)(35 downto 32) = x"1" and ch_data_r(fifo_nr_wr)(31 downto 29) = "011" then + ch_epoch_cntr <= ch_data_r(fifo_nr_wr)(27 downto 0); + end if; + + if ch_data_r(fifo_nr_wr)(35 downto 32) = x"1" and ch_data_r(fifo_nr_wr)(31) = '1' then + ch_hit_time <= ch_epoch_cntr & ch_data_r(fifo_nr_wr)(10 downto 0); + elsif ch_data_r(fifo_nr_wr)(35 downto 32) = x"1" and ch_data_r(fifo_nr_wr)(31 downto 29) = "011" then + ch_hit_time <= (others => '0'); + end if; + end if; + end process ChannelHitTime; + +-- Controls if the data coming from the channel is greater than the trigger window pre-edge + Check_Trigger_Win_Left : process (CLK_100) + begin + if rising_edge(CLK_100) then + if unsigned(TW_pre) <= unsigned(ch_hit_time) then + trg_win_l <= '1'; + else + trg_win_l <= '0'; + end if; + end if; + end process Check_Trigger_Win_Left; + +-- Controls if the data coming from the channel is smaller than the trigger window post-edge + Check_Trigger_Win_Right : process (CLK_100) + begin + if rising_edge(CLK_100) then + if unsigned(ch_hit_time) <= unsigned(TW_post) then + trg_win_r <= '1'; + else + trg_win_r <= '0'; + end if; + end if; + end process Check_Trigger_Win_Right; + +------------------------------------------------------------------------------- +-- Readout +------------------------------------------------------------------------------- +-- Readout fsm + RD_FSM_CLK : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_100 = '1' then + RD_CURRENT <= IDLE; + missing_ref_time <= '0'; + invalid_trg <= '0'; + unknown_trg <= '0'; + fifo_nr_rd <= 0; + else + RD_CURRENT <= RD_NEXT; + rd_en <= rd_en_fsm; + wr_header <= wr_header_fsm; + wr_trailer <= wr_trailer_fsm; + wr_status <= wr_status_fsm; + data_finished <= data_finished_fsm; + trg_release <= trg_release_fsm; + missing_ref_time <= missing_ref_time_fsm; + buf_delay <= buf_delay_fsm; + invalid_trg <= invalid_trg_fsm; + unknown_trg <= unknown_trg_fsm; + idle_time_up <= idle_fsm; + readout_time_up <= readout_fsm; + wait_time_up <= wait_fsm; + fifo_nr_rd <= fifo_nr_rd_fsm; + rd_fsm_debug <= rd_fsm_debug_fsm; + buffer_transfer_done <= and_all(CH_EMPTY_IN); + buffer_transfer_done_r <= buffer_transfer_done; + buffer_transfer_done_2r <= buffer_transfer_done_r; + end if; + end if; + end process RD_FSM_CLK; + READ_EN_OUT <= rd_en; + + RD_FSM_PROC : process (RD_CURRENT, READOUT_RX, stop_status, DEBUG_MODE_EN_IN, fifo_nr_rd, + TRG_WIN_END_RDO_IN, buf_delay, CH_EMPTY_IN, buffer_transfer_done_2r, + MISSING_REF_TIME_IN, isNoHit_r, missing_ref_time, invalid_trg, unknown_trg) + + begin + + RD_NEXT <= RD_CURRENT; + rd_en_fsm <= (others => '0'); + wr_header_fsm <= '0'; + wr_trailer_fsm <= '0'; + wr_status_fsm <= '0'; + data_finished_fsm <= '0'; + trg_release_fsm <= '0'; + missing_ref_time_fsm <= missing_ref_time; + invalid_trg_fsm <= invalid_trg; + unknown_trg_fsm <= unknown_trg; + idle_fsm <= '0'; + readout_fsm <= '0'; + wait_fsm <= '0'; + buf_delay_fsm <= 0; + fifo_nr_rd_fsm <= fifo_nr_rd; + rd_fsm_debug_fsm <= x"0"; + + case (RD_CURRENT) is + when IDLE => + if READOUT_RX.valid_timing_trg = '1' then -- physical trigger + RD_NEXT <= WAIT_FOR_TRG_WIND_END; + elsif READOUT_RX.valid_notiming_trg = '1' then + if READOUT_RX.trg_type = x"E" then -- status trigger + wr_header_fsm <= '1'; + RD_NEXT <= SEND_STATUS; + elsif READOUT_RX.trg_type = x"D" then -- tdc calibration trigger + RD_NEXT <= WAIT_FOR_TRG_WIND_END; + else -- the other triggers + RD_NEXT <= SEND_TRG_RELEASE_A; + end if; + elsif READOUT_RX.invalid_trg = '1' then -- invalid trigger + RD_NEXT <= SEND_TRG_RELEASE_A; + invalid_trg_fsm <= '1'; + end if; + idle_fsm <= '1'; + rd_fsm_debug_fsm <= x"1"; + + when WAIT_FOR_TRG_WIND_END => + if TRG_WIN_END_RDO_IN = '1' then + RD_NEXT <= WAIT_FOR_BUFFER_TRANSFER; + if MISSING_REF_TIME_IN = '1' or isNoHit_r = '0' then + wr_header_fsm <= '1'; + end if; + if MISSING_REF_TIME_IN = '1' then + missing_ref_time_fsm <= '1'; + end if; + end if; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"2"; + + when WAIT_FOR_BUFFER_TRANSFER => -- the data from channel fifo is written to the buffer + if buffer_transfer_done_2r = '0' or buf_delay = 63 then + RD_NEXT <= RD_CH; + else + buf_delay_fsm <= buf_delay+ 1; + end if; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"3"; + + when RD_CH => + if CH_EMPTY_IN(fifo_nr_rd) = '0' then -- read from channel if not empty + rd_en_fsm(fifo_nr_rd) <= '1'; + fifo_nr_rd_fsm <= fifo_nr_rd; + elsif fifo_nr_rd = CHANNEL_NUMBER-1 then -- the last channel + rd_en_fsm(fifo_nr_rd) <= '0'; + if DEBUG_MODE_EN_IN = '1' then -- send status after channel data + RD_NEXT <= SEND_STATUS; + else + RD_NEXT <= WAIT_FOR_LVL1_TRG_A; + end if; + else -- go to the next channel + fifo_nr_rd_fsm <= fifo_nr_rd + 1 after 10 ps; + end if; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"4"; + + when WAIT_FOR_LVL1_TRG_A => -- wait for trigger data valid + if READOUT_RX.data_valid = '1' or READOUT_RX.trg_timeout = '1' then + if READOUT_RX.trg_type /= x"1" and READOUT_RX.trg_type /= x"D" then + unknown_trg_fsm <= '1'; + end if; + RD_NEXT <= SEND_TRG_RELEASE_A; + end if; + wait_fsm <= '1'; + rd_fsm_debug_fsm <= x"6"; + + --when WAIT_FOR_LVL1_TRG_B => + -- RD_NEXT <= WAIT_FOR_LVL1_TRG_C; + -- wait_fsm <= '1'; + -- rd_fsm_debug_fsm <= x"7"; + + --when WAIT_FOR_LVL1_TRG_C => + -- if READOUT_RX.trg_spurious = '1' then + -- wrong_readout_fsm <= '1'; + -- end if; + -- RD_NEXT <= SEND_TRG_RELEASE_A; + -- wait_fsm <= '1'; + -- rd_fsm_debug_fsm <= x"8"; + + when SEND_STATUS => + if stop_status = '1' then + if DEBUG_MODE_EN_IN = '1' then + RD_NEXT <= WAIT_FOR_LVL1_TRG_A; + else + RD_NEXT <= SEND_TRG_RELEASE_A; + end if; + else + wr_status_fsm <= '1'; + end if; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"9"; + + when SEND_TRG_RELEASE_A => + RD_NEXT <= SEND_TRG_RELEASE_B; + wr_trailer_fsm <= '1'; + fifo_nr_rd_fsm <= 0; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"A"; + + when SEND_TRG_RELEASE_B => + RD_NEXT <= SEND_TRG_RELEASE_C; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"A"; + + when SEND_TRG_RELEASE_C => + RD_NEXT <= SEND_TRG_RELEASE_D; + data_finished_fsm <= '1'; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"B"; + + when SEND_TRG_RELEASE_D => + RD_NEXT <= IDLE; + trg_release_fsm <= '1'; + missing_ref_time_fsm <= '0'; + invalid_trg_fsm <= '0'; + unknown_trg_fsm <= '0'; + readout_fsm <= '1'; + rd_fsm_debug_fsm <= x"C"; + + when others => + RD_NEXT <= IDLE; + rd_fsm_debug_fsm <= x"0"; + end case; + end process RD_FSM_PROC; + + + --purpose: FSM for writing data to endpoint buffer + WR_FSM_CLK : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_100 = '1' then + WR_CURRENT <= IDLE; + else + WR_CURRENT <= WR_NEXT; + wr_ch_data <= wr_ch_data_fsm; + fifo_nr_wr <= fifo_nr_wr_fsm; + wr_finished <= wr_finished_fsm; + wr_fsm_debug <= wr_fsm_debug_fsm; + start_write <= or_all(CH_DATA_VALID_IN); + end if; + end if; + end process WR_FSM_CLK; + + WR_FSM : process (WR_CURRENT, fifo_nr_wr, start_write, CH_DATA_VALID_IN, ch_data_2r, + isNoHit_r) + + begin + + WR_NEXT <= WR_CURRENT; + wr_ch_data_fsm <= '0'; + fifo_nr_wr_fsm <= fifo_nr_wr; + wr_finished_fsm <= '0'; + wr_fsm_debug_fsm <= x"0"; + + case (WR_CURRENT) is + when IDLE => + if start_write = '1' then + WR_NEXT <= WR_CH; + end if; + fifo_nr_wr_fsm <= 0; + wr_fsm_debug_fsm <= x"1"; +-- + when WR_CH => + if ch_data_2r(fifo_nr_wr)(35 downto 32) /= x"f" then + if isNoHit_r = '1' then + wr_ch_data_fsm <= '0'; + else + wr_ch_data_fsm <= '1'; + end if; + elsif fifo_nr_wr = CHANNEL_NUMBER-1 then + fifo_nr_wr_fsm <= 0; + wr_finished_fsm <= '1'; + WR_NEXT <= IDLE; + else + fifo_nr_wr_fsm <= fifo_nr_wr + 1; + WR_NEXT <= WAIT_A; + end if; + wr_fsm_debug_fsm <= x"2"; +-- + when WAIT_A => + WR_NEXT <= WAIT_B; + wr_fsm_debug_fsm <= x"3"; +-- + when WAIT_B => + WR_NEXT <= WAIT_C; + wr_fsm_debug_fsm <= x"3"; +-- + when WAIT_C => + WR_NEXT <= WR_CH; --WAIT_D; + wr_fsm_debug_fsm <= x"3"; +-- + when WAIT_D => + WR_NEXT <= WR_CH; + wr_fsm_debug_fsm <= x"3"; +-- + when others => + WR_NEXT <= IDLE; + wr_fsm_debug_fsm <= x"0"; + + end case; + end process WR_FSM; + + fifo_nr_wr_r <= fifo_nr_wr when rising_edge(CLK_100); + fifo_nr_wr_2r <= fifo_nr_wr_r when rising_edge(CLK_100); + fifo_nr_wr_3r <= fifo_nr_wr_2r when rising_edge(CLK_100); + wr_ch_data_r <= wr_ch_data when rising_edge(CLK_100); + +------------------------------------------------------------------------------- +-- Data out mux +------------------------------------------------------------------------------- + isCalibrationTrigger : process (CLK_100) is + begin + if rising_edge(CLK_100) then -- rising clock edge + if trg_release = '1' then + isCalTrig <= '0'; + elsif READOUT_RX.valid_notiming_trg = '1' and READOUT_RX.trg_type = x"D" then + isCalTrig <= '1'; + end if; + end if; + end process isCalibrationTrigger; + + -- Trigger window selection + TriggerWindowElimination : process (CLK_100) + begin + if rising_edge(CLK_100) then + if ch_data_3r(fifo_nr_wr_r)(35 downto 32) = x"1" and ch_data_3r(fifo_nr_wr_r)(31) = '1' then --DATA word + if TRG_WIN_EN_IN = '1' and isCalTrig = '0' then -- trigger window enabled + --elsif (TW_pre(10) = '1' and ref_time_coarse(10) = '0') or (TW_post(10) = '0' and ref_time_coarse(10) = '1') then -- if one of the trigger window edges has an overflow + -- if (trg_win_l = '0' and trg_win_r = '1') or (trg_win_l = '1' and trg_win_r = '0') then + -- ch_data_4r <= ch_data_3r(fifo_nr); + -- data_wr_r <= '1'; + -- else + -- ch_data_4r <= (others => '1'); + -- data_wr_r <= '0'; + -- end if; + if trg_win_l = '1' and trg_win_r = '1' then -- if both of the trigger window edges are in the coarse counter boundries + ch_data_4r <= ch_data_3r(fifo_nr_wr_r)(31 downto 0); + elsif trg_win_r = '0' then -- any hit that might come after the trigger window + ch_data_4r <= (others => '0'); + --else + -- ch_data_4r <= (others => '0'); + end if; + else + ch_data_4r <= ch_data_3r(fifo_nr_wr_r)(31 downto 0); + end if; + else + ch_data_4r <= ch_data_3r(fifo_nr_wr_r)(31 downto 0); + end if; + end if; + end process TriggerWindowElimination; + + + Data_Out_MUX : process (CLK_100) + variable i : integer := 0; + begin + if rising_edge(CLK_100) then + if wr_header = '1' then + --data_out_r <= "001" & "0" & READOUT_RX.trg_type & READOUT_RX.trg_code & header_error_bits; + data_out_r <= "001" & "0" & x"000" & header_error_bits; + stop_status <= '0'; + elsif wr_ch_data_r = '1' then + data_out_r <= ch_data_4r; + stop_status <= '0'; + elsif wr_status = '1' then + case i is + when 0 => data_out_r <= "010" & "00000" & std_logic_vector(trg_number); + when 1 => data_out_r <= "010" & "00001" & std_logic_vector(release_number); + when 2 => data_out_r <= "010" & "00010" & std_logic_vector(valid_tmg_trg_number); + when 3 => data_out_r <= "010" & "00011" & std_logic_vector(valid_NOtmg_trg_number); + when 4 => data_out_r <= "010" & "00100" & std_logic_vector(invalid_trg_number); + when 5 => data_out_r <= "010" & "00101" & std_logic_vector(multi_tmg_trg_number); + when 6 => data_out_r <= "010" & "00110" & std_logic_vector(spurious_trg_number); + when 7 => data_out_r <= "010" & "00111" & std_logic_vector(wrong_readout_number); + when 8 => data_out_r <= "010" & "01000" & std_logic_vector(spike_number); + when 9 => data_out_r <= "010" & "01001" & std_logic_vector(idle_time); + when 10 => data_out_r <= "010" & "01010" & std_logic_vector(wait_time); + when 11 => data_out_r <= "010" & "01011" & std_logic_vector(total_empty_channel); + when 12 => data_out_r <= "010" & "01100" & std_logic_vector(readout_time); + when 13 => data_out_r <= "010" & "01101" & std_logic_vector(timeout_number); + when 14 => data_out_r <= "010" & "01110" & x"000" & INFO_IN.temperature; + when 15 => data_out_r <= "010" & "01111" & x"000000"; --reserved + when 16 => data_out_r <= "010" & "10000" & x"00" & compile_time(15 downto 0); + stop_status <= '1'; -- set always before the last word to be written + when 17 => data_out_r <= "010" & "10001" & x"00" & compile_time(31 downto 16); + i := -1; + when others => null; + end case; + i := i+1; + elsif wr_trailer = '1' then + data_out_r <= "000" & "0" & trailer_trg_type & trailer_trg_code & trailer_error_bits; + stop_status <= '0'; + else + data_out_r <= (others => '1'); + stop_status <= '0'; + end if; + end if; + compile_time <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)); + end process Data_Out_MUX; + + wr_info <= wr_header or wr_status or wr_trailer when rising_edge(CLK_100); + wr_time <= wr_ch_data_r and ch_data_4r(31) when rising_edge(CLK_100); + wr_epoch <= wr_ch_data_r and not data_out_r(31) and data_out_r(30) and data_out_r(29) and ch_data_4r(31); + + + READOUT_TX.data <= data_out_r when rising_edge(CLK_100); + READOUT_TX.data_write <= wr_info or wr_time or wr_epoch when rising_edge(CLK_100); + READOUT_TX.data_finished <= data_finished when rising_edge(CLK_100); + READOUT_TX.busy_release <= trg_release when rising_edge(CLK_100); + READOUT_TX.statusbits <= trg_statusbit when rising_edge(CLK_100); + trg_statusbit(23) <= READOUT_RX.trg_spurious when rising_edge(CLK_100); + + READOUT_DEBUG(3 downto 0) <= rd_fsm_debug; + READOUT_DEBUG(7 downto 4) <= wr_fsm_debug; + READOUT_DEBUG(8) <= data_wr_r; + READOUT_DEBUG(9) <= finished; + READOUT_DEBUG(10) <= trg_release; + READOUT_DEBUG(16 downto 11) <= data_out_r(27 downto 22); + READOUT_DEBUG(31 downto 17) <= (others => '0'); + + -- Error, warning bits set in the header + + header_error_bits(0) <= or_all(CH_ALMOST_FULL_IN); + header_error_bits(15 downto 1) <= (others => '0'); + + -- Error, warning bits set in the trailer + trailer_error_bits(0) <= missing_ref_time; -- info from the triggerhandler + trailer_error_bits(1) <= READOUT_RX.trg_spurious; -- if there is a wrong readout because of a spurious timing trigger + trailer_error_bits(2) <= invalid_trg; -- if there is an invalid trigger + trailer_error_bits(3) <= READOUT_RX.trg_missing; -- if the trigger handler detects no reference time signal + trailer_error_bits(4) <= READOUT_RX.trg_multiple; -- if there is multiple triggers + trailer_error_bits(5) <= READOUT_RX.trg_spike; -- if there is spikes + trailer_error_bits(6) <= READOUT_RX.trg_timeout; -- if there is a timeout signal from the endpoint + trailer_error_bits(7) <= unknown_trg; -- if there is an unknown timing trigger + trailer_error_bits(15 downto 8) <= (others => '0'); + + TrailerTriggerInfo : process (CLK_100) is + begin + if rising_edge(CLK_100) then -- rising clock edge + if READOUT_RX.data_valid = '1' or READOUT_RX.trg_timeout = '1' then + trailer_trg_type <= READOUT_RX.trg_type; + trailer_trg_code <= READOUT_RX.trg_code; + end if; + end if; + end process TrailerTriggerInfo; + +------------------------------------------------------------------------------- +-- Control bits +------------------------------------------------------------------------------- + --purpose: Hit Signal Synchroniser + HitSignalSync : for i in 0 to CHANNEL_NUMBER-2 generate + sync_q(i*3) <= HIT_IN(i+1) when rising_edge(CLK_100); + --sync_q(i*3+1) <= sync_q(i*3); -- when rising_edge(CLK_100); + --sync_q(i*3+2) <= sync_q(i*3+1); -- when rising_edge(CLK_100); + hit_in_i(i+1) <= HIT_IN(i+1); --sync_q(i*3+2); + end generate HitSignalSync; + + any_hit <= or_all(hit_in_i); + + CheckHitStatus : process (CLK_100) is + begin + if rising_edge(CLK_100) then -- rising clock edge + if LIGHT_MODE_IN = '0' or TRG_WIN_EN_IN = '1' then + isNoHit <= '0'; + isNoHit_r <= '0'; + elsif READOUT_RX.valid_timing_trg = '1' then + isNoHit <= '1'; + isNoHit_r <= isNoHit; + elsif or_all(hit_in_i) = '1' then + isNoHit <= '0'; + end if; + end if; + end process CheckHitStatus; +------------------------------------------------------------------------------- +-- Debug and statistics words +------------------------------------------------------------------------------- + + edge_to_pulse_1 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => READOUT_RX.valid_timing_trg, + pulse => valid_timing_trg_p); + + edge_to_pulse_2 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => READOUT_RX.valid_notiming_trg, + pulse => valid_notiming_trg_p); + + edge_to_pulse_3 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => READOUT_RX.invalid_trg, + pulse => invalid_trg_p); + + edge_to_pulse_4 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => READOUT_RX.trg_multiple, + pulse => multi_tmg_trg_p); + + edge_to_pulse_5 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => READOUT_RX.trg_spurious, + pulse => spurious_trg_p); + + edge_to_pulse_6 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => READOUT_RX.trg_spike, + pulse => spike_detected_p); + + edge_to_pulse_7 : edge_to_pulse + port map ( + clock => CLK_100, + en_clk => '1', + signal_in => READOUT_RX.trg_timeout, + pulse => timeout_detected_p); + +-- Internal trigger number counter (only valid triggers) + Statistics_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + trg_number <= (others => '0'); + elsif valid_timing_trg_p = '1' or valid_notiming_trg_p = '1' then + trg_number <= trg_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Trigger_Number; + +-- Internal release number counter + Statistics_Release_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + release_number <= (others => '0'); + elsif trg_release = '1' then + release_number <= release_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Release_Number; + +-- Internal valid timing trigger number counter + Statistics_Valid_Timing_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + valid_tmg_trg_number <= (others => '0'); + elsif valid_timing_trg_p = '1' then + valid_tmg_trg_number <= valid_tmg_trg_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Valid_Timing_Trigger_Number; + +-- Internal valid NOtiming trigger number counter + Statistics_Valid_NoTiming_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + valid_NOtmg_trg_number <= (others => '0'); + elsif valid_notiming_trg_p = '1' then + valid_NOtmg_trg_number <= valid_NOtmg_trg_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Valid_NoTiming_Trigger_Number; + +-- Internal invalid trigger number counter + Statistics_Invalid_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + invalid_trg_number <= (others => '0'); + elsif invalid_trg_p = '1' then + invalid_trg_number <= invalid_trg_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Invalid_Trigger_Number; + +-- Internal multi timing trigger number counter + Statistics_Multi_Timing_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + multi_tmg_trg_number <= (others => '0'); + elsif multi_tmg_trg_p = '1' then + multi_tmg_trg_number <= multi_tmg_trg_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Multi_Timing_Trigger_Number; + +-- Internal spurious trigger number counter + Statistics_Spurious_Trigger_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + spurious_trg_number <= (others => '0'); + elsif spurious_trg_p = '1' then + spurious_trg_number <= spurious_trg_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Spurious_Trigger_Number; + + wrongReadoutUp : entity work.risingEdgeDetect + port map ( + CLK => CLK_100, + SIGNAL_IN => READOUT_RX.trg_spurious, + PULSE_OUT => wrong_readout_up); +-- Number of wrong readout becasue of spurious trigger + Statistics_Wrong_Readout_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + wrong_readout_number <= (others => '0'); + elsif wrong_readout_up = '1' then + wrong_readout_number <= wrong_readout_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Wrong_Readout_Number; + +-- Internal spike number counter + Statistics_Spike_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + spike_number <= (others => '0'); + elsif spike_detected_p = '1' then + spike_number <= spike_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Spike_Number; + +-- Internal timeout number counter + Statistics_Timeout_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + timeout_number <= (others => '0'); + elsif timeout_detected_p = '1' then + timeout_number <= timeout_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Timeout_Number; + +-- IDLE time of the TDC readout + Statistics_Idle_Time : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + idle_time <= (others => '0'); + elsif idle_time_up = '1' then + idle_time <= idle_time + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Idle_Time; + +-- Readout and Wait time of the TDC readout + Statistics_Readout_Wait_Time : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + readout_time <= (others => '0'); + wait_time <= (others => '0'); + elsif readout_time_up = '1' then + readout_time <= readout_time + to_unsigned(1, 1); + elsif wait_time_up = '1' then + wait_time <= wait_time + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Readout_Wait_Time; + + -- Number of sent data finished + Statistics_Finished_Number : process (CLK_100) + begin + if rising_edge(CLK_100) then + if RESET_COUNTERS = '1' then + finished_number <= (others => '0'); + elsif data_finished = '1' then --finished = '1' then + finished_number <= finished_number + to_unsigned(1, 1); + end if; + end if; + end process Statistics_Finished_Number; + + HistoryReadDebug : process (CLK_100) + begin + if rising_edge(CLK_100) then + if rd_fsm_debug_r /= rd_fsm_debug then + history_rd_fsm <= history_rd_fsm(27 downto 0) & rd_fsm_debug; + end if; + rd_fsm_debug_r <= rd_fsm_debug; + end if; + end process HistoryReadDebug; + + HistoryWriteDebug : process (CLK_100) + begin + if rising_edge(CLK_100) then + if wr_fsm_debug_r /= wr_fsm_debug then + history_wr_fsm <= history_wr_fsm(27 downto 0) & wr_fsm_debug; + end if; + wr_fsm_debug_r <= wr_fsm_debug; + end if; + end process HistoryWriteDebug; + +------------------------------------------------------------------------------- +-- STATUS REGISTERS BUS +------------------------------------------------------------------------------- + -- statistics + STATISTICS_OUT(0) <= std_logic_vector(trg_number); + STATISTICS_OUT(1) <= std_logic_vector(valid_tmg_trg_number); + STATISTICS_OUT(2) <= std_logic_vector(valid_NOtmg_trg_number); + STATISTICS_OUT(3) <= std_logic_vector(invalid_trg_number); + STATISTICS_OUT(4) <= std_logic_vector(multi_tmg_trg_number); + STATISTICS_OUT(5) <= std_logic_vector(spurious_trg_number); + STATISTICS_OUT(6) <= std_logic_vector(wrong_readout_number); + STATISTICS_OUT(7) <= std_logic_vector(spike_number); + STATISTICS_OUT(8) <= std_logic_vector(idle_time); + STATISTICS_OUT(9) <= std_logic_vector(wait_time); + STATISTICS_OUT(10) <= std_logic_vector(total_empty_channel); + STATISTICS_OUT(11) <= std_logic_vector(release_number); + STATISTICS_OUT(12) <= std_logic_vector(readout_time); + STATISTICS_OUT(13) <= std_logic_vector(timeout_number); + STATISTICS_OUT(14) <= std_logic_vector(finished_number); + STATISTICS_OUT(15) <= (others => '0'); + +-- readout debug history + --STATUS_REGISTERS_BUS_OUT(19) <= history_rd_fsm; + --STATUS_REGISTERS_BUS_OUT(20) <= history_wr_fsm; + + +------------------------------------------------------------------------------- +-- Registering +------------------------------------------------------------------------------- + ch_data_r <= CH_DATA_IN when rising_edge(CLK_100); + ch_data_2r <= ch_data_r when rising_edge(CLK_100); + ch_data_3r <= ch_data_2r when rising_edge(CLK_100); + +end behavioral; diff --git a/releases/tdc_v2.3/TriggerHandler_noDecode.vhd b/releases/tdc_v2.3/TriggerHandler_noDecode.vhd new file mode 100644 index 0000000..2c3a00e --- /dev/null +++ b/releases/tdc_v2.3/TriggerHandler_noDecode.vhd @@ -0,0 +1,320 @@ +------------------------------------------------------------------------------- +-- Title : TriggerHandler +------------------------------------------------------------------------------- +-- File : TriggerHandler.vhd +-- Author : Cahit Ugur c.ugur@gsi.de +-- Created : 2013-03-13 +-- Last update: 2016-03-07 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; + +entity TriggerHandler is + generic ( + TRIGGER_NUM : integer := 2; -- number of trigger signals sent + PHYSICAL_EVENT_TRG_NUM : integer := 0); -- physical event trigger input number for the trigger window calculations + port ( + CLK_TRG : in std_logic; -- trigger clock domain + CLK_RDO : in std_logic; -- readout clock domain + CLK_TDC : in std_logic; -- tdc clock domain + RESET_TRG : in std_logic; + RESET_RDO : in std_logic; + RESET_TDC : in std_logic; + VALID_TIMING_TRG_IN : in std_logic; + VALID_NOTIMING_TRG_IN : in std_logic; + TRG_TYPE_IN : in std_logic_vector(3 downto 0); + TRG_RELEASE_IN : in std_logic; + TRG_IN : in std_logic_vector(TRIGGER_NUM-1 downto 0); + TRG_RDO_OUT : out std_logic_vector(TRIGGER_NUM-1 downto 0); + TRG_TDC_OUT : out std_logic_vector(TRIGGER_NUM-1 downto 0); + TRG_WIN_EN_IN : in std_logic; + TRG_WIN_POST_IN : in unsigned(10 downto 0); + TRG_WIN_END_RDO_OUT : out std_logic; + TRG_WIN_END_TDC_OUT : out std_logic; + MISSING_REF_TIME_OUT : out std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0); + TRG_TIME_OUT : out std_logic_vector(38 downto 0) := (others => '0'); + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + +end entity TriggerHandler; + +architecture behavioral of TriggerHandler is + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of Behavioral : architecture is "TriggerHandler_group"; + + -- trigger signals + signal trg_in_r : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trg_in_2r : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trg_in_3r : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trg_pulse_trg : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trg_pulse_rdo : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trg_pulse_tdc : std_logic_vector(TRIGGER_NUM-1 downto 0); + signal trg_length : unsigned_array_5(TRIGGER_NUM-1 downto 0); + signal trg_release_200 : std_logic; + signal valid_timing_200 : std_logic; + signal valid_notiming_200 : std_logic; + signal valid_trigger_flag : std_logic := '0'; + -- trigger window signals + type TrgWinCounter_FSM is (IDLE, COUNT, COUNT_CALIBRATION, VALIDATE_TRIGGER, WIN_END, + MISSING_REFERENCE_TIME, WAIT_NEXT_TRIGGER); + signal STATE_TW_CURRENT : TrgWinCounter_FSM; + signal STATE_TW_NEXT : TrgWinCounter_FSM; + signal trg_win_cnt_f : unsigned(11 downto 0); + signal trg_win_cnt : unsigned(11 downto 0); + signal trg_win_end_f : std_logic; + signal trg_win_end_tdc : std_logic; + signal trg_win_end_rdo : std_logic; + signal missing_ref_time_f : std_logic; + signal missing_ref_time_tdc : std_logic; + signal missing_ref_time_rdo : std_logic; + signal trg_time : std_logic_vector(38 downto 0) := (others => '0'); + signal trg_win_state_debug_f : std_logic_vector(3 downto 0); + + +begin -- architecture behavioral + + -- the trigger signals have to be synced + trg_in_r <= TRG_IN when rising_edge(CLK_TDC); + trg_in_2r <= trg_in_r when rising_edge(CLK_TDC); + trg_in_3r <= trg_in_2r when rising_edge(CLK_TDC); + + GEN_TRIGGER : for i in 0 to TRIGGER_NUM-1 generate + Validation : process (CLK_TDC) + begin + if rising_edge(CLK_TDC) then + + -- calculate trigger length + if trg_in_3r(i) = '0' then + trg_length(i) <= (others => '0'); + else + trg_length(i) <= trg_length(i) + to_unsigned(1, 5); + end if; + + -- accept trigger if it is longer than 100 ns + if RESET_TDC = '1' then + trg_pulse_tdc(i) <= '0'; + elsif trg_length(i) = to_unsigned(20, 5) then + trg_pulse_tdc(i) <= '1'; + else + trg_pulse_tdc(i) <= '0'; + end if; + + end if; + end process Validation; + end generate GEN_TRIGGER; + + -- sync the strobes to the readout clock domain + GEN_TDC : for i in 0 to TRIGGER_NUM-1 generate + ThePulseSync : pulse_sync + port map ( + CLK_A_IN => CLK_TDC, + RESET_A_IN => RESET_TDC, + PULSE_A_IN => trg_pulse_tdc(i), + CLK_B_IN => CLK_RDO, + RESET_B_IN => RESET_RDO, + PULSE_B_OUT => trg_pulse_rdo(i)); + end generate GEN_TDC; + + TRG_RDO_OUT <= trg_pulse_rdo when rising_edge(CLK_RDO); + TRG_TDC_OUT <= trg_pulse_tdc when rising_edge(CLK_TDC); + + ValidateTrigger : process (CLK_TDC) is + begin + if rising_edge(CLK_TDC) then -- rising clock edge + if RESET_TDC = '1' then + valid_trigger_flag <= '0'; + elsif valid_timing_200 = '1' then + valid_trigger_flag <= '1'; + elsif trg_release_200 = '1' then + valid_trigger_flag <= '0'; + end if; + end if; + end process ValidateTrigger; + + TriggerReleaseSync : entity work.pulse_sync + port map ( + CLK_A_IN => CLK_RDO, + RESET_A_IN => RESET_RDO, + PULSE_A_IN => TRG_RELEASE_IN, + CLK_B_IN => CLK_TDC, + RESET_B_IN => RESET_TDC, + PULSE_B_OUT => trg_release_200); + + ValidTriggerSync : entity work.pulse_sync + port map ( + CLK_A_IN => CLK_RDO, + RESET_A_IN => RESET_RDO, + PULSE_A_IN => VALID_TIMING_TRG_IN, + CLK_B_IN => CLK_TDC, + RESET_B_IN => RESET_TDC, + PULSE_B_OUT => valid_timing_200); + + ValidNoTriggerSync : entity work.pulse_sync + port map ( + CLK_A_IN => CLK_RDO, + RESET_A_IN => RESET_RDO, + PULSE_A_IN => VALID_NOTIMING_TRG_IN, + CLK_B_IN => CLK_TDC, + RESET_B_IN => RESET_TDC, + PULSE_B_OUT => valid_notiming_200); + +------------------------------------------------------------------------------- +-- Trigger Window State Machine +------------------------------------------------------------------------------- + FSM_TRIGGER_WINDOW_SEQUENTIAL : process (CLK_TDC) is + begin + -- Outputs to be registered + if rising_edge(CLK_TDC) then -- rising clock edge + if RESET_TDC = '1' then + STATE_TW_CURRENT <= IDLE; + else + STATE_TW_CURRENT <= STATE_TW_NEXT; + trg_win_cnt <= trg_win_cnt_f; + trg_win_end_tdc <= trg_win_end_f; + missing_ref_time_tdc <= missing_ref_time_f; + end if; + end if; + -- Outputs not to be registered + end process FSM_TRIGGER_WINDOW_SEQUENTIAL; + DEBUG_OUT(19 downto 0) <= (others => '0'); + DEBUG_OUT(23 downto 20) <= trg_win_state_debug_f when rising_edge(CLK_RDO); + DEBUG_OUT(31 downto 24) <= (others => '0'); + + FSM_TRIGGER_WINDOW_COMBINATIONAL : process (STATE_TW_CURRENT, trg_in_3r, TRG_WIN_EN_IN, + valid_notiming_200, TRG_TYPE_IN, trg_win_cnt, + TRG_WIN_POST_IN, valid_trigger_flag, trg_release_200) is + begin + -- Default values + STATE_TW_NEXT <= STATE_TW_CURRENT; + trg_win_cnt_f <= x"00a"; + trg_win_end_f <= '0'; + missing_ref_time_f <= '0'; + trg_win_state_debug_f <= x"0"; + + case STATE_TW_CURRENT is + when IDLE => + if trg_in_3r(0) = '1' then + if TRG_WIN_EN_IN = '1' then + STATE_TW_NEXT <= COUNT; + else + STATE_TW_NEXT <= COUNT; +-- STATE_TW_NEXT <= VALIDATE_TRIGGER; + end if; + elsif valid_notiming_200 = '1' then + if TRG_TYPE_IN = x"D" then + STATE_TW_NEXT <= COUNT_CALIBRATION; + else + STATE_TW_NEXT <= WAIT_NEXT_TRIGGER; + end if; + elsif valid_timing_200 = '1' then + STATE_TW_NEXT <= MISSING_REFERENCE_TIME; + else + STATE_TW_NEXT <= IDLE; + end if; + trg_win_state_debug_f <= x"1"; + + when COUNT => + if trg_win_cnt(10 downto 0) = TRG_WIN_POST_IN then + STATE_TW_NEXT <= VALIDATE_TRIGGER; + else + STATE_TW_NEXT <= COUNT; + end if; + trg_win_cnt_f <= trg_win_cnt + to_unsigned(1, 12); + trg_win_state_debug_f <= x"3"; + + when COUNT_CALIBRATION => + if trg_win_cnt(6) = '1' then + STATE_TW_NEXT <= WIN_END; + else + STATE_TW_NEXT <= COUNT_CALIBRATION; + end if; + trg_win_cnt_f <= trg_win_cnt + to_unsigned(1, 12); + trg_win_state_debug_f <= x"4"; + + when VALIDATE_TRIGGER => + if valid_trigger_flag = '1' then + STATE_TW_NEXT <= WIN_END; + else + STATE_TW_NEXT <= VALIDATE_TRIGGER; + end if; + trg_win_end_f <= '0'; + trg_win_state_debug_f <= x"5"; + + when WIN_END => + STATE_TW_NEXT <= WAIT_NEXT_TRIGGER; + trg_win_end_f <= '1'; + trg_win_state_debug_f <= x"6"; + + when MISSING_REFERENCE_TIME => + STATE_TW_NEXT <= WAIT_NEXT_TRIGGER; + trg_win_end_f <= '1'; + missing_ref_time_f <= '1'; + trg_win_state_debug_f <= x"7"; + + when WAIT_NEXT_TRIGGER => + if trg_release_200 = '1' then + STATE_TW_NEXT <= IDLE; + else + STATE_TW_NEXT <= WAIT_NEXT_TRIGGER; + end if; + trg_win_end_f <= '0'; + trg_win_state_debug_f <= x"8"; + + when others => + STATE_TW_NEXT <= IDLE; + trg_win_state_debug_f <= x"0"; + end case; + end process FSM_TRIGGER_WINDOW_COMBINATIONAL; + + -- syn trg window end strobe to readout clock domain + TrgWinEndPulseSync : pulse_sync + port map ( + CLK_A_IN => CLK_TDC, + RESET_A_IN => RESET_TDC, + PULSE_A_IN => trg_win_end_tdc, + CLK_B_IN => CLK_RDO, + RESET_B_IN => RESET_RDO, + PULSE_B_OUT => trg_win_end_rdo); + + TRG_WIN_END_TDC_OUT <= trg_win_end_tdc; + TRG_WIN_END_RDO_OUT <= trg_win_end_rdo; + + -- syn missing reference time strobe to readout clock domain + MissRefTimePulseSync : pulse_sync + port map ( + CLK_A_IN => CLK_TDC, + RESET_A_IN => RESET_TDC, + PULSE_A_IN => missing_ref_time_tdc, + CLK_B_IN => CLK_RDO, + RESET_B_IN => RESET_RDO, + PULSE_B_OUT => missing_ref_time_rdo); + + MISSING_REF_TIME_OUT <= missing_ref_time_rdo; + + TriggerTime : process (CLK_TDC) + begin + if rising_edge(CLK_TDC) then + if trg_in_2r(0) = '1' and trg_in_3r(0) = '0' then + trg_time <= EPOCH_COUNTER_IN & COARSE_COUNTER_IN; + end if; + if trg_pulse_tdc(0) = '1' then + TRG_TIME_OUT <= trg_time; --std_logic_vector(unsigned(trg_time) - to_unsigned(2, 39)); + end if; + end if; + end process TriggerTime; + + +end architecture behavioral; diff --git a/releases/tdc_v2.3/tdc_components.vhd b/releases/tdc_v2.3/tdc_components.vhd index 509382f..8b0835b 100644 --- a/releases/tdc_v2.3/tdc_components.vhd +++ b/releases/tdc_v2.3/tdc_components.vhd @@ -399,7 +399,7 @@ package tdc_components is START_IN : in std_logic; THERMOCODE_IN : in std_logic_vector(303 downto 0); FINISHED_OUT : out std_logic; - BINARY_CODE_OUT : out std_logic_vector(9 downto 0); + DECIMAL_CODE_OUT : out std_logic_vector(9 downto 0); ENCODER_INFO_OUT : out std_logic_vector(1 downto 0); ENCODER_DEBUG : out std_logic_vector(31 downto 0)); end component Encoder_304_Bit; @@ -411,9 +411,11 @@ package tdc_components is START_IN : in std_logic; THERMOCODE_IN : in std_logic_vector(287 downto 0); FINISHED_OUT : out std_logic; - BINARY_CODE_OUT : out std_logic_vector(9 downto 0); - ENCODER_INFO_OUT : out std_logic_vector(1 downto 0); - ENCODER_DEBUG : out std_logic_vector(31 downto 0)); + DECIMAL_CODE_OUT : out std_logic_vector(9 downto 0); + ENCODER_INFO_OUT : out std_logic; + ENCODER_DEBUG : out std_logic_vector(31 downto 0); + CHAIN_VALID_OUT : out std_logic; + CHAIN_DATA_OUT : out std_logic_vector(15 downto 0)); end component Encoder_288_Bit; component hit_mux is