From: Ingo Froehlich Date: Tue, 6 Mar 2018 20:37:21 +0000 (+0100) Subject: new pll, IF X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b99ab3a7048765fce8da1a7df8c8855fdb98bc8c;p=padiwa.git new pll, IF --- diff --git a/cores/pll_in133_out33_133_66.edn b/cores/pll_in133_out33_133_66.edn new file mode 100644 index 0000000..5ab2664 --- /dev/null +++ b/cores/pll_in133_out33_133_66.edn @@ -0,0 +1,313 @@ +(edif pll_in133_out33_133_66 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2018 3 6 21 6 21) + (program "SCUBA" (version "Diamond (64-bit) 3.9.1.119")))) + (comment "/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n pll_in133_out33_133_66 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 133 -fclkop 133 -fclkop_tol 0.0 -fclkos 33.25 -fclkos_tol 1.0 -fclkos2 66.5 -fclkos2_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 0 -trims_r -phases2 0 -phase_cntl STATIC -fb_mode 2 ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell EHXPLLJ + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CLKI + (direction INPUT)) + (port CLKFB + (direction INPUT)) + (port PHASESEL1 + (direction INPUT)) + (port PHASESEL0 + (direction INPUT)) + (port PHASEDIR + (direction INPUT)) + (port PHASESTEP + (direction INPUT)) + (port LOADREG + (direction INPUT)) + (port STDBY + (direction INPUT)) + (port PLLWAKESYNC + (direction INPUT)) + (port RST + (direction INPUT)) + (port RESETM + (direction INPUT)) + (port RESETC + (direction INPUT)) + (port RESETD + (direction INPUT)) + (port ENCLKOP + (direction INPUT)) + (port ENCLKOS + (direction INPUT)) + (port ENCLKOS2 + (direction INPUT)) + (port ENCLKOS3 + (direction INPUT)) + (port PLLCLK + (direction INPUT)) + (port PLLRST + (direction INPUT)) + (port PLLSTB + (direction INPUT)) + (port PLLWE + (direction INPUT)) + (port PLLADDR4 + (direction INPUT)) + (port PLLADDR3 + (direction INPUT)) + (port PLLADDR2 + (direction INPUT)) + (port PLLADDR1 + (direction INPUT)) + (port PLLADDR0 + (direction INPUT)) + (port PLLDATI7 + (direction INPUT)) + (port PLLDATI6 + (direction INPUT)) + (port PLLDATI5 + (direction INPUT)) + (port PLLDATI4 + (direction INPUT)) + (port PLLDATI3 + (direction INPUT)) + (port PLLDATI2 + (direction INPUT)) + (port PLLDATI1 + (direction INPUT)) + (port PLLDATI0 + (direction INPUT)) + (port CLKOP + (direction OUTPUT)) + (port CLKOS + (direction OUTPUT)) + (port CLKOS2 + (direction OUTPUT)) + (port CLKOS3 + (direction OUTPUT)) + (port LOCK + (direction OUTPUT)) + (port INTLOCK + (direction OUTPUT)) + (port REFCLK + (direction OUTPUT)) + (port CLKINTFB + (direction OUTPUT)) + (port DPHSRC + (direction OUTPUT)) + (port PLLACK + (direction OUTPUT)) + (port PLLDATO7 + (direction OUTPUT)) + (port PLLDATO6 + (direction OUTPUT)) + (port PLLDATO5 + (direction OUTPUT)) + (port PLLDATO4 + (direction OUTPUT)) + (port PLLDATO3 + (direction OUTPUT)) + (port PLLDATO2 + (direction OUTPUT)) + (port PLLDATO1 + (direction OUTPUT)) + (port PLLDATO0 + (direction OUTPUT))))) + (cell pll_in133_out33_133_66 + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port CLKI + (direction INPUT)) + (port CLKOP + (direction OUTPUT)) + (port CLKOS + (direction OUTPUT)) + (port CLKOS2 + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance PLLInst_0 + (viewRef view1 + (cellRef EHXPLLJ)) + (property DDRST_ENA + (string "DISABLED")) + (property DCRST_ENA + (string "DISABLED")) + (property MRST_ENA + (string "DISABLED")) + (property PLLRST_ENA + (string "DISABLED")) + (property INTFB_WAKE + (string "DISABLED")) + (property STDBY_ENABLE + (string "DISABLED")) + (property DPHASE_SOURCE + (string "DISABLED")) + (property PLL_USE_WB + (string "DISABLED")) + (property CLKOS3_FPHASE + (string "0")) + (property CLKOS3_CPHASE + (string "0")) + (property CLKOS2_FPHASE + (string "0")) + (property CLKOS2_CPHASE + (string "7")) + (property CLKOS_FPHASE + (string "0")) + (property CLKOS_CPHASE + (string "15")) + (property CLKOP_FPHASE + (string "0")) + (property CLKOP_CPHASE + (string "3")) + (property PLL_LOCK_MODE + (string "0")) + (property CLKOS_TRIM_DELAY + (string "0")) + (property CLKOS_TRIM_POL + (string "RISING")) + (property CLKOP_TRIM_DELAY + (string "0")) + (property CLKOP_TRIM_POL + (string "RISING")) + (property FRACN_DIV + (string "0")) + (property FRACN_ENABLE + (string "DISABLED")) + (property OUTDIVIDER_MUXD2 + (string "DIVD")) + (property PREDIVIDER_MUXD1 + (string "0")) + (property VCO_BYPASS_D0 + (string "DISABLED")) + (property CLKOS3_ENABLE + (string "DISABLED")) + (property FREQUENCY_PIN_CLKOS2 + (string "66.500000")) + (property OUTDIVIDER_MUXC2 + (string "DIVC")) + (property PREDIVIDER_MUXC1 + (string "0")) + (property VCO_BYPASS_C0 + (string "DISABLED")) + (property CLKOS2_ENABLE + (string "ENABLED")) + (property FREQUENCY_PIN_CLKOS + (string "33.250000")) + (property OUTDIVIDER_MUXB2 + (string "DIVB")) + (property PREDIVIDER_MUXB1 + (string "0")) + (property VCO_BYPASS_B0 + (string "DISABLED")) + (property CLKOS_ENABLE + (string "ENABLED")) + (property FREQUENCY_PIN_CLKOP + (string "133.000000")) + (property OUTDIVIDER_MUXA2 + (string "DIVA")) + (property PREDIVIDER_MUXA1 + (string "0")) + (property VCO_BYPASS_A0 + (string "DISABLED")) + (property CLKOP_ENABLE + (string "ENABLED")) + (property FREQUENCY_PIN_CLKI + (string "133.000000")) + (property ICP_CURRENT + (string "8")) + (property LPF_RESISTOR + (string "8")) + (property CLKOS3_DIV + (string "1")) + (property CLKOS2_DIV + (string "8")) + (property CLKOS_DIV + (string "16")) + (property CLKOP_DIV + (string "4")) + (property CLKFB_DIV + (string "1")) + (property CLKI_DIV + (string "4")) + (property FEEDBK_PATH + (string "CLKOS"))) + (net LOCK + (joined + (portRef LOCK (instanceRef PLLInst_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef PLLADDR4 (instanceRef PLLInst_0)) + (portRef PLLADDR3 (instanceRef PLLInst_0)) + (portRef PLLADDR2 (instanceRef PLLInst_0)) + (portRef PLLADDR1 (instanceRef PLLInst_0)) + (portRef PLLADDR0 (instanceRef PLLInst_0)) + (portRef PLLDATI7 (instanceRef PLLInst_0)) + (portRef PLLDATI6 (instanceRef PLLInst_0)) + (portRef PLLDATI5 (instanceRef PLLInst_0)) + (portRef PLLDATI4 (instanceRef PLLInst_0)) + (portRef PLLDATI3 (instanceRef PLLInst_0)) + (portRef PLLDATI2 (instanceRef PLLInst_0)) + (portRef PLLDATI1 (instanceRef PLLInst_0)) + (portRef PLLDATI0 (instanceRef PLLInst_0)) + (portRef PLLWE (instanceRef PLLInst_0)) + (portRef PLLSTB (instanceRef PLLInst_0)) + (portRef PLLRST (instanceRef PLLInst_0)) + (portRef PLLCLK (instanceRef PLLInst_0)) + (portRef ENCLKOS3 (instanceRef PLLInst_0)) + (portRef ENCLKOS2 (instanceRef PLLInst_0)) + (portRef ENCLKOS (instanceRef PLLInst_0)) + (portRef ENCLKOP (instanceRef PLLInst_0)) + (portRef RESETD (instanceRef PLLInst_0)) + (portRef RESETC (instanceRef PLLInst_0)) + (portRef RESETM (instanceRef PLLInst_0)) + (portRef RST (instanceRef PLLInst_0)) + (portRef PLLWAKESYNC (instanceRef PLLInst_0)) + (portRef STDBY (instanceRef PLLInst_0)) + (portRef LOADREG (instanceRef PLLInst_0)) + (portRef PHASESTEP (instanceRef PLLInst_0)) + (portRef PHASEDIR (instanceRef PLLInst_0)) + (portRef PHASESEL1 (instanceRef PLLInst_0)) + (portRef PHASESEL0 (instanceRef PLLInst_0)))) + (net CLKOS2 + (joined + (portRef CLKOS2) + (portRef CLKOS2 (instanceRef PLLInst_0)))) + (net CLKOS + (joined + (portRef CLKOS) + (portRef CLKFB (instanceRef PLLInst_0)) + (portRef CLKOS (instanceRef PLLInst_0)))) + (net CLKOP + (joined + (portRef CLKOP) + (portRef CLKOP (instanceRef PLLInst_0)))) + (net CLKI + (joined + (portRef CLKI) + (portRef CLKI (instanceRef PLLInst_0)))))))) + (design pll_in133_out33_133_66 + (cellRef pll_in133_out33_133_66 + (libraryRef ORCLIB))) +) diff --git a/cores/pll_in133_out33_133_66.ipx b/cores/pll_in133_out33_133_66.ipx new file mode 100644 index 0000000..dc565fd --- /dev/null +++ b/cores/pll_in133_out33_133_66.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/cores/pll_in133_out33_133_66.lpc b/cores/pll_in133_out33_133_66.lpc new file mode 100644 index 0000000..653f4d3 --- /dev/null +++ b/cores/pll_in133_out33_133_66.lpc @@ -0,0 +1,87 @@ +[Device] +Family=machxo3lf +PartType=LCMXO3LF-1300C +PartName=LCMXO3LF-1300C-5BG256C +SpeedGrade=5 +Package=CABGA256 +OperatingCondition=COM +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=pll_in133_out33_133_66 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=03/06/2018 +Time=21:06:21 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +mode=Frequency +CLKI=133 +CLKI_DIV=4 +BW=3.223 +VCO=532.000 +fb_mode=CLKOS +CLKFB_DIV=1 +FRACN_ENABLE=0 +FRACN_DIV=0 +DynamicPhase=STATIC +ClkEnable=0 +Standby=0 +Enable_sel=0 +PLLRst=0 +PLLMRst=0 +ClkOS2Rst=0 +ClkOS3Rst=0 +LockSig=0 +LockStk=0 +WBProt=0 +OPBypass=0 +OPUseDiv=0 +CLKOP_DIV=4 +FREQ_PIN_CLKOP=133 +OP_Tol=0.0 +CLKOP_AFREQ=133.000000 +CLKOP_PHASEADJ=0 +CLKOP_TRIM_POL=Rising +CLKOP_TRIM_DELAY=0 +EnCLKOS=1 +OSBypass=0 +OSUseDiv=0 +CLKOS_DIV=16 +FREQ_PIN_CLKOS=33.25 +OS_Tol=1.0 +CLKOS_AFREQ=33.250000 +CLKOS_PHASEADJ=0 +CLKOS_TRIM_POL=Rising +CLKOS_TRIM_DELAY=0 +EnCLKOS2=1 +OS2Bypass=0 +OS2UseDiv=0 +CLKOS2_DIV=8 +FREQ_PIN_CLKOS2=66.5 +OS2_Tol=0.0 +CLKOS2_AFREQ=66.500000 +CLKOS2_PHASEADJ=0 +EnCLKOS3=0 +OS3Bypass=0 +OS3UseDiv=0 +CLKOS3_DIV=1 +FREQ_PIN_CLKOS3=100 +OS3_Tol=0.0 +CLKOS3_AFREQ= +CLKOS3_PHASEADJ=0 + +[Command] +cmd_line= -w -n pll_in133_out33_133_66 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 133 -fclkop 133 -fclkop_tol 0.0 -fclkos 33.25 -fclkos_tol 1.0 -fclkos2 66.5 -fclkos2_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 0 -trims_r -phases2 0 -phase_cntl STATIC -fb_mode 2 diff --git a/cores/pll_in133_out33_133_66.vhd b/cores/pll_in133_out33_133_66.vhd new file mode 100644 index 0000000..88002bf --- /dev/null +++ b/cores/pll_in133_out33_133_66.vhd @@ -0,0 +1,164 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.1.119 +-- Module Version: 5.7 +--/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n pll_in133_out33_133_66 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 133 -fclkop 133 -fclkop_tol 0.0 -fclkos 33.25 -fclkos_tol 1.0 -fclkos2 66.5 -fclkos2_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 0 -trims_r -phases2 0 -phase_cntl STATIC -fb_mode 2 + +-- Tue Mar 6 21:06:21 2018 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library MACHXO3L; +use MACHXO3L.components.all; +-- synopsys translate_on + +entity pll_in133_out33_133_66 is + port ( + CLKI: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + CLKOS2: out std_logic); +end pll_in133_out33_133_66; + +architecture Structure of pll_in133_out33_133_66 is + + -- internal signal declarations + signal LOCK: std_logic; + signal CLKOS2_t: std_logic; + signal CLKOP_t: std_logic; + signal CLKOS_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VLO + port (Z: out std_logic); + end component; + component EHXPLLJ + generic (INTFB_WAKE : in String; DDRST_ENA : in String; + DCRST_ENA : in String; MRST_ENA : in String; + PLLRST_ENA : in String; DPHASE_SOURCE : in String; + STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String; + OUTDIVIDER_MUXC2 : in String; + OUTDIVIDER_MUXB2 : in String; + OUTDIVIDER_MUXA2 : in String; + PREDIVIDER_MUXD1 : in Integer; + PREDIVIDER_MUXC1 : in Integer; + PREDIVIDER_MUXB1 : in Integer; + PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String; + PLL_LOCK_MODE : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer; + FRACN_ENABLE : in String; FEEDBK_PATH : in String; + CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer; + CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer; + CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer; + CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer; + VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String; + VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String; + CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String; + CLKOS_ENABLE : in String; CLKOP_ENABLE : in String; + CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer; + CLKOS_DIV : in Integer; CLKOP_DIV : in Integer; + CLKFB_DIV : in Integer; CLKI_DIV : in Integer); + port (CLKI: in std_logic; CLKFB: in std_logic; + PHASESEL1: in std_logic; PHASESEL0: in std_logic; + PHASEDIR: in std_logic; PHASESTEP: in std_logic; + LOADREG: in std_logic; STDBY: in std_logic; + PLLWAKESYNC: in std_logic; RST: in std_logic; + RESETM: in std_logic; RESETC: in std_logic; + RESETD: in std_logic; ENCLKOP: in std_logic; + ENCLKOS: in std_logic; ENCLKOS2: in std_logic; + ENCLKOS3: in std_logic; PLLCLK: in std_logic; + PLLRST: in std_logic; PLLSTB: in std_logic; + PLLWE: in std_logic; PLLADDR4: in std_logic; + PLLADDR3: in std_logic; PLLADDR2: in std_logic; + PLLADDR1: in std_logic; PLLADDR0: in std_logic; + PLLDATI7: in std_logic; PLLDATI6: in std_logic; + PLLDATI5: in std_logic; PLLDATI4: in std_logic; + PLLDATI3: in std_logic; PLLDATI2: in std_logic; + PLLDATI1: in std_logic; PLLDATI0: in std_logic; + CLKOP: out std_logic; CLKOS: out std_logic; + CLKOS2: out std_logic; CLKOS3: out std_logic; + LOCK: out std_logic; INTLOCK: out std_logic; + REFCLK: out std_logic; CLKINTFB: out std_logic; + DPHSRC: out std_logic; PLLACK: out std_logic; + PLLDATO7: out std_logic; PLLDATO6: out std_logic; + PLLDATO5: out std_logic; PLLDATO4: out std_logic; + PLLDATO3: out std_logic; PLLDATO2: out std_logic; + PLLDATO1: out std_logic; PLLDATO0: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOS2 : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "66.500000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "33.250000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "133.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "133.000000"; + attribute ICP_CURRENT of PLLInst_0 : label is "8"; + attribute LPF_RESISTOR of PLLInst_0 : label is "8"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLJ + generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED", + MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, + CLKOS2_FPHASE=> 0, CLKOS2_CPHASE=> 7, CLKOS_FPHASE=> 0, + CLKOS_CPHASE=> 15, CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 3, + PLL_LOCK_MODE=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=> 0, + FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD", + PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED", + CLKOS2_ENABLE=> "ENABLED", OUTDIVIDER_MUXB2=> "DIVB", + PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "ENABLED", + OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "DISABLED", + CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, CLKOS2_DIV=> 8, + CLKOS_DIV=> 16, CLKOP_DIV=> 4, CLKFB_DIV=> 1, CLKI_DIV=> 4, + FEEDBK_PATH=> "CLKOS") + port map (CLKI=>CLKI, CLKFB=>CLKOS_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo, + PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, RESETM=>scuba_vlo, + RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo, + ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo, + PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo, + PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo, + PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo, + PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo, + PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo, + PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo, + PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo, + PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, + CLKOS2=>CLKOS2_t, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, + REFCLK=>open, CLKINTFB=>open, DPHSRC=>open, PLLACK=>open, + PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open, + PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open, + PLLDATO1=>open, PLLDATO0=>open); + + CLKOS2 <= CLKOS2_t; + CLKOS <= CLKOS_t; + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library MACHXO3L; +configuration Structure_CON of pll_in133_out33_133_66 is + for Structure + for all:VLO use entity MACHXO3L.VLO(V); end for; + for all:EHXPLLJ use entity MACHXO3L.EHXPLLJ(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on