From: Michael Boehmer Date: Mon, 21 Mar 2022 08:33:46 +0000 (+0100) Subject: Cleanup X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=b9b361b10993c76684242354e9ae5f6140b5613b;p=trbnet.git Cleanup --- diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index d7d1697..914c56a 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -37,11 +37,10 @@ entity med_ecp3_sfp_sync_all_RS is MASTER_CLK_IN : in std_logic; -- recovered RX clock in (only master ports in quad) MASTER_CLK_OUT : out std_logic; -- recovered RX clock out (slave port in quad) QUAD_RST_IN : in std_logic; -- HANDLE WITH CARE - LINK_TX_NULL_IN : in std_logic; -- - LINK_RX_NULL_OUT : out std_logic; -- - SLAVE_ACTIVE_OUT : out std_logic; -- for delaying MPs in hub + LINK_TX_NULL_IN : in std_logic; -- K_NULL reset handling + LINK_RX_NULL_OUT : out std_logic; -- K_NULL reset handling TX_PLL_LOL_OUT : out std_logic; -- status signal of TX PLL - TX_CLK_AVAIL_OUT : out std_logic; -- stable RX recovered clock available + TX_CLK_AVAIL_OUT : out std_logic; -- stable RX recovered clock available on port MASTER_CLK_OUT TX_PCS_RST_IN : in std_logic; -- TX PCS reset signal SYNC_TX_PLL_IN : in std_logic; -- bit0 alignment for TX serializer LINK_TX_READY_IN : in std_logic; -- from TX reset generator @@ -102,7 +101,6 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is signal wap_requested_i : std_logic_vector(15 downto 0); signal wap_req_i : std_logic_vector(3 downto 0); signal wap_req_all : std_logic; --- signal wap_req_all_q : std_logic; signal wap_req_all_q : std_logic_vector(2 downto 0); signal stat_rx_control_i : std_logic_vector(4*32-1 downto 0); @@ -120,27 +118,22 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is type u8_arr is array (0 to 3) of unsigned(7 downto 0); signal cv_cnt, cv_cnt_sys : u8_arr; - signal powerup_ch : std_logic_vector(3 downto 0); signal tx_ref_clk_i : std_logic; - signal tx_rst_i : std_logic_vector(3 downto 0); - - signal rx_rst_word_i : std_logic_vector(4*8-1 downto 0); - signal rx_rst_i : std_logic_vector(3 downto 0); - signal rx_dlm_i : std_logic_vector(3 downto 0); - - signal pll_lol_i : std_logic; - + signal powerup_ch : std_logic_vector(3 downto 0); signal link_rx_ready_i : std_logic_vector(3 downto 0); - signal link_rx_null_i : std_logic_vector(3 downto 0); signal link_tx_null_i : std_logic_vector(3 downto 0); - + signal link_active_i : std_logic_vector(3 downto 0); signal word_sync_i : std_logic_vector(3 downto 0); - signal word_sync_sel : std_logic; - signal link_active_i : std_logic_vector(3 downto 0); + signal rx_rst_word_i : std_logic_vector(4*8-1 downto 0); + signal rx_rst_i : std_logic_vector(3 downto 0); + signal rx_dlm_i : std_logic_vector(3 downto 0); + signal tx_rst_i : std_logic_vector(3 downto 0); + signal pll_lol_i : std_logic; + signal quad_mode : integer range 0 to 100; begin @@ -181,8 +174,7 @@ begin '0'; ------------------------------------------------- --- global reset --- output only if a slave port is available in QUAD +-- K_NULL reset handling ------------------------------------------------- LINK_RX_NULL_OUT <= link_rx_null_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else link_rx_null_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else @@ -203,20 +195,11 @@ begin link_rx_ready_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else link_rx_ready_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else '1'; - -------------------------------------------------- --- -------------------------------------------------- - SLAVE_ACTIVE_OUT <= link_active_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else - link_active_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else - link_active_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else - link_active_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else - '0'; ------------------------------------------------- -- byte/word alignment ------------------------------------------------- - word_sync_sel <= word_sync_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else + WORD_SYNC_OUT <= word_sync_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else word_sync_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else word_sync_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else word_sync_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else @@ -226,8 +209,6 @@ begin word_sync_i(3) when ((quad_mode = 1) and (IS_MODE(3) = c_IS_MASTER)) else '1'; - WORD_SYNC_OUT <= word_sync_sel; - -- if a SP is in the quad, we use the received WORD_SYNC. -- in a MP only configuration, the TX WORD_SYNC is used as reference. @@ -411,6 +392,7 @@ begin tx_sync_qd_c => SYNC_TX_PLL_IN ); + -- workaround for clock domain problem clk_tx_full(0) <= MASTER_CLK_IN; clk_tx_full(1) <= MASTER_CLK_IN; clk_tx_full(2) <= MASTER_CLK_IN; diff --git a/media_interfaces/sync/main_rx_reset_RS.vhd b/media_interfaces/sync/main_rx_reset_RS.vhd index 4e39ed4..ea5a254 100644 --- a/media_interfaces/sync/main_rx_reset_RS.vhd +++ b/media_interfaces/sync/main_rx_reset_RS.vhd @@ -4,8 +4,8 @@ USE IEEE.numeric_std.all; entity main_rx_reset_RS is port ( - CLEAR : in std_logic; - CLK_REF : in std_logic; + CLEAR : in std_logic; -- do not use + CLK_REF : in std_logic; -- usually local oscillator sourced CDR_LOL_IN : in std_logic; CV_IN : in std_logic; LSM_IN : in std_logic; diff --git a/media_interfaces/sync/main_tx_reset_RS.vhd b/media_interfaces/sync/main_tx_reset_RS.vhd index cda5e69..5bbc68d 100644 --- a/media_interfaces/sync/main_tx_reset_RS.vhd +++ b/media_interfaces/sync/main_tx_reset_RS.vhd @@ -6,13 +6,13 @@ USE IEEE.numeric_std.all; entity main_tx_reset_RS is port( - CLEAR : in std_logic; -- async reset, active high - CLK_REF : in std_logic; -- usually RX_REFCLK, not TX_REFCLK! + CLEAR : in std_logic; -- async reset, active high, should not be used! + CLK_REF : in std_logic; -- usually local oscillator sourced TX_PLL_LOL_QD_A_IN : in std_logic; -- QUAD A TX_PLL_LOL_QD_B_IN : in std_logic; -- QUAD B TX_PLL_LOL_QD_C_IN : in std_logic; -- QUAD C TX_PLL_LOL_QD_D_IN : in std_logic; -- QUAD D - TX_CLOCK_AVAIL_IN : in std_logic; -- recovered RX clock available (if needed) + TX_CLOCK_AVAIL_IN : in std_logic; -- suitable TX clock available TX_PCS_RST_CH_C_OUT : out std_logic; -- PCS reset SYNC_TX_QUAD_OUT : out std_logic; -- sync all QUADs to TX bit 0 LINK_TX_READY_OUT : out std_logic; -- TX lane can use used now @@ -44,6 +44,11 @@ architecture main_tx_reset_RS_arch of main_tx_reset_RS is begin +-- This reset handler takes care of enabling all TX SerDes blocks in parallel, +-- independently of RX SerDes blocks. The only difference between master and slave +-- ports is the TX_CLOCK_AVAIL_IN input signal. +-- This will delay the TX SerDes startup until the slave RX port is fully active. + -- all four QUADs need to be ready tx_pll_lol_all <= TX_PLL_LOL_QD_A_IN or TX_PLL_LOL_QD_B_IN or TX_PLL_LOL_QD_C_IN or TX_PLL_LOL_QD_D_IN;