From: Jan Michel Date: Wed, 26 Jul 2017 16:22:11 +0000 (+0200) Subject: Add input monitoring and dummy data to template design X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ba66e79db222a1b1be8e932962ad18f8df3b6c90;p=trb3sc.git Add input monitoring and dummy data to template design --- diff --git a/template/config.vhd b/template/config.vhd index 9bb53f5..7358a6b 100644 --- a/template/config.vhd +++ b/template/config.vhd @@ -23,7 +23,7 @@ package config is constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"60"; --set to 0 for backplane serdes, set to 3 for front SFP serdes - constant SERDES_NUM : integer := 3; + constant SERDES_NUM : integer := 0; constant INCLUDE_UART : integer := c_YES; constant INCLUDE_SPI : integer := c_YES; @@ -31,11 +31,11 @@ package config is constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; --input monitor and trigger generation logic - constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; - constant INCLUDE_STATISTICS : integer := c_NO; - constant TRIG_GEN_INPUT_NUM : integer := 0; - constant TRIG_GEN_OUTPUT_NUM : integer := 0; - constant MONITOR_INPUT_NUM : integer := 0; + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_STATISTICS : integer := c_YES; + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 3; + constant MONITOR_INPUT_NUM : integer := 32; ------------------------------------------------------------------------------ --End of design configuration diff --git a/template/config_compile_frankfurt.pl b/template/config_compile_frankfurt.pl index f3d687d..9de99d5 100644 --- a/template/config_compile_frankfurt.pl +++ b/template/config_compile_frankfurt.pl @@ -1,11 +1,11 @@ TOPNAME => "trb3sc_basic", -lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@hadeb05.gsi.de", -lattice_path => '/d/jspc29/lattice/diamond/3.6_x64', -synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/', -synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", +lattice_path => '/d/jspc29/lattice/diamond/3.8_x64', +synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/', +#synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", # synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", -# synplify_command => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #", + nodelist_file => 'nodelist_frankfurt.txt', diff --git a/template/par.p2t b/template/par.p2t index f72683d..e13de7d 100644 --- a/template/par.p2t +++ b/template/par.p2t @@ -4,7 +4,7 @@ -n 1 -y -s 12 --t 24 +-t 25 -c 1 -e 2 #-g guidefile.ncd diff --git a/template/trb3sc_basic.vhd b/template/trb3sc_basic.vhd index e57c6e2..7b81fb5 100644 --- a/template/trb3sc_basic.vhd +++ b/template/trb3sc_basic.vhd @@ -129,8 +129,8 @@ architecture trb3sc_arch of trb3sc_basic is signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 0); - signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bus_master_out : CTRLBUS_RX; - signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, busrdo_rx, bus_master_out : CTRLBUS_RX; + signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, busrdo_tx, bus_master_in : CTRLBUS_TX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -159,7 +159,12 @@ architecture trb3sc_arch of trb3sc_basic is attribute syn_preserve of bustools_rx : signal is true; attribute syn_keep of bustc_rx : signal is true; attribute syn_preserve of bustc_rx : signal is true; - + + type state_t is (IDLE, WRITE, FINISH, BUSYEND); + signal state : state_t; + signal data_counter, data_amount : unsigned(15 downto 0) := (others => '0'); + + begin --------------------------------------------------------------------------- @@ -201,7 +206,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler IS_SYNC_SLAVE => c_YES ) port map( - CLK_REF_FULL => med2int(0).clk_full, + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, CLK_INTERNAL_FULL => clk_full_osc, SYSCLK => clk_sys, RESET => reset_i, @@ -251,9 +256,9 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record TIMING_TRIGGER_RAW => c_YES, --Configure data handler DATA_INTERFACE_NUMBER => 1, - DATA_BUFFER_DEPTH => 10, + DATA_BUFFER_DEPTH => 13, DATA_BUFFER_WIDTH => 32, - DATA_BUFFER_FULL_THRESH => 2**8, + DATA_BUFFER_FULL_THRESH => 2**12+2**11, TRG_RELEASE_AFTER_DATA => c_YES, HEADER_BUFFER_DEPTH => 9, HEADER_BUFFER_FULL_THRESH => 2**8 @@ -296,9 +301,9 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 3, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, others => 0), + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -311,9 +316,11 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED BUS_RX(1) => bussci_rx, --SCI Serdes BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busrdo_rx, --User config BUS_TX(0) => bustools_tx, BUS_TX(1) => bussci_tx, BUS_TX(2) => bustc_tx, + BUS_TX(3) => busrdo_tx, STAT_DEBUG => open ); @@ -348,9 +355,9 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record ADC_MISO => ADC_DOUT, ADC_CLK => ADC_CLK, --Trigger & Monitor - MONITOR_INPUTS => (others => '0'), - TRIG_GEN_INPUTS => (others => '0'), - TRIG_GEN_OUTPUTS => open, + MONITOR_INPUTS => KEL(32 downto 1),--(others => '0'), + TRIG_GEN_INPUTS => KEL(32 downto 1),--(others => '0'), + TRIG_GEN_OUTPUTS => BACK_GPIO(3 downto 1),--open, --SED SED_ERROR_OUT => sed_error_i, --Slowcontrol @@ -378,7 +385,7 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record RJ_IO <= "0000"; - BACK_GPIO <= (others => 'Z'); +-- BACK_GPIO <= (others => 'Z'); BACK_LVDS <= (others => '0'); BACK_3V3 <= (others => 'Z'); @@ -419,12 +426,12 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record end process; -- TEST_LINE <= med_stat_debug(15 downto 0); + TEST_LINE(15 downto 0) <= debug_clock_reset(15 downto 14) & med2int(0).stat_op(13) & clear_i & reset_i & debug_clock_reset(10 downto 0); - -readout_tx(0).data_finished <= '1'; -readout_tx(0).data_write <= '0'; -readout_tx(0).busy_release <= '1'; - +-- readout_tx(0).data_finished <= '1'; +-- readout_tx(0).data_write <= '0'; +-- readout_tx(0).busy_release <= '1'; +-- -- gen_chains : for i in 1 to 16 generate -- process begin @@ -439,6 +446,60 @@ readout_tx(0).busy_release <= '1'; -- -- end generate; + +THE_RDO_STAT : process begin + wait until rising_edge(clk_sys); + busrdo_tx.ack <= '0'; + busrdo_tx.nack <= '0'; + busrdo_tx.unknown <= '0'; + + if busrdo_rx.write = '1' then + if busrdo_rx.addr = x"0000" then + busrdo_tx.ack <= '1'; + data_amount <= unsigned(busrdo_rx.data(15 downto 0)); + else + busrdo_tx.unknown <= '1'; + end if; + elsif busrdo_rx.read = '1' then + if busrdo_rx.addr = x"0000" then + busrdo_tx.ack <= '1'; + busrdo_tx.data(15 downto 0) <= std_logic_vector(data_amount); + else + busrdo_tx.unknown <= '1'; + end if; + end if; +end process; + +THE_RDO : process begin + wait until rising_edge(clk_sys); + readout_tx(0).busy_release <= '0'; + readout_tx(0).data_write <= '0'; + readout_tx(0).data_finished <= '0'; + + case state is + when IDLE => + if readout_rx.valid_timing_trg = '1' or readout_rx.valid_notiming_trg = '1' then + state <= WRITE; + end if; + if readout_rx.invalid_trg = '1' then + state <= FINISH; + end if; + data_counter <= 0; + when WRITE => + readout_tx(0).data <= timer.microsecond; + readout_tx(0).data_write <= '1'; + data_counter <= data_counter + 1; + if data_counter = data_amount then + state <= FINISH; + end if; + when FINISH => + state <= BUSYEND; + readout_tx(0).data_finished <= '1'; + when BUSYEND => + state <= IDLE; + readout_tx(0).busy_release <= '1'; + end case; +end process; end architecture;