From: Jan Michel <j.michel@gsi.de>
Date: Tue, 28 Jun 2022 14:53:18 +0000 (+0200)
Subject: add reload-on-reset option to trb3sc_tools
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=ba95100ebc9e7c7a781666a1e48b6c8bbcc52b2d;p=trb3sc.git

add reload-on-reset option to trb3sc_tools
---

diff --git a/code/trb3sc_tools.vhd b/code/trb3sc_tools.vhd
index 4c65c92..e9f228b 100644
--- a/code/trb3sc_tools.vhd
+++ b/code/trb3sc_tools.vhd
@@ -9,6 +9,9 @@ library work;
   use work.config.all;
 
 entity trb3sc_tools is
+  generic (
+    HEADER_PAGE_ADDR    : std_logic_vector(15 downto 0) := x"7000"
+    );
   port(
     CLK         : in std_logic;
     RESET       : in std_logic;
@@ -80,6 +83,7 @@ signal flash_cs_s, flash_clk_s, flash_out_s  : std_logic;
 signal debug_rx, debug_tx : std_logic;
 signal debug_status : std_logic_vector(31 downto 0);
 signal additional_reg_i : std_logic_vector(31 downto 0);
+signal control_reg_i    : std_logic_vector(15 downto 0);
 
 begin
 
@@ -92,7 +96,7 @@ begin
       PORT_ADDRESSES   => (0 => x"0000", 1 => x"0400", 2 => x"0480", 3 => x"0500", 4 => x"0600", 
                            5 => x"0180", 6 => x"0f00", 7 => x"0f80", 8 => x"0580", others => x"0000"),
       PORT_ADDR_MASK   => (0 => 9,       1 => 5,       2 => 5,       3 => 2,       4 => 2,       
-                           5 => 4,       6 => 7,       7 => 7,       8 => 0,       others => 0),
+                           5 => 4,       6 => 7,       7 => 7,       8 => 1,       others => 0),
       PORT_MASK_ENABLE => 1
       )
     port map(
@@ -137,6 +141,7 @@ begin
       BUS_TX               => busflash_tx,
       
       DO_REBOOT_IN         => REBOOT_IN,     
+      REBOOT_ON_RESET      => control_reg_i(15),
       PROGRAMN             => PROGRAMN,
       
       SPI_CS_OUT           => flash_cs_i,
@@ -150,6 +155,9 @@ begin
 -- Load Settings from Flash
 ---------------------------------------------------------------------------      
 THE_FLASH_REGS : entity work.load_settings
+  generic map(
+    HEADER_PAGE_ADDR => HEADER_PAGE_ADDR
+    )
   port map(
     CLK        => CLK,
     RST        => RESET,
@@ -388,10 +396,18 @@ proc_add_reg : process begin
   busctrl_tx.unknown <= '0';
   
   if busctrl_rx.read = '1' then
-    busctrl_tx.data(additional_reg_i'left downto 0) <= additional_reg_i;
+    if busctrl_rx.addr(0) = '0' then
+      busctrl_tx.data(additional_reg_i'left downto 0) <= additional_reg_i;
+    else
+      busctrl_tx.data(control_reg_i'left downto 0)    <= control_reg_i;   
+    end if;
     busctrl_tx.ack <= '1';
   elsif busctrl_rx.write = '1' then
-    additional_reg_i <= busctrl_rx.data(additional_reg_i'left downto 0);
+    if busctrl_rx.addr(0) = '0' then
+      additional_reg_i <= busctrl_rx.data(additional_reg_i'left downto 0);
+    else
+      control_reg_i    <= busctrl_rx.data(control_reg_i'left downto 0);
+    end if;
     busctrl_tx.ack <= '1';
   end if;
 end process;