From: Jan Michel Date: Thu, 10 Apr 2014 12:17:04 +0000 (+0200) Subject: first version of sctrl X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=baa7b6ca545201e13c7aeea04c02d79a43795571;p=padiwa.git first version of sctrl --- diff --git a/pulser/padiwa_pulser.vhd b/pulser/padiwa_pulser.vhd index 4c9a780..dc062fe 100644 --- a/pulser/padiwa_pulser.vhd +++ b/pulser/padiwa_pulser.vhd @@ -43,9 +43,14 @@ signal clk_osc : std_logic; signal clk_26 : std_logic; signal led : std_logic_vector(3 downto 0) := "1010"; -signal input_i : std_logic_vector(255 downto 0) := (others => '0'); +signal lcd_data_i : std_logic_vector(255 downto 0) := (others => '0'); signal uart_rx_data : std_logic_vector(31 downto 0); +signal uart_tx_data : std_logic_vector(31 downto 0); +signal uart_addr : std_logic_vector(7 downto 0); +signal bus_read : std_logic; +signal bus_write : std_logic; +signal bus_ready : std_logic; begin @@ -81,15 +86,27 @@ THE_UART : entity work.uart_sctrl UART_TX => SPARE_LINE(2), DATA_OUT => uart_rx_data, - DATA_IN => x"00000000", - WRITE_OUT => open, - READ_OUT => open, - READY_IN => '0', + DATA_IN => uart_tx_data, + ADDR_OUT => uart_addr, + WRITE_OUT => bus_write, + READ_OUT => bus_read, + READY_IN => bus_ready, DEBUG => open ); +PROC_REGISTERS : process begin + wait until rising_edge(clk_i); + if WRITE_IN = '1' then + if uart_addr = x"01" then + lcd_data_i(31 downto 0) <= uart_rx_data; + elsif uart_addr = x"02" then + lcd_data_i(79 downto 64) <= uart_rx_data; + end if; + end if; +end process; + --------------------------------------------------------------------------- -- LCD --------------------------------------------------------------------------- @@ -104,20 +121,26 @@ THE_LCD : entity work.lcd CS => TEST_LINE(12), RST => TEST_LINE(11), - INPUT => input_i, + INPUT => lcd_data_i, LED => open ); -TEST_LINE(7 downto 0) <= x"00"; -TEST_LINE(15 downto 13) <= (others => '0'); + + -input_i(31 downto 0) <= uart_rx_data; + --------------------------------------------------------------------------- -- Other I/O --------------------------------------------------------------------------- + +TEST_LINE(7 downto 0) <= x"00"; +--TEST_LINE(12 downto 8) used for serial interface +TEST_LINE(15 downto 13) <= (others => '0'); + +--the two I/O on the pin-header connected to the USB interface SPARE_LINE(1) <= 'Z'; --C1 spare SPARE_LINE(3) <= 'Z'; --C2 spare diff --git a/source/uart_sctrl.vhd b/source/uart_sctrl.vhd index b3d4fa3..c4b6221 100644 --- a/source/uart_sctrl.vhd +++ b/source/uart_sctrl.vhd @@ -4,7 +4,6 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; -use work.trb_net_components.all; use work.version.all; library machxo2; @@ -20,6 +19,7 @@ entity uart_sctrl is DATA_OUT : out std_logic_vector(31 downto 0); DATA_IN : in std_logic_vector(31 downto 0); + ADDR_OUT : out std_logic_vector(7 downto 0); WRITE_OUT : out std_logic; READ_OUT : out std_logic; READY_IN : in std_logic; @@ -39,6 +39,15 @@ signal rx_ready : std_logic; signal tx_send : std_logic; signal tx_ready : std_logic; +type rx_state_t is (IDLE,ADDR,GET_BYTE0,GET_BYTE1,GET_BYTE2,GET_BYTE3,DO_WRITE,DO_READ,SEND_BYTE0,SEND_BYTE1,SEND_BYTE2); +signal state : rx_state_t; +signal addr : std_logic_vector(7 downto 0) := (others => '0'); +signal word : std_logic_vector(31 downto 0) := (others => '0'); +signal timer : unsigned(25 downto 0) := (others => '0'); +signal timeout : std_logic := '0'; +signal cmd_wr : std_logic := '0'; +signal cmd_rd : std_logic := '0'; + begin @@ -63,9 +72,101 @@ THE_TX : entity work.uart_trans TX => UART_TX ); -tx_data <= rx_data; -tx_send <= rx_ready; +PROC_RX : process begin + wait until rising_edge(CLK); + READ_OUT <= '0'; + WRITE_OUT <= '0'; + tx_send <= '0'; + case state is + when IDLE => + cmd_rd <= '0'; + cmd_wr <= '0'; + if rx_ready = '1' then + state <= ADDR; + if rx_data = x"52" then + cmd_rd <= '1'; + elsif rx_data = x"57" then + cmd_wr <= '1'; + else + state <= IDLE; + end if; + end if; + + when ADDR => + if rx_ready = '1' then + addr <= rx_data; + if cmd_wr = '1' then + state <= GET_BYTE3; + else + state <= DO_READ; + READ_OUT <= '1'; + end if; + end if; +--Write cycle + when GET_BYTE3 => + if rx_ready = '1' then + word(31 downto 24) <= rx_data; + state <= GET_BYTE2; + end if; + when GET_BYTE2 => + if rx_ready = '1' then + word(23 downto 16) <= rx_data; + state <= GET_BYTE1; + end if; + when GET_BYTE1 => + if rx_ready = '1' then + word(15 downto 8) <= rx_data; + state <= GET_BYTE0; + end if; + when GET_BYTE0 => + if rx_ready = '1' then + word(7 downto 0) <= rx_data; + state <= DO_WRITE; + end if; + when DO_WRITE => + WRITE_OUT <= '1'; + state <= IDLE; +--Read cycle + when DO_READ => + if READY_IN = '1' then + word <= DATA_IN; + tx_send <= '1'; + tx_data <= DATA_IN(31 downto 24); + state <= SEND_BYTE2; + end if; + when SEND_BYTE2=> + if tx_ready = '1' then + tx_send <= '1'; + tx_data <= word(23 downto 16); + state <= SEND_BYTE1; + end if; + when SEND_BYTE1=> + if tx_ready = '1' then + tx_send <= '1'; + tx_data <= word(15 downto 8); + state <= SEND_BYTE0; + end if; + when SEND_BYTE0=> + if tx_ready = '1' then + tx_send <= '1'; + tx_data <= word(7 downto 0); + state <= IDLE; + end if; + + end case; + + if RESET = '1' or timeout = '1' then + state <= IDLE; + timer <= (others => '0'); + end if; +end process; + + +timeout <= timer(25); + + +DATA_OUT <= word; +ADDR_OUT <= addr; -DATA_OUT(7 downto 0) <= rx_data; end architecture; \ No newline at end of file