From: Jan Michel Date: Wed, 26 Jun 2013 13:39:46 +0000 (+0200) Subject: resolved conflict X-Git-Tag: oldGBE~2 X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=bba9d87df95ef36b934f1a4c25a130dc0d5f0ad5;p=trbnet.git resolved conflict --- bba9d87df95ef36b934f1a4c25a130dc0d5f0ad5 diff --cc trb_net_components.vhd index 6d6c05b,88a0bec..74add9d --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@@ -1018,572 -57,1533 +57,1432 @@@ package trb_net_components i + component adc_ltc2308_readout is + generic( + CLOCK_FREQUENCY : integer := 100 --MHz + ); + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + ADC_SCK : out std_logic; + ADC_SDI : out std_logic; + ADC_SDO : in std_logic; + ADC_CONVST : out std_logic; + + DAT_ADDR_IN : in std_logic_vector(5 downto 0); + DAT_READ_EN_IN : in std_logic; + DAT_WRITE_EN_IN : in std_logic; + DAT_DATA_OUT : out std_logic_vector(31 downto 0); + DAT_DATA_IN : in std_logic_vector(31 downto 0); + DAT_DATAREADY_OUT : out std_logic; + DAT_NO_MORE_DATA_OUT : out std_logic; + DAT_WRITE_ACK_OUT : out std_logic; + DAT_UNKNOWN_ADDR_OUT : out std_logic; + DAT_TIMEOUT_IN : in std_logic; + + STAT_VOLTAGES_OUT : out std_logic_vector(31 downto 0) + ); + end component; + + + + + + + component trb_net16_addresses is + generic( + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001" + ); + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + RAM_DATA_IN : in std_logic_vector(15 downto 0); + RAM_DATA_OUT : out std_logic_vector(15 downto 0); + RAM_ADDR_IN : in std_logic_vector(2 downto 0); + RAM_WR_IN : in std_logic; + API_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + API_DATAREADY_OUT : out std_logic; + API_READ_IN : in std_logic; + ADDRESS_REJECTED : out std_logic; + DONT_UNDERSTAND_OUT : out std_logic; + API_SEND_OUT : out std_logic; + ADDRESS_OUT : out std_logic_vector(15 downto 0); + STAT_DEBUG : out std_logic_vector(15 downto 0) + ); + end component; + + + + + + + component trb_net16_api_base is + generic ( + API_TYPE : integer range 0 to 1 := c_API_PASSIVE; + FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6; --std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6; --std_FIFO_DEPTH; + FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + SECURE_MODE_TO_APL : integer range 0 to 1 := c_YES; + SECURE_MODE_TO_INT : integer range 0 to 1 := c_YES; + APL_WRITE_ALL_WORDS : integer range 0 to 1 := c_NO; + ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF" + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_DATAREADY_IN : in std_logic; + APL_READ_OUT : out std_logic; + APL_SHORT_TRANSFER_IN : in std_logic; + APL_DTYPE_IN : in std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + APL_SEND_IN : in std_logic; + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- the target (only for active APIs) + -- Receiver port + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; + -- APL Control port + APL_RUN_OUT : out std_logic; + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + APL_LENGTH_IN : in std_logic_vector (15 downto 0); + APL_FIFO_COUNT_OUT : out std_logic_vector (10 downto 0); + -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + -- master_data_out and slave_data_in are only used in active API for termination + INT_MASTER_DATAREADY_OUT : out std_logic; + INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_IN : in std_logic; + INT_MASTER_DATAREADY_IN : in std_logic; + INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_OUT : out std_logic; + INT_SLAVE_DATAREADY_OUT : out std_logic; + INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_IN : in std_logic; + INT_SLAVE_DATAREADY_IN : in std_logic; + INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_OUT : out std_logic; + -- Status and control port + CTRL_SEQNR_RESET : in std_logic; + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); + end component; + + + + + component trb_net16_api_ipu_streaming is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Internal direction port + + FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + FEE_INIT_DATAREADY_OUT : out std_logic; + FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + FEE_INIT_READ_IN : in std_logic; + + FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + FEE_REPLY_DATAREADY_IN : in std_logic; + FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + FEE_REPLY_READ_OUT : out std_logic; + + CTS_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + CTS_INIT_DATAREADY_IN : in std_logic; + CTS_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + CTS_INIT_READ_OUT : out std_logic; + + CTS_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + CTS_REPLY_DATAREADY_OUT : out std_logic; + CTS_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + CTS_REPLY_READ_IN : in std_logic; + + --Event information coming from CTS + CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); + CTS_CODE_OUT : out std_logic_vector (7 downto 0); + CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); + CTS_START_READOUT_OUT : out std_logic; + + --Information sent to CTS + --status data, equipped with DHDR + CTS_DATA_IN : in std_logic_vector (31 downto 0); + CTS_DATAREADY_IN : in std_logic; + CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM + CTS_READ_OUT : out std_logic; + CTS_LENGTH_IN : in std_logic_vector (15 downto 0); + CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + + -- Data from Frontends + FEE_DATA_OUT : out std_logic_vector (15 downto 0); + FEE_DATAREADY_OUT : out std_logic; + FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready + FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + FEE_BUSY_OUT : out std_logic; + + MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + CTRL_SEQNR_RESET : in std_logic + + ); + end component; + + + component trb_net16_api_ipu_streaming_internal is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Internal direction port + + FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + FEE_INIT_DATAREADY_OUT : out std_logic; + FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + FEE_INIT_READ_IN : in std_logic; + + FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + FEE_REPLY_DATAREADY_IN : in std_logic; + FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + FEE_REPLY_READ_OUT : out std_logic; + + --Event information coming from CTS + CTS_SEND_IN : in std_logic; + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); --valid while start_readout is high + CTS_CODE_IN : in std_logic_vector (7 downto 0); --valid while start_readout is high + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); --valid while start_readout is high + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); --valid while start_readout is high + + CTS_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + CTS_BUSY_OUT : out std_logic; --goes high after CTS_SEND_IN, goes low after GBE_READOUT_FINISHED_IN + + --connection to GbE + GBE_CTS_NUMBER_OUT : out std_logic_vector (15 downto 0); --valid while start_readout is high + GBE_CTS_CODE_OUT : out std_logic_vector (7 downto 0); --valid while start_readout is high + GBE_CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0); --valid while start_readout is high + GBE_CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); --valid while start_readout is high + GBE_CTS_START_READOUT_OUT : out std_logic; + + GBE_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM, should be high 1 CLK cycle + GBE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); --valid when readout_finished is high + + GBE_FEE_DATA_OUT : out std_logic_vector (15 downto 0); --data from FEE + GBE_FEE_DATAREADY_OUT : out std_logic; --data on data_out is valid + GBE_FEE_READ_IN : in std_logic; --must be high always unless connected entity can not read data, otherwise you will never get a dataready + GBE_FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); --valid after busy is low again + GBE_FEE_BUSY_OUT : out std_logic; --goes high shortly after start_readout; goes low when last dataword from FEE + --has been read. + + MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + CTRL_SEQNR_RESET : in std_logic + + ); + end component; + + + component trb_net_bridge_pcie_apl is + generic( + USE_CHANNELS : channel_config_t := (c_YES, c_YES, c_NO, c_YES) + ); + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + --TrbNet connect + APL_DATA_OUT : out std_logic_vector (16*3-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (3*3-1 downto 0); + APL_DATAREADY_OUT : out std_logic_vector (3-1 downto 0); + APL_READ_IN : in std_logic_vector (3-1 downto 0); + APL_SHORT_TRANSFER_OUT : out std_logic_vector (3-1 downto 0); + APL_DTYPE_OUT : out std_logic_vector (3*4-1 downto 0); + APL_ERROR_PATTERN_OUT : out std_logic_vector (32*3-1 downto 0); + APL_SEND_OUT : out std_logic_vector (3-1 downto 0); + APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*3-1 downto 0); + APL_DATA_IN : in std_logic_vector (16*3-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (3*3-1 downto 0); + APL_TYP_IN : in std_logic_vector (3*3-1 downto 0); + APL_DATAREADY_IN : in std_logic_vector (3-1 downto 0); + APL_READ_OUT : out std_logic_vector (3-1 downto 0); + APL_RUN_IN : in std_logic_vector (3-1 downto 0); + APL_SEQNR_IN : in std_logic_vector (8*3-1 downto 0); + APL_FIFO_COUNT_IN : in std_logic_vector (11*3-1 downto 0); + + --Internal Data Bus + BUS_ADDR_IN : in std_logic_vector(31 downto 0); + BUS_WDAT_IN : in std_logic_vector(31 downto 0); + BUS_RDAT_OUT : out std_logic_vector(31 downto 0); + BUS_SEL_IN : in std_logic_vector(3 downto 0); + BUS_WE_IN : in std_logic; + BUS_CYC_IN : in std_logic; + BUS_STB_IN : in std_logic; + BUS_LOCK_IN : in std_logic; + BUS_ACK_OUT : out std_logic; + + EXT_TRIGGER_INFO : out std_logic_vector(15 downto 0); + SEND_RESET_OUT : out std_logic; + --DMA interface + + --Debug + STAT : out std_logic_vector (31 downto 0); + CTRL : in std_logic_vector (31 downto 0) + ); + end component; + + + component trb_net_bridge_pcie_endpoint is + generic( + USE_CHANNELS : channel_config_t := (c_YES, c_YES, c_NO, c_YES) + ); + port( + RESET : in std_logic; + CLK : in std_logic; + + BUS_ADDR_IN : in std_logic_vector(31 downto 0); + BUS_WDAT_IN : in std_logic_vector(31 downto 0); + BUS_RDAT_OUT : out std_logic_vector(31 downto 0); + BUS_SEL_IN : in std_logic_vector(3 downto 0); + BUS_WE_IN : in std_logic; + BUS_CYC_IN : in std_logic; + BUS_STB_IN : in std_logic; + BUS_LOCK_IN : in std_logic; + BUS_ACK_OUT : out std_logic; + + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + + MED_ERROR_IN : in std_logic_vector(2 downto 0); + SEND_RESET_OUT : out std_logic; + STAT : out std_logic_vector(31 downto 0); + STAT_ENDP : out std_logic_vector(31 downto 0); + STAT_API1 : out std_logic_vector(31 downto 0) + ); + end component; + + + component trb_net_bridge_pcie_endpoint_hub is + generic( + NUM_LINKS : integer range 1 to 4 := 2; + COMPILE_TIME : std_logic_vector(31 downto 0) := (others => '0') + ); + port( + RESET : in std_logic; + RESET_TRBNET : in std_logic; + CLK : in std_logic; + CLK_125_IN : in std_logic; + + BUS_ADDR_IN : in std_logic_vector(31 downto 0); + BUS_WDAT_IN : in std_logic_vector(31 downto 0); + BUS_RDAT_OUT : out std_logic_vector(31 downto 0); + BUS_SEL_IN : in std_logic_vector(3 downto 0); + BUS_WE_IN : in std_logic; + BUS_CYC_IN : in std_logic; + BUS_STB_IN : in std_logic; + BUS_LOCK_IN : in std_logic; + BUS_ACK_OUT : out std_logic; + + SPI_CLK_OUT : out std_logic; + SPI_D_OUT : out std_logic; + SPI_D_IN : in std_logic; + SPI_CE_OUT : out std_logic; + + MED_DATAREADY_IN : in std_logic_vector (NUM_LINKS-1 downto 0); + MED_DATA_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (3*NUM_LINKS-1 downto 0); + MED_READ_OUT : out std_logic_vector (NUM_LINKS-1 downto 0); + + MED_DATAREADY_OUT : out std_logic_vector (NUM_LINKS-1 downto 0); + MED_DATA_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (3*NUM_LINKS-1 downto 0); + MED_READ_IN : in std_logic_vector (NUM_LINKS-1 downto 0); + + MED_STAT_OP_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0); + MED_CTRL_OP_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0); + + REQUESTOR_ID_IN : in std_logic_vector(15 downto 0); + TX_ST_OUT : out std_logic; --tx first word + TX_END_OUT : out std_logic; --tx last word + TX_DWEN_OUT : out std_logic; --tx use only upper 32 bit + TX_DATA_OUT : out std_logic_vector(63 downto 0); --tx data out + TX_REQ_OUT : out std_logic; --tx request out + TX_RDY_IN : in std_logic; --tx arbiter can read + TX_VAL_IN : in std_logic; --tx data is valid + TX_CA_PH_IN : in std_logic_vector(8 downto 0); --header credit for write + TX_CA_PD_IN : in std_logic_vector(12 downto 0); --data credits in 32 bit words + TX_CA_NPH_IN : in std_logic_vector(8 downto 0); --header credit for read + + RX_CR_CPLH_OUT : out std_logic; + RX_CR_CPLD_OUT : out std_logic_vector(7 downto 0); + UNEXP_CMPL_OUT : out std_logic; + RX_ST_IN : in std_logic; + RX_END_IN : in std_logic; + RX_DWEN_IN : in std_logic; + RX_DATA_IN : in std_logic_vector(63 downto 0); + + PROGRMN_OUT : out std_logic; + SEND_RESET_OUT : out std_logic; + MAKE_RESET_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector (31 downto 0) + ); + end component; + + component trb_net_CRC is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(15 downto 0); + CRC_OUT : out std_logic_vector(15 downto 0); + CRC_match : out std_logic + ); + end component; + + + component trb_net_CRC8 is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + CRC_OUT : out std_logic_vector(7 downto 0); + CRC_match : out std_logic + ); + end component; + + component ddr_off is + port ( + Clk : in std_logic; + Data : in std_logic_vector(1 downto 0); + Q : out std_logic_vector(0 downto 0) + ); + end component; + + + + component dll_in100_out100 is + port ( + clk : in std_logic; + aluhold : in std_logic; + clkop : out std_logic; + clkos : out std_logic; + lock : out std_logic + ); + end component; + + + component dll_in200_out100 is + port ( + clk : in std_logic; + aluhold : in std_logic; + clkop : out std_logic; + clkos : out std_logic; + lock : out std_logic + ); + end component; + + + component trb_net16_dummy_fifo is + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_IN : in std_logic_vector(1 downto 0); + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; + EMPTY_OUT : out std_logic + ); + end component; + + + + + + component trb_net16_endpoint_hades_full is + generic ( + USE_CHANNEL : channel_config_t := (c_YES, c_YES, c_NO, c_YES); + IBUF_DEPTH : channel_config_t := (6, 6, 6, 6); + FIFO_TO_INT_DEPTH : channel_config_t := (6, 6, 6, 6); + FIFO_TO_APL_DEPTH : channel_config_t := (1, 1, 1, 1); + IBUF_SECURE_MODE : channel_config_t := (c_YES, c_YES, c_YES, c_YES); + API_SECURE_MODE_TO_APL : channel_config_t := (c_YES, c_YES, c_YES, c_YES); + API_SECURE_MODE_TO_INT : channel_config_t := (c_YES, c_YES, c_YES, c_YES); + OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH; + INIT_CAN_SEND_DATA : channel_config_t := (c_NO, c_NO, c_NO, c_NO); + REPLY_CAN_SEND_DATA : channel_config_t := (c_YES, c_YES, c_YES, c_YES); + REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO, c_NO, c_NO, c_NO); + USE_CHECKSUM : channel_config_t := (c_NO, c_YES, c_YES, c_YES); + APL_WRITE_ALL_WORDS : channel_config_t := (c_NO, c_NO, c_NO, c_NO); + ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; + TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES; + REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers + REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + --standard values for output registers + REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); + --set to 0 for unused ctrl registers to save resources + REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1'); + --set to 0 for each unused bit in a register + REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); + REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR + REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; + CLOCK_FREQUENCY : integer range 1 to 200 := 100 + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic := '1'; + + -- Media direction port + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_STAT_OP_IN : in std_logic_vector(15 downto 0); + MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); + + -- LVL1 trigger APL + TRG_TIMING_TRG_RECEIVED_IN : in std_logic; --strobe when timing trigger received + + LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid + LVL1_TRG_VALID_TIMING_OUT : out std_logic; --valid timing trigger has been received + LVL1_TRG_VALID_NOTIMING_OUT : out std_logic; --valid trigger without timing trigger has been received + LVL1_TRG_INVALID_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...) + + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); + + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; + LVL1_TRG_RELEASE_IN : in std_logic := '0'; + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only + + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT : out std_logic; + TRG_TIMEOUT_DETECTED_OUT : out std_logic; + TRG_SPURIOUS_TRG_OUT : out std_logic; + TRG_MISSING_TMG_TRG_OUT : out std_logic; + TRG_SPIKE_DETECTED_OUT : out std_logic; + TRG_LONG_TRG_OUT : out std_logic; + --Data Port + IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); + IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); + IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + --start strobe + IPU_START_READOUT_OUT : out std_logic; + --detector data, equipped with DHDR + IPU_DATA_IN : in std_logic_vector (31 downto 0); + IPU_DATAREADY_IN : in std_logic; + --no more data, end transfer, send TRM + IPU_READOUT_FINISHED_IN : in std_logic; + --will be low every second cycle due to 32bit -> 16bit conversion + IPU_READ_OUT : out std_logic; + IPU_LENGTH_IN : in std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0'); + REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0); + COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0); + STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); + CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + --following ports only used when using internal data port + REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; + REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + REGIO_DATAREADY_IN : in std_logic := '0'; + REGIO_NO_MORE_DATA_IN : in std_logic := '0'; + REGIO_WRITE_ACK_IN : in std_logic := '0'; + REGIO_UNKNOWN_ADDR_IN : in std_logic := '0'; + REGIO_TIMEOUT_OUT : out std_logic; + --IDRAM is used if no 1-wire interface, onewire used otherwise + REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0'); + REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000"; + REGIO_IDRAM_WR_IN : in std_logic := '0'; + REGIO_ONEWIRE_INOUT : inout std_logic; --temperature sensor + REGIO_ONEWIRE_MONITOR_IN : in std_logic := '0'; + REGIO_ONEWIRE_MONITOR_OUT : out std_logic; + REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0'); + + GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds + LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger + TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick + --Debugging & Status information + STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); + STAT_DEBUG_1 : out std_logic_vector (31 downto 0); + STAT_DEBUG_2 : out std_logic_vector (31 downto 0); + MED_STAT_OP : out std_logic_vector (15 downto 0); + CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0'); + IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); + STAT_ONEWIRE : out std_logic_vector (31 downto 0); + STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0); + STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0); + DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0) + ); + end component; + + + component trb_net16_endpoint_hades_full_handler is + generic ( + IBUF_DEPTH : channel_config_t := (6, 6, 6, 6); + FIFO_TO_INT_DEPTH : channel_config_t := (6, 6, 6, 6); + FIFO_TO_APL_DEPTH : channel_config_t := (1, 1, 1, 1); + APL_WRITE_ALL_WORDS : channel_config_t := (c_NO, c_NO, c_NO, c_NO); + ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; + REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers + REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0'); + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR + REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; + TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES; + CLOCK_FREQUENCY : integer range 1 to 200 := 100; + --Configure data handler + DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; + DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; + DATA_BUFFER_WIDTH : integer range 1 to 32 := 31; + DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8; + TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; + HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; + HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-2 := 2**8 + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic := '1'; + + -- Media direction port + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_STAT_OP_IN : in std_logic_vector(15 downto 0); + MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN : in std_logic; + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid + LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received + LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received + LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...) + + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0); + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only + + --Response from FEE + FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + + --Information about trigger handler errors + TRG_MULTIPLE_TRG_OUT : out std_logic; + TRG_TIMEOUT_DETECTED_OUT : out std_logic; + TRG_SPURIOUS_TRG_OUT : out std_logic; + TRG_MISSING_TMG_TRG_OUT : out std_logic; + TRG_SPIKE_DETECTED_OUT : out std_logic; + + --Slow Control Port + --common registers + REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0); + REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0); + --user defined registers + REGIO_STAT_REG_IN : in std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0'); + REGIO_CTRL_REG_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0); + REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); + REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + --internal data port + BUS_ADDR_OUT : out std_logic_vector(16-1 downto 0); + BUS_DATA_OUT : out std_logic_vector(32-1 downto 0); + BUS_READ_ENABLE_OUT : out std_logic; + BUS_WRITE_ENABLE_OUT : out std_logic; + BUS_TIMEOUT_OUT : out std_logic; + BUS_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + BUS_DATAREADY_IN : in std_logic := '0'; + BUS_WRITE_ACK_IN : in std_logic := '0'; + BUS_NO_MORE_DATA_IN : in std_logic := '0'; + BUS_UNKNOWN_ADDR_IN : in std_logic := '0'; + --Onewire + ONEWIRE_INOUT : inout std_logic; --temperature sensor + ONEWIRE_MONITOR_IN : in std_logic := '0'; + ONEWIRE_MONITOR_OUT : out std_logic; + --Config endpoint id, if not statically assigned + REGIO_VAR_ENDPOINT_ID : in std_logic_vector (15 downto 0) := (others => '0'); + + --Timing registers + TIME_GLOBAL_OUT : out std_logic_vector (31 downto 0); --global time, microseconds + TIME_LOCAL_OUT : out std_logic_vector (7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG_OUT : out std_logic_vector (31 downto 0); --local time, resetted with each trigger + TIME_TICKS_OUT : out std_logic_vector (1 downto 0); --bit 1 ms-tick, 0 us-tick + + --Debugging & Status information + STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); + STAT_DEBUG_1 : out std_logic_vector (31 downto 0); + STAT_DEBUG_2 : out std_logic_vector (31 downto 0); + STAT_DEBUG_DATA_HANDLER_OUT : out std_logic_vector (31 downto 0); + STAT_DEBUG_IPU_HANDLER_OUT : out std_logic_vector (31 downto 0); + CTRL_MPLEX : in std_logic_vector (31 downto 0) := (others => '0'); + IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); + STAT_ONEWIRE : out std_logic_vector (31 downto 0); + STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0); + STAT_TRIGGER_OUT : out std_logic_vector (79 downto 0); + DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0) + ); + end component; + + component trb_net16_endpoint_hades_cts is + generic( + USE_CHANNEL : channel_config_t := (c_YES, c_YES, c_NO, c_YES); + IBUF_DEPTH : channel_config_t := (1, 6, 6, 6); + FIFO_TO_INT_DEPTH : channel_config_t := (1, 1, 6, 6); + FIFO_TO_APL_DEPTH : channel_config_t := (1, 6, 6, 6); + INIT_CAN_SEND_DATA : channel_config_t := (c_YES, c_YES, c_NO, c_NO); + REPLY_CAN_SEND_DATA : channel_config_t := (c_NO, c_NO, c_NO, c_YES); + REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_YES, c_YES, c_NO, c_NO); + USE_CHECKSUM : channel_config_t := (c_NO, c_YES, c_YES, c_YES); + APL_WRITE_ALL_WORDS : channel_config_t := (c_NO, c_NO, c_NO, c_NO); + ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + REGIO_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers + REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + --standard values for output registers + REGIO_INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0'); + --set to 0 for unused ctrl registers to save resources + REGIO_USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := x"0001"; + --set to 0 for each unused bit in a register + REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); + REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"0000_0000_0000_0000"; + REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"0000_0000"; + REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"50000000"; + REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR + REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; + CLOCK_FREQUENCY : integer range 1 to 200 := 100 + ); + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + + MED_STAT_OP_IN : in std_logic_vector(15 downto 0); + MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); + + --LVL1 trigger + TRG_SEND_IN : in std_logic; + TRG_TYPE_IN : in std_logic_vector (3 downto 0); + TRG_NUMBER_IN : in std_logic_vector (15 downto 0); + TRG_INFORMATION_IN : in std_logic_vector (23 downto 0); + TRG_RND_CODE_IN : in std_logic_vector (7 downto 0); + TRG_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + TRG_BUSY_OUT : out std_logic; + + --IPU Channel + IPU_SEND_IN : in std_logic; + IPU_TYPE_IN : in std_logic_vector (3 downto 0); + IPU_NUMBER_IN : in std_logic_vector (15 downto 0); + IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); + IPU_RND_CODE_IN : in std_logic_vector (7 downto 0); + -- Receiver port + IPU_DATA_OUT : out std_logic_vector (31 downto 0); + IPU_DATAREADY_OUT : out std_logic; + IPU_READ_IN : in std_logic; + IPU_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + IPU_BUSY_OUT : out std_logic; + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0'); + REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + COMMON_STAT_REG_STROBE : out std_logic_vector(std_COMSTATREG-1 downto 0); + COMMON_CTRL_REG_STROBE : out std_logic_vector(std_COMCTRLREG-1 downto 0); + STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0); + CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + --following ports only used when using internal data port + REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; + REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + REGIO_DATAREADY_IN : in std_logic := '0'; + REGIO_NO_MORE_DATA_IN : in std_logic := '0'; + REGIO_WRITE_ACK_IN : in std_logic := '0'; + REGIO_UNKNOWN_ADDR_IN : in std_logic := '0'; + REGIO_TIMEOUT_OUT : out std_logic; + REGIO_ONEWIRE_INOUT : inout std_logic; + REGIO_ONEWIRE_MONITOR_OUT : out std_logic; + REGIO_ONEWIRE_MONITOR_IN : in std_logic; + REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0'); + TRIGGER_MONITOR_IN : in std_logic := '0'; --strobe when timing trigger received + GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds + LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency + TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger + TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); --bit 1 ms-tick, 0 us-tick + STAT_DEBUG_1 : out std_logic_vector(31 downto 0); + STAT_DEBUG_2 : out std_logic_vector(31 downto 0) + ); + + end component; + + + + + component etrax_interface is + generic( + STATUS_REGISTERS : integer := 4; + CONTROL_REGISTERS : integer := 4 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + --Connection to Etrax + ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0); + ETRAX_DATA_BUS_C : in std_logic_vector(17 downto 0); + ETRAX_BUS_BUSY : out std_logic; + --Connection to internal FPGA logic (all addresses above 0x100) + INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0); + INTERNAL_DATA_IN : in std_logic_vector(31 downto 0); + INTERNAL_READ_OUT : out std_logic; + INTERNAL_WRITE_OUT : out std_logic; + INTERNAL_DATAREADY_IN : in std_logic; + INTERNAL_ADDRESS_OUT : out std_logic_vector(15 downto 0); + --Easy-to-use status and control registers (Addresses 0-15 (stat) and 16-31 (ctrl) + FPGA_REGISTER_IN : in std_logic_vector(STATUS_REGISTERS*32-1 downto 0); + FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0); + --Reset FPGA via Etrax + EXTERNAL_RESET : out std_logic; + STAT : out std_logic_vector(15 downto 0) + ); + end component; + + + + + + + + + component trb_net16_fifo is + generic ( + USE_VENDOR_CORES : integer range 0 to 1 := c_NO; + USE_DATA_COUNT : integer range 0 to 1 := c_NO; + DEPTH : integer := 6 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_IN : in std_logic_vector(1 downto 0); + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); + READ_ENABLE_IN : in std_logic; + DATA_COUNT_OUT : out std_logic_vector(10 downto 0); + FULL_OUT : out std_logic; + EMPTY_OUT : out std_logic + ); + end component; + + + + + + component trb_net_fifo_16bit_bram_dualport is + generic( + USE_STATUS_FLAGS : integer := c_YES + ); + port(read_clock_in : in std_logic; + write_clock_in : in std_logic; + read_enable_in : in std_logic; + write_enable_in : in std_logic; + fifo_gsr_in : in std_logic; + write_data_in : in std_logic_vector(17 downto 0); + read_data_out : out std_logic_vector(17 downto 0); + full_out : out std_logic; + empty_out : out std_logic; + fifostatus_out : out std_logic_vector(3 downto 0); + valid_read_out : out std_logic; + almost_empty_out : out std_logic; + almost_full_out : out std_logic + ); + end component; + + + + + + + component fifo_dualclock_width_16_reg is + port ( + Data : in std_logic_vector(17 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(17 downto 0); + Empty : out std_logic; + Full : out std_logic); + end component; + + + - --- component trb_net16_gbe_buf is --- generic( --- DO_SIMULATION : integer range 0 to 1 := 1; --- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 --- ); --- port( --- CLK : in std_logic; --- TEST_CLK : in std_logic; -- only for simulation! --- CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode --- CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode --- RESET : in std_logic; --- GSR_N : in std_logic; --- -- Debug --- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); --- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); --- -- configuration interface --- IP_CFG_START_IN : in std_logic; --- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); --- IP_CFG_DONE_OUT : out std_logic; --- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); --- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); --- IP_CFG_MEM_CLK_OUT : out std_logic; --- MR_RESET_IN : in std_logic; --- MR_MODE_IN : in std_logic; --- MR_RESTART_IN : in std_logic; --- -- gk 29.03.10 --- SLV_ADDR_IN : in std_logic_vector(7 downto 0); --- SLV_READ_IN : in std_logic; --- SLV_WRITE_IN : in std_logic; --- SLV_BUSY_OUT : out std_logic; --- SLV_ACK_OUT : out std_logic; --- SLV_DATA_IN : in std_logic_vector(31 downto 0); --- SLV_DATA_OUT : out std_logic_vector(31 downto 0); --- -- gk 22.04.10 --- -- registers setup interface --- BUS_ADDR_IN : in std_logic_vector(7 downto 0); --- BUS_DATA_IN : in std_logic_vector(31 downto 0); --- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 --- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 --- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 --- BUS_ACK_OUT : out std_logic; -- gk 26.04.10 --- -- gk 23.04.10 --- LED_PACKET_SENT_OUT : out std_logic; --- LED_AN_DONE_N_OUT : out std_logic; --- -- CTS interface --- CTS_NUMBER_IN : in std_logic_vector (15 downto 0); --- CTS_CODE_IN : in std_logic_vector (7 downto 0); --- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); --- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); --- CTS_START_READOUT_IN : in std_logic; --- CTS_DATA_OUT : out std_logic_vector (31 downto 0); --- CTS_DATAREADY_OUT : out std_logic; --- CTS_READOUT_FINISHED_OUT : out std_logic; --- CTS_READ_IN : in std_logic; --- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); --- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); --- -- Data payload interface --- FEE_DATA_IN : in std_logic_vector (15 downto 0); --- FEE_DATAREADY_IN : in std_logic; --- FEE_READ_OUT : out std_logic; --- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); --- FEE_BUSY_IN : in std_logic; --- --SFP Connection --- SFP_RXD_P_IN : in std_logic; --- SFP_RXD_N_IN : in std_logic; --- SFP_TXD_P_OUT : out std_logic; --- SFP_TXD_N_OUT : out std_logic; --- SFP_REFCLK_P_IN : in std_logic; --- SFP_REFCLK_N_IN : in std_logic; --- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) --- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) --- SFP_TXDIS_OUT : out std_logic; -- SFP disable --- -- debug ports --- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) --- ); --- end component; - - + component fpga_reboot is + port( + CLK : in std_logic; + RESET : in std_logic; + DO_REBOOT : in std_logic; + PROGRAMN : out std_logic + ); + end component; + + + component handler_data is + generic( + DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; + DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; + DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; + DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8; + TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; + HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; + HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8 + ); + port( + CLOCK : in std_logic; + RESET : in std_logic; + + --LVL1 Handler + LVL1_VALID_TRIGGER_IN : in std_logic; --received valid trigger, readout starts + LVL1_TRG_DATA_VALID_IN : in std_logic; --TRG Info valid & FEE busy + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); --trigger type + LVL1_TRG_INFO_IN : in std_logic_vector(23 downto 0); --further trigger details + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); --trigger number + LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + LVL1_TRG_RELEASE_OUT : out std_logic; + + --FEE + FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + + --IPU Handler + IPU_DATA_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + IPU_DATA_READ_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + IPU_DATA_EMPTY_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + IPU_DATA_LENGTH_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0); + IPU_DATA_FLAGS_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0); + + IPU_HDR_DATA_OUT : out std_logic_vector(31 downto 0); + IPU_HDR_DATA_READ_IN : in std_logic; + IPU_HDR_DATA_EMPTY_OUT : out std_logic; + + TMG_TRG_ERROR_IN : in std_logic; + MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0) := x"FFFF"; + --Status + STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); + + --Debug + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + + end component; + + + + + + component handler_ipu is + generic( + DATA_INTERFACE_NUMBER : integer range 1 to 7 := 1 + ); + port( + CLOCK : in std_logic; + RESET : in std_logic; + + --From Data Handler + DAT_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + DAT_DATA_READ_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + DAT_DATA_EMPTY_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + DAT_DATA_LENGTH_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0); + DAT_DATA_FLAGS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0); + DAT_HDR_DATA_IN : in std_logic_vector(31 downto 0); + DAT_HDR_DATA_READ_OUT : out std_logic; + DAT_HDR_DATA_EMPTY_IN : in std_logic; + + --To IPU Channel + IPU_NUMBER_IN : in std_logic_vector (15 downto 0); + IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); + IPU_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + IPU_START_READOUT_IN : in std_logic; + IPU_DATA_OUT : out std_logic_vector (31 downto 0); + IPU_DATAREADY_OUT : out std_logic; + IPU_READOUT_FINISHED_OUT : out std_logic; + IPU_READ_IN : in std_logic; + IPU_LENGTH_OUT : out std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + + --Debug + STATUS_OUT : out std_logic_vector(31 downto 0) + ); + + end component; + + + + component handler_lvl1 is + generic( + TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES + ); + port( + RESET : in std_logic; + RESET_FLAGS_IN : in std_logic; + RESET_STATS_IN : in std_logic; + CLOCK : in std_logic; + --Timing Trigger + LVL1_TIMING_TRG_IN : in std_logic; --raw trigger signal input, min. 80 ns or strobe, see generics + LVL1_PSEUDO_TMG_TRG_IN : in std_logic; --strobe for dummy timing trigger + --LVL1_handler connection + LVL1_TRG_RECEIVED_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); --errorbits to CTS + LVL1_TRG_RELEASE_OUT : out std_logic := '0'; --release to CTS + + LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); -- increased after trigger release + LVL1_INT_TRG_LOAD_IN : in std_logic; -- load internal trigger counter + LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter + + --FEE logic / Data Handler + LVL1_TRG_DATA_VALID_OUT : out std_logic; -- trigger type, number, code, information are valid + LVL1_VALID_TIMING_TRG_OUT : out std_logic; -- valid timing trigger has been received + LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; -- valid trigger without timing trigger has been received + LVL1_INVALID_TRG_OUT : out std_logic; -- the current trigger is invalid (e.g. no timing trigger, no LVL1...) + LVL1_MULTIPLE_TRG_OUT : out std_logic; -- more than one timing trigger detected + LVL1_DELAY_OUT : out std_logic_vector(15 downto 0); + LVL1_TIMEOUT_DETECTED_OUT : out std_logic; -- gk 11.09.10 + LVL1_SPURIOUS_TRG_OUT : out std_logic; -- gk 11.09.10 + LVL1_MISSING_TMG_TRG_OUT : out std_logic; -- gk 11.09.10 + LVL1_LONG_TRG_OUT : out std_logic; + SPIKE_DETECTED_OUT : out std_logic; -- gk 12.09.10 + + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern from FEE + LVL1_TRG_RELEASE_IN : in std_logic := '0'; -- trigger release from FEE + + --Stat/Control + STATUS_OUT : out std_logic_vector (63 downto 0); -- bits for status registers + TRG_ENABLE_IN : in std_logic; -- trigger enable flag + TRG_INVERT_IN : in std_logic; -- trigger invert flag + COUNTERS_STATUS_OUT : out std_logic_vector (79 downto 0); + --Debug + DEBUG_OUT : out std_logic_vector (15 downto 0) + ); + end component; + + + + + + component handler_trigger_and_data is + generic( + DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; + DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; + DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; + DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8; + TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; + HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; + HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8 + ); + port( + CLOCK : in std_logic; + RESET : in std_logic; + RESET_IPU : in std_logic; + + --To Endpoint + --Timing Trigger (registered) + LVL1_VALID_TRIGGER_IN : in std_logic; + LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + --LVL1_handler connection + LVL1_TRG_DATA_VALID_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + LVL1_TRG_RELEASE_OUT : out std_logic; + + --IPU channel + IPU_NUMBER_IN : in std_logic_vector(15 downto 0); + IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); + IPU_READOUT_TYPE_IN : in std_logic_vector(3 downto 0); + IPU_START_READOUT_IN : in std_logic; + IPU_DATA_OUT : out std_logic_vector(31 downto 0); + IPU_DATAREADY_OUT : out std_logic; + IPU_READOUT_FINISHED_OUT : out std_logic; + IPU_READ_IN : in std_logic; + IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); + IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + + --To FEE + --FEE to Trigger + FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + + --Data Input from FEE + FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + + TMG_TRG_ERROR_IN : in std_logic; + MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0) := x"FFFF"; + --Status Registers + STATUS_OUT : out std_logic_vector(127 downto 0); + STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); + STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); + TIMER_TICKS_IN : in std_logic_vector(1 downto 0); + STATISTICS_DATA_OUT : out std_logic_vector(31 downto 0); + STATISTICS_ADDR_IN : in std_logic_vector(4 downto 0); + STATISTICS_READY_OUT : out std_logic; + STATISTICS_READ_IN : in std_logic; + STATISTICS_UNKNOWN_OUT : out std_logic; + + --Debug + DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0); + DEBUG_IPU_HANDLER_OUT : out std_logic_vector(31 downto 0) + + ); + end component; + + + + + + + + component trb_net16_ibuf is + generic ( + DEPTH : integer range 0 to 7 := c_FIFO_BRAM; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_ERROR_IN : in std_logic_vector (2 downto 0); + -- Internal direction port + INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + INT_INIT_DATAREADY_OUT : out std_logic; + INT_INIT_READ_IN : in std_logic; + INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + INT_REPLY_DATAREADY_OUT : out std_logic; + INT_REPLY_READ_IN : in std_logic; + INT_ERROR_OUT : out std_logic_vector (2 downto 0); + -- Status and control port + STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0); + STAT_DATA_COUNTER : out std_logic_vector (31 downto 0); + STAT_BUFFER : out std_logic_vector (31 downto 0); + CTRL_STAT : in std_logic_vector (15 downto 0) + ); + end component; + + + + + + + component fifo_36x512 is + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic + ); + end component; + + ---component fifo_var_oreg is ---generic( - --FIFO_WIDTH : integer range 1 to 64 := 36; - --FIFO_DEPTH : integer range 1 to 16 := 8 - --); ---port( - --Data : in std_logic_vector(FIFO_WIDTH-1 downto 0); - --Clock : in std_logic; - --WrEn : in std_logic; - --RdEn : in std_logic; - --Reset : in std_logic; - --AmFullThresh : in std_logic_vector(FIFO_DEPTH-1 downto 0); - --Q : out std_logic_vector(FIFO_WIDTH-1 downto 0); - --WCNT : out std_logic_vector(FIFO_DEPTH downto 0); - --Empty : out std_logic; - --Full : out std_logic; - --AlmostFull : out std_logic - --); ---end component; - - - + component trb_net16_iobuf is + generic ( + IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM; --std_FIFO_DEPTH; + IBUF_SECURE_MODE : integer range 0 to 1 := c_NO; --std_IBUF_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + SBUF_VERSION_OBUF : integer range 0 to 6 := std_SBUF_VERSION; + OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; + INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT : out std_logic; + MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN : in std_logic; + MED_REPLY_DATAREADY_OUT : out std_logic; + MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN : in std_logic; + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_ERROR_IN : in std_logic_vector (2 downto 0); + -- Internal direction port + INT_INIT_DATAREADY_OUT : out std_logic; + INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_IN : in std_logic; + INT_INIT_DATAREADY_IN : in std_logic; + INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_OUT : out std_logic; + INT_REPLY_DATAREADY_OUT : out std_logic; + INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_IN : in std_logic; + INT_REPLY_DATAREADY_IN : in std_logic; + INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_OUT : out std_logic; + -- Status and control port + STAT_GEN : out std_logic_vector (31 downto 0); + STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); + CTRL_GEN : in std_logic_vector (31 downto 0); + CTRL_OBUF_settings : in std_logic_vector (31 downto 0) := (others => '0'); + STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0); + STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0); + STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0); + STAT_DATA_COUNTER : out std_logic_vector (31 downto 0); + TIMER_TICKS_IN : in std_logic_vector (1 downto 0); + CTRL_STAT : in std_logic_vector (15 downto 0) + ); + end component; - -- component trb_net16_gbe_buf is - -- generic( - -- DO_SIMULATION : integer range 0 to 1 := 1; - -- USE_125MHZ_EXTCLK : integer range 0 to 1 := 1 - -- ); - -- port( - -- CLK : in std_logic; - -- TEST_CLK : in std_logic; -- only for simulation! - -- CLK_125_TX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode - -- CLK_125_RX_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode - -- RESET : in std_logic; - -- GSR_N : in std_logic; - -- -- Debug - -- STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); - -- STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); - -- -- configuration interface - -- IP_CFG_START_IN : in std_logic; - -- IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); - -- IP_CFG_DONE_OUT : out std_logic; - -- IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); - -- IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); - -- IP_CFG_MEM_CLK_OUT : out std_logic; - -- MR_RESET_IN : in std_logic; - -- MR_MODE_IN : in std_logic; - -- MR_RESTART_IN : in std_logic; - -- -- gk 29.03.10 - -- SLV_ADDR_IN : in std_logic_vector(7 downto 0); - -- SLV_READ_IN : in std_logic; - -- SLV_WRITE_IN : in std_logic; - -- SLV_BUSY_OUT : out std_logic; - -- SLV_ACK_OUT : out std_logic; - -- SLV_DATA_IN : in std_logic_vector(31 downto 0); - -- SLV_DATA_OUT : out std_logic_vector(31 downto 0); - -- -- gk 22.04.10 - -- -- registers setup interface - -- BUS_ADDR_IN : in std_logic_vector(7 downto 0); - -- BUS_DATA_IN : in std_logic_vector(31 downto 0); - -- BUS_DATA_OUT : out std_logic_vector(31 downto 0); -- gk 26.04.10 - -- BUS_WRITE_EN_IN : in std_logic; -- gk 26.04.10 - -- BUS_READ_EN_IN : in std_logic; -- gk 26.04.10 - -- BUS_ACK_OUT : out std_logic; -- gk 26.04.10 - -- -- gk 23.04.10 - -- LED_PACKET_SENT_OUT : out std_logic; - -- LED_AN_DONE_N_OUT : out std_logic; - -- -- CTS interface - -- CTS_NUMBER_IN : in std_logic_vector (15 downto 0); - -- CTS_CODE_IN : in std_logic_vector (7 downto 0); - -- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); - -- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - -- CTS_START_READOUT_IN : in std_logic; - -- CTS_DATA_OUT : out std_logic_vector (31 downto 0); - -- CTS_DATAREADY_OUT : out std_logic; - -- CTS_READOUT_FINISHED_OUT : out std_logic; - -- CTS_READ_IN : in std_logic; - -- CTS_LENGTH_OUT : out std_logic_vector (15 downto 0); - -- CTS_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - -- -- Data payload interface - -- FEE_DATA_IN : in std_logic_vector (15 downto 0); - -- FEE_DATAREADY_IN : in std_logic; - -- FEE_READ_OUT : out std_logic; - -- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); - -- FEE_BUSY_IN : in std_logic; - -- --SFP Connection - -- SFP_RXD_P_IN : in std_logic; - -- SFP_RXD_N_IN : in std_logic; - -- SFP_TXD_P_OUT : out std_logic; - -- SFP_TXD_N_OUT : out std_logic; - -- SFP_REFCLK_P_IN : in std_logic; - -- SFP_REFCLK_N_IN : in std_logic; - -- SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) - -- SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - -- SFP_TXDIS_OUT : out std_logic; -- SFP disable - -- -- debug ports - -- ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) - -- ); - -- end component; - component fpga_reboot is - port( - CLK : in std_logic; - RESET : in std_logic; - DO_REBOOT : in std_logic; - PROGRAMN : out std_logic - ); - end component; - - - component handler_data is - generic( - DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; - DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; - DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; - DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8; - TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; - HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; - HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8 - ); - port( - CLOCK : in std_logic; - RESET : in std_logic; - - --LVL1 Handler - LVL1_VALID_TRIGGER_IN : in std_logic; --received valid trigger, readout starts - LVL1_TRG_DATA_VALID_IN : in std_logic; --TRG Info valid & FEE busy - LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); --trigger type - LVL1_TRG_INFO_IN : in std_logic_vector(23 downto 0); --further trigger details - LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); - LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); --trigger number - LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0); - LVL1_TRG_RELEASE_OUT : out std_logic; - - --FEE - FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - - --IPU Handler - IPU_DATA_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - IPU_DATA_READ_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - IPU_DATA_EMPTY_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - IPU_DATA_LENGTH_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0); - IPU_DATA_FLAGS_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0); - - IPU_HDR_DATA_OUT : out std_logic_vector(31 downto 0); - IPU_HDR_DATA_READ_IN : in std_logic; - IPU_HDR_DATA_EMPTY_OUT : out std_logic; - - TMG_TRG_ERROR_IN : in std_logic; - MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0) := x"FFFF"; - --Status - STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); - - --Debug - DEBUG_OUT : out std_logic_vector(31 downto 0) - ); - - end component; - - - - - - component handler_ipu is - generic( - DATA_INTERFACE_NUMBER : integer range 1 to 7 := 1 - ); - port( - CLOCK : in std_logic; - RESET : in std_logic; - - --From Data Handler - DAT_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - DAT_DATA_READ_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - DAT_DATA_EMPTY_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - DAT_DATA_LENGTH_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*16-1 downto 0); - DAT_DATA_FLAGS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*4-1 downto 0); - DAT_HDR_DATA_IN : in std_logic_vector(31 downto 0); - DAT_HDR_DATA_READ_OUT : out std_logic; - DAT_HDR_DATA_EMPTY_IN : in std_logic; - - --To IPU Channel - IPU_NUMBER_IN : in std_logic_vector (15 downto 0); - IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); - IPU_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - IPU_START_READOUT_IN : in std_logic; - IPU_DATA_OUT : out std_logic_vector (31 downto 0); - IPU_DATAREADY_OUT : out std_logic; - IPU_READOUT_FINISHED_OUT : out std_logic; - IPU_READ_IN : in std_logic; - IPU_LENGTH_OUT : out std_logic_vector (15 downto 0); - IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - - --Debug - STATUS_OUT : out std_logic_vector(31 downto 0) - ); - - end component; - - - - component handler_lvl1 is - generic( - TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES - ); - port( - RESET : in std_logic; - RESET_FLAGS_IN : in std_logic; - RESET_STATS_IN : in std_logic; - CLOCK : in std_logic; - --Timing Trigger - LVL1_TIMING_TRG_IN : in std_logic; --raw trigger signal input, min. 80 ns or strobe, see generics - LVL1_PSEUDO_TMG_TRG_IN : in std_logic; --strobe for dummy timing trigger - --LVL1_handler connection - LVL1_TRG_RECEIVED_IN : in std_logic; - LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); - LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); --errorbits to CTS - LVL1_TRG_RELEASE_OUT : out std_logic := '0'; --release to CTS - - LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); -- increased after trigger release - LVL1_INT_TRG_LOAD_IN : in std_logic; -- load internal trigger counter - LVL1_INT_TRG_COUNTER_IN : in std_logic_vector(15 downto 0); -- load value for internal trigger counter - - --FEE logic / Data Handler - LVL1_TRG_DATA_VALID_OUT : out std_logic; -- trigger type, number, code, information are valid - LVL1_VALID_TIMING_TRG_OUT : out std_logic; -- valid timing trigger has been received - LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; -- valid trigger without timing trigger has been received - LVL1_INVALID_TRG_OUT : out std_logic; -- the current trigger is invalid (e.g. no timing trigger, no LVL1...) - LVL1_MULTIPLE_TRG_OUT : out std_logic; -- more than one timing trigger detected - LVL1_DELAY_OUT : out std_logic_vector(15 downto 0); - LVL1_TIMEOUT_DETECTED_OUT : out std_logic; -- gk 11.09.10 - LVL1_SPURIOUS_TRG_OUT : out std_logic; -- gk 11.09.10 - LVL1_MISSING_TMG_TRG_OUT : out std_logic; -- gk 11.09.10 - LVL1_LONG_TRG_OUT : out std_logic; - SPIKE_DETECTED_OUT : out std_logic; -- gk 12.09.10 - - LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); -- error pattern from FEE - LVL1_TRG_RELEASE_IN : in std_logic := '0'; -- trigger release from FEE - - --Stat/Control - STATUS_OUT : out std_logic_vector (63 downto 0); -- bits for status registers - TRG_ENABLE_IN : in std_logic; -- trigger enable flag - TRG_INVERT_IN : in std_logic; -- trigger invert flag - COUNTERS_STATUS_OUT : out std_logic_vector (79 downto 0); - --Debug - DEBUG_OUT : out std_logic_vector (15 downto 0) - ); - end component; - - - - - - component handler_trigger_and_data is - generic( - DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; - DATA_BUFFER_DEPTH : integer range 9 to 14 := 9; - DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; - DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-1 := 2**8; - TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; - HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9; - HEADER_BUFFER_FULL_THRESH : integer range 2**8 to 2**14-1 := 2**8 - ); - port( - CLOCK : in std_logic; - RESET : in std_logic; - RESET_IPU : in std_logic; - - --To Endpoint - --Timing Trigger (registered) - LVL1_VALID_TRIGGER_IN : in std_logic; - LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - --LVL1_handler connection - LVL1_TRG_DATA_VALID_IN : in std_logic; - LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); - LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - LVL1_TRG_RELEASE_OUT : out std_logic; - - --IPU channel - IPU_NUMBER_IN : in std_logic_vector(15 downto 0); - IPU_INFORMATION_IN : in std_logic_vector(7 downto 0); - IPU_READOUT_TYPE_IN : in std_logic_vector(3 downto 0); - IPU_START_READOUT_IN : in std_logic; - IPU_DATA_OUT : out std_logic_vector(31 downto 0); - IPU_DATAREADY_OUT : out std_logic; - IPU_READOUT_FINISHED_OUT : out std_logic; - IPU_READ_IN : in std_logic; - IPU_LENGTH_OUT : out std_logic_vector(15 downto 0); - IPU_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); - - --To FEE - --FEE to Trigger - FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - - --Data Input from FEE - FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); - - TMG_TRG_ERROR_IN : in std_logic; - MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0); - --Status Registers - STATUS_OUT : out std_logic_vector(127 downto 0); - STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); - STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); - TIMER_TICKS_IN : in std_logic_vector(1 downto 0); - STATISTICS_DATA_OUT : out std_logic_vector(31 downto 0); - STATISTICS_ADDR_IN : in std_logic_vector(4 downto 0); - STATISTICS_READY_OUT : out std_logic; - STATISTICS_READ_IN : in std_logic; - STATISTICS_UNKNOWN_OUT : out std_logic; - - --Debug - DEBUG_DATA_HANDLER_OUT : out std_logic_vector(31 downto 0); - DEBUG_IPU_HANDLER_OUT : out std_logic_vector(31 downto 0) - - ); - end component; - - - - - - - - component trb_net16_ibuf is - generic ( - DEPTH : integer range 0 to 7 := c_FIFO_BRAM; - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; - USE_CHECKSUM : integer range 0 to 1 := c_YES; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; - REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; - MED_ERROR_IN : in std_logic_vector (2 downto 0); - -- Internal direction port - INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - INT_INIT_DATAREADY_OUT : out std_logic; - INT_INIT_READ_IN : in std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0); - INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_READ_IN : in std_logic; - INT_ERROR_OUT : out std_logic_vector (2 downto 0); - -- Status and control port - STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0); - STAT_DATA_COUNTER : out std_logic_vector (31 downto 0); - STAT_BUFFER : out std_logic_vector (31 downto 0); - CTRL_STAT : in std_logic_vector (15 downto 0) - ); - end component; - - - - - - - component fifo_36x512 is - port ( - Data: in std_logic_vector(35 downto 0); - Clock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - Q: out std_logic_vector(35 downto 0); - Empty: out std_logic; - Full: out std_logic - ); - end component; - - - --component fifo_var_oreg is - --generic( - --FIFO_WIDTH : integer range 1 to 64 := 36; - --FIFO_DEPTH : integer range 1 to 16 := 8 - --); - --port( - --Data : in std_logic_vector(FIFO_WIDTH-1 downto 0); - --Clock : in std_logic; - --WrEn : in std_logic; - --RdEn : in std_logic; - --Reset : in std_logic; - --AmFullThresh : in std_logic_vector(FIFO_DEPTH-1 downto 0); - --Q : out std_logic_vector(FIFO_WIDTH-1 downto 0); - --WCNT : out std_logic_vector(FIFO_DEPTH downto 0); - --Empty : out std_logic; - --Full : out std_logic; - --AlmostFull : out std_logic - --); - --end component; - - - - component trb_net16_iobuf is - generic ( - IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; - IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - SBUF_VERSION_OBUF : integer range 0 to 6 := std_SBUF_VERSION; - OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; - USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; - USE_CHECKSUM : integer range 0 to 1 := c_YES; - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; - REPLY_CAN_RECEIVE_DATA: integer range 0 to 1 := c_YES; - INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; - REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_INIT_DATAREADY_OUT : out std_logic; - MED_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_INIT_READ_IN : in std_logic; - MED_REPLY_DATAREADY_OUT : out std_logic; - MED_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_REPLY_READ_IN : in std_logic; - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; - MED_ERROR_IN : in std_logic_vector (2 downto 0); - -- Internal direction port - INT_INIT_DATAREADY_OUT : out std_logic; - INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_IN : in std_logic; - INT_INIT_DATAREADY_IN : in std_logic; - INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_INIT_READ_OUT : out std_logic; - INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_IN : in std_logic; - INT_REPLY_DATAREADY_IN : in std_logic; - INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - INT_REPLY_READ_OUT : out std_logic; - -- Status and control port - STAT_GEN : out std_logic_vector (31 downto 0); - STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); - CTRL_GEN : in std_logic_vector (31 downto 0); - CTRL_OBUF_settings : in std_logic_vector (31 downto 0) := (others => '0'); - STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0); - STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0); - STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0); - STAT_DATA_COUNTER : out std_logic_vector (31 downto 0); - TIMER_TICKS_IN : in std_logic_vector (1 downto 0); - CTRL_STAT : in std_logic_vector (15 downto 0) - ); - end component; - - - - - - - component trb_net16_io_multiplexer is - generic( - USE_INPUT_SBUF : multiplexer_config_t := (others => c_NO) - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN : in STD_LOGIC; - MED_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out STD_LOGIC; - MED_DATAREADY_OUT : out STD_LOGIC; - MED_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - MED_READ_IN : in STD_LOGIC; - -- Internal direction port - INT_DATA_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); - INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); - INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); - INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); - INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); - INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); - -- Status and control port - CTRL : in STD_LOGIC_VECTOR (31 downto 0); - STAT : out STD_LOGIC_VECTOR (31 downto 0) - ); - end component; - - - - - - component trb_net16_ipudata is - generic( - DO_CHECKS : integer range c_NO to c_YES := c_YES - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Port to API - API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); - API_DATAREADY_OUT : out std_logic; - API_READ_IN : in std_logic; - API_SHORT_TRANSFER_OUT : out std_logic; - API_DTYPE_OUT : out std_logic_vector (3 downto 0); - API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); - API_SEND_OUT : out std_logic; - -- Receiver port - API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - API_TYP_IN : in std_logic_vector (2 downto 0); - API_DATAREADY_IN : in std_logic; - API_READ_OUT : out std_logic; - -- APL Control port - API_RUN_IN : in std_logic; - API_SEQNR_IN : in std_logic_vector (7 downto 0); - API_LENGTH_OUT : out std_logic_vector (15 downto 0); - MY_ADDRESS_IN : in std_logic_vector (15 downto 0); - - --Information received with request - IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); - IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); - IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); - IPU_CODE_OUT : out std_logic_vector (7 downto 0); - --start strobe - IPU_START_READOUT_OUT: out std_logic; - --detector data, equipped with DHDR - IPU_DATA_IN : in std_logic_vector (31 downto 0); - IPU_DATAREADY_IN : in std_logic; - --no more data, end transfer, send TRM - IPU_READOUT_FINISHED_IN : in std_logic; - --will be low every second cycle due to 32bit -> 16bit conversion - IPU_READ_OUT : out std_logic; - IPU_LENGTH_IN : in std_logic_vector (15 downto 0); - IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); - - STAT_DEBUG : out std_logic_vector(31 downto 0) - ); - end component; + + + + component trb_net16_io_multiplexer is + generic( + USE_INPUT_SBUF : multiplexer_config_t := (others => c_NO) + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + -- Internal direction port + INT_DATA_OUT : out std_logic_vector (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT : out std_logic_vector (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_DATAREADY_IN : in std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT : out std_logic_vector (2**c_MUX_WIDTH-1 downto 0); + -- Status and control port + CTRL : in std_logic_vector (31 downto 0); + STAT : out std_logic_vector (31 downto 0) + ); + end component; + + + + + + component trb_net16_ipudata is + generic( + DO_CHECKS : integer range c_NO to c_YES := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Port to API + API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_DATAREADY_OUT : out std_logic; + API_READ_IN : in std_logic; + API_SHORT_TRANSFER_OUT : out std_logic; + API_DTYPE_OUT : out std_logic_vector (3 downto 0); + API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + API_SEND_OUT : out std_logic; + -- Receiver port + API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_TYP_IN : in std_logic_vector (2 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + -- APL Control port + API_RUN_IN : in std_logic; + API_SEQNR_IN : in std_logic_vector (7 downto 0); + API_LENGTH_OUT : out std_logic_vector (15 downto 0); + MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + + --Information received with request + IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); + IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); + IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + IPU_CODE_OUT : out std_logic_vector (7 downto 0); + --start strobe + IPU_START_READOUT_OUT : out std_logic; + --detector data, equipped with DHDR + IPU_DATA_IN : in std_logic_vector (31 downto 0); + IPU_DATAREADY_IN : in std_logic; + --no more data, end transfer, send TRM + IPU_READOUT_FINISHED_IN : in std_logic; + --will be low every second cycle due to 32bit -> 16bit conversion + IPU_READ_OUT : out std_logic; + IPU_LENGTH_IN : in std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + + STAT_DEBUG : out std_logic_vector(31 downto 0) + ); + end component; -- -- component trb_net16_gbe_buf is -- generic(