From: Jan Michel Date: Thu, 9 Nov 2017 14:01:35 +0000 (+0100) Subject: fix media interface in TRB3sc CTS X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=bbe7f810bf8c856e3970c7a334fdd795ecbfbd01;p=trb3sc.git fix media interface in TRB3sc CTS --- diff --git a/cts/trb3sc_cts.lpf b/cts/trb3sc_cts.lpf index fe8dd87..15546ca 100644 --- a/cts/trb3sc_cts.lpf +++ b/cts/trb3sc_cts.lpf @@ -5,8 +5,11 @@ # LOCATE COMP "gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST" SITE "PCSD" ; LOCATE COMP "gen_PCSB.THE_MEDIA_PCSB/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB"; +LOCATE COMP "gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC"; LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD"; + + REGION "MEDIA_DOWN1" "R102C40D" 13 100; #LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_DOWN1" ; #LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; @@ -14,6 +17,7 @@ REGION "MEDIA_DOWN1" "R102C40D" 13 100; #LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_DOWN1" ; #LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_DOWN1" ; LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; +LOCATE UGROUP "gen_PCSC.THE_MEDIA_PCSC/media_interface_group" REGION "MEDIA_DOWN1" ; FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; @@ -35,6 +39,13 @@ BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_write_i"; BLOCK PATH TO CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i"; BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i"; # +MULTICYCLE TO CELL "gen_PCSC.THE_MEDIA_PCSC/sci*" 20 ns; +MULTICYCLE FROM CELL "gen_PCSC.THE_MEDIA_PCSC/sci*" 20 ns; +MULTICYCLE TO CELL "gen_PCSC.THE_MEDIA_PCSC/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_write_i"; +BLOCK PATH FROM CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_write_i"; +BLOCK PATH TO CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_read_i"; +BLOCK PATH FROM CLKNET "gen_PCSC.THE_MEDIA_PCSC/sci_read_i"; #MULTICYCLE TO CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci*" 20 ns; #MULTICYCLE FROM CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci*" 20 ns; #MULTICYCLE TO CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/PROC_SCI_CTRL.wa*" 20 ns; @@ -66,6 +77,9 @@ BLOCK PATH FROM CLKNET "gen_PCSB.THE_MEDIA_PCSB/sci_read_i"; MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; MAXDELAY TO ASIC gen_PCSB.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; # +MULTICYCLE TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MAXDELAY TO ASIC gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; + #MULTICYCLE TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; #MAXDELAY TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; # diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj index fb474e9..f320377 100644 --- a/cts/trb3sc_cts.prj +++ b/cts/trb3sc_cts.prj @@ -65,6 +65,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" #Basic Infrastructure add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd" add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd" add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd" add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd" add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd" diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 54955e5..7ef0714 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -232,6 +232,8 @@ architecture trb3sc_arch of trb3sc_cts is signal cts_ipu_status_bits : std_logic_vector(31 downto 0); signal cts_ipu_busy : std_logic; + signal reset_via_gbe_long, reset_via_gbe_timer, last_reset_via_gbe_long, make_reset : std_logic; + attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; attribute syn_keep of bussci1_rx : signal is true; @@ -253,7 +255,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler EXT_CLK_IN => CLK_EXT_PLL_LEFT, NET_CLK_FULL_IN => '0', NET_CLK_HALF_IN => '0', - RESET_FROM_NET => reset_via_gbe, + RESET_FROM_NET => make_reset, BUS_RX => bustc_rx, BUS_TX => bustc_tx, @@ -273,6 +275,20 @@ THE_CLOCK_RESET : entity work.clock_reset_handler ); + make_reset : process begin + wait until rising_edge(clk_sys); + if(reset_via_gbe = '1') then + reset_via_gbe_long <= '1'; + reset_via_gbe_timer <= '1'; + end if; + if timer_ticks(0) = '1' then + reset_via_gbe_timer <= '0'; + reset_via_gbe_long <= reset_via_gbe_timer; + end if; + last_reset_via_gbe_long <= reset_via_gbe_long; + make_reset <= last_reset_via_gbe_long and not reset_via_gbe_long; + end process; + --------------------------------------------------------------------------- -- PCSA --------------------------------------------------------------------------- @@ -327,7 +343,8 @@ end generate; -- bussci3_tx.ack <= '0'; -- bussci3_tx.nack <= '0'; -- bussci3_tx.unknown <= '1'; - THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_4 +gen_PCSC : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate + THE_MEDIA_PCSC : entity work.med_ecp3_sfp_sync_4 generic map( IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), IS_USED => (c_YES,c_YES ,c_YES ,c_YES) @@ -379,14 +396,11 @@ end generate; STAT_DEBUG => open, --med_stat_debug(63 downto 0), CTRL_DEBUG => open ); - +end generate; --------------------------------------------------------------------------- --- PCSD GBE ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- --- GbE +-- GbE (PCSD) --------------------------------------------------------------------------- GBE : entity work.gbe_wrapper generic map( @@ -420,7 +434,7 @@ end generate; RESET => reset_i, GSR_N => GSR_N, - TRIGGER_IN => '0', + TRIGGER_IN => cts_rdo_trg_data_valid, SD_PRSNT_N_IN(0) => SFP_MOD0(0), SD_LOS_IN(0) => SFP_LOS(0), @@ -486,8 +500,8 @@ end generate; USE_ONEWIRE => c_YES, BROADCAST_SPECIAL_ADDR => x"35", RDO_ADDITIONAL_PORT => cts_rdo_additional_ports, - RDO_DATA_BUFFER_DEPTH => 9, - RDO_DATA_BUFFER_FULL_THRESH => 2**9-128, + RDO_DATA_BUFFER_DEPTH => 10, + RDO_DATA_BUFFER_FULL_THRESH => 2**9-2, RDO_HEADER_BUFFER_DEPTH => 9, RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16 ) @@ -853,11 +867,11 @@ end generate; --- gen_hub_leds : for i in 1 to 4 generate --- LED_HUB_LINKOK(i) <= not med2int(i).stat_op(9); --- LED_HUB_TX(i) <= not (med2int(i).stat_op(10) or not med2int(i).stat_op(9)); --- LED_HUB_RX(i) <= not (med2int(i).stat_op(11)); --- end generate; +gen_hub_leds : for i in 1 to 4 generate + LED_HUB_LINKOK(i) <= not med2int(i).stat_op(9); + LED_HUB_TX(i) <= not (med2int(i).stat_op(10) or not med2int(i).stat_op(9)); + LED_HUB_RX(i) <= not (med2int(i).stat_op(11)); +end generate; -- LED_HUB_LINKOK(8) <= not med2int(7).stat_op(9) when INCLUDE_GBE = 0 else -- '1';