From: hadaq <hadaq>
Date: Fri, 30 Mar 2012 14:17:18 +0000 (+0000)
Subject: anti/concidence logic cntrl update (bit 17-16 in CO)
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=bc3d39da519afc72229286b217783f9a12a858e3;p=daqdocu.git

anti/concidence logic cntrl update (bit 17-16 in CO)
---

diff --git a/cts.tex b/cts.tex
index 9d78ebd..3024fc9 100644
--- a/cts.tex
+++ b/cts.tex
@@ -28,7 +28,7 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
      \item[Bit 10] Disable all triggers
      \item[Bit 14] Enable beam inhibit for generation of Shower trigger - look into beam inhibit signal settings register 0xA0D9
      \item[Bit 15] Enable beam inhibit to make system silent when there is no beam (only cal trigger are accepted) - look into beam inhibit signal settings register 0xA0DD
-     \item[Bit 16] Enable TOF/RPC multiplicity signals to be treated as a Start signal see  Fig.\ref{cts_logic}
+     \item[Bit 17--16] If 0 then only START is used for coincidence logic, if 1 then also VETO is used for anticoincidence, if 2 enable TOF/RPC multiplicity signals to be treated as a Start signal see  Fig.\ref{cts_logic}
      \item[Bit 23 -- 20] Set width for VETO signal used for anti coincidence logic - $value * 1.25\,ns$
      \item[Bit 28 -- 29] not used  
      \item[Bit 30] When set to '1' it generates RICH special APV trigger (double pulse on RICH connector) - edge sensitive 0 -> 1