From: Michael Boehmer Date: Fri, 1 Jul 2022 21:57:05 +0000 (+0200) Subject: Gbe hub rising... X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=bdcd68de79ebe33d4b6c67e581439c43fdf1bfb5;p=trb3sc.git Gbe hub rising... --- diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index 617dc29..af6cad3 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -14,14 +14,9 @@ entity clock_reset_handler is port( INT_CLK_IN : in std_logic; -- oscillator EXT_CLK_IN : in std_logic; -- external clock input - NET_CLK_FULL_IN : in std_logic; -- TO BE REMOVED - NET_CLK_HALF_IN : in std_logic; -- TO BE REMOVED GLOBAL_RESET_IN : in std_logic; -- from Link Layer RESET_FROM_NET_IN : in std_logic := '0'; -- stat_op(13) - BUS_RX : in CTRLBUS_RX; -- NOT USED - BUS_TX : out CTRLBUS_TX; -- NOT USED - RESET_OUT : out std_logic; -- active high CLEAR_OUT : out std_logic; -- active high GSR_OUT : out std_logic; -- active low @@ -222,18 +217,11 @@ RESET_OUT <= reset_i; LOCK => open ); -DEBUG_OUT(0) <= pll_int_lock; -DEBUG_OUT(1) <= clear_n_i; -DEBUG_OUT(13 downto 2) <= debug_reset_handler(13 downto 2); -DEBUG_OUT(14) <= pll_ext_lock; -DEBUG_OUT(15) <= clock_select; +DEBUG_OUT(0) <= pll_int_lock; +DEBUG_OUT(1) <= clear_n_i; +DEBUG_OUT(13 downto 2) <= debug_reset_handler(13 downto 2); +DEBUG_OUT(14) <= pll_ext_lock; +DEBUG_OUT(15) <= clock_select; DEBUG_OUT(31 downto 16) <= (others => '0'); -BUS_TX.data <= (others => '0'); -BUS_TX.unknown <= '1'; -BUS_TX.ack <= '0'; -BUS_TX.nack <= '0'; -BUS_TX.rack <= '0'; -BUS_TX.wack <= '0'; - end architecture; diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 5ddf8e7..94b4d2e 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -489,10 +489,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate port map ( CLEAR => init_quad, CLK_REF => link_clock, - TX_PLL_LOL_QD_A_IN => '0', - TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i, - TX_PLL_LOL_QD_C_IN => '0', - TX_PLL_LOL_QD_D_IN => '0', + TX_PLL_LOL_IN => tx_pll_lol_qd_b_i, TX_CLOCK_AVAIL_IN => '1', TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i, SYNC_TX_QUAD_OUT => sync_tx_quad_i, diff --git a/hub/gbe_hub/config.vhd b/hub/gbe_hub/config.vhd new file mode 100644 index 0000000..990f82e --- /dev/null +++ b/hub/gbe_hub/config.vhd @@ -0,0 +1,174 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; +use work.trb_net16_hub_func.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + +--design options: backplane or front SFP, with or without GBE + constant USE_BACKPLANE : integer := c_YES; + constant INCLUDE_GBE : integer := c_NO; + +--We want an ECP3 + constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 + +-- Link speed + constant LINK_SPEED : integer := 125; -- 125: 1.25Gbps, 200: 2.00Gbps + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + constant USE_200MHZOSCILLATOR : integer := c_YES; + constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; -- DEPRECIATED + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"d00f"; + + constant INCLUDE_UART : integer := c_YES; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_LCD : integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_NO; + constant TRIG_GEN_INPUT_NUM : integer := 0; + constant TRIG_GEN_OUTPUT_NUM : integer := 0; + constant MONITOR_INPUT_NUM : integer := 0; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := ( + x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch + x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + + x"48", x"75", x"62", x"41", x"64", x"64", x"4f", x"6e", x"0a", + x"0a", + x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a", + x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a", + x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a", + others => x"00"); + + + +--With GbE: +-- for MII_NUMBER=5 (4 downlinks, 1 uplink): +-- port 0,1,2,3: downlinks to other FPGA +-- port MII-1: LVL1/Data channel on uplink to CTS, but internal endpoint on SCTRL +-- port MII: SCTRL channel on uplink to CTS +-- port MII+1: SCTRL channel from GbE interface + +--With no GbE: +-- for MII_NUMBER=5 (4 downlinks, 1 uplink): +-- port 0,1,2,3: downlinks to other FPGA +-- port 4: uplink +-- port 5: internal endpoint on SCTRL + + + type hub_mii_t is array(0 to 3) of integer; + type hub_ct is array(0 to 16) of integer; + type hub_cfg_t is array(0 to 3) of hub_ct; + type hw_info_t is array(0 to 3) of std_logic_vector(31 downto 0); + type intlist_t is array(0 to 7) of integer; + + + --order: no backplane, no GBE 8x AddOn, SFP downlink, SFP uplink + -- backplane, no GBE 8x AddOn, 2x SFP downlink, backplane uplink + -- no backplane, GBE 7x AddOn, 1x SFP uplink, GBE sctrl + -- backplane, GBE 8x AddOn, backplane uplink, GBE sctrl + + constant INTERFACE_NUM_ARR : hub_mii_t := (10,11,8,9); +-- 0 1 2 3 4 5 6 7 8 9 a b c d e f + constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0), + (0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0)); + constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1,1,1,1,1,1,0,1,0,0,0,0,0,0), + (1,1,1,1,1,1,1,1,1,1,0,1,0,0,0,0,0), + (1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0), + (1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0)); + constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0)); + + constant INTERFACE_NUM : integer; + constant IS_UPLINK : hub_ct; + constant IS_DOWNLINK : hub_ct; + constant IS_UPLINK_ONLY : hub_ct; + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + + constant HW_INFO_BASE : unsigned(31 downto 0) := x"9500A000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + constant BROADCAST_SPECIAL_ADDR : std_logic_vector; + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + constant CFG_MODE : integer := INCLUDE_GBE*2 + USE_BACKPLANE; + + constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE); + constant IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE); + constant IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE); + constant IS_UPLINK_ONLY : hub_ct := IS_UPLINK_ONLY_ARR(CFG_MODE); + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := std_logic_vector(to_unsigned(100+CFG_MODE,8)); + + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 + if INCLUDE_GBE = c_YES then + t(22 downto 16) := "0100111"; --sctrl via GbE + end if; + t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); + t(27 downto 24) := std_logic_vector(to_unsigned(INTERFACE_NUM-USE_BACKPLANE,4)); --num SFPs with TrbNet + t(28 downto 28) := std_logic_vector(to_unsigned(USE_BACKPLANE,1)); + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + t(55 downto 55) := std_logic_vector(to_unsigned(USE_200MHZOSCILLATOR,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/hub/gbe_hub/config_compile_frankfurt.pl b/hub/gbe_hub/config_compile_frankfurt.pl new file mode 100644 index 0000000..6aa6e41 --- /dev/null +++ b/hub/gbe_hub/config_compile_frankfurt.pl @@ -0,0 +1,20 @@ +TOPNAME => "trb3sc_hub", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', +synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1', +#synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/', +#synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", +#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", + +nodelist_file => 'nodelist_frankfurt.txt', + + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, diff --git a/hub/gbe_hub/config_compile_gsi.pl b/hub/gbe_hub/config_compile_gsi.pl new file mode 100644 index 0000000..3296cf7 --- /dev/null +++ b/hub/gbe_hub/config_compile_gsi.pl @@ -0,0 +1,19 @@ +TOPNAME => "trb3sc_gbe_hub", +lm_license_file_for_synplify => "27000\@lxcad04.gsi.de", +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/opt/lattice/diamond/3.12', +synplify_path => '/opt/synplicity/R-2020.09-SP1', +synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier", + +nodelist_file => 'nodelist.txt', +#pinout_file => '', +par_options => '../par.p2t', +mapper_options => '-u -retime -split_node', + +include_TDC => 0, +include_GBE => 0, + +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 0, #if there is no serdes being used + diff --git a/hub/gbe_hub/nodelist.txt b/hub/gbe_hub/nodelist.txt new file mode 100644 index 0000000..a99f562 --- /dev/null +++ b/hub/gbe_hub/nodelist.txt @@ -0,0 +1,8 @@ +// nodes file for parallel place&route + +[hades66] +system = linux +corenum = 24 +ENV = /home/compile/bin/diamond_env +workdir = /home/compile/vhdl/dirich/dirich/workdir + diff --git a/hub/gbe_hub/par.p2t b/hub/gbe_hub/par.p2t new file mode 100644 index 0000000..8b65fde --- /dev/null +++ b/hub/gbe_hub/par.p2t @@ -0,0 +1,66 @@ +-w +-l 5 +-s 12 +-t 34 # seed setting here! # 32 +-c 1 +-e 2 +-i 15 +-y +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR= +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help + diff --git a/hub/gbe_hub/trb3sc_hub.lpf b/hub/gbe_hub/trb3sc_hub.lpf new file mode 100644 index 0000000..c08b9c4 --- /dev/null +++ b/hub/gbe_hub/trb3sc_hub.lpf @@ -0,0 +1,48 @@ +# locate the PCS blocks +LOCATE COMP "gen_PCSA.THE_MEDIA_PCSA/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSA"; +LOCATE COMP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSB"; +LOCATE COMP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSB"; +LOCATE COMP "THE_MEDIA_4_PCSC/THE_SERDES/gen_SERDES.PCSD_INST" SITE "PCSC"; +LOCATE COMP "gen_PCSD.THE_MEDIA_4_PCSD/gen_SERDES.THE_SERDES/PCSD_INST" SITE "PCSD"; +LOCATE COMP "gen_GBE.GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD"; + +# locate the media interfaces inside fabric +REGION "MEDIA_LEFT" "R102C17D" 13 75; # LEFT is for PCSD/PCSB +REGION "MEDIA_RIGHT" "R102C92D" 13 75; # RIGHT is for PCSA/PCSC +LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_RIGHT"; +LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_LEFT"; +LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_LEFT"; +LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_RIGHT"; +LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_LEFT"; + +# primary nets +USE PRIMARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[0]"; +USE PRIMARY NET "THE_MEDIA_4_PCSC/clk_rx_full[0]"; +USE PRIMARY NET "gen_PCSD.THE_MEDIA_4_PCSD/clk_rx_full[0]"; + +# secondary nets +USE SECONDARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[1]"; +USE SECONDARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[2]"; +USE SECONDARY NET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/clk_rx_full[3]"; +USE SECONDARY NET "THE_MEDIA_4_PCSC/clk_rx_full[1]"; +USE SECONDARY NET "THE_MEDIA_4_PCSC/clk_rx_full[2]"; +USE SECONDARY NET "THE_MEDIA_4_PCSC/clk_rx_full[3]"; +USE SECONDARY NET "gen_PCSD.THE_MEDIA_4_PCSD/clk_rx_full[1]"; + +# read from SCI can be delayed due to long read strobe +# write strobe can be delayed due to A/D being stable after access +MULTICYCLE FROM ASIC gen_PCSA.THE_MEDIA_PCSA/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE TO ASIC gen_PCSA.THE_MEDIA_PCSA/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; +MULTICYCLE FROM ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE TO ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; +MULTICYCLE FROM ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; +MULTICYCLE FROM ASIC THE_MEDIA_4_PCSC/THE_SERDES/gen_SERDES.PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/gen_SERDES.PCSD_INST PIN SCIWSTN 15 ns; +MULTICYCLE FROM ASIC gen_PCSD.THE_MEDIA_4_PCSD/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns; +MULTICYCLE TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns; + +################################ + +FREQUENCY NET "gen_GBE.GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; +FREQUENCY NET "gen_GBE.GBE/clk_125_rx_from_pcs[3]" 125 MHz; diff --git a/hub/gbe_hub/trb3sc_hub.prj b/hub/gbe_hub/trb3sc_hub.prj new file mode 100644 index 0000000..b29cb87 --- /dev/null +++ b/hub/gbe_hub/trb3sc_hub.prj @@ -0,0 +1,257 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN1156C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3sc_gbe_hub" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3sc_gbe_hub.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd" +add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd" +add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" +add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/ram_18x256_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.vhd" + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +#Hub +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_accel.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_accel.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" +add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd" + + +#GbE +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v" + +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x72.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2048x8x16.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_65536x18x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/ip_mem.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd" + + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + + + + +add_file -vhdl -lib work "./trb3sc_hub.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/hub/gbe_hub/trb3sc_hub.vhd b/hub/gbe_hub/trb3sc_hub.vhd new file mode 100644 index 0000000..03201a3 --- /dev/null +++ b/hub/gbe_hub/trb3sc_hub.vhd @@ -0,0 +1,970 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.trb_net16_hub_func.all; +use work.version.all; +use work.trb_net_gbe_components.all; +use work.med_sync_define_RS.all; + +entity trb3sc_gbe_hub is + port( + CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE + CLK_CORE_PCLK : in std_logic; --Main Oscillator + CLK_EXT_PLL_LEFT : in std_logic; --External Clock + --Additional IO +-- HDR_IO : inout std_logic_vector(10 downto 1); + BACK_LVDS : inout std_logic_vector( 1 downto 0); + BACK_GPIO : inout std_logic_vector( 3 downto 0); + --LED + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector( 1 downto 0); + LED_RJ_RED : out std_logic_vector( 1 downto 0); + LED_WHITE : out std_logic_vector( 1 downto 0); + LED_SFP_GREEN : out std_logic_vector( 1 downto 0); + LED_SFP_RED : out std_logic_vector( 1 downto 0); + --SFP + SFP_LOS : in std_logic_vector( 1 downto 0); + SFP_MOD0 : in std_logic_vector( 1 downto 0); + SFP_MOD1 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); + SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); + SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0'); + LED_HUB_LINKOK : out std_logic_vector(8 downto 1); + LED_HUB_RX : out std_logic_vector(8 downto 1); + LED_HUB_TX : out std_logic_vector(8 downto 1); + HUB_MOD0 : in std_logic_vector(8 downto 1); + HUB_MOD1 : inout std_logic_vector(8 downto 1); + HUB_MOD2 : inout std_logic_vector(8 downto 1); + HUB_TXDIS : out std_logic_vector(8 downto 1); + HUB_LOS : in std_logic_vector(8 downto 1); + --Serdes switch + PCSSW_ENSMB : out std_logic; + PCSSW_EQ : out std_logic_vector( 3 downto 0); + PCSSW_PE : out std_logic_vector( 3 downto 0); + PCSSW : out std_logic_vector( 7 downto 0); + --ADC + ADC_CLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; + --Flash, 1-wire, Reload + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + PROGRAMN : out std_logic; + ENPIRION_CLOCK : out std_logic; + TEMPSENS : inout std_logic + --Test Connectors +-- TEST_LINE : out std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_IN : signal is true; + attribute syn_useioff of FLASH_OUT : signal is true; + +end entity; + +architecture trb3sc_arch of trb3sc_gbe_hub is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal do_reboot_i, reboot_from_gbe : std_logic; + signal external_reset_i : std_logic; + + signal time_counter : unsigned(31 downto 0) := (others => '0'); + signal led : std_logic_vector(1 downto 0); + signal debug_clock_reset : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 10); + signal int2med : int2med_array_t(0 to 10); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + + signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bussci4_rx, bustools_rx, + bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX; + signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bussci4_tx, bustools_tx, + bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal bus_master_active : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal uart_tx, uart_rx : std_logic; + + signal timer : TIMERS; + signal lcd_data : std_logic_vector(511 downto 0); + + signal cts_number : std_logic_vector(15 downto 0); + signal cts_code : std_logic_vector(7 downto 0); + signal cts_information : std_logic_vector(7 downto 0); + signal cts_start_readout : std_logic; + signal cts_readout_type : std_logic_vector(3 downto 0); + signal cts_data : std_logic_vector(31 downto 0); + signal cts_dataready : std_logic; + signal cts_readout_finished : std_logic; + signal cts_read : std_logic; + signal cts_length : std_logic_vector(15 downto 0); + signal cts_status_bits : std_logic_vector(31 downto 0); + signal fee_data : std_logic_vector(15 downto 0); + signal fee_dataready : std_logic; + signal fee_read : std_logic; + signal fee_status_bits : std_logic_vector(31 downto 0); + signal fee_busy : std_logic; + signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0); + signal gsc_init_read, gsc_reply_read : std_logic; + signal gsc_init_dataready, gsc_reply_dataready : std_logic; + signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); + signal gsc_busy : std_logic; + signal my_address : std_logic_vector(15 downto 0); + signal mc_unique_id : std_logic_vector(63 downto 0); + signal reset_via_gbe : std_logic := '0'; + + signal med_dataready_out : std_logic_vector (11-1 downto 0); + signal med_data_out : std_logic_vector (11*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_out : std_logic_vector (11*c_NUM_WIDTH-1 downto 0); + signal med_read_in : std_logic_vector (11-1 downto 0); + signal med_dataready_in : std_logic_vector (11-1 downto 0); + signal med_data_in : std_logic_vector (11*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_in : std_logic_vector (11*c_NUM_WIDTH-1 downto 0); + signal med_read_out : std_logic_vector (11-1 downto 0); + signal med_stat_op : std_logic_vector (11*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (11*16-1 downto 0); + signal rdack, wrack : std_logic; + + signal trig_gen_out_i : std_logic_vector(3 downto 0); + signal monitor_inputs_i : std_logic_vector(17 downto 0); + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + attribute syn_keep of bussci1_rx : signal is true; + attribute syn_preserve of bussci1_rx : signal is true; + attribute syn_keep of bustools_rx : signal is true; + attribute syn_preserve of bustools_rx : signal is true; + attribute syn_keep of bustc_rx : signal is true; + attribute syn_preserve of bustc_rx : signal is true; + + signal word_sync_i : std_logic; + signal master_clk_i : std_logic; + signal global_reset_i : std_logic; + signal tx_pll_lol_qd_a_i : std_logic; + signal tx_pll_lol_qd_b_i : std_logic; + signal tx_pll_lol_qd_c_i : std_logic; + signal tx_pll_lol_qd_d_i : std_logic; + signal tx_clk_avail_i : std_logic; + signal tx_pcs_rst_i : std_logic; + signal sync_tx_quad_i : std_logic; + signal link_tx_ready_i : std_logic; + signal rx_dlm_i : std_logic; + signal tx_reset_state : std_logic_vector(3 downto 0); + signal debug_i : std_logic_vector(31 downto 0); + + signal send_rst_i : std_logic; + signal send_rst_word_i : std_logic_vector(7 downto 0); + signal send_dlm_word_i : std_logic_vector(7 downto 0); + + signal init_quad : std_logic; + signal link_clock : std_logic; + +begin +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- +THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + INT_CLK_IN => CLK_CORE_PCLK, + EXT_CLK_IN => CLK_EXT_PLL_LEFT, + NET_CLK_FULL_IN => med2int(INTERFACE_NUM-1).clk_full, + NET_CLK_HALF_IN => med2int(INTERFACE_NUM-1).clk_half, + GLOBAL_RESET_IN => global_reset_i, + RESET_FROM_NET_IN => '0', + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + RESET_OUT => reset_i, + CLEAR_OUT => open, + GSR_OUT => GSR_N, + FULL_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + REF_CLK_OUT => clk_full_osc, + ENPIRION_CLOCK => ENPIRION_CLOCK, + LED_RED_OUT => LED_RJ_RED, + LED_GREEN_OUT => LED_RJ_GREEN, + DEBUG_OUT => debug_clock_reset + ); + + init_quad <= not GSR_N; + + -- select link speed, wrong values are catched in media interface + link_clock <= CLK_SUPPL_PCLK when (LINK_SPEED = 125) else + clk_full_osc when (LINK_SPEED = 200) else + '0'; + +--------------------------------------------------------------------------- +-- PCSA: Uplink when backplane is used +--------------------------------------------------------------------------- +gen_PCSA : if USE_BACKPLANE = c_YES generate + THE_MEDIA_PCSA : entity work.med_ecp3_sfp_sync_all_RS + generic map( + IS_MODE => (c_IS_SLAVE, c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED) + ) + port map( + -- Clocks and reset + CLK_REF_FULL => CLK_SUPPL_PCLK, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => init_quad, + -- Media Interface TX/RX + MEDIA_MED2INT(0) => med2int(INTERFACE_NUM-1), + MEDIA_MED2INT(1 to 3) => open, + MEDIA_INT2MED(0) => int2med(INTERFACE_NUM-1), + MEDIA_INT2MED(1 to 3) => open, + -- komma operation + RX_DLM_OUT(3 downto 1) => open, + RX_DLM_OUT(0) => rx_dlm_i, + RX_DLM_WORD_OUT(31 downto 8) => open, + RX_DLM_WORD_OUT(7 downto 0) => send_dlm_word_i, + TX_DLM_IN => rx_dlm_i, + TX_DLM_WORD_IN => send_dlm_word_i, + RX_RST_OUT => send_rst_i, + RX_RST_WORD_OUT => send_rst_word_i, + TX_RST_IN => '0', + TX_RST_WORD_IN => x"00", + -- sync operation + WORD_SYNC_IN => word_sync_i, + WORD_SYNC_OUT => word_sync_i, + MASTER_CLK_IN => master_clk_i, + MASTER_CLK_OUT => master_clk_i, + LINK_TX_NULL_IN => global_reset_i, + LINK_RX_NULL_OUT => global_reset_i, + TX_PLL_LOL_OUT => tx_pll_lol_qd_a_i, + TX_CLK_AVAIL_OUT => tx_clk_avail_i, + TX_PCS_RST_IN => tx_pcs_rst_i, + SYNC_TX_PLL_IN => sync_tx_quad_i, + LINK_TX_READY_IN => link_tx_ready_i, + DESTROY_LINK_IN => (others => '0'), + WAP_REQUESTED_IN => x"0", + --SFP Connection + SD_PRSNT_N_IN(0) => BACK_GPIO(1), + SD_PRSNT_N_IN(3 downto 1) => (others => '1'), + SD_LOS_IN(0) => BACK_GPIO(1), + SD_LOS_IN(3 downto 1) => (others => '1'), + SD_TXDIS_OUT(0) => BACK_GPIO(0), + SD_TXDIS_OUT(3 downto 1) => open, + --Control Interface + BUS_RX => bussci1_rx, + BUS_TX => bussci1_tx, + -- Status and control port + STAT_DEBUG => open, + CTRL_DEBUG => open, + DEBUG_OUT => debug_i + ); +end generate; + +--------------------------------------------------------------------------- +-- PCSB: TrbNet downlinks (backplane) +--------------------------------------------------------------------------- +gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate + THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_RS + generic map( + IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER) + ) + port map( + -- Clocks and reset + CLK_REF_FULL => link_clock, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => init_quad, + -- Media Interface TX/RX + MEDIA_MED2INT(0) => med2int(4), + MEDIA_MED2INT(1) => med2int(5), + MEDIA_MED2INT(2) => med2int(6), + MEDIA_MED2INT(3) => med2int(9-2*INCLUDE_GBE), + MEDIA_INT2MED(0) => int2med(4), + MEDIA_INT2MED(1) => int2med(5), + MEDIA_INT2MED(2) => int2med(6), + MEDIA_INT2MED(3) => int2med(9-2*INCLUDE_GBE), + -- komma operation + RX_DLM_OUT(0) => open, + RX_DLM_OUT(1) => open, + RX_DLM_OUT(2) => open, + RX_DLM_OUT(3) => open, + RX_DLM_WORD_OUT => open, + TX_DLM_IN => rx_dlm_i, + TX_DLM_WORD_IN => send_dlm_word_i, + RX_RST_OUT => open, + RX_RST_WORD_OUT => open, + TX_RST_IN => send_rst_i, + TX_RST_WORD_IN => send_rst_word_i, + -- sync operation + WORD_SYNC_IN => word_sync_i, + WORD_SYNC_OUT => open, + MASTER_CLK_IN => master_clk_i, + MASTER_CLK_OUT => open, + LINK_TX_NULL_IN => global_reset_i, + LINK_RX_NULL_OUT => open, + TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, + TX_CLK_AVAIL_OUT => open, + TX_PCS_RST_IN => tx_pcs_rst_i, + SYNC_TX_PLL_IN => sync_tx_quad_i, + LINK_TX_READY_IN => link_tx_ready_i, + DESTROY_LINK_IN => (others => '0'), + WAP_REQUESTED_IN => x"0", + --SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(5), + SD_PRSNT_N_IN(1) => HUB_MOD0(6), + SD_PRSNT_N_IN(2) => HUB_MOD0(7), + SD_PRSNT_N_IN(3) => SFP_MOD0(1), + SD_LOS_IN(0) => HUB_LOS(5), + SD_LOS_IN(1) => HUB_LOS(6), + SD_LOS_IN(2) => HUB_LOS(7), + SD_LOS_IN(3) => SFP_LOS(1), + SD_TXDIS_OUT(0) => HUB_TXDIS(5), + SD_TXDIS_OUT(1) => HUB_TXDIS(6), + SD_TXDIS_OUT(2) => HUB_TXDIS(7), + SD_TXDIS_OUT(3) => SFP_TX_DIS(1), + --Control Interface + BUS_RX => bussci2_rx, + BUS_TX => bussci2_tx, + -- Status and control port + STAT_DEBUG => open, + CTRL_DEBUG => open, + DEBUG_OUT => open + ); +end generate; + +--------------------------------------------------------------------------- +-- PCSB: TrbNet one uplink and three downlinks (no backplane) +--------------------------------------------------------------------------- +gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate + THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_all_RS + generic map( + IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_SLAVE) + ) + port map( + -- Clocks and reset + CLK_REF_FULL => link_clock, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => init_quad, + -- Media Interface TX/RX + MEDIA_MED2INT(0) => med2int(4), + MEDIA_MED2INT(1) => med2int(5), + MEDIA_MED2INT(2) => med2int(6), + MEDIA_MED2INT(3) => med2int(INTERFACE_NUM-1), + MEDIA_INT2MED(0) => int2med(4), + MEDIA_INT2MED(1) => int2med(5), + MEDIA_INT2MED(2) => int2med(6), + MEDIA_INT2MED(3) => int2med(INTERFACE_NUM-1), + -- komma operation + RX_DLM_OUT(0) => open, + RX_DLM_OUT(1) => open, + RX_DLM_OUT(2) => open, + RX_DLM_OUT(3) => rx_dlm_i, + RX_DLM_WORD_OUT(23 downto 0) => open, + RX_DLM_WORD_OUT(31 downto 24) => send_dlm_word_i, + TX_DLM_IN => rx_dlm_i, + TX_DLM_WORD_IN => send_dlm_word_i, + RX_RST_OUT => send_rst_i, + RX_RST_WORD_OUT => send_rst_word_i, + TX_RST_IN => send_rst_i, + TX_RST_WORD_IN => send_rst_word_i, + -- sync operation + WORD_SYNC_IN => word_sync_i, + WORD_SYNC_OUT => word_sync_i, + MASTER_CLK_IN => master_clk_i, + MASTER_CLK_OUT => master_clk_i, + LINK_TX_NULL_IN => global_reset_i, + LINK_RX_NULL_OUT => global_reset_i, + TX_PLL_LOL_OUT => tx_pll_lol_qd_b_i, + TX_CLK_AVAIL_OUT => tx_clk_avail_i, + TX_PCS_RST_IN => tx_pcs_rst_i, + SYNC_TX_PLL_IN => sync_tx_quad_i, + LINK_TX_READY_IN => link_tx_ready_i, + DESTROY_LINK_IN => (others => '0'), + WAP_REQUESTED_IN => x"0", + --SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(5), + SD_PRSNT_N_IN(1) => HUB_MOD0(6), + SD_PRSNT_N_IN(2) => HUB_MOD0(7), + SD_PRSNT_N_IN(3) => SFP_MOD0(1), + SD_LOS_IN(0) => HUB_LOS(5), + SD_LOS_IN(1) => HUB_LOS(6), + SD_LOS_IN(2) => HUB_LOS(7), + SD_LOS_IN(3) => SFP_LOS(1), + SD_TXDIS_OUT(0) => HUB_TXDIS(5), + SD_TXDIS_OUT(1) => HUB_TXDIS(6), + SD_TXDIS_OUT(2) => HUB_TXDIS(7), + SD_TXDIS_OUT(3) => SFP_TX_DIS(1), + --Control Interface + BUS_RX => bussci2_rx, + BUS_TX => bussci2_tx, + -- Status and control port + STAT_DEBUG => open, + CTRL_DEBUG => open, + DEBUG_OUT => open + ); + + tx_pll_lol_qd_a_i <= '0'; + +end generate; + + THE_MAIN_TX_RST: main_tx_reset_RS + port map ( + CLEAR => init_quad, + CLK_REF => link_clock, + TX_PLL_LOL_QD_A_IN => tx_pll_lol_qd_a_i, + TX_PLL_LOL_QD_B_IN => tx_pll_lol_qd_b_i, + TX_PLL_LOL_QD_C_IN => tx_pll_lol_qd_c_i, + TX_PLL_LOL_QD_D_IN => tx_pll_lol_qd_d_i, + TX_CLOCK_AVAIL_IN => tx_clk_avail_i, + TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i, + SYNC_TX_QUAD_OUT => sync_tx_quad_i, + LINK_TX_READY_OUT => link_tx_ready_i, + STATE_OUT => tx_reset_state + ); + +--------------------------------------------------------------------------- +-- PCSC: 4 downlinks +--------------------------------------------------------------------------- + THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_all_RS + generic map( + IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER) + ) + port map( + -- Clocks and reset + CLK_REF_FULL => link_clock, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => init_quad, + -- Media Interface TX/RX + MEDIA_MED2INT(0) => med2int(2), + MEDIA_MED2INT(1) => med2int(3), + MEDIA_MED2INT(2) => med2int(0), + MEDIA_MED2INT(3) => med2int(1), + MEDIA_INT2MED(0) => int2med(2), + MEDIA_INT2MED(1) => int2med(3), + MEDIA_INT2MED(2) => int2med(0), + MEDIA_INT2MED(3) => int2med(1), + -- komma operation + RX_DLM_OUT => open, + RX_DLM_WORD_OUT => open, + TX_DLM_IN => rx_dlm_i, + TX_DLM_WORD_IN => send_dlm_word_i, + RX_RST_OUT => open, + RX_RST_WORD_OUT => open, + TX_RST_IN => send_rst_i, + TX_RST_WORD_IN => send_rst_word_i, + -- sync operation + WORD_SYNC_IN => word_sync_i, + WORD_SYNC_OUT => open, + MASTER_CLK_IN => master_clk_i, + MASTER_CLK_OUT => open, + LINK_TX_NULL_IN => global_reset_i, + LINK_RX_NULL_OUT => open, + TX_PLL_LOL_OUT => tx_pll_lol_qd_c_i, + TX_CLK_AVAIL_OUT => open, + TX_PCS_RST_IN => tx_pcs_rst_i, + SYNC_TX_PLL_IN => sync_tx_quad_i, + LINK_TX_READY_IN => link_tx_ready_i, + DESTROY_LINK_IN => (others => '0'), + WAP_REQUESTED_IN => x"0", + --SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(3), + SD_PRSNT_N_IN(1) => HUB_MOD0(4), + SD_PRSNT_N_IN(2) => HUB_MOD0(1), + SD_PRSNT_N_IN(3) => HUB_MOD0(2), + SD_LOS_IN(0) => HUB_LOS(3), + SD_LOS_IN(1) => HUB_LOS(4), + SD_LOS_IN(2) => HUB_LOS(1), + SD_LOS_IN(3) => HUB_LOS(2), + SD_TXDIS_OUT(0) => HUB_TXDIS(3), + SD_TXDIS_OUT(1) => HUB_TXDIS(4), + SD_TXDIS_OUT(2) => HUB_TXDIS(1), + SD_TXDIS_OUT(3) => HUB_TXDIS(2), + --Control Interface + BUS_RX => bussci3_rx, + BUS_TX => bussci3_tx, + -- Status and control port + STAT_DEBUG => open, + CTRL_DEBUG => open, + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- PCSD: 2 downlinks (no GbE) +--------------------------------------------------------------------------- +gen_PCSD : if INCLUDE_GBE = c_NO generate + THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_all_RS + generic map( + IS_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_UNUSED, c_IS_UNUSED) + ) + port map( + -- Clocks and reset + CLK_REF_FULL => link_clock, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => init_quad, + -- Media Interface TX/RX + MEDIA_MED2INT(0) => med2int(8), + MEDIA_MED2INT(1) => med2int(7), + MEDIA_MED2INT(2) => open, + MEDIA_MED2INT(3) => open, + MEDIA_INT2MED(0) => int2med(8), + MEDIA_INT2MED(1) => int2med(7), + MEDIA_INT2MED(2) => open, + MEDIA_INT2MED(3) => open, + -- komma operation + RX_DLM_OUT => open, + RX_DLM_WORD_OUT => open, + TX_DLM_IN => rx_dlm_i, + TX_DLM_WORD_IN => send_dlm_word_i, + RX_RST_OUT => open, + RX_RST_WORD_OUT => open, + TX_RST_IN => send_rst_i, + TX_RST_WORD_IN => send_rst_word_i, + -- sync operation + WORD_SYNC_IN => word_sync_i, + WORD_SYNC_OUT => open, + MASTER_CLK_IN => master_clk_i, + MASTER_CLK_OUT => open, + LINK_TX_NULL_IN => global_reset_i, + LINK_RX_NULL_OUT => open, + TX_PLL_LOL_OUT => tx_pll_lol_qd_d_i, + TX_CLK_AVAIL_OUT => open, + TX_PCS_RST_IN => tx_pcs_rst_i, + SYNC_TX_PLL_IN => sync_tx_quad_i, + LINK_TX_READY_IN => link_tx_ready_i, + DESTROY_LINK_IN => (others => '0'), + WAP_REQUESTED_IN => x"0", + --SFP Connection + SD_PRSNT_N_IN(0) => SFP_MOD0(0), + SD_PRSNT_N_IN(1) => HUB_MOD0(8), + SD_PRSNT_N_IN(2) => '1', + SD_PRSNT_N_IN(3) => '1', + SD_LOS_IN(0) => SFP_LOS(0), + SD_LOS_IN(1) => HUB_LOS(8), + SD_LOS_IN(2) => '1', + SD_LOS_IN(3) => '1', + SD_TXDIS_OUT(0) => SFP_TX_DIS(0), + SD_TXDIS_OUT(1) => HUB_TXDIS(8), + SD_TXDIS_OUT(2) => open, + SD_TXDIS_OUT(3) => open, + --Control Interface + BUS_RX => bussci4_rx, + BUS_TX => bussci4_tx, + -- Status and control port + STAT_DEBUG => open, + CTRL_DEBUG => open, + DEBUG_OUT => open + ); +end generate; + +--------------------------------------------------------------------------- +-- GbE +--------------------------------------------------------------------------- +gen_noGBE : if INCLUDE_GBE = c_NO generate + gsc_reply_read <= '1'; + gsc_init_dataready <= '0'; + busgbeip_tx.unknown <= busgbeip_rx.read or busgbeip_rx.write; + busgbereg_tx.unknown <= busgbereg_rx.read or busgbereg_rx.write; +end generate; + +--------------------------------------------------------------------------- +-- PCSD: GbE +--------------------------------------------------------------------------- +gen_GBE : if INCLUDE_GBE = c_YES generate + GBE : entity work.gbe_wrapper + generic map( + DO_SIMULATION => 0, + INCLUDE_DEBUG => 0, + USE_INTERNAL_TRBNET_DUMMY => 0, + USE_EXTERNAL_TRBNET_DUMMY => 0, + RX_PATH_ENABLE => 1, + FIXED_SIZE_MODE => 1, + INCREMENTAL_MODE => 1, + FIXED_SIZE => 100, + FIXED_DELAY_MODE => 1, + UP_DOWN_MODE => 0, + UP_DOWN_LIMIT => 100, + FIXED_DELAY => 100, + + NUMBER_OF_GBE_LINKS => 4, + LINKS_ACTIVE => "0001", + + LINK_HAS_READOUT => "0001", + LINK_HAS_SLOWCTRL => "0001", + LINK_HAS_DHCP => "0001", + LINK_HAS_ARP => "0001", + LINK_HAS_PING => "0001" + ) + port map( + CLK_SYS_IN => clk_sys, + CLK_125_IN => CLK_SUPPL_PCLK, + RESET => reset_i, + GSR_N => GSR_N, + -- + TRIGGER_IN => '0', + -- + SD_PRSNT_N_IN(0) => SFP_MOD0(0), + SD_PRSNT_N_IN(3 downto 1) => "111", + SD_LOS_IN(0) => SFP_LOS(0), + SD_LOS_IN(3 downto 1) => "111", + SD_TXDIS_OUT(0) => SFP_TX_DIS(0), + -- + CTS_NUMBER_IN => cts_number, + CTS_CODE_IN => cts_code, + CTS_INFORMATION_IN => cts_information, + CTS_READOUT_TYPE_IN => cts_readout_type, + CTS_START_READOUT_IN => cts_start_readout, + CTS_DATA_OUT => cts_data, + CTS_DATAREADY_OUT => cts_dataready, + CTS_READOUT_FINISHED_OUT => cts_readout_finished, + CTS_READ_IN => cts_read, + CTS_LENGTH_OUT => cts_length, + CTS_ERROR_PATTERN_OUT => cts_status_bits, + -- + FEE_DATA_IN => fee_data, + FEE_DATAREADY_IN => fee_dataready, + FEE_READ_OUT => fee_read, + FEE_STATUS_BITS_IN => fee_status_bits, + FEE_BUSY_IN => fee_busy, + -- + MC_UNIQUE_ID_IN => mc_unique_id, + MY_TRBNET_ADDRESS_IN => my_address, + ISSUE_REBOOT_OUT => reboot_from_gbe, + -- + GSC_CLK_IN => clk_sys, + GSC_INIT_DATAREADY_OUT => gsc_init_dataready, + GSC_INIT_DATA_OUT => gsc_init_data, + GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, + GSC_INIT_READ_IN => gsc_init_read, + GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, + GSC_REPLY_DATA_IN => gsc_reply_data, + GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, + GSC_REPLY_READ_OUT => gsc_reply_read, + GSC_BUSY_IN => gsc_busy, + -- + BUS_IP_RX => busgbeip_rx, + BUS_IP_TX => busgbeip_tx, + BUS_REG_RX => busgbereg_rx, + BUS_REG_TX => busgbereg_tx, + -- + MAKE_RESET_OUT => reset_via_gbe, + -- + DEBUG_OUT => open + ); +end generate; + +--------------------------------------------------------------------------- +-- Hub +--------------------------------------------------------------------------- +gen_hub_with_gbe : if INCLUDE_GBE = c_YES generate + THE_HUB: entity work.trb_net16_hub_streaming_port_sctrl_record + generic map( + HUB_USED_CHANNELS => (1,1,0,1), + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => IS_UPLINK, + MII_IS_DOWNLINK => IS_DOWNLINK, + MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, + USE_ONEWIRE => c_YES, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0001", + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR + ) + port map( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + --Media interfacces + MEDIA_MED2INT => med2int(0 to INTERFACE_NUM-1), + MEDIA_INT2MED => int2med(0 to INTERFACE_NUM-1), + --Event information coming from CTSCTS_READOUT_TYPE_OUT + CTS_NUMBER_OUT => cts_number, + CTS_CODE_OUT => cts_code, + CTS_INFORMATION_OUT => cts_information, + CTS_READOUT_TYPE_OUT => cts_readout_type, + CTS_START_READOUT_OUT => cts_start_readout, + --Information sent to CTS + --status data, equipped with DHDR + CTS_DATA_IN => cts_data, + CTS_DATAREADY_IN => cts_dataready, + CTS_READOUT_FINISHED_IN => cts_readout_finished, + CTS_READ_OUT => cts_read, + CTS_LENGTH_IN => cts_length, + CTS_STATUS_BITS_IN => cts_status_bits, + -- Data from Frontends + FEE_DATA_OUT => fee_data, + FEE_DATAREADY_OUT => fee_dataready, + FEE_READ_IN => fee_read, + FEE_STATUS_BITS_OUT => fee_status_bits, + FEE_BUSY_OUT => fee_busy, + MY_ADDRESS_IN => my_address, + COMMON_STAT_REGS => common_stat_reg, --open, + COMMON_CTRL_REGS => common_ctrl_reg, --open, + ONEWIRE => TEMPSENS, + MY_ADDRESS_OUT => my_address, + UNIQUE_ID_OUT => mc_unique_id, + EXTERNAL_SEND_RESET => external_reset_i, + -- + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + TIMER => timer, + --Gbe Sctrl Input + GSC_INIT_DATAREADY_IN => gsc_init_dataready, + GSC_INIT_DATA_IN => gsc_init_data, + GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num, + GSC_INIT_READ_OUT => gsc_init_read, + GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready, + GSC_REPLY_DATA_OUT => gsc_reply_data, + GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, + GSC_REPLY_READ_IN => gsc_reply_read, + GSC_BUSY_OUT => gsc_busy, + --status and control ports + HUB_STAT_CHANNEL => open, + HUB_STAT_GEN => open, + MPLEX_CTRL => (others => '0'), + MPLEX_STAT => open, + STAT_REGS => open, + STAT_CTRL_REGS => open, + --Fixed status and control ports + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') + ); + external_reset_i <= reset_via_gbe; +end generate; + + +gen_hub_no_gbe : if INCLUDE_GBE = c_NO generate + THE_HUB : trb_net16_hub_base + generic map( + HUB_USED_CHANNELS => (1,1,0,1), + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => IS_UPLINK, + MII_IS_DOWNLINK => IS_DOWNLINK, + MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, + USE_ONEWIRE => c_YES, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0001", + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + --Media interfacces + MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => med_dataready_out(INTERFACE_NUM*1-1 downto 0), + MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => med_data_out(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => med_packet_num_out(INTERFACE_NUM*3-1 downto 0), + MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => med_read_in(INTERFACE_NUM*1-1 downto 0), + MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => med_dataready_in(INTERFACE_NUM*1-1 downto 0), + MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => med_data_in(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => med_packet_num_in(INTERFACE_NUM*3-1 downto 0), + MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => med_read_out(INTERFACE_NUM*1-1 downto 0), + MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => med_stat_op(INTERFACE_NUM*16-1 downto 0), + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => med_ctrl_op(INTERFACE_NUM*16-1 downto 0), + + COMMON_STAT_REGS => common_stat_reg, + COMMON_CTRL_REGS => common_ctrl_reg, + MY_ADDRESS_OUT => my_address, + --REGIO INTERFACE + REGIO_ADDR_OUT => ctrlbus_rx.addr, + REGIO_READ_ENABLE_OUT => ctrlbus_rx.read, + REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write, + REGIO_DATA_OUT => ctrlbus_rx.data, + REGIO_DATA_IN => ctrlbus_tx.data, + REGIO_DATAREADY_IN => rdack, + REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack, + REGIO_WRITE_ACK_IN => wrack, + REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, + REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, + + ONEWIRE => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + --Status ports (for debugging) + MPLEX_CTRL => (others => '0'), + CTRL_DEBUG => (others => '0'), + STAT_DEBUG => open + ); + + gen_media_record : for i in 0 to INTERFACE_NUM-1 generate + med_data_in(i*16+15 downto i*16) <= med2int(i).data; + med_packet_num_in(i*3+2 downto i*3) <= med2int(i).packet_num; + med_dataready_in(i) <= med2int(i).dataready; + med_read_in(i) <= med2int(i).tx_read; + med_stat_op(i*16+15 downto i*16) <= med2int(i).stat_op; + + int2med(i).data <= med_data_out(i*16+15 downto i*16); + int2med(i).packet_num <= med_packet_num_out(i*3+2 downto i*3); + int2med(i).dataready <= med_dataready_out(i); + int2med(i).ctrl_op <= med_ctrl_op(i*16+15 downto i*16); + end generate; + + rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack; + wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack; + +end generate; + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 8, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"b600", 6 => x"8100", 7 => x"8300", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 9, 6 => 8, 7 => 8, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => handlerbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bustc_rx, --Clock switch + BUS_RX(2) => bussci1_rx, --SCI Serdes + BUS_RX(3) => bussci2_rx, + BUS_RX(4) => bussci3_rx, + BUS_RX(5) => bussci4_rx, + BUS_RX(6) => busgbeip_rx, + BUS_RX(7) => busgbereg_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bustc_tx, + BUS_TX(2) => bussci1_tx, + BUS_TX(3) => bussci2_tx, + BUS_TX(4) => bussci3_tx, + BUS_TX(5) => bussci4_tx, + BUS_TX(6) => busgbeip_tx, + BUS_TX(7) => busgbereg_tx, + STAT_DEBUG => open + ); + + handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out; + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS: entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_OUT, + FLASH_OUT => FLASH_IN, + PROGRAMN => PROGRAMN, + REBOOT_IN => do_reboot_i, + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT=> spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => open, --HDR_IO, + --LCD + LCD_DATA_IN => open, + --ADC + ADC_CS => ADC_CS, + ADC_MOSI => ADC_DIN, + ADC_MISO => ADC_DOUT, + ADC_CLK => ADC_CLK, + --Trigger & Monitor + MONITOR_INPUTS => open, + TRIG_GEN_INPUTS => open, + TRIG_GEN_OUTPUTS => open, + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => ctrlbus_tx, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => open + ); + +gen_reboot_no_gbe : if INCLUDE_GBE = c_NO generate + do_reboot_i <= common_ctrl_reg(15); +end generate; +gen_reboot_with_gbe : if INCLUDE_GBE = c_YES generate + do_reboot_i <= common_ctrl_reg(15) or reboot_from_gbe; +end generate; + + +--------------------------------------------------------------------------- +-- Switchesadding signal probes +--------------------------------------------------------------------------- +--Serdes Select + PCSSW_ENSMB <= '0'; + PCSSW_EQ <= x"0"; + PCSSW_PE <= x"F"; + PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) + LED_GREEN <= not debug_i(0 + 3); -- LFD --debug_clock_reset(0); + LED_ORANGE <= not debug_i(0 + 2); -- LHD --debug_clock_reset(1); + LED_RED <= not debug_i(0 + 1); -- LRR --not sed_error_i; + LED_YELLOW <= not debug_i(0 + 0); -- LTR --debug_clock_reset(2); + +gen_hub_leds : for i in 0 to 6 generate + LED_HUB_LINKOK(i+1) <= not med2int(i).stat_op(9); + LED_HUB_TX(i+1) <= not (med2int(i).stat_op(10) or not med2int(i).stat_op(9)); + LED_HUB_RX(i+1) <= not (med2int(i).stat_op(11)); +end generate; + + LED_HUB_LINKOK(8) <= not med2int(7).stat_op(9) when INCLUDE_GBE = c_NO else + '1'; + LED_HUB_TX(8) <= not (med2int(7).stat_op(10) or not med2int(7).stat_op(9)) when INCLUDE_GBE = c_NO else + '1'; + LED_HUB_RX(8) <= not (med2int(7).stat_op(11)) when INCLUDE_GBE = c_NO else + '1'; + LED_SFP_GREEN(0) <= not med2int(8).stat_op(9) when INCLUDE_GBE = c_NO else + '1'; + LED_SFP_RED(0) <= not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = c_NO else + '1'; + + LED_SFP_GREEN(1) <= not med2int(9).stat_op(9) when INCLUDE_GBE = c_NO else + not med2int(7).stat_op(9); + LED_SFP_RED(1) <= not (med2int(9).stat_op(10) or med2int(9).stat_op(11) or not med2int(9).stat_op(9)) when INCLUDE_GBE = c_NO else + not (med2int(7).stat_op(10) or med2int(7).stat_op(11) or not med2int(7).stat_op(9)); + + LED_WHITE(1) <= not send_dlm_word_i(7); + LED_WHITE(0) <= not send_rst_word_i(0); + +end architecture; + + + diff --git a/pinout/trb3sc_gbe_hub.lpf b/pinout/trb3sc_gbe_hub.lpf new file mode 100644 index 0000000..e17e268 --- /dev/null +++ b/pinout/trb3sc_gbe_hub.lpf @@ -0,0 +1,409 @@ +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_SUPPL_PCLK" SITE "V9"; #was SUPPL_CLOCK3_P +LOCATE COMP "CLK_CORE_PCLK" SITE "U9"; #was "CORE_CLOCK0_P" +LOCATE COMP "CLK_EXT_PLL_LEFT" SITE "N7"; #was "EXT_CLOCK2_P" +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +################################################################# +# AddOn Connector +################################################################# + + LOCATE COMP "LED_HUB_LINKOK_1" SITE "AA2"; #was "DQLL0_0_P" 1 + LOCATE COMP "LED_HUB_RX_1" SITE "AA1"; + LOCATE COMP "LED_HUB_TX_1" SITE "AB2"; #was "DQLL0_1_P" 5 + LOCATE COMP "HUB_MOD0_1" SITE "AB1"; + LOCATE COMP "HUB_MOD1_1" SITE "AA4"; #was "DQLL0_2_P" 9 + LOCATE COMP "HUB_MOD2_1" SITE "AA3"; +# LOCATE COMP "HUB_RATESEL_1" SITE "AA10"; #was "DQSLL0_T" 13 + LOCATE COMP "HUB_TXDIS_1" SITE "AB9"; + LOCATE COMP "HUB_LOS_1" SITE "AA5"; #was "DQLL0_3_P" 17 +# LOCATE COMP "HUB_TXFAULT_1" SITE "AB5"; + + LOCATE COMP "LED_HUB_LINKOK_2" SITE "Y7"; #was "DQLL0_4_P" 21 + LOCATE COMP "LED_HUB_RX_2" SITE "AA7"; + LOCATE COMP "LED_HUB_TX_2" SITE "AC5"; #was "DQLL2_0_P" 25 + LOCATE COMP "HUB_MOD0_2" SITE "AC4"; + LOCATE COMP "HUB_MOD1_2" SITE "AC2"; #was "DQLL2_1_P" 29 + LOCATE COMP "HUB_MOD2_2" SITE "AC1"; +# LOCATE COMP "HUB_RATESEL_2" SITE "AB4"; #was "DQLL2_2_P" 33 + LOCATE COMP "HUB_TXDIS_2" SITE "AB3"; + LOCATE COMP "HUB_LOS_2" SITE "AD5"; #was "DQSLL2_T" 37 +# LOCATE COMP "HUB_TXFAULT_2" SITE "AE5"; + + LOCATE COMP "LED_HUB_LINKOK_3" SITE "AE4"; #was "DQLL3_0_P" 2 + LOCATE COMP "LED_HUB_RX_3" SITE "AE3"; + LOCATE COMP "LED_HUB_TX_3" SITE "AB10"; #was "DQLL3_1_P" 6 + LOCATE COMP "HUB_MOD0_3" SITE "AC10"; + LOCATE COMP "HUB_MOD1_3" SITE "AE2"; #was "DQLL3_2_P" 10 + LOCATE COMP "HUB_MOD2_3" SITE "AE1"; +# LOCATE COMP "HUB_RATESEL_3" SITE "AJ1"; #was "DQSLL3_T" 14 + LOCATE COMP "HUB_TXDIS_3" SITE "AK1"; + LOCATE COMP "HUB_LOS_3" SITE "AD4"; #was "DQLL3_3_P" 18 +# LOCATE COMP "HUB_TXFAULT_3" SITE "AD3"; + + LOCATE COMP "LED_HUB_LINKOK_4" SITE "AC9"; #was "DQLL3_4_P" 22 + LOCATE COMP "LED_HUB_RX_4" SITE "AC8"; + LOCATE COMP "LED_HUB_TX_4" SITE "Y2"; #was "DQLL1_0_P" 26 + LOCATE COMP "HUB_MOD0_4" SITE "Y1"; + LOCATE COMP "HUB_MOD1_4" SITE "W4"; #was "DQLL1_1_P" 30 + LOCATE COMP "HUB_MOD2_4" SITE "W3"; +# LOCATE COMP "HUB_RATESEL_4" SITE "W2"; #was "DQLL1_2_P" 34 + LOCATE COMP "HUB_TXDIS_4" SITE "W1"; + LOCATE COMP "HUB_LOS_4" SITE "W6"; #was "DQSLL1_T" 38 +# LOCATE COMP "HUB_TXFAULT_4" SITE "Y6"; + + LOCATE COMP "LED_HUB_LINKOK_5" SITE "AD31"; #was "DQLR1_0_P" 169 + LOCATE COMP "LED_HUB_RX_5" SITE "AD30"; + LOCATE COMP "LED_HUB_TX_5" SITE "AB32"; #was "DQLR1_1_P" 173 + LOCATE COMP "HUB_MOD0_5" SITE "AB31"; + LOCATE COMP "HUB_MOD1_5" SITE "AE34"; #was "DQLR1_2_P" 177 + LOCATE COMP "HUB_MOD2_5" SITE "AE33"; +# LOCATE COMP "HUB_RATESEL_5" SITE "AB26"; #was "DQSLR1_T" 181 + LOCATE COMP "HUB_TXDIS_5" SITE "AB25"; + LOCATE COMP "HUB_LOS_5" SITE "AD33"; #was "DQLR1_3_P" 185 +# LOCATE COMP "HUB_TXFAULT_5" SITE "AD34" + + LOCATE COMP "LED_HUB_LINKOK_6" SITE "W30"; #was "DQLR2_0_P" 170 + LOCATE COMP "LED_HUB_RX_6" SITE "W29"; + LOCATE COMP "LED_HUB_TX_6" SITE "W27"; #was "DQLR2_1_P" 174 + LOCATE COMP "HUB_MOD0_6" SITE "W26"; + LOCATE COMP "HUB_MOD1_6" SITE "W34"; #was "DQLR2_2_P" 178 + LOCATE COMP "HUB_MOD2_6" SITE "W33"; +# LOCATE COMP "HUB_RATESEL_6" SITE "Y30"; #was "DQSLR2_T" 182 + LOCATE COMP "HUB_TXDIS_6" SITE "AA29"; + LOCATE COMP "HUB_LOS_6" SITE "Y34"; #was "DQLR2_3_P" 186 +# LOCATE COMP "HUB_TXFAULT_6" SITE "Y33"; + + LOCATE COMP "LED_HUB_LINKOK_7" SITE "AB34"; #was "DQLR0_0_P" 129 + LOCATE COMP "LED_HUB_RX_7" SITE "AB33"; + LOCATE COMP "LED_HUB_TX_7" SITE "AA25"; #was "DQLR0_1_P" 133 + LOCATE COMP "HUB_MOD0_7" SITE "AA26"; + LOCATE COMP "HUB_MOD1_7" SITE "AC34"; #was "DQLR0_2_P" 137 + LOCATE COMP "HUB_MOD2_7" SITE "AC33"; +# LOCATE COMP "HUB_RATESEL_7" SITE "AB30"; #was "DQSLR0_T" 141 + LOCATE COMP "HUB_TXDIS_7" SITE "AC30"; + LOCATE COMP "HUB_LOS_7" SITE "L26"; #was "DQUR0_0_P" 105 #SITE "AA31"; #was "DQLR0_3_P" 145 +# LOCATE COMP "HUB_TXFAULT_7" SITE "AA30" + + LOCATE COMP "LED_HUB_LINKOK_8" SITE "T32"; #was "DQUR2_0_P" 130 + LOCATE COMP "LED_HUB_RX_8" SITE "T31"; + LOCATE COMP "LED_HUB_TX_8" SITE "T26"; #was "DQUR2_1_P" 134 + LOCATE COMP "HUB_MOD0_8" SITE "T27"; + LOCATE COMP "HUB_MOD1_8" SITE "U32"; #was "DQUR2_2_P" 138 + LOCATE COMP "HUB_MOD2_8" SITE "U31"; +# LOCATE COMP "HUB_RATESEL_8" SITE "T30"; #was "DQSUR2_T" 142 + LOCATE COMP "HUB_TXDIS_8" SITE "U30"; + LOCATE COMP "HUB_LOS_8" SITE "T34"; #was "DQUR2_3_P" 146 +# LOCATE COMP "HUB_TXFAULT_8" SITE "T33"; + +DEFINE PORT GROUP "HUB_group" "HUB*" ; +IOBUF GROUP "HUB_group" IO_TYPE=LVCMOS25 PULLMODE=UP; +DEFINE PORT GROUP "LED_HUB_group" "LED_HUB*" ; +IOBUF GROUP "LED_HUB_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + + +################################################################# +# Pin-header IO +################################################################# +# #on KEL1 +# LOCATE COMP "INP_64" SITE "AP5"; +# LOCATE COMP "INP_65" SITE "AP2"; +# LOCATE COMP "INP_66" SITE "AN1"; +# LOCATE COMP "INP_67" SITE "AN3"; +# LOCATE COMP "INP_68" SITE "AL5"; +# LOCATE COMP "INP_69" SITE "AM6"; +# LOCATE COMP "INP_70" SITE "AL4"; +# LOCATE COMP "INP_71" SITE "AJ5"; +# LOCATE COMP "INP_72" SITE "AJ2"; +# LOCATE COMP "INP_73" SITE "AL3"; +# LOCATE COMP "INP_74" SITE "AD9"; +# LOCATE COMP "INP_75" SITE "AJ4"; +# LOCATE COMP "INP_76" SITE "V4"; +# LOCATE COMP "INP_77" SITE "V5"; +# LOCATE COMP "INP_78" SITE "T9"; +# LOCATE COMP "INP_79" SITE "T2"; +# #on KEL2 +# LOCATE COMP "INP_80" SITE "AP29"; +# LOCATE COMP "INP_81" SITE "AP33"; +# LOCATE COMP "INP_82" SITE "AN34"; +# LOCATE COMP "INP_83" SITE "AP31"; +# LOCATE COMP "INP_84" SITE "AN32"; +# LOCATE COMP "INP_85" SITE "AM29"; +# LOCATE COMP "INP_86" SITE "AL31"; +# LOCATE COMP "INP_87" SITE "AL30"; +# LOCATE COMP "INP_88" SITE "AL34"; +# LOCATE COMP "INP_89" SITE "AJ31"; +# LOCATE COMP "INP_90" SITE "AH33"; +# LOCATE COMP "INP_91" SITE "AL32"; +# LOCATE COMP "INP_92" SITE "AF32"; +# LOCATE COMP "INP_93" SITE "AE32"; +# LOCATE COMP "INP_94" SITE "AE30"; +# LOCATE COMP "INP_95" SITE "AD26"; +# DEFINE PORT GROUP "INP_group" "INP*" ; +# IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; +# +# LOCATE COMP "DAC_IN_SDI_5" SITE "P7"; +# LOCATE COMP "DAC_IN_SDI_6" SITE "M29"; +# DEFINE PORT GROUP "IN_group" "DAC_IN*" ; +# IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; +# +# +# LOCATE COMP "DAC_OUT_SDO_5" SITE "R8"; +# LOCATE COMP "DAC_OUT_SCK_5" SITE "R2"; +# LOCATE COMP "DAC_OUT_CS_5" SITE "P9"; +# LOCATE COMP "DAC_OUT_SDO_6" SITE "AC28"; +# LOCATE COMP "DAC_OUT_SCK_6" SITE "M34"; +# LOCATE COMP "DAC_OUT_CS_6" SITE "L28"; +# DEFINE PORT GROUP "OUT_group" "DAC_OUT*" ; +# IOBUF GROUP "OUT_group" IO_TYPE=LVDS25 DIFFRESISTOR=OFF; +LOCATE COMP "KEL_1" SITE "AP5"; +LOCATE COMP "KEL_2" SITE "AP2"; +LOCATE COMP "KEL_3" SITE "AN1"; +LOCATE COMP "KEL_4" SITE "AN3"; +LOCATE COMP "KEL_5" SITE "AL5"; +LOCATE COMP "KEL_6" SITE "AM6"; +LOCATE COMP "KEL_7" SITE "AL4"; +LOCATE COMP "KEL_8" SITE "AJ5"; +LOCATE COMP "KEL_9" SITE "AJ2"; +LOCATE COMP "KEL_10" SITE "AL3"; +LOCATE COMP "KEL_11" SITE "AD9"; +LOCATE COMP "KEL_12" SITE "AJ4"; +LOCATE COMP "KEL_13" SITE "V4"; +LOCATE COMP "KEL_14" SITE "V5"; +LOCATE COMP "KEL_15" SITE "T9"; +LOCATE COMP "KEL_16" SITE "T2"; +LOCATE COMP "KEL_17" SITE "P7"; +LOCATE COMP "KEL_18" SITE "R8"; +LOCATE COMP "KEL_19" SITE "R2"; +LOCATE COMP "KEL_20" SITE "P9"; +LOCATE COMP "KEL_21" SITE "AP29"; +LOCATE COMP "KEL_22" SITE "AP33"; +LOCATE COMP "KEL_23" SITE "AN34"; +LOCATE COMP "KEL_24" SITE "AP31"; +LOCATE COMP "KEL_25" SITE "AN32"; +LOCATE COMP "KEL_26" SITE "AM29"; +LOCATE COMP "KEL_27" SITE "AL31"; +LOCATE COMP "KEL_28" SITE "AL30"; +LOCATE COMP "KEL_29" SITE "AL34"; +LOCATE COMP "KEL_30" SITE "AJ31"; +LOCATE COMP "KEL_31" SITE "AH33"; +LOCATE COMP "KEL_32" SITE "AL32"; +LOCATE COMP "KEL_33" SITE "AF32"; +LOCATE COMP "KEL_34" SITE "AE32"; +LOCATE COMP "KEL_35" SITE "AE30"; +LOCATE COMP "KEL_36" SITE "AD26"; +LOCATE COMP "KEL_37" SITE "M29"; +LOCATE COMP "KEL_38" SITE "AC28"; +LOCATE COMP "KEL_39" SITE "M34"; +LOCATE COMP "KEL_40" SITE "L28"; +DEFINE PORT GROUP "KEL_group" "KEL*" ; +IOBUF GROUP "KEL_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +################################################################# +# Pin-header IO +################################################################# +LOCATE COMP "HDR_IO_1" SITE "AP28"; +LOCATE COMP "HDR_IO_2" SITE "AN28"; +LOCATE COMP "HDR_IO_3" SITE "AP27"; +LOCATE COMP "HDR_IO_4" SITE "AN27"; +LOCATE COMP "HDR_IO_5" SITE "AM27"; +LOCATE COMP "HDR_IO_6" SITE "AL27"; +LOCATE COMP "HDR_IO_7" SITE "AH26"; +LOCATE COMP "HDR_IO_8" SITE "AG26"; +LOCATE COMP "HDR_IO_9" SITE "AM28"; +LOCATE COMP "HDR_IO_10" SITE "AL28"; +DEFINE PORT GROUP "HDR_group" "HDR*" ; +IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + + +################################################################# +# Many LED +################################################################# +LOCATE COMP "LED_RJ_GREEN_0" SITE "C25"; +LOCATE COMP "LED_RJ_RED_0" SITE "D25"; +LOCATE COMP "LED_GREEN" SITE "D24"; +LOCATE COMP "LED_ORANGE" SITE "E24"; +LOCATE COMP "LED_RED" SITE "K23"; +LOCATE COMP "LED_RJ_GREEN_1" SITE "G26"; +LOCATE COMP "LED_RJ_RED_1" SITE "G25"; +LOCATE COMP "LED_YELLOW" SITE "K24"; +IOBUF PORT "LED_RJ_GREEN_0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_RED_0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_GREEN" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_ORANGE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RED" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_GREEN_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_RED_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_YELLOW" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "LED_SFP_GREEN_0" SITE "B4"; +LOCATE COMP "LED_SFP_GREEN_1" SITE "A6"; +LOCATE COMP "LED_SFP_RED_0" SITE "A3"; +LOCATE COMP "LED_SFP_RED_1" SITE "A8"; +DEFINE PORT GROUP "LED_SFP_group" "LED_SFP*" ; +IOBUF GROUP "LED_SFP_group" IO_TYPE=LVTTL33 ; + +LOCATE COMP "LED_WHITE_0" SITE "A32"; +LOCATE COMP "LED_WHITE_1" SITE "A33"; +DEFINE PORT GROUP "LED_WHITE_group" "LED_WHITE*" ; +IOBUF GROUP "LED_WHITE_group" IO_TYPE=LVTTL33 ; + +################################################################# +# SFP Control Signals +################################################################# +LOCATE COMP "SFP_LOS_0" SITE "B6"; +LOCATE COMP "SFP_LOS_1" SITE "C9"; +LOCATE COMP "SFP_MOD0_0" SITE "A5"; +LOCATE COMP "SFP_MOD0_1" SITE "K11"; +LOCATE COMP "SFP_MOD1_0" SITE "B7"; +LOCATE COMP "SFP_MOD1_1" SITE "J11"; +LOCATE COMP "SFP_MOD2_0" SITE "A7"; +LOCATE COMP "SFP_MOD2_1" SITE "D9"; +LOCATE COMP "SFP_TX_DIS_0" SITE "D6"; +LOCATE COMP "SFP_TX_DIS_1" SITE "A9"; + +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVTTL33 ; + + + +################################################################# +# Serdes Output Switch +################################################################# +LOCATE COMP "PCSSW_ENSMB" SITE "B3"; +LOCATE COMP "PCSSW_EQ_0" SITE "B1"; +LOCATE COMP "PCSSW_EQ_1" SITE "B2"; +LOCATE COMP "PCSSW_EQ_2" SITE "E4"; +LOCATE COMP "PCSSW_EQ_3" SITE "D4"; +LOCATE COMP "PCSSW_PE_0" SITE "C3"; +LOCATE COMP "PCSSW_PE_1" SITE "C4"; +LOCATE COMP "PCSSW_PE_2" SITE "D3"; +LOCATE COMP "PCSSW_PE_3" SITE "C2"; +LOCATE COMP "PCSSW_1" SITE "D5"; +LOCATE COMP "PCSSW_0" SITE "A2"; +LOCATE COMP "PCSSW_2" SITE "E13"; +LOCATE COMP "PCSSW_3" SITE "F13"; +LOCATE COMP "PCSSW_4" SITE "G13"; +LOCATE COMP "PCSSW_5" SITE "H14"; +LOCATE COMP "PCSSW_6" SITE "A13"; +LOCATE COMP "PCSSW_7" SITE "B13"; +DEFINE PORT GROUP "PCSSW_group" "PCSSW*" ; +IOBUF GROUP "PCSSW_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; + + +################################################################# +# ADC +################################################################# +LOCATE COMP "ADC_CLK" SITE "A14"; +LOCATE COMP "ADC_CS" SITE "B14"; +LOCATE COMP "ADC_DIN" SITE "G17"; +LOCATE COMP "ADC_DOUT" SITE "G16"; +IOBUF PORT "ADC_CLK" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_CS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_DIN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_DOUT" IO_TYPE=LVTTL33 PULLMODE=UP ; + +################################################################# +# RJ-45 connectors +################################################################# +LOCATE COMP "RJ_IO_0" SITE "R28"; +LOCATE COMP "RJ_IO_1" SITE "R31"; +LOCATE COMP "RJ_IO_2" SITE "R26"; +LOCATE COMP "RJ_IO_3" SITE "R34"; +#LOCATE COMP "RJ_IO_1_N" SITE "R27"; +#LOCATE COMP "RJ_IO_2_N" SITE "R30"; +#LOCATE COMP "RJ_IO_3_N" SITE "R25"; +#LOCATE COMP "RJ_IO_4_N" SITE "R33"; +IOBUF PORT "RJ_IO_0" IO_TYPE=LVDS25 ; +IOBUF PORT "RJ_IO_1" IO_TYPE=LVDS25 ; +IOBUF PORT "RJ_IO_2" IO_TYPE=LVDS25E ; +IOBUF PORT "RJ_IO_3" IO_TYPE=LVDS25E ; + + +LOCATE COMP "SPARE_IN_0" SITE "K31"; +LOCATE COMP "SPARE_IN_1" SITE "R4"; +#LOCATE COMP "SPARE_IN0_N" SITE "K32"; +#LOCATE COMP "SPARE_IN1_N" SITE "R3"; +IOBUF PORT "SPARE_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; +IOBUF PORT "SPARE_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; + +################################################################# +# Backplane I/O +################################################################# +LOCATE COMP "BACK_GPIO_0" SITE "C26"; +LOCATE COMP "BACK_GPIO_1" SITE "D26"; +LOCATE COMP "BACK_GPIO_2" SITE "B27"; +LOCATE COMP "BACK_GPIO_3" SITE "C27"; +LOCATE COMP "BACK_GPIO_4" SITE "D27"; +LOCATE COMP "BACK_GPIO_5" SITE "E27"; +LOCATE COMP "BACK_GPIO_6" SITE "B28"; +LOCATE COMP "BACK_GPIO_7" SITE "A28"; +LOCATE COMP "BACK_GPIO_8" SITE "A26"; +LOCATE COMP "BACK_GPIO_9" SITE "A27"; +LOCATE COMP "BACK_GPIO_10" SITE "A29"; +LOCATE COMP "BACK_GPIO_11" SITE "A30"; +LOCATE COMP "BACK_GPIO_12" SITE "H26"; +LOCATE COMP "BACK_GPIO_13" SITE "H25"; +LOCATE COMP "BACK_GPIO_14" SITE "A31"; +LOCATE COMP "BACK_GPIO_15" SITE "B31"; +DEFINE PORT GROUP "BACK_GPIO_group" "BACK_GPIO*" ; +IOBUF GROUP "BACK_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + +LOCATE COMP "BACK_LVDS_0" SITE "V2"; +LOCATE COMP "BACK_LVDS_1" SITE "T4"; +# LOCATE COMP "BACK_LVDS_0_N" SITE "V1"; +# LOCATE COMP "BACK_LVDS_1_N" SITE "T3"; +DEFINE PORT GROUP "BACK_LVDS_group" "BACK_LVDS*" ; +IOBUF GROUP "BACK_LVDS_group" IO_TYPE=LVDS25; + + +################################################################# +# Flash ROM and Reboot +################################################################# +LOCATE COMP "FLASH_CLK" SITE "F34"; #was "SPI_CLK" +LOCATE COMP "FLASH_CS" SITE "D34"; #was "SPI_CS" +LOCATE COMP "FLASH_IN" SITE "F33"; #was "SPI_IN" +LOCATE COMP "FLASH_OUT" SITE "F32"; #was "SPI_OUT" +LOCATE COMP "PROGRAMN" SITE "C31"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE; +IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + +LOCATE COMP "ENPIRION_CLOCK" SITE "H23"; +IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "J13"; #was TEMP_OWB +IOBUF PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Test I/O +################################################################# +LOCATE COMP "TEST_LINE_0" SITE "A19"; +LOCATE COMP "TEST_LINE_1" SITE "B19"; +LOCATE COMP "TEST_LINE_2" SITE "K20"; +LOCATE COMP "TEST_LINE_3" SITE "L19"; +LOCATE COMP "TEST_LINE_4" SITE "C19"; +LOCATE COMP "TEST_LINE_5" SITE "D19"; +LOCATE COMP "TEST_LINE_6" SITE "J19"; +LOCATE COMP "TEST_LINE_7" SITE "K19"; +LOCATE COMP "TEST_LINE_8" SITE "A20"; +LOCATE COMP "TEST_LINE_9" SITE "B20"; +LOCATE COMP "TEST_LINE_10" SITE "G20"; +LOCATE COMP "TEST_LINE_11" SITE "G21"; +LOCATE COMP "TEST_LINE_12" SITE "C20"; +LOCATE COMP "TEST_LINE_13" SITE "D20"; +LOCATE COMP "TEST_LINE_14" SITE "F21"; +LOCATE COMP "TEST_LINE_15" SITE "F22"; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;